Timing Report Max Delay Analysis

SmartTime Version v10.0 SP2
Actel Corporation - Actel Designer Software Release v10.0 SP2 (Version 10.0.20.2)
Copyright (c) 1989-2012
Date: Thu Jul 26 15:14:17 2012


Design: TOP_IAP
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.661
External Hold (ns):         1.288
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_macclk
Period (ns):                25.000
Frequency (MHz):            40.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               MSS_IAP_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      2.681
Max Clock-To-Out (ns):      9.529

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_IAP_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          MSS_IAP_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.937
  Slack (ns):
  Arrival (ns):                0.937
  Required (ns):
  Setup (ns):                  -2.139
  External Setup (ns):         -1.661


Expanded Path 1
  From: MSS_RESET_N
  To: MSS_IAP_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.937
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        MSS_IAP_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.937          cell: ADLIB:IOPAD_IN
  0.937                        MSS_IAP_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: MSS_IAP_0/MSS_RESET_0_MSS_RESET_N_Y
  0.937                        MSS_IAP_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.937                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.459          net: MSS_IAP_0/GLA0
  N/C                          MSS_IAP_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -2.139          Library setup time: ADLIB:MSS_APB_IP
  N/C                          MSS_IAP_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_macclk

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_IAP_0/MSS_ADLIB_INST/U_CORE:MACCLKCCC

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MSS_IAP_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          FAB_CLK
  Delay (ns):                  9.529
  Slack (ns):
  Arrival (ns):                9.529
  Required (ns):
  Clock to Out (ns):           9.529

Path 2
  From:                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To:                          GLC
  Delay (ns):                  5.875
  Slack (ns):
  Arrival (ns):                5.875
  Required (ns):
  Clock to Out (ns):           5.875


Expanded Path 1
  From: MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA
  To: FAB_CLK
  data required time                             N/C
  data arrival time                          -   9.529
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_IAP_0/MSS_CCC_0/I_XTLOSC:CLKOUT
               +     0.000          Clock source
  0.000                        MSS_IAP_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
               +     0.000          net: MSS_IAP_0/MSS_CCC_0/N_CLKA_XTLOSC
  0.000                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:CLKA (r)
               +     4.798          cell: ADLIB:MSS_CCC_IP
  4.798                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (f)
               +     0.000          net: MSS_IAP_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  4.798                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (f)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.798                        MSS_IAP_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (f)
               +     0.762          net: FAB_CLK
  5.560                        FAB_CLK_pad/U0/U1:D (f)
               +     0.600          cell: ADLIB:IOTRI_OB_EB
  6.160                        FAB_CLK_pad/U0/U1:DOUT (f)
               +     0.000          net: FAB_CLK_pad/U0/NET1
  6.160                        FAB_CLK_pad/U0/U0:D (f)
               +     3.369          cell: ADLIB:IOPAD_TRI
  9.529                        FAB_CLK_pad/U0/U0:PAD (f)
               +     0.000          net: FAB_CLK_c
  9.529                        FAB_CLK (f)
                                    
  9.529                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MSS_IAP_0/MSS_CCC_0/I_XTLOSC:CLKOUT
               +     0.000          Clock source
  N/C                          MSS_IAP_0/MSS_CCC_0/I_XTLOSC:CLKOUT (r)
                                    
  N/C                          FAB_CLK (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

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Path set User Sets

