`timescale 1 ns/100 ps
// Version: 10.0 SP1 10.0.10.4


module TOP_IAP(
       EMC_CLK,
       EMC_CS0_N,
       EMC_CS1_N,
       EMC_OEN0_N,
       EMC_OEN1_N,
       EMC_RW_N,
       UART_1_TXD,
       UART_1_RXD,
       UART_0_TXD,
       UART_0_RXD,
       I2C_0_SCL,
       I2C_0_SDA,
       SPI_1_DO,
       SPI_1_SS,
       SPI_1_CLK,
       SPI_1_DI,
       SPI_0_DO,
       SPI_0_CLK,
       SPI_0_SS,
       SPI_0_DI,
       I2C_1_SDA,
       I2C_1_SCL,
       MAC_MDIO,
       MAC_MDC,
       MAC_CRSDV,
       MAC_RXER,
       MAC_TXEN,
       MSS_RESET_N,
       MAINXIN,
       GLC,
       FAB_CLK,
       EMC_DB,
       EMC_AB,
       EMC_BYTEN,
       MAC_RXD,
       MAC_TXD
    );
output EMC_CLK;
output EMC_CS0_N;
output EMC_CS1_N;
output EMC_OEN0_N;
output EMC_OEN1_N;
output EMC_RW_N;
output UART_1_TXD;
input  UART_1_RXD;
output UART_0_TXD;
input  UART_0_RXD;
inout  I2C_0_SCL;
inout  I2C_0_SDA;
output SPI_1_DO;
inout  SPI_1_SS;
inout  SPI_1_CLK;
input  SPI_1_DI;
output SPI_0_DO;
inout  SPI_0_CLK;
inout  SPI_0_SS;
input  SPI_0_DI;
inout  I2C_1_SDA;
inout  I2C_1_SCL;
inout  MAC_MDIO;
output MAC_MDC;
input  MAC_CRSDV;
input  MAC_RXER;
output MAC_TXEN;
input  MSS_RESET_N;
input  MAINXIN;
output GLC;
output FAB_CLK;
inout  [15:0] EMC_DB;
output [25:0] EMC_AB;
output [1:0] EMC_BYTEN;
input  [1:0] MAC_RXD;
output [1:0] MAC_TXD;

    wire GND_net, VCC_net;
    
    VCC VCC (.Y(VCC_net));
    GND GND (.Y(GND_net));
    MSS_IAP MSS_IAP_0 (.EMC_CLK(EMC_CLK), .EMC_CS0_N(EMC_CS0_N), 
        .EMC_CS1_N(EMC_CS1_N), .EMC_OEN0_N(EMC_OEN0_N), .EMC_OEN1_N(
        EMC_OEN1_N), .EMC_RW_N(EMC_RW_N), .UART_0_TXD(UART_0_TXD), 
        .UART_0_RXD(UART_0_RXD), .UART_1_TXD(UART_1_TXD), .UART_1_RXD(
        UART_1_RXD), .I2C_1_SDA(I2C_1_SDA), .I2C_1_SCL(I2C_1_SCL), 
        .SPI_1_DI(SPI_1_DI), .SPI_1_DO(SPI_1_DO), .SPI_1_CLK(SPI_1_CLK)
        , .SPI_1_SS(SPI_1_SS), .SPI_0_DI(SPI_0_DI), .SPI_0_DO(SPI_0_DO)
        , .SPI_0_CLK(SPI_0_CLK), .SPI_0_SS(SPI_0_SS), .I2C_0_SCL(
        I2C_0_SCL), .I2C_0_SDA(I2C_0_SDA), .MSS_RESET_N(MSS_RESET_N), 
        .MAC_MDIO(MAC_MDIO), .MAC_CRSDV(MAC_CRSDV), .MAC_RXER(MAC_RXER)
        , .MAC_TXEN(MAC_TXEN), .MAC_MDC(MAC_MDC), .GLC(GLC), .MAINXIN(
        MAINXIN), .FAB_CLK(FAB_CLK), .EMC_DB({EMC_DB[15], EMC_DB[14], 
        EMC_DB[13], EMC_DB[12], EMC_DB[11], EMC_DB[10], EMC_DB[9], 
        EMC_DB[8], EMC_DB[7], EMC_DB[6], EMC_DB[5], EMC_DB[4], 
        EMC_DB[3], EMC_DB[2], EMC_DB[1], EMC_DB[0]}), .EMC_AB({
        EMC_AB[25], EMC_AB[24], EMC_AB[23], EMC_AB[22], EMC_AB[21], 
        EMC_AB[20], EMC_AB[19], EMC_AB[18], EMC_AB[17], EMC_AB[16], 
        EMC_AB[15], EMC_AB[14], EMC_AB[13], EMC_AB[12], EMC_AB[11], 
        EMC_AB[10], EMC_AB[9], EMC_AB[8], EMC_AB[7], EMC_AB[6], 
        EMC_AB[5], EMC_AB[4], EMC_AB[3], EMC_AB[2], EMC_AB[1], 
        EMC_AB[0]}), .EMC_BYTEN({EMC_BYTEN[1], EMC_BYTEN[0]}), 
        .MAC_RXD({MAC_RXD[1], MAC_RXD[0]}), .MAC_TXD({MAC_TXD[1], 
        MAC_TXD[0]}));
    
endmodule
