-- Version: 10.0 SP1 10.0.10.4

library ieee;
use ieee.std_logic_1164.all;
library smartfusion;
use smartfusion.all;

entity TOP_IAP is

    port( FAB_CLK     : out   std_logic;
          MAC_TXD     : out   std_logic_vector(1 downto 0);
          MAC_RXD     : in    std_logic_vector(1 downto 0);
          MAC_CLK     : in    std_logic;
          MAINXIN     : in    std_logic;
          MAC_MDC     : out   std_logic;
          MAC_TXEN    : out   std_logic;
          MAC_RXER    : in    std_logic;
          MAC_CRSDV   : in    std_logic;
          MAC_MDIO    : inout std_logic := 'Z';
          MSS_RESET_N : in    std_logic;
          UART_0_RXD  : in    std_logic;
          UART_0_TXD  : out   std_logic
        );

end TOP_IAP;

architecture DEF_ARCH of TOP_IAP is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component Ethernet_IAP
    port( UART_0_TXD  : out   std_logic;
          UART_0_RXD  : in    std_logic := 'U';
          MSS_RESET_N : in    std_logic := 'U';
          MAC_MDIO    : inout   std_logic;
          MAC_CRSDV   : in    std_logic := 'U';
          MAC_RXER    : in    std_logic := 'U';
          MAC_TXEN    : out   std_logic;
          MAC_MDC     : out   std_logic;
          FAB_CLK     : out   std_logic;
          MAINXIN     : in    std_logic := 'U';
          MAC_CLK     : in    std_logic := 'U';
          MAC_RXD     : in    std_logic_vector(1 downto 0) := (others => 'U');
          MAC_TXD     : out   std_logic_vector(1 downto 0)
        );
  end component;

    signal GND_net, VCC_net : std_logic;

begin 


    \VCC\ : VCC
      port map(Y => VCC_net);
    
    \GND\ : GND
      port map(Y => GND_net);
    
    \Ethernet_IAP\ : Ethernet_IAP
      port map(UART_0_TXD => UART_0_TXD, UART_0_RXD => UART_0_RXD, 
        MSS_RESET_N => MSS_RESET_N, MAC_MDIO => MAC_MDIO, 
        MAC_CRSDV => MAC_CRSDV, MAC_RXER => MAC_RXER, MAC_TXEN
         => MAC_TXEN, MAC_MDC => MAC_MDC, FAB_CLK => FAB_CLK, 
        MAINXIN => MAINXIN, MAC_CLK => MAC_CLK, MAC_RXD(1) => 
        MAC_RXD(1), MAC_RXD(0) => MAC_RXD(0), MAC_TXD(1) => 
        MAC_TXD(1), MAC_TXD(0) => MAC_TXD(0));
    

end DEF_ARCH; 
