@W: MT462 :"c:\a2f_ac362_df\a2f_500\programming_fpgafabric\ethernet_host_pc_iap\component\work\ethernet_iap\mss_ccc_0\ethernet_iap_tmp_mss_ccc_0_mss_ccc.vhd":125:4:125:11|Net \\Ethernet_IAP\\.MSS_ADLIB_INST_FCLK appears to be an unidentified clock source. Assuming default frequency. 
@W: MT246 :"c:\a2f_ac362_df\a2f_500\programming_fpgafabric\ethernet_host_pc_iap\component\work\ethernet_iap\mss_ccc_0\ethernet_iap_tmp_mss_ccc_0_mss_ccc.vhd":163:4:163:11|Blackbox MSS_XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock TOP_IAP|MAC_CLK with period 10.00ns. Please declare a user-defined clock on object "p:MAC_CLK"
@W: MT420 |Found inferred clock TOP_IAP|\\Ethernet_IAP\\.MSS_ADLIB_INST_EMCCLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:\Ethernet_IAP\.MSS_ADLIB_INST_EMCCLK"
