`timescale 1 ns/100 ps
// Version: 10.0 10.0.9.37


module top_level_fat_fs(
       UART_0_TXD,
       UART_0_RXD,
       SPI_1_DO,
       SPI_1_SS,
       SPI_1_CLK,
       SPI_1_DI,
       SPI_0_DO,
       SPI_0_CLK,
       SPI_0_SS,
       SPI_0_DI,
       MAC_MDIO,
       MAC_MDC,
       MAC_CRSDV,
       MAC_RXER,
       MAC_TXEN,
       MSS_RESET_N,
       MAINXIN,
       GLC,
       MAC_RXD,
       MAC_TXD
    );
output UART_0_TXD;
input  UART_0_RXD;
output SPI_1_DO;
inout  SPI_1_SS;
inout  SPI_1_CLK;
input  SPI_1_DI;
output SPI_0_DO;
inout  SPI_0_CLK;
inout  SPI_0_SS;
input  SPI_0_DI;
inout  MAC_MDIO;
output MAC_MDC;
input  MAC_CRSDV;
input  MAC_RXER;
output MAC_TXEN;
input  MSS_RESET_N;
input  MAINXIN;
output GLC;
input  [1:0] MAC_RXD;
output [1:0] MAC_TXD;

    wire GND_net, VCC_net;
    
    fat_fs mss_fat_fs_0 (.UART_0_TXD(UART_0_TXD), .UART_0_RXD(
        UART_0_RXD), .SPI_1_DI(SPI_1_DI), .SPI_1_DO(SPI_1_DO), 
        .SPI_1_CLK(SPI_1_CLK), .SPI_1_SS(SPI_1_SS), .SPI_0_DI(SPI_0_DI)
        , .SPI_0_DO(SPI_0_DO), .SPI_0_CLK(SPI_0_CLK), .SPI_0_SS(
        SPI_0_SS), .MSS_RESET_N(MSS_RESET_N), .MAC_MDIO(MAC_MDIO), 
        .MAC_CRSDV(MAC_CRSDV), .MAC_RXER(MAC_RXER), .MAC_TXEN(MAC_TXEN)
        , .MAC_MDC(MAC_MDC), .GLC(GLC), .MAINXIN(MAINXIN), .MAC_RXD({
        MAC_RXD[1], MAC_RXD[0]}), .MAC_TXD({MAC_TXD[1], MAC_TXD[0]}));
    VCC VCC (.Y(VCC_net));
    GND GND (.Y(GND_net));
    
endmodule
