`

    #Build: Synplify Pro E-2010.09A-1, Build 006R, Oct  6 2010
    #install: \\idm\tools\releases\production\Libero\Libero_91\PC_Libero_9_1_0_18_winxp_32\Synopsys\synplify_E201009A-1
    #OS: Windows XP 5.1
    #Hostname: VXP-ARNIS

    #Implementation: synthesis

    #Wed Apr 27 11:18:24 2011

    $ Start of Compile
    #Wed Apr 27 11:18:24 2011

    Synopsys Verilog Compiler, version comp520rcp1, Build 028R, built Sep 23 2010
    @N: :  | Running in 32-bit mode
    Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved

    @I::"\\idm\tools\releases\production\Libero\Libero_91\PC_Libero_9_1_0_18_winxp_32\Synopsys\synplify_E201009A-1\lib\proasic\smartfusion.v"
    @I::"\\idm\tools\releases\production\Libero\Libero_91\PC_Libero_9_1_0_18_winxp_32\Synopsys\synplify_E201009A-1\lib\vlog\hypermods.v"
    @I::"C:\appnotes\AC360\A2F_AC360_DF\HW\component\Actel\SmartFusionMSS\MSS\2.4.105\mss_comps.v"
    @I::"C:\appnotes\AC360\A2F_AC360_DF\HW\component\work\mss_fat_fs\MSS_CCC_0\mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC.v"
    @I::"C:\appnotes\AC360\A2F_AC360_DF\HW\component\work\mss_fat_fs\mss_tshell.v"
    @I::"C:\appnotes\AC360\A2F_AC360_DF\HW\component\work\mss_fat_fs\mss_fat_fs.v"
    @I::"C:\appnotes\AC360\A2F_AC360_DF\HW\component\work\top_level_fat_fs\top_level_fat_fs.v"
    Verilog syntax check successful!
    File C:\appnotes\AC360\A2F_AC360_DF\HW\component\Actel\SmartFusionMSS\MSS\2.4.105\mss_comps.v changed - recompiling
    File C:\appnotes\AC360\A2F_AC360_DF\HW\component\work\mss_fat_fs\MSS_CCC_0\mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC.v changed - recompiling
    File C:\appnotes\AC360\A2F_AC360_DF\HW\component\work\mss_fat_fs\mss_tshell.v changed - recompiling
    File C:\appnotes\AC360\A2F_AC360_DF\HW\component\work\mss_fat_fs\mss_fat_fs.v changed - recompiling
    File C:\appnotes\AC360\A2F_AC360_DF\HW\component\work\top_level_fat_fs\top_level_fat_fs.v changed - recompiling
    Selecting top level module top_level_fat_fs
    @N:CG364 : mss_comps.v(23) | Synthesizing module INBUF_MSS

    @N:CG364 : mss_comps.v(37) | Synthesizing module OUTBUF_MSS

    @N:CG364 : mss_comps.v(151) | Synthesizing module MSS_CCC

    @N:CG364 : mss_comps.v(1) | Synthesizing module MSS_XTLOSC

    @N:CG364 : smartfusion.v(1133) | Synthesizing module GND

    @N:CG364 : smartfusion.v(1814) | Synthesizing module VCC

    @N:CG364 : mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC.v(5) | Synthesizing module mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC

    @N:CG364 : mss_comps.v(67) | Synthesizing module BIBUF_MSS

    @N:CG364 : mss_comps.v(51) | Synthesizing module TRIBUFF_MSS

    @N:CG364 : mss_tshell.v(1) | Synthesizing module MSS_APB

    @N:CG364 : mss_fat_fs.v(5) | Synthesizing module mss_fat_fs

    @N:CG364 : top_level_fat_fs.v(5) | Synthesizing module top_level_fat_fs

    @W:CL168 : top_level_fat_fs.v(59) | Pruning instance GND - not in use ...

    @W:CL168 : top_level_fat_fs.v(58) | Pruning instance VCC - not in use ...

    @W:CL157 : mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC.v(62) | *Output RCOSC_CLKOUT has undriven bits - a simulation mismatch is possible
    @W:CL157 : mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC.v(63) | *Output MAINXIN_CLKOUT has undriven bits - a simulation mismatch is possible
    @W:CL157 : mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC.v(64) | *Output LPXIN_CLKOUT has undriven bits - a simulation mismatch is possible
    @W:CL159 : mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC.v(36) | Input CLKA is unused
    @W:CL159 : mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC.v(37) | Input CLKA_PAD is unused
    @W:CL159 : mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC.v(38) | Input CLKA_PADP is unused
    @W:CL159 : mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC.v(39) | Input CLKA_PADN is unused
    @W:CL159 : mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC.v(40) | Input CLKB is unused
    @W:CL159 : mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC.v(41) | Input CLKB_PAD is unused
    @W:CL159 : mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC.v(42) | Input CLKB_PADP is unused
    @W:CL159 : mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC.v(43) | Input CLKB_PADN is unused
    @W:CL159 : mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC.v(44) | Input CLKC is unused
    @W:CL159 : mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC.v(45) | Input CLKC_PAD is unused
    @W:CL159 : mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC.v(46) | Input CLKC_PADP is unused
    @W:CL159 : mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC.v(47) | Input CLKC_PADN is unused
    @W:CL159 : mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC.v(49) | Input LPXIN is unused
    @W:CL159 : mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC.v(50) | Input MAC_CLK is unused
    @END
    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Wed Apr 27 11:18:25 2011

    ###########################################################]

`
Synopsys Actel Technology Mapper, Version mapact, Build 023R, Built Sep 29 2010 09:29:00 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved Product Version E-2010.09A-1 @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled @W:MO111 : mss_fat_fs_tmp_mss_ccc_0_mss_ccc.v(62) | tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC) @W:MO111 : mss_fat_fs_tmp_mss_ccc_0_mss_ccc.v(63) | tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC) @W:MO111 : mss_fat_fs_tmp_mss_ccc_0_mss_ccc.v(64) | tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC) Available hyper_sources - for debug and ip models None Found @W: : mss_fat_fs_tmp_mss_ccc_0_mss_ccc.v(78) | Net mss_fat_fs_0.MSS_ADLIB_INST_FCLK appears to be a clock source which was not identfied. Assuming default frequency. @W: : mss_fat_fs_tmp_mss_ccc_0_mss_ccc.v(78) | Net mss_fat_fs_0.MSS_ADLIB_INST_MACCLKCCC appears to be a clock source which was not identfied. Assuming default frequency. Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB) Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB) Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB) Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB) Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Writing Analyst data base C:\appnotes\AC360\A2F_AC360_DF\HW\synthesis\top_level_fat_fs.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Writing EDIF Netlist and constraint files E-2010.09A-1 Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) @W:MT246 : mss_fat_fs.v(94) | Blackbox TRIBUFF_MSS is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : mss_fat_fs_tmp_mss_ccc_0_mss_ccc.v(96) | Blackbox MSS_XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock mss_fat_fs|MSS_ADLIB_INST_EMCCLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:mss_fat_fs_0.MSS_ADLIB_INST_EMCCLK" @W:MT420 : | Found inferred clock mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_MACCLKCCC_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:mss_fat_fs_0.MSS_ADLIB_INST_MACCLKCCC" @W:MT420 : | Found inferred clock mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:mss_fat_fs_0.MSS_ADLIB_INST_FCLK" ##### START OF TIMING REPORT #####[ # Timing Report written on Wed Apr 27 11:18:29 2011 # Top view: top_level_fat_fs Library name: smartfusion Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree ) Requested Frequency: 100.0 MHz Wire load mode: top Wire load model: smartfusion Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: 4.731 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock 100.0 MHz 189.8 MHz 10.000 5.269 4.731 inferred Inferred_clkgroup_1 System 100.0 MHz NA 10.000 NA NA system system_clkgroup ========================================================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------------- mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock System | 10.000 4.732 | No paths - | No paths - | No paths - =================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------- mss_fat_fs_0.MSS_ADLIB_INST mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB SPI0DOE MSS_SPI_0_DO_E 4.947 4.731 mss_fat_fs_0.MSS_ADLIB_INST mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB SPI1DO MSS_SPI_1_DO_D 4.643 5.035 mss_fat_fs_0.MSS_ADLIB_INST mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB SPI0DO MSS_SPI_0_DO_D 4.350 5.329 mss_fat_fs_0.MSS_ADLIB_INST mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB SPI1DOE MSS_SPI_1_DO_E 4.318 5.361 ==================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------- mss_fat_fs_0.MSS_SPI_0_DO mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock TRIBUFF_MSS E MSS_SPI_0_DO_E 10.000 4.731 mss_fat_fs_0.MSS_SPI_1_DO mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock TRIBUFF_MSS D MSS_SPI_1_DO_D 10.000 5.035 mss_fat_fs_0.MSS_SPI_0_DO mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock TRIBUFF_MSS D MSS_SPI_0_DO_D 10.000 5.329 mss_fat_fs_0.MSS_SPI_1_DO mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock TRIBUFF_MSS E MSS_SPI_1_DO_E 10.000 5.361 =================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 10.000 - Propagation time: 5.269 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 4.731 Number of logic level(s): 0 Starting point: mss_fat_fs_0.MSS_ADLIB_INST / SPI0DOE Ending point: mss_fat_fs_0.MSS_SPI_0_DO / E The start point is clocked by mss_fat_fs_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------- mss_fat_fs_0.MSS_ADLIB_INST MSS_APB SPI0DOE Out 4.947 4.947 - MSS_SPI_0_DO_E Net - - 0.322 - 1 mss_fat_fs_0.MSS_SPI_0_DO TRIBUFF_MSS E In - 5.269 - ==================================================================================================== Total path delay (propagation time + setup) of 5.269 is 4.947(93.9%) logic and 0.322(6.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Target Part: A2F200M3F_FBGA256_Std Report for cell top_level_fat_fs.verilog Core Cell usage: cell count area count*area GND 3 0.0 0.0 MSS_CCC 1 0.0 0.0 VCC 3 0.0 0.0 MSS_APB 1 0.0 0.0 ----- ---------- TOTAL 8 0.0 IO Cell usage: cell count BIBUF_MSS 5 INBUF_MSS 8 MSS_XTLOSC 1 OUTBUF 1 OUTBUF_MSS 5 TRIBUFF_MSS 2 ----- TOTAL 22 Core Cells : 0 of 4608 (0%) IO Cells : 22 RAM/ROM Usage Summary Block Rams : 0 of 8 (0%) Mapper successful! Process took 0h:00m:02s realtime, 0h:00m:01s cputime # Wed Apr 27 11:18:29 2011 ###########################################################]