#Build: Synplify Pro E-2010.09A-1, Build 006R, Oct 6 2010 #install: C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1 #OS: 6.1 #Hostname: W7-KOLAGADIM #Implementation: synthesis #Thu Dec 29 13:54:27 2011 $ Start of Compile #Thu Dec 29 13:54:27 2011 Synopsys VHDL Compiler, version comp520rcp1, Build 028R, built Sep 23 2010 @N: : | Running in 32-bit mode Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved @N:CD720 : std.vhd(123) | Setting time resolution to ns @N: : usbee_top_level.vhd(8) | Top entity is set to usbee_top_level. VHDL syntax check successful! File F:\ac356\A2F_AC356_DF2\A2F_AC356_DF\USBee\USBee_HW\component\Actel\SmartFusionMSS\MSS\2.2.101\mss_comps.vhd changed - recompiling File F:\ac356\A2F_AC356_DF2\A2F_AC356_DF\USBee\USBee_HW\component\work\usb_mss\MSS_CCC_0\usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd changed - recompiling File F:\ac356\A2F_AC356_DF2\A2F_AC356_DF\USBee\USBee_HW\component\work\usb_mss\usb_mss.vhd changed - recompiling File F:\ac356\A2F_AC356_DF2\A2F_AC356_DF\USBee\USBee_HW\component\work\usbee_top_level\usbee_top_level.vhd changed - recompiling @N:CD630 : usbee_top_level.vhd(8) | Synthesizing work.usbee_top_level.def_arch @N:CD630 : usb_slave.vhd(30) | Synthesizing work.usb_slave.usb_slave @N:CD233 : usb_slave.vhd(55) | Using sequential encoding for type ahb_master_states @N:CD231 : usb_slave.vhd(54) | Using onehot encoding for type fifo_read_states (idle="1000000") @N:CD233 : usb_slave.vhd(56) | Using sequential encoding for type input_data_states @W:CD638 : usb_slave.vhd(59) | Signal data_states is undriven @W:CD638 : usb_slave.vhd(61) | Signal send_data is undriven @W:CD638 : usb_slave.vhd(62) | Signal usb_32bit_data is undriven @W:CD638 : usb_slave.vhd(63) | Signal usb_24bit_data is undriven @W:CD638 : usb_slave.vhd(70) | Signal usb_data_out is undriven @W:CD638 : usb_slave.vhd(71) | Signal aempty is undriven @W:CD638 : usb_slave.vhd(75) | Signal count is undriven @N:CD630 : Em_Fifo_256_32.vhd(8) | Synthesizing work.em_fifo_256_32.def_arch @N:CD630 : smartfusion.vhd(3215) | Synthesizing smartfusion.fifo4k18.syn_black_box Post processing for smartfusion.fifo4k18.syn_black_box @N:CD630 : smartfusion.vhd(13) | Synthesizing smartfusion.and2.syn_black_box Post processing for smartfusion.and2.syn_black_box @N:CD630 : smartfusion.vhd(2043) | Synthesizing smartfusion.nand2.syn_black_box Post processing for smartfusion.nand2.syn_black_box @N:CD630 : smartfusion.vhd(2209) | Synthesizing smartfusion.or2.syn_black_box Post processing for smartfusion.or2.syn_black_box @N:CD630 : smartfusion.vhd(2051) | Synthesizing smartfusion.nand2a.syn_black_box Post processing for smartfusion.nand2a.syn_black_box @N:CD630 : smartfusion.vhd(1945) | Synthesizing smartfusion.inv.syn_black_box Post processing for smartfusion.inv.syn_black_box @N:CD630 : smartfusion.vhd(1784) | Synthesizing smartfusion.gnd.syn_black_box Post processing for smartfusion.gnd.syn_black_box @N:CD630 : smartfusion.vhd(2742) | Synthesizing smartfusion.vcc.syn_black_box Post processing for smartfusion.vcc.syn_black_box Post processing for work.em_fifo_256_32.def_arch @N:CD630 : smartfusion.vhd(639) | Synthesizing smartfusion.bibuf_lvcmos33u.syn_black_box Post processing for smartfusion.bibuf_lvcmos33u.syn_black_box Post processing for work.usb_slave.usb_slave @W:CL252 : usb_slave.vhd(70) | Bit 0 of signal USB_DATA_OUT is floating - a simulation mismatch is possible @W:CL252 : usb_slave.vhd(70) | Bit 1 of signal USB_DATA_OUT is floating - a simulation mismatch is possible @W:CL252 : usb_slave.vhd(70) | Bit 2 of signal USB_DATA_OUT is floating - a simulation mismatch is possible @W:CL252 : usb_slave.vhd(70) | Bit 3 of signal USB_DATA_OUT is floating - a simulation mismatch is possible @W:CL252 : usb_slave.vhd(70) | Bit 4 of signal USB_DATA_OUT is floating - a simulation mismatch is possible @W:CL252 : usb_slave.vhd(70) | Bit 5 of signal USB_DATA_OUT is floating - a simulation mismatch is possible @W:CL252 : usb_slave.vhd(70) | Bit 6 of signal USB_DATA_OUT is floating - a simulation mismatch is possible @W:CL252 : usb_slave.vhd(70) | Bit 7 of signal USB_DATA_OUT is floating - a simulation mismatch is possible @W:CL167 : usb_slave.vhd(102) | Input d of instance DATA_PINS is floating @W:CL167 : usb_slave.vhd(102) | Input d of instance DATA_PINS is floating @W:CL167 : usb_slave.vhd(102) | Input d of instance DATA_PINS is floating @W:CL167 : usb_slave.vhd(102) | Input d of instance DATA_PINS is floating @W:CL167 : usb_slave.vhd(102) | Input d of instance DATA_PINS is floating @W:CL167 : usb_slave.vhd(102) | Input d of instance DATA_PINS is floating @W:CL167 : usb_slave.vhd(102) | Input d of instance DATA_PINS is floating @W:CL167 : usb_slave.vhd(102) | Input d of instance DATA_PINS is floating @N:CL177 : usb_slave.vhd(163) | Sharing sequential element HSIZE. @N:CL177 : usb_slave.vhd(163) | Sharing sequential element HSEL. @N:CD630 : usb_mss.vhd(8) | Synthesizing work.usb_mss.def_arch @N:CD630 : mss_comps.vhd(65) | Synthesizing work.bibuf_mss.def_arch Post processing for work.bibuf_mss.def_arch @N:CD630 : mss_comps.vhd(24) | Synthesizing work.outbuf_mss.def_arch Post processing for work.outbuf_mss.def_arch @N:CD630 : mss_comps.vhd(4) | Synthesizing work.inbuf_mss.def_arch Post processing for work.inbuf_mss.def_arch @N:CD630 : mss_comps.vhd(183) | Synthesizing work.mss_ahb.def_arch Post processing for work.mss_ahb.def_arch @N:CD630 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(8) | Synthesizing work.usb_mss_tmp_mss_ccc_0_mss_ccc.def_arch @N:CD630 : mss_comps.vhd(907) | Synthesizing work.mss_xtlosc.def_arch Post processing for work.mss_xtlosc.def_arch @N:CD630 : mss_comps.vhd(947) | Synthesizing work.mss_ccc.def_arch Post processing for work.mss_ccc.def_arch Post processing for work.usb_mss_tmp_mss_ccc_0_mss_ccc.def_arch @W:CL240 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(38) | LPXIN_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible @W:CL240 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(37) | MAINXIN_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible @W:CL240 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(36) | RCOSC_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible Post processing for work.usb_mss.def_arch Post processing for work.usbee_top_level.def_arch @W:CL168 : usbee_top_level.vhd(271) | Pruning instance GND - not in use ... @W:CL168 : usbee_top_level.vhd(134) | Pruning instance VCC - not in use ... @W:CL159 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(10) | Input CLKA is unused @W:CL159 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(11) | Input CLKA_PAD is unused @W:CL159 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(12) | Input CLKA_PADP is unused @W:CL159 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(13) | Input CLKA_PADN is unused @W:CL159 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(14) | Input CLKB is unused @W:CL159 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(15) | Input CLKB_PAD is unused @W:CL159 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(16) | Input CLKB_PADP is unused @W:CL159 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(17) | Input CLKB_PADN is unused @W:CL159 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(18) | Input CLKC is unused @W:CL159 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(19) | Input CLKC_PAD is unused @W:CL159 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(20) | Input CLKC_PADP is unused @W:CL159 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(21) | Input CLKC_PADN is unused @W:CL159 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(23) | Input LPXIN is unused @W:CL159 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(24) | Input MAC_CLK is unused @N:CL177 : usb_slave.vhd(163) | Sharing sequential element ahb_states. @N:CL201 : usb_slave.vhd(126) | Trying to extract state machine for register input_states Extracted state machine for register input_states State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL159 : usb_slave.vhd(45) | Input HRESP is unused @W:CL159 : usb_slave.vhd(46) | Input HRDATA is unused @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Dec 29 13:54:27 2011 ###########################################################] Synopsys Actel Technology Mapper, Version mapact, Build 023R, Built Sep 29 2010 09:29:00 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved Product Version E-2010.09A-1 @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled Available hyper_sources - for debug and ip models None Found @W: : usb_mss_tmp_mss_ccc_0_mss_ccc.vhd(118) | Net usb_slave_0/HCLK appears to be a clock source which was not identfied. Assuming default frequency. Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB) @N: : usb_slave.vhd(204) | Found counter in view:work.usb_slave(usb_slave) inst INTRPT_COUNT[7:0] @N: : usb_slave.vhd(163) | Found counter in view:work.usb_slave(usb_slave) inst HADDR_TEMP[29:0] Encoding state machine work.usb_slave(usb_slave)-input_states[0:3] original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @W:MO129 : usb_slave.vhd(163) | Sequential instance usb_slave_0.HTRANS_1[0] has been reduced to a combinational gate by constant propagation @W:BN132 : usb_slave.vhd(163) | Removing sequential instance usb_slave_0.HWRITE_1, because it is equivalent to instance usb_slave_0.HTRANS_1[1] Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 56MB) Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB) Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB) Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB) Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 58MB) High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes ----------------------------------------------------------------------- usb_mss_0.FIO_INBUF_0 / Y 43 : 35 asynchronous set/reset usb_mss_0.MSS_ADLIB_INST / M2FRESETn 43 : 41 asynchronous set/reset usb_slave_0.HADDR_TEMP_0_sqmuxa / Y 32 ======================================================================= @N:FP130 : | Promoting Net USB_CLK_c on CLKBUF USB_CLK_pad Replicating Combinational Instance usb_slave_0.HADDR_TEMP_0_sqmuxa, fanout 32 segments 2 Buffering IO_0_Y, fanout 43 segments 2 Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 58MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 58MB) Added 1 Buffers Added 1 Cells via replication Added 0 Sequential Cells via replication Added 1 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 58MB) Writing Analyst data base F:\ac356\A2F_AC356_DF2\A2F_AC356_DF\USBee\USBee_HW\synthesis\usbee_top_level.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 58MB) Writing EDIF Netlist and constraint files E-2010.09A-1 Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 58MB) @W:MT246 : usb_mss.vhd(593) | Blackbox MSS_AHB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : usb_mss_tmp_mss_ccc_0_mss_ccc.vhd(156) | Blackbox MSS_XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock usbee_top_level|USB_CLK with period 1000.00ns. A user-defined clock should be declared on object "p:USB_CLK" @W:MT420 : | Found inferred clock usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock with period 1000.00ns. A user-defined clock should be declared on object "n:FAB_CLK" ##### START OF TIMING REPORT #####[ # Timing Report written on Thu Dec 29 13:54:28 2011 # Top view: usbee_top_level Library name: smartfusion Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree ) Requested Frequency: 1.0 MHz Wire load mode: top Wire load model: smartfusion Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: 977.359 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------------------------- usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock 1.0 MHz 44.2 MHz 1000.000 22.641 977.359 inferred Inferred_clkgroup_1 usbee_top_level|USB_CLK 1.0 MHz 160.8 MHz 1000.000 6.218 993.782 inferred Inferred_clkgroup_0 System 1.0 MHz 171.5 MHz 1000.000 5.831 994.169 system system_clkgroup ============================================================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System System | 1000.000 994.169 | No paths - | No paths - | No paths - System usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock | 1000.000 995.429 | No paths - | No paths - | No paths - usbee_top_level|USB_CLK usbee_top_level|USB_CLK | 1000.000 993.782 | No paths - | No paths - | No paths - usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock System | 1000.000 996.781 | No paths - | No paths - | No paths - usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock | 1000.000 977.359 | No paths - | No paths - | No paths - ==================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------- usb_slave_0.HADDR_TEMP[1] usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1P0 Q Z\\usb_slave_0_HADDR_\[3\]\\ 0.580 977.359 usb_slave_0.HADDR_TEMP[0] usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1P0 Q Z\\usb_slave_0_HADDR_\[2\]\\ 0.580 977.362 usb_slave_0.HADDR_TEMP[2] usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1P0 Q Z\\usb_slave_0_HADDR_\[4\]\\ 0.580 977.694 usb_slave_0.HADDR_TEMP[3] usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1P0 Q Z\\usb_slave_0_HADDR_\[5\]\\ 0.580 978.888 usb_slave_0.HADDR_TEMP[4] usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1P0 Q Z\\usb_slave_0_HADDR_\[6\]\\ 0.580 979.124 usb_slave_0.HADDR_TEMP[5] usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1P0 Q Z\\usb_slave_0_HADDR_\[7\]\\ 0.580 980.318 usb_slave_0.HADDR_TEMP[6] usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1P0 Q Z\\usb_slave_0_HADDR_\[8\]\\ 0.580 980.555 usb_slave_0.HADDR_TEMP[7] usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1P0 Q Z\\usb_slave_0_HADDR_\[9\]\\ 0.580 981.749 usb_slave_0.HADDR_TEMP[8] usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1P0 Q Z\\usb_slave_0_HADDR_\[10\]\\ 0.737 981.983 usb_slave_0.HADDR_TEMP[9] usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1P0 Q Z\\usb_slave_0_HADDR_\[11\]\\ 0.580 983.179 ================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------- usb_slave_0.HADDR_TEMP[29] usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1C0 D HADDR_TEMP_n29 999.461 977.359 usb_slave_0.HADDR_TEMP[28] usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1P0 D HADDR_TEMP_n28 999.427 977.885 usb_slave_0.HADDR_TEMP[27] usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1P0 D HADDR_TEMP_n27 999.427 978.759 usb_slave_0.HADDR_TEMP[26] usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1C0 D HADDR_TEMP_n26 999.461 979.242 usb_slave_0.HADDR_TEMP[25] usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1P0 D HADDR_TEMP_n25 999.427 979.769 usb_slave_0.HADDR_TEMP[24] usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1P0 D HADDR_TEMP_n24 999.531 980.742 usb_slave_0.HADDR_TEMP[23] usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1P0 D HADDR_TEMP_n23 999.427 981.199 usb_slave_0.HADDR_TEMP[22] usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1P0 D HADDR_TEMP_n22 999.531 982.173 usb_slave_0.HADDR_TEMP[21] usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1P0 D HADDR_TEMP_n21 999.427 982.630 usb_slave_0.HADDR_TEMP[20] usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock DFN1E1P0 D HADDR_TEMP_n20 999.531 983.603 ==================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 999.461 - Propagation time: 22.103 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 977.359 Number of logic level(s): 15 Starting point: usb_slave_0.HADDR_TEMP[1] / Q Ending point: usb_slave_0.HADDR_TEMP[29] / D The start point is clocked by usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by usb_mss_tmp_MSS_CCC_0_MSS_CCC|FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------ usb_slave_0.HADDR_TEMP[1] DFN1E1P0 Q Out 0.580 0.580 - Z\\usb_slave_0_HADDR_\[3\]\\ Net - - 1.184 - 4 usb_slave_0.HADDR_TEMP_RNIASPM[2] NOR3C B In - 1.764 - usb_slave_0.HADDR_TEMP_RNIASPM[2] NOR3C Y Out 0.624 2.388 - HADDR_TEMP_c2 Net - - 0.806 - 3 usb_slave_0.HADDR_TEMP_RNIBF061[4] NOR3C B In - 3.194 - usb_slave_0.HADDR_TEMP_RNIBF061[4] NOR3C Y Out 0.624 3.818 - HADDR_TEMP_c4 Net - - 0.806 - 3 usb_slave_0.HADDR_TEMP_RNIG27L1[6] NOR3C B In - 4.625 - usb_slave_0.HADDR_TEMP_RNIG27L1[6] NOR3C Y Out 0.624 5.248 - HADDR_TEMP_c6 Net - - 0.806 - 3 usb_slave_0.HADDR_TEMP_RNIPLD42[8] NOR3C B In - 6.055 - usb_slave_0.HADDR_TEMP_RNIPLD42[8] NOR3C Y Out 0.624 6.679 - HADDR_TEMP_c8 Net - - 0.806 - 3 usb_slave_0.HADDR_TEMP_RNID2NH2[10] NOR3C B In - 7.485 - usb_slave_0.HADDR_TEMP_RNID2NH2[10] NOR3C Y Out 0.624 8.109 - HADDR_TEMP_c10 Net - - 0.806 - 3 usb_slave_0.HADDR_TEMP_RNICK3T2[12] NOR3C B In - 8.915 - usb_slave_0.HADDR_TEMP_RNICK3T2[12] NOR3C Y Out 0.624 9.539 - HADDR_TEMP_c12 Net - - 0.806 - 3 usb_slave_0.HADDR_TEMP_RNIFMG83[14] NOR3C B In - 10.346 - usb_slave_0.HADDR_TEMP_RNIFMG83[14] NOR3C Y Out 0.624 10.970 - HADDR_TEMP_c14 Net - - 0.806 - 3 usb_slave_0.HADDR_TEMP_RNIM8UJ3[16] NOR3C B In - 11.776 - usb_slave_0.HADDR_TEMP_RNIM8UJ3[16] NOR3C Y Out 0.624 12.400 - HADDR_TEMP_c16 Net - - 0.806 - 3 usb_slave_0.HADDR_TEMP_RNI1BCV3[18] NOR3C B In - 13.206 - usb_slave_0.HADDR_TEMP_RNI1BCV3[18] NOR3C Y Out 0.624 13.830 - HADDR_TEMP_c18 Net - - 0.806 - 3 usb_slave_0.HADDR_TEMP_RNI7LPA4[20] NOR3C B In - 14.637 - usb_slave_0.HADDR_TEMP_RNI7LPA4[20] NOR3C Y Out 0.624 15.261 - HADDR_TEMP_c20 Net - - 0.806 - 3 usb_slave_0.HADDR_TEMP_RNI876M4[22] NOR3C B In - 16.067 - usb_slave_0.HADDR_TEMP_RNI876M4[22] NOR3C Y Out 0.624 16.691 - HADDR_TEMP_c22 Net - - 0.806 - 3 usb_slave_0.HADDR_TEMP_RNID9J15[24] NOR3C B In - 17.497 - usb_slave_0.HADDR_TEMP_RNID9J15[24] NOR3C Y Out 0.624 18.121 - HADDR_TEMP_c24 Net - - 0.806 - 3 usb_slave_0.HADDR_TEMP_RNIMR0D5[26] NOR3C B In - 18.928 - usb_slave_0.HADDR_TEMP_RNIMR0D5[26] NOR3C Y Out 0.624 19.552 - HADDR_TEMP_c26 Net - - 0.386 - 2 usb_slave_0.HADDR_TEMP_RNISQNI5[27] NOR2B A In - 19.937 - usb_slave_0.HADDR_TEMP_RNISQNI5[27] NOR2B Y Out 0.488 20.426 - HADDR_TEMP_c27 Net - - 0.386 - 2 usb_slave_0.HADDR_TEMP_RNO[29] AX1C B In - 20.811 - usb_slave_0.HADDR_TEMP_RNO[29] AX1C Y Out 0.970 21.781 - HADDR_TEMP_n29 Net - - 0.322 - 1 usb_slave_0.HADDR_TEMP[29] DFN1E1C0 D In - 22.103 - ====================================================================================================== Total path delay (propagation time + setup) of 22.641 is 10.688(47.2%) logic and 11.954(52.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: usbee_top_level|USB_CLK ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------- usb_slave_0.FIFO_INST.FIFOBLOCK_1_inst usbee_top_level|USB_CLK FIFO4K18 FULL FULLX_I_1_net 2.183 993.782 usb_slave_0.FIFO_INST.FIFOBLOCK_0_inst usbee_top_level|USB_CLK FIFO4K18 FULL FULLX_I_0_net 2.183 993.933 usb_slave_0.input_states[0] usbee_top_level|USB_CLK DFN1C1 Q input_states[0] 0.737 994.215 usb_slave_0.input_states[1] usbee_top_level|USB_CLK DFN1C1 Q input_states[1] 0.737 994.491 usb_slave_0.wr_en usbee_top_level|USB_CLK DFN1E0P1 Q wr_en 0.737 996.745 usb_slave_0.input_32_bit_data[0] usbee_top_level|USB_CLK DFN1C1 Q input_32_bit_data[0] 0.737 997.404 usb_slave_0.input_32_bit_data[1] usbee_top_level|USB_CLK DFN1C1 Q input_32_bit_data[1] 0.737 997.404 usb_slave_0.input_32_bit_data[2] usbee_top_level|USB_CLK DFN1C1 Q input_32_bit_data[2] 0.737 997.404 usb_slave_0.input_32_bit_data[3] usbee_top_level|USB_CLK DFN1C1 Q input_32_bit_data[3] 0.737 997.404 usb_slave_0.input_32_bit_data[4] usbee_top_level|USB_CLK DFN1C1 Q input_32_bit_data[4] 0.737 997.404 ========================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------- usb_slave_0.FIFO_INST.FIFOBLOCK_0_inst usbee_top_level|USB_CLK FIFO4K18 WEN WRITE_ENABLE_I 998.783 993.782 usb_slave_0.FIFO_INST.FIFOBLOCK_1_inst usbee_top_level|USB_CLK FIFO4K18 WEN WRITE_ENABLE_I 998.783 993.782 usb_slave_0.input_32_bit_data[0] usbee_top_level|USB_CLK DFN1C1 D input_32_bit_data_RNO[0] 999.461 994.215 usb_slave_0.input_32_bit_data[1] usbee_top_level|USB_CLK DFN1C1 D N_7 999.461 994.215 usb_slave_0.input_32_bit_data[2] usbee_top_level|USB_CLK DFN1C1 D N_9 999.461 994.215 usb_slave_0.input_32_bit_data[3] usbee_top_level|USB_CLK DFN1C1 D input_32_bit_data_RNO[3] 999.461 994.215 usb_slave_0.input_32_bit_data[4] usbee_top_level|USB_CLK DFN1C1 D input_32_bit_data_RNO[4] 999.461 994.215 usb_slave_0.input_32_bit_data[5] usbee_top_level|USB_CLK DFN1C1 D input_32_bit_data_RNO[5] 999.461 994.215 usb_slave_0.input_32_bit_data[6] usbee_top_level|USB_CLK DFN1C1 D input_32_bit_data_RNO[6] 999.461 994.215 usb_slave_0.input_32_bit_data[7] usbee_top_level|USB_CLK DFN1C1 D input_32_bit_data_RNO[7] 999.461 994.215 ============================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: 1.217 + Clock delay at ending point: 0.000 (ideal) = Required time: 998.783 - Propagation time: 5.002 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 993.782 Number of logic level(s): 3 Starting point: usb_slave_0.FIFO_INST.FIFOBLOCK_1_inst / FULL Ending point: usb_slave_0.FIFO_INST.FIFOBLOCK_0_inst / WEN The start point is clocked by usbee_top_level|USB_CLK [rising] on pin WCLK The end point is clocked by usbee_top_level|USB_CLK [rising] on pin WCLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------- usb_slave_0.FIFO_INST.FIFOBLOCK_1_inst FIFO4K18 FULL Out 2.183 2.183 - FULLX_I_1_net Net - - 0.322 - 1 usb_slave_0.FIFO_INST.OR2_FULL OR2 B In - 2.504 - usb_slave_0.FIFO_INST.OR2_FULL OR2 Y Out 0.514 3.019 - FIFO_FULL Net - - 0.322 - 1 usb_slave_0.FIFO_INST.WRITE_FSTOP_GATE NAND2 A In - 3.340 - usb_slave_0.FIFO_INST.WRITE_FSTOP_GATE NAND2 Y Out 0.488 3.829 - WRITE_FSTOP_ENABLE Net - - 0.322 - 1 usb_slave_0.FIFO_INST.WRITE_AND NAND2A B In - 4.150 - usb_slave_0.FIFO_INST.WRITE_AND NAND2A Y Out 0.466 4.616 - WRITE_ENABLE_I Net - - 0.386 - 2 usb_slave_0.FIFO_INST.FIFOBLOCK_0_inst FIFO4K18 WEN In - 5.002 - ========================================================================================================= Total path delay (propagation time + setup) of 6.218 is 4.868(78.3%) logic and 1.350(21.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------- usb_mss_0.MSS_CCC_0.I_XTLOSC System MSS_XTLOSC CLKOUT N_CLKA_XTLOSC 0.000 994.169 usb_mss_0.MSS_ADLIB_INST System MSS_AHB FABHREADYOUT usb_mss_0_FABHREADYOUT 0.000 995.429 usb_mss_0.MSS_ADLIB_INST System MSS_AHB EMCCLK MSS_EMI_0_CLK_D 0.000 999.614 ============================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------- usb_mss_0.MSS_ADLIB_INST System MSS_AHB PLLLOCK MSS_ADLIB_INST_PLLLOCK 1000.000 994.169 usb_mss_0.MSS_ADLIB_INST System MSS_AHB FCLK MSS_ADLIB_INST_FCLK 1000.000 994.491 usb_slave_0.HADDR_TEMP[0] System DFN1P0 D HADDR_TEMP_RNO[0] 999.461 995.429 usb_slave_0.rd_en System DFN1P0 D HADDR_TEMPe_i 999.461 995.433 usb_slave_0.HADDR_TEMP[1] System DFN1E1P0 E HADDR_TEMPe_0 999.392 996.192 usb_slave_0.HADDR_TEMP[2] System DFN1E1P0 E HADDR_TEMPe 999.392 996.192 usb_slave_0.HADDR_TEMP[3] System DFN1E1P0 E HADDR_TEMPe 999.392 996.192 usb_slave_0.HADDR_TEMP[4] System DFN1E1P0 E HADDR_TEMPe 999.392 996.192 usb_slave_0.HADDR_TEMP[5] System DFN1E1P0 E HADDR_TEMPe 999.392 996.192 usb_slave_0.HADDR_TEMP[6] System DFN1E1P0 E HADDR_TEMPe 999.392 996.192 ==================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 1000.000 - Propagation time: 5.831 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 994.169 Number of logic level(s): 1 Starting point: usb_mss_0.MSS_CCC_0.I_XTLOSC / CLKOUT Ending point: usb_mss_0.MSS_ADLIB_INST / PLLLOCK The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------- usb_mss_0.MSS_CCC_0.I_XTLOSC MSS_XTLOSC CLKOUT Out 0.000 0.000 - N_CLKA_XTLOSC Net - - 0.322 - 1 usb_mss_0.MSS_CCC_0.I_MSSCCC MSS_CCC CLKA In - 0.322 - usb_mss_0.MSS_CCC_0.I_MSSCCC MSS_CCC LOCKMSS Out 5.188 5.509 - MSS_ADLIB_INST_PLLLOCK Net - - 0.322 - 1 usb_mss_0.MSS_ADLIB_INST MSS_AHB PLLLOCK In - 5.831 - ==================================================================================================== Total path delay (propagation time + setup) of 5.831 is 5.188(89.0%) logic and 0.643(11.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Target Part: A2F500M3G_FBGA256_Std Report for cell usbee_top_level.def_arch Core Cell usage: cell count area count*area AND2 1 1.0 1.0 AO1 1 1.0 1.0 AO1B 1 1.0 1.0 AOI1 1 1.0 1.0 AX1C 15 1.0 15.0 BUFF 1 1.0 1.0 GND 5 0.0 0.0 INV 3 1.0 3.0 MSS_AHB 1 0.0 0.0 MSS_CCC 1 0.0 0.0 MX2 32 1.0 32.0 MX2C 1 1.0 1.0 NAND2 2 1.0 2.0 NAND2A 1 1.0 1.0 NOR2 3 1.0 3.0 NOR2A 2 1.0 2.0 NOR2B 3 1.0 3.0 NOR3 1 1.0 1.0 NOR3A 4 1.0 4.0 NOR3C 14 1.0 14.0 OA1 1 1.0 1.0 OR2 2 1.0 2.0 OR2A 1 1.0 1.0 OR2B 2 1.0 2.0 VCC 5 0.0 0.0 XA1 1 1.0 1.0 XA1B 4 1.0 4.0 XA1C 1 1.0 1.0 XOR2 17 1.0 17.0 DFN1C0 9 1.0 9.0 DFN1C1 34 1.0 34.0 DFN1E0P1 1 1.0 1.0 DFN1E1C0 3 1.0 3.0 DFN1E1P0 27 1.0 27.0 DFN1P0 2 1.0 2.0 FIFO4K18 2 0.0 0.0 ----- ---------- TOTAL 205 191.0 IO Cell usage: cell count BIBUF_LVCMOS33U 8 BIBUF_MSS 16 CLKBUF 1 INBUF_MSS 3 MSS_XTLOSC 1 OUTBUF_MSS 35 ----- TOTAL 64 Core Cells : 191 of 11520 (2%) IO Cells : 64 RAM/ROM Usage Summary Block Rams : 0 of 24 (0%) Mapper successful! Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Dec 29 13:54:28 2011 ###########################################################]