#Build: Synplify Pro E-2010.09A-1, Build 006R, Oct 6 2010 #install: C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1 #OS: 6.1 #Hostname: W7-KOLAGADIM #Implementation: synthesis #Thu Dec 29 18:17:05 2011 $ Start of Compile #Thu Dec 29 18:17:05 2011 Synopsys Verilog Compiler, version comp520rcp1, Build 028R, built Sep 23 2010 @N: : | Running in 32-bit mode Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved @I::"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\smartfusion.v" @I::"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\vlog\hypermods.v" @I::"F:\ac356\A2F_AC356_DF2\A2F_AC356_DF\FTDI\FTDI_SPI_HW\component\Actel\SmartFusionMSS\MSS\2.2.101\mss_comps.v" @I::"F:\ac356\A2F_AC356_DF2\A2F_AC356_DF\FTDI\FTDI_SPI_HW\component\work\mss_top\MSS_CCC_0\mss_top_tmp_MSS_CCC_0_MSS_CCC.v" @I::"F:\ac356\A2F_AC356_DF2\A2F_AC356_DF\FTDI\FTDI_SPI_HW\component\work\mss_top\mss_top.v" @I::"F:\ac356\A2F_AC356_DF2\A2F_AC356_DF\FTDI\FTDI_SPI_HW\hdl\spi_master.v" @I::"F:\ac356\A2F_AC356_DF2\A2F_AC356_DF\FTDI\FTDI_SPI_HW\hdl\spi_slave.v" @I::"F:\ac356\A2F_AC356_DF2\A2F_AC356_DF\FTDI\FTDI_SPI_HW\hdl\spi_sfr.v" @I::"F:\ac356\A2F_AC356_DF2\A2F_AC356_DF\FTDI\FTDI_SPI_HW\hdl\spi.v" @I::"F:\ac356\A2F_AC356_DF2\A2F_AC356_DF\FTDI\FTDI_SPI_HW\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3_muxptob3.v" @I::"F:\ac356\A2F_AC356_DF2\A2F_AC356_DF\FTDI\FTDI_SPI_HW\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v" @I::"F:\ac356\A2F_AC356_DF2\A2F_AC356_DF\FTDI\FTDI_SPI_HW\component\work\top_level\top_level.v" Verilog syntax check successful! File F:\ac356\A2F_AC356_DF2\A2F_AC356_DF\FTDI\FTDI_SPI_HW\component\Actel\SmartFusionMSS\MSS\2.2.101\mss_comps.v changed - recompiling File F:\ac356\A2F_AC356_DF2\A2F_AC356_DF\FTDI\FTDI_SPI_HW\component\work\mss_top\MSS_CCC_0\mss_top_tmp_MSS_CCC_0_MSS_CCC.v changed - recompiling File F:\ac356\A2F_AC356_DF2\A2F_AC356_DF\FTDI\FTDI_SPI_HW\component\work\mss_top\mss_top.v changed - recompiling File F:\ac356\A2F_AC356_DF2\A2F_AC356_DF\FTDI\FTDI_SPI_HW\hdl\spi_sfr.v changed - recompiling File F:\ac356\A2F_AC356_DF2\A2F_AC356_DF\FTDI\FTDI_SPI_HW\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3_muxptob3.v changed - recompiling File F:\ac356\A2F_AC356_DF2\A2F_AC356_DF\FTDI\FTDI_SPI_HW\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v changed - recompiling File F:\ac356\A2F_AC356_DF2\A2F_AC356_DF\FTDI\FTDI_SPI_HW\component\work\top_level\top_level.v changed - recompiling Selecting top level module top_level @W:CG775 : coreapb3.v(30) | Found Component CoreAPB3 in library COREAPB3_LIB @N:CG364 : coreapb3_muxptob3.v(30) | Synthesizing module COREAPB3_MUXPTOB3 @N:CG364 : coreapb3.v(30) | Synthesizing module CoreAPB3 APB_DWIDTH=6'b100000 RANGESIZE=21'b000000000000100000000 IADDR_ENABLE=1'b0 APBSLOT0ENABLE=1'b1 APBSLOT1ENABLE=1'b0 APBSLOT2ENABLE=1'b0 APBSLOT3ENABLE=1'b0 APBSLOT4ENABLE=1'b0 APBSLOT5ENABLE=1'b0 APBSLOT6ENABLE=1'b0 APBSLOT7ENABLE=1'b0 APBSLOT8ENABLE=1'b0 APBSLOT9ENABLE=1'b0 APBSLOT10ENABLE=1'b0 APBSLOT11ENABLE=1'b0 APBSLOT12ENABLE=1'b0 APBSLOT13ENABLE=1'b0 APBSLOT14ENABLE=1'b0 APBSLOT15ENABLE=1'b0 RANGEBITS=32'b00000000000000000000000000001000 RANGEBITS_LT16=32'b00000000000000000000000000001000 IADDR_31_24_8B_A=8'b00001100 IADDR_23_16_8B_A=8'b00001000 IADDR_15_8_8B_A=8'b00000100 IADDR_7_0_8B_A=8'b00000000 IADDR_31_16_16B_A=8'b00000100 IADDR_15_0_16B_A=8'b00000000 IADDR_31_0_32B_A=8'b00000000 SL0=16'b0000000000000001 SL1=16'b0000000000000000 SL2=16'b0000000000000000 SL3=16'b0000000000000000 SL4=16'b0000000000000000 SL5=16'b0000000000000000 SL6=16'b0000000000000000 SL7=16'b0000000000000000 SL8=16'b0000000000000000 SL9=16'b0000000000000000 SL10=16'b0000000000000000 SL11=16'b0000000000000000 SL12=16'b0000000000000000 SL13=16'b0000000000000000 SL14=16'b0000000000000000 SL15=16'b0000000000000000 Generated name = CoreAPB3_Z1 @N:CG364 : smartfusion.v(1814) | Synthesizing module VCC @N:CG364 : mss_comps.v(67) | Synthesizing module BIBUF_MSS @N:CG364 : mss_comps.v(23) | Synthesizing module INBUF_MSS @N:CG364 : mss_comps.v(37) | Synthesizing module OUTBUF_MSS @N:CG364 : mss_comps.v(85) | Synthesizing module BIBUF_OPEND_MSS @N:CG364 : mss_comps.v(51) | Synthesizing module TRIBUFF_MSS @N:CG364 : smartfusion.v(1133) | Synthesizing module GND @N:CG364 : mss_comps.v(151) | Synthesizing module MSS_CCC @N:CG364 : mss_comps.v(1) | Synthesizing module MSS_XTLOSC @N:CG364 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(5) | Synthesizing module mss_top_tmp_MSS_CCC_0_MSS_CCC @N:CG364 : mss_comps.v(680) | Synthesizing module MSS_APB @N:CG364 : mss_comps.v(145) | Synthesizing module MSSINT @N:CG364 : mss_top.v(5) | Synthesizing module mss_top @N:CG364 : spi_sfr.v(14) | Synthesizing module SPI_SFR USE_MASTER=32'b00000000000000000000000000000001 USE_SLAVE=32'b00000000000000000000000000000001 Generated name = SPI_SFR_1s_1s @N:CG364 : spi_master.v(12) | Synthesizing module spi_master @W:CL118 : spi_master.v(217) | Latch generated from always block for signal next_state[3:0], probably caused by a missing assignment in an if or case stmt @W:CS149 : spi_sfr.v(381) | Port width mismatch for port tx_data_reg. Formal has width 8, Actual 32 @N:CG364 : spi_slave.v(12) | Synthesizing module spi_slave @N:CG364 : spi.v(10) | Synthesizing module SPI @N:CG364 : top_level.v(5) | Synthesizing module top_level @W:CL246 : spi.v(38) | Input port bits 23 to 4 of PADDR[23:0] are unused @W:CL246 : spi.v(38) | Input port bits 1 to 0 of PADDR[23:0] are unused @W:CL157 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(62) | *Output RCOSC_CLKOUT has undriven bits - a simulation mismatch is possible @W:CL157 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(63) | *Output MAINXIN_CLKOUT has undriven bits - a simulation mismatch is possible @W:CL157 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(64) | *Output LPXIN_CLKOUT has undriven bits - a simulation mismatch is possible @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(36) | Input CLKA is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(37) | Input CLKA_PAD is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(38) | Input CLKA_PADP is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(39) | Input CLKA_PADN is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(40) | Input CLKB is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(41) | Input CLKB_PAD is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(42) | Input CLKB_PADP is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(43) | Input CLKB_PADN is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(44) | Input CLKC is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(45) | Input CLKC_PAD is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(46) | Input CLKC_PADP is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(47) | Input CLKC_PADN is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(49) | Input LPXIN is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(50) | Input MAC_CLK is unused @W:CL246 : coreapb3.v(54) | Input port bits 23 to 12 of PADDR[23:0] are unused @W:CL159 : coreapb3.v(52) | Input PRESETN is unused @W:CL159 : coreapb3.v(53) | Input PCLK is unused @W:CL159 : coreapb3.v(84) | Input PRDATAS1 is unused @W:CL159 : coreapb3.v(85) | Input PRDATAS2 is unused @W:CL159 : coreapb3.v(86) | Input PRDATAS3 is unused @W:CL159 : coreapb3.v(87) | Input PRDATAS4 is unused @W:CL159 : coreapb3.v(88) | Input PRDATAS5 is unused @W:CL159 : coreapb3.v(89) | Input PRDATAS6 is unused @W:CL159 : coreapb3.v(90) | Input PRDATAS7 is unused @W:CL159 : coreapb3.v(91) | Input PRDATAS8 is unused @W:CL159 : coreapb3.v(92) | Input PRDATAS9 is unused @W:CL159 : coreapb3.v(93) | Input PRDATAS10 is unused @W:CL159 : coreapb3.v(94) | Input PRDATAS11 is unused @W:CL159 : coreapb3.v(95) | Input PRDATAS12 is unused @W:CL159 : coreapb3.v(96) | Input PRDATAS13 is unused @W:CL159 : coreapb3.v(97) | Input PRDATAS14 is unused @W:CL159 : coreapb3.v(98) | Input PRDATAS15 is unused @W:CL159 : coreapb3.v(100) | Input PREADYS1 is unused @W:CL159 : coreapb3.v(101) | Input PREADYS2 is unused @W:CL159 : coreapb3.v(102) | Input PREADYS3 is unused @W:CL159 : coreapb3.v(103) | Input PREADYS4 is unused @W:CL159 : coreapb3.v(104) | Input PREADYS5 is unused @W:CL159 : coreapb3.v(105) | Input PREADYS6 is unused @W:CL159 : coreapb3.v(106) | Input PREADYS7 is unused @W:CL159 : coreapb3.v(107) | Input PREADYS8 is unused @W:CL159 : coreapb3.v(108) | Input PREADYS9 is unused @W:CL159 : coreapb3.v(109) | Input PREADYS10 is unused @W:CL159 : coreapb3.v(110) | Input PREADYS11 is unused @W:CL159 : coreapb3.v(111) | Input PREADYS12 is unused @W:CL159 : coreapb3.v(112) | Input PREADYS13 is unused @W:CL159 : coreapb3.v(113) | Input PREADYS14 is unused @W:CL159 : coreapb3.v(114) | Input PREADYS15 is unused @W:CL159 : coreapb3.v(116) | Input PSLVERRS1 is unused @W:CL159 : coreapb3.v(117) | Input PSLVERRS2 is unused @W:CL159 : coreapb3.v(118) | Input PSLVERRS3 is unused @W:CL159 : coreapb3.v(119) | Input PSLVERRS4 is unused @W:CL159 : coreapb3.v(120) | Input PSLVERRS5 is unused @W:CL159 : coreapb3.v(121) | Input PSLVERRS6 is unused @W:CL159 : coreapb3.v(122) | Input PSLVERRS7 is unused @W:CL159 : coreapb3.v(123) | Input PSLVERRS8 is unused @W:CL159 : coreapb3.v(124) | Input PSLVERRS9 is unused @W:CL159 : coreapb3.v(125) | Input PSLVERRS10 is unused @W:CL159 : coreapb3.v(126) | Input PSLVERRS11 is unused @W:CL159 : coreapb3.v(127) | Input PSLVERRS12 is unused @W:CL159 : coreapb3.v(128) | Input PSLVERRS13 is unused @W:CL159 : coreapb3.v(129) | Input PSLVERRS14 is unused @W:CL159 : coreapb3.v(130) | Input PSLVERRS15 is unused @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Dec 29 18:17:06 2011 ###########################################################] Synopsys Actel Technology Mapper, Version mapact, Build 023R, Built Sep 29 2010 09:29:00 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved Product Version E-2010.09A-1 @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled @W:MO111 : mss_top_tmp_mss_ccc_0_mss_ccc.v(62) | tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module mss_top_tmp_MSS_CCC_0_MSS_CCC) @W:MO111 : mss_top_tmp_mss_ccc_0_mss_ccc.v(63) | tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module mss_top_tmp_MSS_CCC_0_MSS_CCC) @W:MO111 : mss_top_tmp_mss_ccc_0_mss_ccc.v(64) | tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module mss_top_tmp_MSS_CCC_0_MSS_CCC) Available hyper_sources - for debug and ip models None Found @W: : mss_top_tmp_mss_ccc_0_mss_ccc.v(78) | Net SPI_0/PCLK appears to be a clock source which was not identfied. Assuming default frequency. @W: : spi_master.v(218) | Net SPI_0/ucorespi_sfr/genblk6\.genblk7\.u_master/un3_busy appears to be a clock source which was not identfied. Assuming default frequency. Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB) @N: : spi_master.v(85) | Found counter in view:work.spi_master(verilog) inst clock_count[7:0] @N:MO106 : spi_master.v(217) | Found ROM, 'sck_enable', 11 words by 1 bits @W:MO161 : spi_master.v(436) | Register bit rx_shift_reg[0] is always 0, optimizing ... @W:MO161 : spi_master.v(481) | Register bit rx_data_reg[0] is always 0, optimizing ... @W:MO161 : spi_master.v(436) | Register bit rx_shift_reg[1] is always 0, optimizing ... @W:MO161 : spi_master.v(481) | Register bit rx_data_reg[1] is always 0, optimizing ... @W:MO161 : spi_master.v(436) | Register bit rx_shift_reg[2] is always 0, optimizing ... @W:MO161 : spi_master.v(481) | Register bit rx_data_reg[2] is always 0, optimizing ... @W:MO161 : spi_master.v(436) | Register bit rx_shift_reg[3] is always 0, optimizing ... @W:MO161 : spi_master.v(481) | Register bit rx_data_reg[3] is always 0, optimizing ... @W:MO161 : spi_master.v(436) | Register bit rx_shift_reg[4] is always 0, optimizing ... @W:MO161 : spi_master.v(481) | Register bit rx_data_reg[4] is always 0, optimizing ... @W:MO161 : spi_master.v(436) | Register bit rx_shift_reg[5] is always 0, optimizing ... @W:MO161 : spi_master.v(481) | Register bit rx_data_reg[5] is always 0, optimizing ... @W:MO161 : spi_master.v(436) | Register bit rx_shift_reg[6] is always 0, optimizing ... @W:MO161 : spi_master.v(481) | Register bit rx_data_reg[6] is always 0, optimizing ... @W:MO161 : spi_master.v(436) | Register bit rx_shift_reg[7] is always 0, optimizing ... @W:MO161 : spi_master.v(481) | Register bit rx_data_reg[7] is always 0, optimizing ... @N:BN116 : spi_master.v(421) | Removing sequential instance rx_shift_enable2 of view:PrimLib.dffr(prim) because there are no references to its outputs @N: : spi_slave.v(143) | Found counter in view:work.spi_slave(verilog) inst count[5:0] Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 57MB) @N:BN116 : spi_master.v(457) | Removing sequential instance SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.tx_shift_reg[7] of view:PrimLib.dffr(prim) because there are no references to its outputs @N:BN116 : spi_master.v(457) | Removing sequential instance SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.tx_shift_reg[6] of view:PrimLib.dffr(prim) because there are no references to its outputs @N:BN116 : spi_master.v(457) | Removing sequential instance SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.tx_shift_reg[5] of view:PrimLib.dffr(prim) because there are no references to its outputs @N:BN116 : spi_master.v(457) | Removing sequential instance SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.tx_shift_reg[4] of view:PrimLib.dffr(prim) because there are no references to its outputs @N:BN116 : spi_master.v(457) | Removing sequential instance SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.tx_shift_reg[3] of view:PrimLib.dffr(prim) because there are no references to its outputs @N:BN116 : spi_master.v(457) | Removing sequential instance SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.tx_shift_reg[2] of view:PrimLib.dffr(prim) because there are no references to its outputs @N:BN116 : spi_master.v(457) | Removing sequential instance SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.tx_shift_reg[1] of view:PrimLib.dffr(prim) because there are no references to its outputs @N:BN116 : spi_master.v(457) | Removing sequential instance SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.tx_shift_reg[0] of view:PrimLib.dffr(prim) because there are no references to its outputs @N:BN116 : spi_master.v(161) | Removing sequential instance SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.tsck of view:PrimLib.dffr(prim) because there are no references to its outputs @N:BN116 : spi_master.v(457) | Removing sequential instance SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.mosi of view:PrimLib.dffr(prim) because there are no references to its outputs Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 57MB) Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 58MB) Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 58MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 58MB) Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 59MB) High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes ---------------------------------------------------------------------------------------------------------- mss_top_0.MSS_ADLIB_INST / M2FRESETn 151 : 151 asynchronous set/reset SPI_0.ucorespi_sfr.control_reg[5] / Q 55 SPI_0.ucorespi_sfr.genblk10.genblk11.u_slave.i_ss / Q 37 SPI_0.ucorespi_sfr.genblk10.genblk11.u_slave.un1_i_ss_1 / Y 32 SPI_0.ucorespi_sfr.tx_reg_we / Y 37 SPI_0.ucorespi_sfr.rx_reg_re / Y 29 SPI_0.ucorespi_sfr.data_out_1 / Y 32 SPI_0.ucorespi_sfr.enable_master / Y 47 SPI_0.ucorespi_sfr.genblk10.genblk11.u_slave.rx_data_reg_0_sqmuxa / Y 32 ========================================================================================================== @N:FP130 : | Promoting Net SPI_0.ucorespi_sfr.control_reg[5] on CLKINT I_72 @N:FP130 : | Promoting Net SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.un3_busy on CLKINT SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.un3_busy_inferred_clock Replicating Combinational Instance SPI_0.ucorespi_sfr.genblk10.genblk11.u_slave.rx_data_reg_0_sqmuxa, fanout 32 segments 2 Replicating Combinational Instance SPI_0.ucorespi_sfr.enable_master, fanout 47 segments 2 Replicating Combinational Instance SPI_0.ucorespi_sfr.data_out_1, fanout 32 segments 2 Replicating Combinational Instance SPI_0.ucorespi_sfr.rx_reg_re, fanout 30 segments 2 Replicating Combinational Instance SPI_0.ucorespi_sfr.tx_reg_we, fanout 37 segments 2 Replicating Combinational Instance SPI_0.ucorespi_sfr.genblk10.genblk11.u_slave.un1_i_ss_1, fanout 32 segments 2 Replicating Sequential Instance SPI_0.ucorespi_sfr.genblk10.genblk11.u_slave.i_ss, fanout 38 segments 2 Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 60MB peak: 61MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 60MB peak: 61MB) Added 0 Buffers Added 7 Cells via replication Added 1 Sequential Cells via replication Added 6 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 60MB peak: 61MB) Writing Analyst data base F:\ac356\A2F_AC356_DF2\A2F_AC356_DF\FTDI\FTDI_SPI_HW\synthesis\top_level.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:00s; Memory used current: 60MB peak: 61MB) Writing EDIF Netlist and constraint files E-2010.09A-1 Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:01s; Memory used current: 60MB peak: 61MB) @W:MT246 : mss_top.v(421) | Blackbox TRIBUFF_MSS is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : mss_top.v(418) | Blackbox MSSINT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : mss_top.v(262) | Blackbox MSS_APB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : mss_top_tmp_mss_ccc_0_mss_ccc.v(96) | Blackbox MSS_XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock spi_master|un3_busy_inferred_clock with period 1000.00ns. A user-defined clock should be declared on object "n:SPI_0.ucorespi_sfr.genblk6.genblk7.u_master.un3_busy" @W:MT420 : | Found inferred clock mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock with period 1000.00ns. A user-defined clock should be declared on object "n:mss_top_0_FAB_CLK" ##### START OF TIMING REPORT #####[ # Timing Report written on Thu Dec 29 18:17:09 2011 # Top view: top_level Library name: smartfusion Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree ) Requested Frequency: 1.0 MHz Wire load mode: top Wire load model: smartfusion Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: 988.418 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock 1.0 MHz 93.3 MHz 1000.000 10.718 989.282 inferred Inferred_clkgroup_0 spi_master|un3_busy_inferred_clock 1.0 MHz NA 1000.000 NA NA inferred Inferred_clkgroup_1 System 1.0 MHz 86.3 MHz 1000.000 11.582 988.418 system system_clkgroup ======================================================================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ System System | 1000.000 988.418 | No paths - | No paths - | No paths - System mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock | 1000.000 991.180 | No paths - | No paths - | No paths - mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock System | 1000.000 990.980 | No paths - | No paths - | No paths - mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock | 1000.000 989.282 | No paths - | No paths - | No paths - mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock spi_master|un3_busy_inferred_clock | No paths - | No paths - | Diff grp - | No paths - spi_master|un3_busy_inferred_clock mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock | No paths - | No paths - | No paths - | Diff grp - ======================================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.state[0] mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock DFN1C0 Q state[0] 0.737 989.282 SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.state[3] mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock DFN1C0 Q state[3] 0.580 989.473 SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.state[1] mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock DFN1C0 Q state[1] 0.737 989.710 SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.state[2] mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock DFN1C0 Q state[2] 0.737 989.842 SPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.count[0] mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock DFN1E1C0 Q count[0] 0.580 990.662 SPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.count[3] mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock DFN1E1C0 Q count[3] 0.580 990.745 SPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.count[1] mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock DFN1E1C0 Q count[1] 0.580 990.923 SPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.count[4] mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock DFN1E1C0 Q count[4] 0.580 990.971 SPI_0.ucorespi_sfr.control_reg[6] mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock DFN1E1C0 Q control_reg[6] 0.737 990.980 SPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.count[2] mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock DFN1E1C0 Q count[2] 0.580 991.149 ========================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.count[0] mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock DFN1E1C0 E counte 999.392 990.662 SPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.count[1] mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock DFN1E1C0 E counte 999.392 990.662 SPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.count[2] mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock DFN1E1C0 E counte 999.392 990.662 SPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.count[3] mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock DFN1E1C0 E counte 999.392 990.662 SPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.count[4] mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock DFN1E1C0 E counte 999.392 990.662 SPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.count[5] mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock DFN1E1C0 E counte 999.392 990.662 mss_top_0.MSS_ADLIB_INST mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock MSS_APB MSSPRDATA[1] control_reg_RNIOTIEA[1] 1000.000 990.980 SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.rx_data_waiting mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock DFN1E0C0 E un1_rx_data_waiting7 999.392 991.074 SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.rx_error_i mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock DFN1E0C0 E un1_rx_reg_re_3 999.392 991.074 mss_top_0.MSS_ADLIB_INST mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock MSS_APB MSSPRDATA[3] control_reg_RNIS5T9A[3] 1000.000 991.382 =================================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 999.461 - Propagation time: 10.179 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 989.282 Number of logic level(s): 7 Starting point: SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.state[0] / Q Ending point: SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.tss / D The start point is clocked by mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by mss_top_tmp_MSS_CCC_0_MSS_CCC|mss_top_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------- SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.state[0] DFN1C0 Q Out 0.737 0.737 - state[0] Net - - 1.776 - 11 SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.state_RNIHRL2_0[3] OR2B B In - 2.513 - SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.state_RNIHRL2_0[3] OR2B Y Out 0.627 3.140 - clear_tx_data_ready25_1 Net - - 1.184 - 4 SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.state_RNI2NB5[2] OR2 A In - 4.324 - SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.state_RNI2NB5[2] OR2 Y Out 0.363 4.687 - clear_tx_data_ready25 Net - - 0.806 - 3 SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.state_RNINHDD[2] NOR3C C In - 5.494 - SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.state_RNINHDD[2] NOR3C Y Out 0.666 6.159 - un3_busy_3 Net - - 0.322 - 1 SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.state_RNIVDS21[0] NOR3B A In - 6.481 - SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.state_RNIVDS21[0] NOR3B Y Out 0.666 7.146 - un3_busy_i Net - - 0.322 - 1 SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.state_RNIVDS21_0[0] CLKINT A In - 7.468 - SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.state_RNIVDS21_0[0] CLKINT Y Out 0.174 7.642 - state_RNIVDS21_0[0] Net - - 0.640 - 5 SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.tss_RNO_0 NOR3 C In - 8.281 - SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.tss_RNO_0 NOR3 Y Out 0.683 8.964 - un3_busy_2 Net - - 0.322 - 1 SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.tss_RNO MX2C B In - 9.286 - SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.tss_RNO MX2C Y Out 0.572 9.858 - i_ss_1 Net - - 0.322 - 1 SPI_0.ucorespi_sfr.genblk6\.genblk7\.u_master.tss DFN1P0 D In - 10.179 - ================================================================================================================================== Total path delay (propagation time + setup) of 10.718 is 5.026(46.9%) logic and 5.692(53.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------- mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPSEL mss_top_0_MSS_MASTER_APB_PSELx 0.000 988.418 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPADDR[10] mss_top_0_MSS_MASTER_APB_PADDR_\[10\] 0.000 988.429 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPENABLE CoreAPB3_0_APBmslave0_PENABLE 0.000 988.455 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPADDR[11] mss_top_0_MSS_MASTER_APB_PADDR_\[11\] 0.000 988.528 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPADDR[9] mss_top_0_MSS_MASTER_APB_PADDR_\[9\] 0.000 988.568 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPADDR[8] mss_top_0_MSS_MASTER_APB_PADDR_\[8\] 0.000 988.570 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPADDR[2] mss_top_0_MSS_MASTER_APB_PADDR_\[2\] 0.000 988.902 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPADDR[3] mss_top_0_MSS_MASTER_APB_PADDR_\[3\] 0.000 989.041 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPWRITE CoreAPB3_0_APBmslave0_PWRITE 0.000 990.469 mss_top_0.MSS_CCC_0.I_XTLOSC System MSS_XTLOSC CLKOUT N_CLKA_XTLOSC 0.000 994.169 ============================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------- mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPRDATA[7] control_reg_RNI314V9[7] 1000.000 988.418 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPRDATA[0] control_reg_RNIG0K0A[0] 1000.000 988.856 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPRDATA[1] control_reg_RNIOTIEA[1] 1000.000 988.856 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPRDATA[2] control_reg_RNI3HHFA[2] 1000.000 988.856 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPRDATA[3] control_reg_RNIS5T9A[3] 1000.000 988.856 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPRDATA[10] rx_data_reg_RNIKPLA4[21] 1000.000 989.145 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPRDATA[11] rx_data_reg_RNIKPLA4[20] 1000.000 989.145 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPRDATA[12] rx_data_reg_RNIT1NA4[19] 1000.000 989.145 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPRDATA[13] rx_data_reg_RNIT1NA4[18] 1000.000 989.145 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPRDATA[14] rx_data_reg_RNIT1NA4[17] 1000.000 989.145 ========================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 1000.000 - Propagation time: 11.582 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (critical) : 988.418 Number of logic level(s): 7 Starting point: mss_top_0.MSS_ADLIB_INST / MSSPSEL Ending point: mss_top_0.MSS_ADLIB_INST / MSSPRDATA[7] The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- mss_top_0.MSS_ADLIB_INST MSS_APB MSSPSEL Out 0.000 0.000 - mss_top_0_MSS_MASTER_APB_PSELx Net - - 0.322 - 1 SPI_0.cpu_re_1_2 NOR2A A In - 0.322 - SPI_0.cpu_re_1_2 NOR2A Y Out 0.516 0.838 - cpu_re_1_2 Net - - 0.322 - 1 SPI_0.cpu_re_1 OR3C C In - 1.159 - SPI_0.cpu_re_1 OR3C Y Out 0.666 1.825 - cpu_re_1 Net - - 1.708 - 10 SPI_0.ucorespi_sfr.rx_reg_re OR3 B In - 3.533 - SPI_0.ucorespi_sfr.rx_reg_re OR3 Y Out 0.714 4.247 - rx_reg_re Net - - 2.127 - 15 SPI_0.ucorespi_sfr.control_reg_RNIP02Q1[5] NOR2 A In - 6.375 - SPI_0.ucorespi_sfr.control_reg_RNIP02Q1[5] NOR2 Y Out 0.507 6.882 - data_out_1 Net - - 2.172 - 16 SPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.rx_data_reg_RNIFHI12_0[7] OR2B B In - 9.055 - SPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.rx_data_reg_RNIFHI12_0[7] OR2B Y Out 0.516 9.571 - i_rx_data_reg_1_m[7] Net - - 0.322 - 1 SPI_0.ucorespi_sfr.i_enable_spi_RNIJCTV3 AOI1B C In - 9.892 - SPI_0.ucorespi_sfr.i_enable_spi_RNIJCTV3 AOI1B Y Out 0.405 10.297 - data_out_iv_1[7] Net - - 0.322 - 1 SPI_0.ucorespi_sfr.control_reg_RNI314V9[7] OR3C C In - 10.619 - SPI_0.ucorespi_sfr.control_reg_RNI314V9[7] OR3C Y Out 0.641 11.260 - control_reg_RNI314V9[7] Net - - 0.322 - 1 mss_top_0.MSS_ADLIB_INST MSS_APB MSSPRDATA[7] In - 11.582 - ================================================================================================================================================== Total path delay (propagation time + setup) of 11.582 is 3.966(34.2%) logic and 7.616(65.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Target Part: A2F500M3G_FBGA256_Std Report for cell top_level.verilog Core Cell usage: cell count area count*area AO1A 2 1.0 2.0 AO1B 24 1.0 24.0 AOI1B 14 1.0 14.0 AX1C 4 1.0 4.0 AX1E 2 1.0 2.0 CLKINT 2 0.0 0.0 GND 7 0.0 0.0 INV 2 1.0 2.0 MSSINT 1 0.0 0.0 MSS_APB 1 0.0 0.0 MSS_CCC 1 0.0 0.0 MX2 68 1.0 68.0 MX2C 4 1.0 4.0 NOR2 15 1.0 15.0 NOR2A 12 1.0 12.0 NOR2B 25 1.0 25.0 NOR3 5 1.0 5.0 NOR3A 5 1.0 5.0 NOR3B 4 1.0 4.0 NOR3C 6 1.0 6.0 OA1A 2 1.0 2.0 OA1C 1 1.0 1.0 OAI1 2 1.0 2.0 OR2 9 1.0 9.0 OR2A 14 1.0 14.0 OR2B 21 1.0 21.0 OR3 3 1.0 3.0 OR3A 6 1.0 6.0 OR3B 24 1.0 24.0 OR3C 29 1.0 29.0 VCC 7 0.0 0.0 XA1B 1 1.0 1.0 XA1C 1 1.0 1.0 XNOR2 3 1.0 3.0 XO1A 1 1.0 1.0 XOR2 5 1.0 5.0 XOR3 1 1.0 1.0 DFN1C0 11 1.0 11.0 DFN1E0C0 46 1.0 46.0 DFN1E0P0 3 1.0 3.0 DFN1E1C0 89 1.0 89.0 DFN1E1P0 1 1.0 1.0 DFN1P0 2 1.0 2.0 DLN0 4 1.0 4.0 ----- ---------- TOTAL 490 471.0 IO Cell usage: cell count BIBUF_MSS 21 BIBUF_OPEND_MSS 4 INBUF 3 INBUF_MSS 9 MSS_XTLOSC 1 OUTBUF 1 OUTBUF_MSS 40 TRIBUFF_MSS 2 ----- TOTAL 81 Core Cells : 471 of 11520 (4%) IO Cells : 81 RAM/ROM Usage Summary Block Rams : 0 of 24 (0%) Mapper successful! Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Dec 29 18:17:09 2011 ###########################################################]