#Build: Synplify Pro D-2009.12A, Build 040R, Jan 20 2010 #install: C:\Actel\Libero_v9.0\Synopsys\synplify_D200912A #OS: Windows XP 5.1 #Hostname: WXPL-CHERUKUPAL #Implementation: synthesis_1 #Tue Aug 17 14:54:00 2010 $ Running Identify Instrumentor. See log file: @N: : identify.log | #Tue Aug 17 14:54:00 2010 $ Start of Compile #Tue Aug 17 14:54:05 2010 Synopsys Verilog Compiler, version comp475rc, Build 060R, built Jan 15 2010 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved @I::"C:\Actel\Libero_v9.0\Synopsys\synplify_D200912A\lib\proasic\fusion.v" @I::"D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\synthesis\synthesis_1\instr_sources\Actel\SmartFusionMSS\MSS\2.2.101\mss_comps.v" @I::"D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\synthesis\synthesis_1\instr_sources\work\mss_top\MSS_CCC_0\mss_top_tmp_MSS_CCC_0_MSS_CCC.v" @I::"D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\synthesis\synthesis_1\instr_sources\work\mss_top\mss_top.v" @I::"D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\synthesis\synthesis_1\instr_sources\Actel\DirectCore\CORESPI\3.0.156\rtl\vlog\core\spi_master.v" @I::"D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\synthesis\synthesis_1\instr_sources\Actel\DirectCore\CORESPI\3.0.156\rtl\vlog\core\spi_slave.v" @I::"D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\synthesis\synthesis_1\instr_sources\Actel\DirectCore\CORESPI\3.0.156\rtl\vlog\core\corespi_sfr.v" @I::"D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\synthesis\synthesis_1\instr_sources\Actel\DirectCore\CORESPI\3.0.156\rtl\vlog\core\corespi.v" @I::"D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\synthesis\synthesis_1\instr_sources\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3_muxptob3.v" @I::"D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\synthesis\synthesis_1\instr_sources\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v" @I::"D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\synthesis\synthesis_1\instr_sources\work\top_level\top_level.v" @I::"D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\synthesis\synthesis_1\instr_sources\syn_dics.v" @N:CG347 : syn_dics.v(119) | Read parallel_case directive @N:CG347 : syn_dics.v(307) | Read parallel_case directive @N:CG347 : syn_dics.v(344) | Read parallel_case directive @N:CG334 : syn_dics.v(585) | Read directive translate_off @N:CG333 : syn_dics.v(588) | Read directive translate_on @N:CG347 : syn_dics.v(633) | Read parallel_case directive @N:CG347 : syn_dics.v(650) | Read parallel_case directive @N:CG334 : syn_dics.v(841) | Read directive translate_off @N:CG333 : syn_dics.v(844) | Read directive translate_on @N:CG347 : syn_dics.v(983) | Read parallel_case directive @N:CG347 : syn_dics.v(1043) | Read parallel_case directive Verilog syntax check successful! File D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\synthesis\synthesis_1\instr_sources\.filemap changed - recompiling File D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\synthesis\synthesis_1\instr_sources\Actel\DirectCore\CORESPI\3.0.156\rtl\vlog\core\spi_slave.v changed - recompiling File D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\synthesis\synthesis_1\instr_sources\Actel\DirectCore\CORESPI\3.0.156\rtl\vlog\core\corespi_sfr.v changed - recompiling File D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\synthesis\synthesis_1\instr_sources\Actel\DirectCore\CORESPI\3.0.156\rtl\vlog\core\corespi.v changed - recompiling File D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\synthesis\synthesis_1\instr_sources\work\top_level\top_level.v changed - recompiling File D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\synthesis\synthesis_1\instr_sources\syn_dics.v changed - recompiling Selecting top level module top_level @N:CG364 : coreapb3_muxptob3.v(30) | Synthesizing module COREAPB3_MUXPTOB3 @N:CG364 : coreapb3.v(30) | Synthesizing module CoreAPB3 APB_DWIDTH=6'b001000 RANGESIZE=21'b000000000000100000000 IADDR_ENABLE=1'b0 APBSLOT0ENABLE=1'b1 APBSLOT1ENABLE=1'b0 APBSLOT2ENABLE=1'b0 APBSLOT3ENABLE=1'b0 APBSLOT4ENABLE=1'b0 APBSLOT5ENABLE=1'b0 APBSLOT6ENABLE=1'b0 APBSLOT7ENABLE=1'b0 APBSLOT8ENABLE=1'b0 APBSLOT9ENABLE=1'b0 APBSLOT10ENABLE=1'b0 APBSLOT11ENABLE=1'b0 APBSLOT12ENABLE=1'b0 APBSLOT13ENABLE=1'b0 APBSLOT14ENABLE=1'b0 APBSLOT15ENABLE=1'b0 RANGEBITS=32'b00000000000000000000000000001000 RANGEBITS_LT16=32'b00000000000000000000000000001000 IADDR_31_24_8B_A=8'b00001100 IADDR_23_16_8B_A=8'b00001000 IADDR_15_8_8B_A=8'b00000100 IADDR_7_0_8B_A=8'b00000000 IADDR_31_16_16B_A=8'b00000100 IADDR_15_0_16B_A=8'b00000000 IADDR_31_0_32B_A=8'b00000000 SL0=16'b0000000000000001 SL1=16'b0000000000000000 SL2=16'b0000000000000000 SL3=16'b0000000000000000 SL4=16'b0000000000000000 SL5=16'b0000000000000000 SL6=16'b0000000000000000 SL7=16'b0000000000000000 SL8=16'b0000000000000000 SL9=16'b0000000000000000 SL10=16'b0000000000000000 SL11=16'b0000000000000000 SL12=16'b0000000000000000 SL13=16'b0000000000000000 SL14=16'b0000000000000000 SL15=16'b0000000000000000 Generated name = CoreAPB3_Z1 @N:CG364 : fusion.v(2043) | Synthesizing module VCC @N:CG364 : mss_comps.v(67) | Synthesizing module BIBUF_MSS @N:CG364 : mss_comps.v(23) | Synthesizing module INBUF_MSS @N:CG364 : mss_comps.v(37) | Synthesizing module OUTBUF_MSS @N:CG364 : mss_comps.v(85) | Synthesizing module BIBUF_OPEND_MSS @N:CG364 : mss_comps.v(51) | Synthesizing module TRIBUFF_MSS @N:CG364 : fusion.v(1224) | Synthesizing module GND @N:CG364 : mss_comps.v(151) | Synthesizing module MSS_CCC @N:CG364 : mss_comps.v(1) | Synthesizing module MSS_XTLOSC @N:CG364 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(5) | Synthesizing module mss_top_tmp_MSS_CCC_0_MSS_CCC @N:CG364 : mss_comps.v(680) | Synthesizing module MSS_APB @N:CG364 : mss_comps.v(145) | Synthesizing module MSSINT @N:CG364 : mss_top.v(5) | Synthesizing module mss_top @N:CG364 : syn_dics.v(1379) | Synthesizing module ldic7_0 @N:CG364 : corespi_sfr.v(19) | Synthesizing module CORESPI_SFR USE_MASTER=32'b00000000000000000000000000000000 USE_SLAVE=32'b00000000000000000000000000000001 Generated name = CORESPI_SFR_0s_1s @N:CG364 : syn_dics.v(1389) | Synthesizing module ldic8_0 @N:CG364 : spi_slave.v(18) | Synthesizing module spi_slave @N:CG364 : syn_dics.v(1354) | Synthesizing module ldic6_0 @N:CG364 : corespi.v(13) | Synthesizing module CORESPI FAMILY=32'b00000000000000000000000000001111 USE_MASTER=32'b00000000000000000000000000000000 USE_SLAVE=32'b00000000000000000000000000000001 Generated name = CORESPI_15s_0s_1s @N:CG364 : fusion.v(3086) | Synthesizing module UJTAG @N:CG364 : syn_dics.v(31) | Synthesizing module jtag_interface @N:CG364 : syn_dics.v(162) | Synthesizing module b16_Rcmi_qlx9_yHpm7y @N:CG364 : syn_dics.v(1) | Synthesizing module b9_ORbIwXaEF @N:CG364 : syn_dics.v(213) | Synthesizing module comm_block @N:CG364 : syn_dics.v(1344) | Synthesizing module ldic1_0 @N:CG364 : syn_dics.v(1138) | Synthesizing module b8_nR_ymqrG b7_nUTZIuY=32'b00000000000000000000000000000111 b8_Nr4_94ip=32'b00000000000000000000000000000101 b8_Nr4_a8Up=5'b00000 Generated name = b8_nR_ymqrG_7s_5s_0 @N:CG364 : syn_dics.v(517) | Synthesizing module b7_OCByLXC b7_nUTZIuY=32'b00000000000000000000000000000111 b13_Ocm0f_TkA86EZ=4'b0000 b13_Ocm0f_A7A86Rv=4'b0001 b13_Ocm0f_HiP76Rv=4'b0010 b13_Ocm0f_p5BT6Rv=4'b0011 b12_Ocm0f_Q7B8qG=4'b0100 b17_Ocm0f_TkQcUqbQVN5=4'b1101 b8_Nr4_94ip=32'b00000000000000000000000000000101 b8_Nr4_a8Up=5'b00000 b7_Nr4_Yh8=5'b00001 b9_Nr4_YoSpQ=5'b00010 b7_Nr4_aj9=5'b11101 b22_Nr4_Yh8_K58DYdFN5_avNJ=5'b00100 b22_Nr4_Yh8_K58DYdFN5_EK2w=5'b01000 b17_Nr4_Yh8_CTNEmG_rg=5'b10000 b9_Vz2n_4X6U=5'b00000 b9_Vz2n_O64Y=5'b00001 b11_Vz2n_1V6Qca=5'b00010 b9_Vz2n_AT6B=5'b00100 b8_Vz2n_48l=5'b01000 b10_c70EHoH6Cp=7'b0000001 Generated name = b7_OCByLXC_Z2 @N:CG364 : syn_dics.v(319) | Synthesizing module b8_1LbcQDr1 @N:CG364 : syn_dics.v(404) | Synthesizing module b9_O2yyf_fG2 @N:CG364 : syn_dics.v(411) | Synthesizing module b14_CRGcTCua_eH4_s @N:CG364 : syn_dics.v(422) | Synthesizing module b11_PSyil9s1fkT @N:CG364 : syn_dics.v(375) | Synthesizing module b5_nvmFL b5_2Rs0m=32'b00000000000000000000000000001100 Generated name = b5_nvmFL_12s @N:CG364 : syn_dics.v(470) | Synthesizing module b7_PfFzrNY @N:CG364 : syn_dics.v(1251) | Synthesizing module b3_12m @N:CG364 : syn_dics.v(925) | Synthesizing module b12_nvmFL_la1xyH @N:CG364 : syn_dics.v(998) | Synthesizing module b7_PLF_6lN @N:CG364 : syn_dics.v(1058) | Synthesizing module b3_uKr @N:CG364 : syn_dics.v(781) | Synthesizing module ram_block @N:CL134 : syn_dics.v(796) | Found RAM mem, depth=128, width=14 @N:CG364 : syn_dics.v(726) | Synthesizing module b12_OFWNT9_wMeEd b5_2Rs0m=32'b00000000000000000000000000000111 Generated name = b12_OFWNT9_wMeEd_7s @N:CG364 : syn_dics.v(808) | Synthesizing module b7_OFWNT9s @N:CG364 : syn_dics.v(1405) | Synthesizing module iice_0 @N:CG364 : top_level.v(5) | Synthesizing module top_level @W:CL246 : syn_dics.v(481) | Input port bits 4 to 14 of b9_SLyy_NrGD[0:14] are unused @N:CL201 : syn_dics.v(617) | Trying to extract state machine for register b13_nAzGfFM_sLsv3 Extracted state machine for register b13_nAzGfFM_sLsv3 State machine has 6 reachable states with original encodings of: 0000 0001 0010 0011 0100 1101 @W:CL246 : corespi.v(41) | Input port bits 1 to 0 of PADDR[3:0] are unused @W:CL159 : corespi_sfr.v(36) | Input m_miso is unused @W:CL157 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(62) | *Output RCOSC_CLKOUT has undriven bits - a simulation mismatch is possible @W:CL157 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(63) | *Output MAINXIN_CLKOUT has undriven bits - a simulation mismatch is possible @W:CL157 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(64) | *Output LPXIN_CLKOUT has undriven bits - a simulation mismatch is possible @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(36) | Input CLKA is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(37) | Input CLKA_PAD is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(38) | Input CLKA_PADP is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(39) | Input CLKA_PADN is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(40) | Input CLKB is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(41) | Input CLKB_PAD is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(42) | Input CLKB_PADP is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(43) | Input CLKB_PADN is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(44) | Input CLKC is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(45) | Input CLKC_PAD is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(46) | Input CLKC_PADP is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(47) | Input CLKC_PADN is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(49) | Input LPXIN is unused @W:CL159 : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(50) | Input MAC_CLK is unused @W:CL246 : coreapb3.v(54) | Input port bits 23 to 12 of PADDR[23:0] are unused @W:CL159 : coreapb3.v(52) | Input PRESETN is unused @W:CL159 : coreapb3.v(53) | Input PCLK is unused @W:CL159 : coreapb3.v(84) | Input PRDATAS1 is unused @W:CL159 : coreapb3.v(85) | Input PRDATAS2 is unused @W:CL159 : coreapb3.v(86) | Input PRDATAS3 is unused @W:CL159 : coreapb3.v(87) | Input PRDATAS4 is unused @W:CL159 : coreapb3.v(88) | Input PRDATAS5 is unused @W:CL159 : coreapb3.v(89) | Input PRDATAS6 is unused @W:CL159 : coreapb3.v(90) | Input PRDATAS7 is unused @W:CL159 : coreapb3.v(91) | Input PRDATAS8 is unused @W:CL159 : coreapb3.v(92) | Input PRDATAS9 is unused @W:CL159 : coreapb3.v(93) | Input PRDATAS10 is unused @W:CL159 : coreapb3.v(94) | Input PRDATAS11 is unused @W:CL159 : coreapb3.v(95) | Input PRDATAS12 is unused @W:CL159 : coreapb3.v(96) | Input PRDATAS13 is unused @W:CL159 : coreapb3.v(97) | Input PRDATAS14 is unused @W:CL159 : coreapb3.v(98) | Input PRDATAS15 is unused @W:CL159 : coreapb3.v(100) | Input PREADYS1 is unused @W:CL159 : coreapb3.v(101) | Input PREADYS2 is unused @W:CL159 : coreapb3.v(102) | Input PREADYS3 is unused @W:CL159 : coreapb3.v(103) | Input PREADYS4 is unused @W:CL159 : coreapb3.v(104) | Input PREADYS5 is unused @W:CL159 : coreapb3.v(105) | Input PREADYS6 is unused @W:CL159 : coreapb3.v(106) | Input PREADYS7 is unused @W:CL159 : coreapb3.v(107) | Input PREADYS8 is unused @W:CL159 : coreapb3.v(108) | Input PREADYS9 is unused @W:CL159 : coreapb3.v(109) | Input PREADYS10 is unused @W:CL159 : coreapb3.v(110) | Input PREADYS11 is unused @W:CL159 : coreapb3.v(111) | Input PREADYS12 is unused @W:CL159 : coreapb3.v(112) | Input PREADYS13 is unused @W:CL159 : coreapb3.v(113) | Input PREADYS14 is unused @W:CL159 : coreapb3.v(114) | Input PREADYS15 is unused @W:CL159 : coreapb3.v(116) | Input PSLVERRS1 is unused @W:CL159 : coreapb3.v(117) | Input PSLVERRS2 is unused @W:CL159 : coreapb3.v(118) | Input PSLVERRS3 is unused @W:CL159 : coreapb3.v(119) | Input PSLVERRS4 is unused @W:CL159 : coreapb3.v(120) | Input PSLVERRS5 is unused @W:CL159 : coreapb3.v(121) | Input PSLVERRS6 is unused @W:CL159 : coreapb3.v(122) | Input PSLVERRS7 is unused @W:CL159 : coreapb3.v(123) | Input PSLVERRS8 is unused @W:CL159 : coreapb3.v(124) | Input PSLVERRS9 is unused @W:CL159 : coreapb3.v(125) | Input PSLVERRS10 is unused @W:CL159 : coreapb3.v(126) | Input PSLVERRS11 is unused @W:CL159 : coreapb3.v(127) | Input PSLVERRS12 is unused @W:CL159 : coreapb3.v(128) | Input PSLVERRS13 is unused @W:CL159 : coreapb3.v(129) | Input PSLVERRS14 is unused @W:CL159 : coreapb3.v(130) | Input PSLVERRS15 is unused @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Aug 17 14:54:05 2010 ###########################################################] Synopsys Actel Technology Mapper, Version map500act, Build 058R, Built Jan 18 2010 09:16:23 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved Product Version D-2009.12A @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled @W:MO111 : mss_top_tmp_mss_ccc_0_mss_ccc.v(62) | tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module mss_top_tmp_MSS_CCC_0_MSS_CCC) @W:MO111 : mss_top_tmp_mss_ccc_0_mss_ccc.v(63) | tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module mss_top_tmp_MSS_CCC_0_MSS_CCC) @W:MO111 : mss_top_tmp_mss_ccc_0_mss_ccc.v(64) | tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module mss_top_tmp_MSS_CCC_0_MSS_CCC) Automatic dissolve during optimization of view:work.spi_slave(verilog) of ldic8_inst_0(ldic8_0) Automatic dissolve during optimization of view:work.CORESPI_SFR_0s_1s(verilog) of ldic7_inst_0(ldic7_0) Automatic dissolve during optimization of view:work.CORESPI_15s_0s_1s(verilog) of ldic6_inst_0(ldic6_0) Automatic dissolve during optimization of view:work.b14_CRGcTCua_eH4_s(verilog) of b19_O2yyf_fG2_MiQA1E6_q(b9_O2yyf_fG2) Automatic dissolve during optimization of view:work.b11_PSyil9s1fkT(verilog) of b6_2ZGFQ9(b14_CRGcTCua_eH4_s) Automatic dissolve during optimization of view:work.top_level(verilog) of ldic1_inst_0(ldic1_0) Automatic dissolve at startup in view:work.CoreAPB3_Z1(verilog) of u_mux_p_to_b3(COREAPB3_MUXPTOB3) Automatic dissolve at startup in view:work.mss_top(verilog) of MSS_CCC_0(mss_top_tmp_MSS_CCC_0_MSS_CCC) Automatic dissolve at startup in view:work.comm_block(verilog) of b9_ORb_xNywD(b9_ORbIwXaEF) Automatic dissolve at startup in view:work.comm_block(verilog) of b7_Rcmi_ql(b16_Rcmi_qlx9_yHpm7y) Automatic dissolve at startup in view:work.b7_OCByLXC_Z2(verilog) of b11_nUTGT_khWqH(b8_nR_ymqrG_7s_5s_0) @N:BN116 : syn_dics.v(1222) | Removing sequential instance b11_nUTGT_khWqH.b9_ibScJX_E2 of view:PrimLib.dffre(prim) because there are no references to its outputs @N:BN116 : syn_dics.v(1230) | Removing sequential instance b11_nUTGT_khWqH.b11_ibScJX_E2_P of view:PrimLib.dffe(prim) because there are no references to its outputs Automatic dissolve at startup in view:work.b7_PfFzrNY(verilog) of b5_PbrtL(b5_nvmFL_12s) Automatic dissolve at startup in view:work.b7_OFWNT9s(verilog) of b3_SoW(ram_block) Automatic dissolve at startup in view:work.top_level(verilog) of mss_top_0(mss_top) Automatic dissolve at startup in view:work.top_level(verilog) of CoreAPB3_0(CoreAPB3_Z1) Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 58MB) @N: : spi_slave.v(149) | Found counter in view:work.spi_slave(verilog) inst count[3:0] Encoding state machine work.b7_OCByLXC_Z2(verilog)-b13_nAzGfFM_sLsv3[5:0] original code -> new code 0000 -> 000001 0001 -> 000010 0010 -> 000100 0011 -> 001000 0100 -> 010000 1101 -> 100000 @W:MO129 : syn_dics.v(592) | Sequential instance iice_inst_0.b8_12m_IFLY.b5_nUTGT.b3_nfs[1] has been reduced to a combinational gate by constant propagation Ram Decomposition Statistics for b3_SoW.mem[13:0] RAM 512x9 : 0 RAM 512x9 : 0 @A:BN291 : syn_dics.v(801) | Boundary register b3_SoW.data_out[13] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : syn_dics.v(801) | Boundary register b3_SoW.data_out[12] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : syn_dics.v(801) | Boundary register b3_SoW.data_out[11] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : syn_dics.v(801) | Boundary register b3_SoW.data_out[10] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : syn_dics.v(801) | Boundary register b3_SoW.data_out[9] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : syn_dics.v(801) | Boundary register b3_SoW.data_out[8] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : syn_dics.v(801) | Boundary register b3_SoW.data_out[7] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : syn_dics.v(801) | Boundary register b3_SoW.data_out[6] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : syn_dics.v(801) | Boundary register b3_SoW.data_out[5] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : syn_dics.v(801) | Boundary register b3_SoW.data_out[4] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : syn_dics.v(801) | Boundary register b3_SoW.data_out[3] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : syn_dics.v(801) | Boundary register b3_SoW.data_out[2] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : syn_dics.v(801) | Boundary register b3_SoW.data_out[1] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : syn_dics.v(801) | Boundary register b3_SoW.data_out[0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. Automatic dissolve during optimization of view:work.top_level(verilog) of CORESPI_0(CORESPI_15s_0s_1s) Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 58MB peak: 59MB) Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 58MB peak: 59MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 60MB peak: 60MB) Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 60MB peak: 61MB) Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 60MB peak: 61MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 60MB peak: 61MB) Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 61MB peak: 62MB) High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes ----------------------------------------------------------------------------------- comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[7] / Q 35 comm_block_inst.b9_ORb_xNywD.un1_b3_ORb9 / Y 32 comm_block_inst.jtagi.b10_nv_ywKMm9X / Y 64 mss_top_0.MSS_ADLIB_INST / M2FRESETn 49 : 49 asynchronous set/reset =================================================================================== @N:FP130 : | Promoting Net b3_PK3 on CLKINT jtagi.b3_PK3_inferred_clock @N:FP130 : | Promoting Net b9_nv_oQwfYF on CLKINT jtagi.identify_clk2_no_clk_buffer_needed @N:FP130 : | Promoting Net b7_oSD_3vW on CLKINT jtagi.b7_oSD_3vW_inferred_clock Buffering uplink_8_a[4], fanout 50 segments 3 Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 61MB peak: 62MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 61MB peak: 62MB) Added 2 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Added 2 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Added 2 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Added 2 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 62MB peak: 62MB) Writing Analyst data base D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\synthesis\synthesis_1\top_level.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:01s; Memory used current: 61MB peak: 62MB) Writing EDIF Netlist and constraint files D-2009.12A Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:01s; Memory used current: 62MB peak: 63MB) @W:MT420 : | Found inferred clock top_level|atck with period 10.00ns. A user-defined clock should be declared on object "p:atck" @W:MT420 : | Found inferred clock top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:mss_top_0_FAB_CLK" @W:MT420 : | Found inferred clock jtag_interface|b7_oSD_3vW_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:comm_block_inst.jtagi.b7_oSD_3vW" @W:MT420 : | Found inferred clock jtag_interface|identify_clk2_no_clk_buffer_needed with period 10.00ns. A user-defined clock should be declared on object "n:comm_block_inst.jtagi.identify_clk2_no_clk_buffer_needed" @W:MT420 : | Found inferred clock jtag_interface|b3_PK3_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:comm_block_inst.jtagi.b3_PK3" @W:MT246 : mss_top.v(471) | Blackbox INBUF_MSS is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : mss_top.v(469) | Blackbox BIBUF_MSS is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : mss_top.v(467) | Blackbox OUTBUF_MSS is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : mss_top.v(444) | Blackbox BIBUF_OPEND_MSS is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : mss_top.v(421) | Blackbox TRIBUFF_MSS is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : mss_top.v(418) | Blackbox MSSINT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : mss_top.v(262) | Blackbox MSS_APB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : mss_top_tmp_mss_ccc_0_mss_ccc.v(96) | Blackbox MSS_XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : mss_top_tmp_mss_ccc_0_mss_ccc.v(78) | Blackbox MSS_CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) ##### START OF TIMING REPORT #####[ # Timing Report written on Tue Aug 17 14:54:09 2010 # Top view: top_level Library name: fusion Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree ) Requested Frequency: 100.0 MHz Wire load mode: top Wire load model: fusion Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: -3.801 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- jtag_interface|b3_PK3_inferred_clock 100.0 MHz 98.6 MHz 10.000 10.146 -0.146 inferred Inferred_clkgroup_3 jtag_interface|b7_oSD_3vW_inferred_clock 100.0 MHz 589.6 MHz 10.000 1.696 8.304 inferred Inferred_clkgroup_4 jtag_interface|identify_clk2_no_clk_buffer_needed 100.0 MHz 123.4 MHz 10.000 8.106 1.894 inferred Inferred_clkgroup_1 top_level|atck 100.0 MHz 88.4 MHz 10.000 11.310 -1.310 inferred Inferred_clkgroup_2 top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock 100.0 MHz 72.5 MHz 10.000 13.801 -3.801 inferred Inferred_clkgroup_0 System 100.0 MHz 81.9 MHz 10.000 12.204 -2.204 system default_clkgroup ====================================================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock | 10.000 -3.801 | No paths - | No paths - | No paths - top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock jtag_interface|b3_PK3_inferred_clock | Diff grp - | No paths - | No paths - | No paths - jtag_interface|identify_clk2_no_clk_buffer_needed top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - jtag_interface|identify_clk2_no_clk_buffer_needed jtag_interface|identify_clk2_no_clk_buffer_needed | 10.000 1.894 | No paths - | No paths - | No paths - jtag_interface|identify_clk2_no_clk_buffer_needed top_level|atck | No paths - | No paths - | Diff grp - | No paths - jtag_interface|identify_clk2_no_clk_buffer_needed jtag_interface|b3_PK3_inferred_clock | Diff grp - | No paths - | No paths - | No paths - top_level|atck jtag_interface|identify_clk2_no_clk_buffer_needed | No paths - | No paths - | No paths - | Diff grp - top_level|atck top_level|atck | No paths - | 10.000 -1.310 | No paths - | No paths - top_level|atck jtag_interface|b3_PK3_inferred_clock | No paths - | No paths - | No paths - | Diff grp - top_level|atck jtag_interface|b7_oSD_3vW_inferred_clock | No paths - | No paths - | No paths - | Diff grp - jtag_interface|b3_PK3_inferred_clock top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - jtag_interface|b3_PK3_inferred_clock jtag_interface|identify_clk2_no_clk_buffer_needed | Diff grp - | No paths - | No paths - | No paths - jtag_interface|b3_PK3_inferred_clock top_level|atck | No paths - | No paths - | Diff grp - | No paths - jtag_interface|b3_PK3_inferred_clock jtag_interface|b3_PK3_inferred_clock | 10.000 -0.146 | No paths - | No paths - | No paths - jtag_interface|b7_oSD_3vW_inferred_clock jtag_interface|identify_clk2_no_clk_buffer_needed | Diff grp - | No paths - | No paths - | No paths - jtag_interface|b7_oSD_3vW_inferred_clock top_level|atck | No paths - | No paths - | Diff grp - | No paths - jtag_interface|b7_oSD_3vW_inferred_clock jtag_interface|b7_oSD_3vW_inferred_clock | 10.000 8.304 | No paths - | No paths - | No paths - ======================================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: jtag_interface|b3_PK3_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------- iice_inst_0.b3_SoW.b9_v_mzCDYXs[1] jtag_interface|b3_PK3_inferred_clock DFN1 Q b9_v_mzCDYXs[1] 0.737 -0.146 iice_inst_0.b3_SoW.b9_v_mzCDYXs[4] jtag_interface|b3_PK3_inferred_clock DFN1 Q b9_v_mzCDYXs[4] 0.737 0.019 iice_inst_0.b3_SoW.b9_v_mzCDYXs[2] jtag_interface|b3_PK3_inferred_clock DFN1 Q b9_v_mzCDYXs[2] 0.737 0.210 iice_inst_0.b3_SoW.b9_v_mzCDYXs[0] jtag_interface|b3_PK3_inferred_clock DFN1 Q b9_v_mzCDYXs[0] 0.737 0.445 iice_inst_0.b3_SoW.b9_v_mzCDYXs[3] jtag_interface|b3_PK3_inferred_clock DFN1 Q b9_v_mzCDYXs[3] 0.737 0.558 iice_inst_0.b3_SoW.b9_v_mzCDYXs[5] jtag_interface|b3_PK3_inferred_clock DFN1 Q b9_v_mzCDYXs[5] 0.737 0.701 iice_inst_0.b3_SoW.b9_v_mzCDYXs[6] jtag_interface|b3_PK3_inferred_clock DFN1 Q b9_v_mzCDYXs[6] 0.737 0.852 iice_inst_0.b3_SoW.b7_nYJ_BFM[14] jtag_interface|b3_PK3_inferred_clock DFN1 Q b7_nYJ_BFM[14] 0.580 1.158 iice_inst_0.b3_SoW.b3_SoW.mem_tile.I_1 jtag_interface|b3_PK3_inferred_clock RAM512X18 RD13 b7_vFW_PlM[13] 2.963 1.712 iice_inst_0.b3_SoW.b3_SoW.mem_tile.I_1 jtag_interface|b3_PK3_inferred_clock RAM512X18 RD1 b7_vFW_PlM[1] 2.963 1.754 ================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------ iice_inst_0.b3_SoW.b9_v_mzCDYXs[3] jtag_interface|b3_PK3_inferred_clock DFN1 D b9_v_mzCDYXs_4[3] 9.461 -0.146 iice_inst_0.b3_SoW.b9_v_mzCDYXs[4] jtag_interface|b3_PK3_inferred_clock DFN1 D b9_v_mzCDYXs_4[4] 9.461 -0.146 iice_inst_0.b3_SoW.b9_v_mzCDYXs[5] jtag_interface|b3_PK3_inferred_clock DFN1 D b9_v_mzCDYXs_4[5] 9.461 -0.104 iice_inst_0.b3_SoW.b9_v_mzCDYXs[6] jtag_interface|b3_PK3_inferred_clock DFN1 D b9_v_mzCDYXs_4[6] 9.461 -0.104 iice_inst_0.b3_SoW.b9_v_mzCDYXs[2] jtag_interface|b3_PK3_inferred_clock DFN1 D b9_v_mzCDYXs_4[2] 9.461 0.031 iice_inst_0.b3_SoW.b3_SoW.mem_tile.I_1 jtag_interface|b3_PK3_inferred_clock RAM512X18 RADDR3 b9_v_mzCDYXs_4[3] 9.719 0.111 iice_inst_0.b3_SoW.b3_SoW.mem_tile.I_1 jtag_interface|b3_PK3_inferred_clock RAM512X18 RADDR4 b9_v_mzCDYXs_4[4] 9.719 0.111 iice_inst_0.b3_SoW.b3_SoW.mem_tile.I_1 jtag_interface|b3_PK3_inferred_clock RAM512X18 RADDR5 b9_v_mzCDYXs_4[5] 9.719 0.153 iice_inst_0.b3_SoW.b3_SoW.mem_tile.I_1 jtag_interface|b3_PK3_inferred_clock RAM512X18 RADDR6 b9_v_mzCDYXs_4[6] 9.719 0.153 iice_inst_0.b3_SoW.b3_SoW.mem_tile.I_1 jtag_interface|b3_PK3_inferred_clock RAM512X18 RADDR2 b9_v_mzCDYXs_4[2] 9.719 0.289 ====================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 9.607 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.146 Number of logic level(s): 6 Starting point: iice_inst_0.b3_SoW.b9_v_mzCDYXs[1] / Q Ending point: iice_inst_0.b3_SoW.b9_v_mzCDYXs[3] / D The start point is clocked by jtag_interface|b3_PK3_inferred_clock [rising] on pin CLK The end point is clocked by jtag_interface|b3_PK3_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------- iice_inst_0.b3_SoW.b9_v_mzCDYXs[1] DFN1 Q Out 0.737 0.737 - b9_v_mzCDYXs[1] Net - - 1.526 - 7 iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNILLJD[6] NOR3C A In - 2.263 - iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNILLJD[6] NOR3C Y Out 0.464 2.727 - G_11_3 Net - - 0.322 - 1 iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNINVNV[0] NOR3C C In - 3.048 - iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNINVNV[0] NOR3C Y Out 0.641 3.690 - N_1_5 Net - - 0.322 - 1 iice_inst_0.b3_SoW.b7_nYJ_BFM_RNI8O3I1[14] OR2 B In - 4.011 - iice_inst_0.b3_SoW.b7_nYJ_BFM_RNI8O3I1[14] OR2 Y Out 0.646 4.658 - N_2 Net - - 0.806 - 3 iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.G_1 NOR2A B In - 5.464 - iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.G_1 NOR2A Y Out 0.407 5.871 - DWACT_ADD_CI_0_TMP_0[0] Net - - 1.423 - 6 iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.G_8 OR3C C In - 7.294 - iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.G_8 OR3C Y Out 0.666 7.960 - N_1_1 Net - - 0.322 - 1 iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNIV2N84[3] XA1A B In - 8.281 - iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNIV2N84[3] XA1A Y Out 0.940 9.221 - b9_v_mzCDYXs_4[3] Net - - 0.386 - 2 iice_inst_0.b3_SoW.b9_v_mzCDYXs[3] DFN1 D In - 9.607 - =========================================================================================================== Total path delay (propagation time + setup) of 10.146 is 5.040(49.7%) logic and 5.106(50.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 9.607 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.146 Number of logic level(s): 6 Starting point: iice_inst_0.b3_SoW.b9_v_mzCDYXs[1] / Q Ending point: iice_inst_0.b3_SoW.b9_v_mzCDYXs[4] / D The start point is clocked by jtag_interface|b3_PK3_inferred_clock [rising] on pin CLK The end point is clocked by jtag_interface|b3_PK3_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------- iice_inst_0.b3_SoW.b9_v_mzCDYXs[1] DFN1 Q Out 0.737 0.737 - b9_v_mzCDYXs[1] Net - - 1.526 - 7 iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNILLJD[6] NOR3C A In - 2.263 - iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNILLJD[6] NOR3C Y Out 0.464 2.727 - G_11_3 Net - - 0.322 - 1 iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNINVNV[0] NOR3C C In - 3.048 - iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNINVNV[0] NOR3C Y Out 0.641 3.690 - N_1_5 Net - - 0.322 - 1 iice_inst_0.b3_SoW.b7_nYJ_BFM_RNI8O3I1[14] OR2 B In - 4.011 - iice_inst_0.b3_SoW.b7_nYJ_BFM_RNI8O3I1[14] OR2 Y Out 0.646 4.658 - N_2 Net - - 0.806 - 3 iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.G_1 NOR2A B In - 5.464 - iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.G_1 NOR2A Y Out 0.407 5.871 - DWACT_ADD_CI_0_TMP_0[0] Net - - 1.423 - 6 iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.G_10 OR3C C In - 7.294 - iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.G_10 OR3C Y Out 0.666 7.960 - N_1_3 Net - - 0.322 - 1 iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNIHB8D4[4] XA1A B In - 8.281 - iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNIHB8D4[4] XA1A Y Out 0.940 9.221 - b9_v_mzCDYXs_4[4] Net - - 0.386 - 2 iice_inst_0.b3_SoW.b9_v_mzCDYXs[4] DFN1 D In - 9.607 - =========================================================================================================== Total path delay (propagation time + setup) of 10.146 is 5.040(49.7%) logic and 5.106(50.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 9.566 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.104 Number of logic level(s): 6 Starting point: iice_inst_0.b3_SoW.b9_v_mzCDYXs[1] / Q Ending point: iice_inst_0.b3_SoW.b9_v_mzCDYXs[5] / D The start point is clocked by jtag_interface|b3_PK3_inferred_clock [rising] on pin CLK The end point is clocked by jtag_interface|b3_PK3_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------- iice_inst_0.b3_SoW.b9_v_mzCDYXs[1] DFN1 Q Out 0.737 0.737 - b9_v_mzCDYXs[1] Net - - 1.526 - 7 iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNILLJD[6] NOR3C A In - 2.263 - iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNILLJD[6] NOR3C Y Out 0.464 2.727 - G_11_3 Net - - 0.322 - 1 iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNINVNV[0] NOR3C C In - 3.048 - iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNINVNV[0] NOR3C Y Out 0.641 3.690 - N_1_5 Net - - 0.322 - 1 iice_inst_0.b3_SoW.b7_nYJ_BFM_RNI8O3I1[14] OR2 B In - 4.011 - iice_inst_0.b3_SoW.b7_nYJ_BFM_RNI8O3I1[14] OR2 Y Out 0.646 4.658 - N_2 Net - - 0.806 - 3 iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.G_1 NOR2A B In - 5.464 - iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.G_1 NOR2A Y Out 0.407 5.871 - DWACT_ADD_CI_0_TMP_0[0] Net - - 1.423 - 6 iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.G_7 OR3B B In - 7.294 - iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.G_7 OR3B Y Out 0.624 7.918 - N_1_0 Net - - 0.322 - 1 iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNI4OPH4[5] XA1A B In - 8.239 - iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNI4OPH4[5] XA1A Y Out 0.940 9.180 - b9_v_mzCDYXs_4[5] Net - - 0.386 - 2 iice_inst_0.b3_SoW.b9_v_mzCDYXs[5] DFN1 D In - 9.566 - =========================================================================================================== Total path delay (propagation time + setup) of 10.104 is 4.998(49.5%) logic and 5.106(50.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 9.566 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.104 Number of logic level(s): 6 Starting point: iice_inst_0.b3_SoW.b9_v_mzCDYXs[1] / Q Ending point: iice_inst_0.b3_SoW.b9_v_mzCDYXs[6] / D The start point is clocked by jtag_interface|b3_PK3_inferred_clock [rising] on pin CLK The end point is clocked by jtag_interface|b3_PK3_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------- iice_inst_0.b3_SoW.b9_v_mzCDYXs[1] DFN1 Q Out 0.737 0.737 - b9_v_mzCDYXs[1] Net - - 1.526 - 7 iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNILLJD[6] NOR3C A In - 2.263 - iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNILLJD[6] NOR3C Y Out 0.464 2.727 - G_11_3 Net - - 0.322 - 1 iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNINVNV[0] NOR3C C In - 3.048 - iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNINVNV[0] NOR3C Y Out 0.641 3.690 - N_1_5 Net - - 0.322 - 1 iice_inst_0.b3_SoW.b7_nYJ_BFM_RNI8O3I1[14] OR2 B In - 4.011 - iice_inst_0.b3_SoW.b7_nYJ_BFM_RNI8O3I1[14] OR2 Y Out 0.646 4.658 - N_2 Net - - 0.806 - 3 iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.G_1 NOR2A B In - 5.464 - iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.G_1 NOR2A Y Out 0.407 5.871 - DWACT_ADD_CI_0_TMP_0[0] Net - - 1.423 - 6 iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.G_6 OR3B B In - 7.294 - iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.G_6 OR3B Y Out 0.624 7.918 - N_1 Net - - 0.322 - 1 iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNIO8BM4[6] XA1A B In - 8.239 - iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNIO8BM4[6] XA1A Y Out 0.940 9.180 - b9_v_mzCDYXs_4[6] Net - - 0.386 - 2 iice_inst_0.b3_SoW.b9_v_mzCDYXs[6] DFN1 D In - 9.566 - =========================================================================================================== Total path delay (propagation time + setup) of 10.104 is 4.998(49.5%) logic and 5.106(50.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 9.442 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 0.019 Number of logic level(s): 6 Starting point: iice_inst_0.b3_SoW.b9_v_mzCDYXs[4] / Q Ending point: iice_inst_0.b3_SoW.b9_v_mzCDYXs[3] / D The start point is clocked by jtag_interface|b3_PK3_inferred_clock [rising] on pin CLK The end point is clocked by jtag_interface|b3_PK3_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------- iice_inst_0.b3_SoW.b9_v_mzCDYXs[4] DFN1 Q Out 0.737 0.737 - b9_v_mzCDYXs[4] Net - - 1.184 - 4 iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNILLJD[6] NOR3C C In - 1.921 - iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNILLJD[6] NOR3C Y Out 0.641 2.562 - G_11_3 Net - - 0.322 - 1 iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNINVNV[0] NOR3C C In - 2.883 - iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNINVNV[0] NOR3C Y Out 0.641 3.525 - N_1_5 Net - - 0.322 - 1 iice_inst_0.b3_SoW.b7_nYJ_BFM_RNI8O3I1[14] OR2 B In - 3.846 - iice_inst_0.b3_SoW.b7_nYJ_BFM_RNI8O3I1[14] OR2 Y Out 0.646 4.493 - N_2 Net - - 0.806 - 3 iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.G_1 NOR2A B In - 5.299 - iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.G_1 NOR2A Y Out 0.407 5.706 - DWACT_ADD_CI_0_TMP_0[0] Net - - 1.423 - 6 iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.G_8 OR3C C In - 7.129 - iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.G_8 OR3C Y Out 0.666 7.795 - N_1_1 Net - - 0.322 - 1 iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNIV2N84[3] XA1A B In - 8.116 - iice_inst_0.b3_SoW.b9_v_mzCDYXs_RNIV2N84[3] XA1A Y Out 0.940 9.056 - b9_v_mzCDYXs_4[3] Net - - 0.386 - 2 iice_inst_0.b3_SoW.b9_v_mzCDYXs[3] DFN1 D In - 9.442 - =========================================================================================================== Total path delay (propagation time + setup) of 9.981 is 5.217(52.3%) logic and 4.764(47.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: jtag_interface|b7_oSD_3vW_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------- comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[1] jtag_interface|b7_oSD_3vW_inferred_clock DFN1E1 Q b9_OvyH3_saL[1] 0.737 8.304 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[2] jtag_interface|b7_oSD_3vW_inferred_clock DFN1E1 Q b9_OvyH3_saL[2] 0.737 8.304 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[3] jtag_interface|b7_oSD_3vW_inferred_clock DFN1E1 Q b9_OvyH3_saL[3] 0.737 8.304 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[4] jtag_interface|b7_oSD_3vW_inferred_clock DFN1E1 Q b9_OvyH3_saL[4] 0.737 8.304 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[5] jtag_interface|b7_oSD_3vW_inferred_clock DFN1E1 Q b9_OvyH3_saL[5] 0.737 8.304 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[6] jtag_interface|b7_oSD_3vW_inferred_clock DFN1E1 Q b9_OvyH3_saL[6] 0.737 8.304 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[7] jtag_interface|b7_oSD_3vW_inferred_clock DFN1E1 Q b9_OvyH3_saL[7] 0.737 8.304 ==================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------- comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[0] jtag_interface|b7_oSD_3vW_inferred_clock DFN1E1 D b9_OvyH3_saL[1] 9.427 8.304 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[1] jtag_interface|b7_oSD_3vW_inferred_clock DFN1E1 D b9_OvyH3_saL[2] 9.427 8.304 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[2] jtag_interface|b7_oSD_3vW_inferred_clock DFN1E1 D b9_OvyH3_saL[3] 9.427 8.304 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[3] jtag_interface|b7_oSD_3vW_inferred_clock DFN1E1 D b9_OvyH3_saL[4] 9.427 8.304 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[4] jtag_interface|b7_oSD_3vW_inferred_clock DFN1E1 D b9_OvyH3_saL[5] 9.427 8.304 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[5] jtag_interface|b7_oSD_3vW_inferred_clock DFN1E1 D b9_OvyH3_saL[6] 9.427 8.304 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[6] jtag_interface|b7_oSD_3vW_inferred_clock DFN1E1 D b9_OvyH3_saL[7] 9.427 8.304 ===================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.573 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.427 - Propagation time: 1.123 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 8.304 Number of logic level(s): 0 Starting point: comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[1] / Q Ending point: comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[0] / D The start point is clocked by jtag_interface|b7_oSD_3vW_inferred_clock [rising] on pin CLK The end point is clocked by jtag_interface|b7_oSD_3vW_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------- comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[1] DFN1E1 Q Out 0.737 0.737 - b9_OvyH3_saL[1] Net - - 0.386 - 2 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[0] DFN1E1 D In - 1.123 - =========================================================================================================== Total path delay (propagation time + setup) of 1.696 is 1.310(77.3%) logic and 0.386(22.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: jtag_interface|identify_clk2_no_clk_buffer_needed ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------- comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[0] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1E0 Q b11_uRrc_WYOFjZ[0] 0.737 1.894 comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[5] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1E0 Q b13_nvmFL_fx2rbuQ[4] 0.580 2.887 comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[1] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1E0 Q b13_nvmFL_fx2rbuQ[0] 0.580 3.081 comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[6] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1E0 Q b13_nvmFL_fx2rbuQ[5] 0.737 3.146 comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[3] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1E0 Q b13_nvmFL_fx2rbuQ[2] 0.737 3.292 comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[2] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1E0 Q b13_nvmFL_fx2rbuQ[1] 0.737 3.756 comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[4] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1E0 Q b13_nvmFL_fx2rbuQ[3] 0.580 3.818 ==================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- iice_inst_0.b8_12m_IFLY.b5_nUTGT.b11_nUTGT_khWqH.b3_nUT[0] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1E1 E b15_nYhI39swMeEd_Mg 9.392 1.894 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b11_nUTGT_khWqH.b3_nUT[1] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1E1 E b15_nYhI39swMeEd_Mg 9.392 1.894 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b11_nUTGT_khWqH.b3_nUT[2] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1E1 E b15_nYhI39swMeEd_Mg 9.392 1.894 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b11_nUTGT_khWqH.b3_nUT[3] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1E1 E b15_nYhI39swMeEd_Mg 9.392 1.894 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b11_nUTGT_khWqH.b3_nUT[4] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1E1 E b15_nYhI39swMeEd_Mg 9.392 1.894 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b11_nUTGT_khWqH.b3_nUT[5] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1E1 E b15_nYhI39swMeEd_Mg 9.392 1.894 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b11_nUTGT_khWqH.b3_nUT[6] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1E1 E b15_nYhI39swMeEd_Mg 9.392 1.894 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b11_nUTGT_khWqH.b3_nfs[0] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1E1 E b12_nUTQBgfDb_bd 9.392 2.110 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b11_nUTGT_khWqH.b3_nfs[1] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1E1 E b12_nUTQBgfDb_bd 9.392 2.110 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b11_nUTGT_khWqH.b3_nfs[2] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1E1 E b12_nUTQBgfDb_bd 9.392 2.110 ================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.608 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.392 - Propagation time: 7.497 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 1.894 Number of logic level(s): 4 Starting point: comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[0] / Q Ending point: iice_inst_0.b8_12m_IFLY.b5_nUTGT.b11_nUTGT_khWqH.b3_nUT[0] / E The start point is clocked by jtag_interface|identify_clk2_no_clk_buffer_needed [rising] on pin CLK The end point is clocked by jtag_interface|identify_clk2_no_clk_buffer_needed [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------- comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[0] DFN1E0 Q Out 0.737 0.737 - b11_uRrc_WYOFjZ[0] Net - - 0.322 - 1 comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3_RNIN64N[0] NOR2B A In - 1.058 - comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3_RNIN64N[0] NOR2B Y Out 0.514 1.573 - b11_uRrc_9urXBb[0] Net - - 0.386 - 2 iice_inst_0.b8_uKr_IFLY.b10_nvscB_rGsL.b9_nvmFLz_ab_5 NOR3A A In - 1.959 - iice_inst_0.b8_uKr_IFLY.b10_nvscB_rGsL.b9_nvmFLz_ab_5 NOR3A Y Out 0.641 2.600 - b9_nvmFLH_ab_5 Net - - 0.806 - 3 iice_inst_0.b8_uKr_IFLY.b10_nvscB_rGsL.b9_nvmFLz_ab_0_a2_0 NOR3A A In - 3.406 - iice_inst_0.b8_uKr_IFLY.b10_nvscB_rGsL.b9_nvmFLz_ab_0_a2_0 NOR3A Y Out 0.641 4.048 - N_26 Net - - 1.184 - 4 iice_inst_0.b8_uKr_IFLY.b10_nvscB_rGsL.b9_nvmFLP_ab0_0_a2 NOR2B B In - 5.231 - iice_inst_0.b8_uKr_IFLY.b10_nvscB_rGsL.b9_nvmFLP_ab0_0_a2 NOR2B Y Out 0.627 5.859 - b15_nYhI39swMeEd_Mg Net - - 1.639 - 8 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b11_nUTGT_khWqH.b3_nUT[0] DFN1E1 E In - 7.497 - =========================================================================================================================== Total path delay (propagation time + setup) of 8.106 is 3.770(46.5%) logic and 4.336(53.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: top_level|atck ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------ comm_block_inst.jtagi.b9_Rcmi_KsDw top_level|atck UJTAG UIREG3 b6_uS_MrX[2] 2.211 -1.310 comm_block_inst.jtagi.b9_Rcmi_KsDw top_level|atck UJTAG UIREG4 b6_uS_MrX[3] 2.211 -1.171 comm_block_inst.jtagi.b9_Rcmi_KsDw top_level|atck UJTAG UIREG5 b6_uS_MrX[4] 2.211 -1.112 comm_block_inst.jtagi.b9_Rcmi_KsDw top_level|atck UJTAG UIREG6 b3_1Um 1.960 -0.971 comm_block_inst.jtagi.b9_Rcmi_KsDw top_level|atck UJTAG UIREG2 b6_uS_MrX[1] 2.211 -0.551 comm_block_inst.jtagi.b9_Rcmi_KsDw top_level|atck UJTAG UIREG1 b6_uS_MrX[0] 1.960 -0.410 ================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------- comm_block_inst.jtagi.b9_Rcmi_KsDw top_level|atck UJTAG UTDO b6_PLF_Bq 8.279 -1.310 ============================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 1.721 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.279 - Propagation time: 9.590 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.310 Number of logic level(s): 6 Starting point: comm_block_inst.jtagi.b9_Rcmi_KsDw / UIREG3 Ending point: comm_block_inst.jtagi.b9_Rcmi_KsDw / UTDO The start point is clocked by top_level|atck [falling] on pin TCK The end point is clocked by top_level|atck [falling] on pin TCK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------- comm_block_inst.jtagi.b9_Rcmi_KsDw UJTAG UIREG3 Out 2.211 2.211 - b6_uS_MrX[2] Net - - 0.322 - 1 comm_block_inst.jtagi.b9_Rcmi_KsDw_RNION17 NOR2 B In - 2.532 - comm_block_inst.jtagi.b9_Rcmi_KsDw_RNION17 NOR2 Y Out 0.646 3.179 - b9_nv_cLqgOF_2 Net - - 0.806 - 3 comm_block_inst.jtagi.b9_Rcmi_KsDw_RNI875L NOR3C B In - 3.985 - comm_block_inst.jtagi.b9_Rcmi_KsDw_RNI875L NOR3C Y Out 0.624 4.609 - b9_nv_cLqgOF Net - - 1.184 - 4 comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3_RNIN64N[0] NOR2B B In - 5.793 - comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3_RNIN64N[0] NOR2B Y Out 0.516 6.309 - b11_uRrc_9urXBb[0] Net - - 0.386 - 2 iice_inst_0.b8_uKr_IFLY.b11_uRrc_9urXBb_RNI1IK63 NOR3C C In - 6.694 - iice_inst_0.b8_uKr_IFLY.b11_uRrc_9urXBb_RNI1IK63 NOR3C Y Out 0.666 7.360 - b3_PLF Net - - 0.322 - 1 comm_block_inst.iice2comm_link_iice_0_RNINNLO OR3B B In - 7.682 - comm_block_inst.iice2comm_link_iice_0_RNINNLO OR3B Y Out 0.624 8.306 - iice2comm_link_iice_0_m Net - - 0.322 - 1 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL_RNI38F72[0] OR3C C In - 8.627 - comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL_RNI38F72[0] OR3C Y Out 0.641 9.268 - b6_PLF_Bq Net - - 0.322 - 1 comm_block_inst.jtagi.b9_Rcmi_KsDw UJTAG UTDO In - 9.590 - ====================================================================================================================== Total path delay (propagation time + setup) of 11.310 is 7.649(67.6%) logic and 3.662(32.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 1.721 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.279 - Propagation time: 9.451 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.171 Number of logic level(s): 6 Starting point: comm_block_inst.jtagi.b9_Rcmi_KsDw / UIREG4 Ending point: comm_block_inst.jtagi.b9_Rcmi_KsDw / UTDO The start point is clocked by top_level|atck [falling] on pin TCK The end point is clocked by top_level|atck [falling] on pin TCK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------- comm_block_inst.jtagi.b9_Rcmi_KsDw UJTAG UIREG4 Out 2.211 2.211 - b6_uS_MrX[3] Net - - 0.322 - 1 comm_block_inst.jtagi.b9_Rcmi_KsDw_RNION17 NOR2 A In - 2.532 - comm_block_inst.jtagi.b9_Rcmi_KsDw_RNION17 NOR2 Y Out 0.507 3.040 - b9_nv_cLqgOF_2 Net - - 0.806 - 3 comm_block_inst.jtagi.b9_Rcmi_KsDw_RNI875L NOR3C B In - 3.846 - comm_block_inst.jtagi.b9_Rcmi_KsDw_RNI875L NOR3C Y Out 0.624 4.470 - b9_nv_cLqgOF Net - - 1.184 - 4 comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3_RNIN64N[0] NOR2B B In - 5.654 - comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3_RNIN64N[0] NOR2B Y Out 0.516 6.170 - b11_uRrc_9urXBb[0] Net - - 0.386 - 2 iice_inst_0.b8_uKr_IFLY.b11_uRrc_9urXBb_RNI1IK63 NOR3C C In - 6.555 - iice_inst_0.b8_uKr_IFLY.b11_uRrc_9urXBb_RNI1IK63 NOR3C Y Out 0.666 7.221 - b3_PLF Net - - 0.322 - 1 comm_block_inst.iice2comm_link_iice_0_RNINNLO OR3B B In - 7.543 - comm_block_inst.iice2comm_link_iice_0_RNINNLO OR3B Y Out 0.624 8.166 - iice2comm_link_iice_0_m Net - - 0.322 - 1 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL_RNI38F72[0] OR3C C In - 8.488 - comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL_RNI38F72[0] OR3C Y Out 0.641 9.129 - b6_PLF_Bq Net - - 0.322 - 1 comm_block_inst.jtagi.b9_Rcmi_KsDw UJTAG UTDO In - 9.451 - ====================================================================================================================== Total path delay (propagation time + setup) of 11.171 is 7.509(67.2%) logic and 3.662(32.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 1.721 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.279 - Propagation time: 9.392 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.112 Number of logic level(s): 6 Starting point: comm_block_inst.jtagi.b9_Rcmi_KsDw / UIREG5 Ending point: comm_block_inst.jtagi.b9_Rcmi_KsDw / UTDO The start point is clocked by top_level|atck [falling] on pin TCK The end point is clocked by top_level|atck [falling] on pin TCK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------- comm_block_inst.jtagi.b9_Rcmi_KsDw UJTAG UIREG5 Out 2.211 2.211 - b6_uS_MrX[4] Net - - 0.322 - 1 comm_block_inst.jtagi.b9_Rcmi_KsDw_RNION17_0 NOR2A B In - 2.532 - comm_block_inst.jtagi.b9_Rcmi_KsDw_RNION17_0 NOR2A Y Out 0.407 2.939 - b9_nv_cLqgOF_3 Net - - 0.806 - 3 comm_block_inst.jtagi.b9_Rcmi_KsDw_RNI875L NOR3C C In - 3.745 - comm_block_inst.jtagi.b9_Rcmi_KsDw_RNI875L NOR3C Y Out 0.666 4.411 - b9_nv_cLqgOF Net - - 1.184 - 4 comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3_RNIN64N[0] NOR2B B In - 5.594 - comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3_RNIN64N[0] NOR2B Y Out 0.516 6.111 - b11_uRrc_9urXBb[0] Net - - 0.386 - 2 iice_inst_0.b8_uKr_IFLY.b11_uRrc_9urXBb_RNI1IK63 NOR3C C In - 6.496 - iice_inst_0.b8_uKr_IFLY.b11_uRrc_9urXBb_RNI1IK63 NOR3C Y Out 0.666 7.162 - b3_PLF Net - - 0.322 - 1 comm_block_inst.iice2comm_link_iice_0_RNINNLO OR3B B In - 7.483 - comm_block_inst.iice2comm_link_iice_0_RNINNLO OR3B Y Out 0.624 8.107 - iice2comm_link_iice_0_m Net - - 0.322 - 1 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL_RNI38F72[0] OR3C C In - 8.429 - comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL_RNI38F72[0] OR3C Y Out 0.641 9.070 - b6_PLF_Bq Net - - 0.322 - 1 comm_block_inst.jtagi.b9_Rcmi_KsDw UJTAG UTDO In - 9.392 - ====================================================================================================================== Total path delay (propagation time + setup) of 11.112 is 7.450(67.0%) logic and 3.662(33.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 1.721 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.279 - Propagation time: 9.251 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.971 Number of logic level(s): 6 Starting point: comm_block_inst.jtagi.b9_Rcmi_KsDw / UIREG6 Ending point: comm_block_inst.jtagi.b9_Rcmi_KsDw / UTDO The start point is clocked by top_level|atck [falling] on pin TCK The end point is clocked by top_level|atck [falling] on pin TCK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------- comm_block_inst.jtagi.b9_Rcmi_KsDw UJTAG UIREG6 Out 1.960 1.960 - b3_1Um Net - - 0.322 - 1 comm_block_inst.jtagi.b9_Rcmi_KsDw_RNION17_0 NOR2A A In - 2.282 - comm_block_inst.jtagi.b9_Rcmi_KsDw_RNION17_0 NOR2A Y Out 0.516 2.798 - b9_nv_cLqgOF_3 Net - - 0.806 - 3 comm_block_inst.jtagi.b9_Rcmi_KsDw_RNI875L NOR3C C In - 3.604 - comm_block_inst.jtagi.b9_Rcmi_KsDw_RNI875L NOR3C Y Out 0.666 4.270 - b9_nv_cLqgOF Net - - 1.184 - 4 comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3_RNIN64N[0] NOR2B B In - 5.454 - comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3_RNIN64N[0] NOR2B Y Out 0.516 5.970 - b11_uRrc_9urXBb[0] Net - - 0.386 - 2 iice_inst_0.b8_uKr_IFLY.b11_uRrc_9urXBb_RNI1IK63 NOR3C C In - 6.356 - iice_inst_0.b8_uKr_IFLY.b11_uRrc_9urXBb_RNI1IK63 NOR3C Y Out 0.666 7.021 - b3_PLF Net - - 0.322 - 1 comm_block_inst.iice2comm_link_iice_0_RNINNLO OR3B B In - 7.343 - comm_block_inst.iice2comm_link_iice_0_RNINNLO OR3B Y Out 0.624 7.966 - iice2comm_link_iice_0_m Net - - 0.322 - 1 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL_RNI38F72[0] OR3C C In - 8.288 - comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL_RNI38F72[0] OR3C Y Out 0.641 8.929 - b6_PLF_Bq Net - - 0.322 - 1 comm_block_inst.jtagi.b9_Rcmi_KsDw UJTAG UTDO In - 9.251 - ====================================================================================================================== Total path delay (propagation time + setup) of 10.971 is 7.310(66.6%) logic and 3.662(33.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 1.721 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.279 - Propagation time: 8.830 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.551 Number of logic level(s): 6 Starting point: comm_block_inst.jtagi.b9_Rcmi_KsDw / UIREG2 Ending point: comm_block_inst.jtagi.b9_Rcmi_KsDw / UTDO The start point is clocked by top_level|atck [falling] on pin TCK The end point is clocked by top_level|atck [falling] on pin TCK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------- comm_block_inst.jtagi.b9_Rcmi_KsDw UJTAG UIREG2 Out 2.211 2.211 - b6_uS_MrX[1] Net - - 0.386 - 2 comm_block_inst.jtagi.b9_Rcmi_KsDw_RNION17_2 NOR2A B In - 2.596 - comm_block_inst.jtagi.b9_Rcmi_KsDw_RNION17_2 NOR2A Y Out 0.407 3.003 - b9_nv_cLqgOF_0 Net - - 0.322 - 1 comm_block_inst.jtagi.b9_Rcmi_KsDw_RNI875L NOR3C A In - 3.325 - comm_block_inst.jtagi.b9_Rcmi_KsDw_RNI875L NOR3C Y Out 0.525 3.849 - b9_nv_cLqgOF Net - - 1.184 - 4 comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3_RNIN64N[0] NOR2B B In - 5.033 - comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3_RNIN64N[0] NOR2B Y Out 0.516 5.549 - b11_uRrc_9urXBb[0] Net - - 0.386 - 2 iice_inst_0.b8_uKr_IFLY.b11_uRrc_9urXBb_RNI1IK63 NOR3C C In - 5.935 - iice_inst_0.b8_uKr_IFLY.b11_uRrc_9urXBb_RNI1IK63 NOR3C Y Out 0.666 6.601 - b3_PLF Net - - 0.322 - 1 comm_block_inst.iice2comm_link_iice_0_RNINNLO OR3B B In - 6.922 - comm_block_inst.iice2comm_link_iice_0_RNINNLO OR3B Y Out 0.624 7.546 - iice2comm_link_iice_0_m Net - - 0.322 - 1 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL_RNI38F72[0] OR3C C In - 7.867 - comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL_RNI38F72[0] OR3C Y Out 0.641 8.509 - b6_PLF_Bq Net - - 0.322 - 1 comm_block_inst.jtagi.b9_Rcmi_KsDw UJTAG UTDO In - 8.830 - ====================================================================================================================== Total path delay (propagation time + setup) of 10.551 is 7.310(69.3%) logic and 3.241(30.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- iice_inst_0.b8_12m_IFLY.b5_nUTGT.b13_nAzGfFM_sLsv3[3] top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock DFN1C1 Q b13_nAzGfFM_sLsv3[3] 0.737 -3.801 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b10_nYhI3_umjB top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock DFN1 Q b10_nYhI3_umjB 0.580 -3.571 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b3_nfs[2] top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock DFN1C1 Q b3_nfs[2] 0.737 -3.179 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b3_nfs[0] top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock DFN1C1 Q b3_nfs[0] 0.737 -2.932 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b13_nAzGfFM_sLsv3[1] top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock DFN1C1 Q b13_nAzGfFM_sLsv3[1] 0.737 -2.722 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b3_nfs[4] top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock DFN1C1 Q b3_nfs[4] 0.737 -2.353 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b3_nfs[3] top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock DFN1C1 Q b3_nfs[3] 0.737 -2.332 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b13_nAzGfFM_sLsv3[0] top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock DFN1P1 Q b13_nAzGfFM_sLsv3[0] 0.737 -2.235 iice_inst_0.b3_SoW.b9_2_mzCDYXs[2] top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock DFN1 Q b9_2_mzCDYXs[2] 0.737 -1.883 iice_inst_0.b3_SoW.b9_2_mzCDYXs[5] top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock DFN1 Q b9_2_mzCDYXs[5] 0.737 -1.788 =========================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- iice_inst_0.b8_12m_IFLY.b5_nUTGT.b7_nYhI39s[5] top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock DFN1 D b7_nYhI39s_5[5] 9.427 -3.801 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b7_nYhI39s[6] top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock DFN1 D b7_nYhI39s_5[6] 9.427 -3.465 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b7_nYhI39s[4] top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock DFN1 D b7_nYhI39s_5[4] 9.427 -3.396 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b7_nYhI39s[3] top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock DFN1 D b7_nYhI39s_5[3] 9.427 -3.226 iice_inst_0.b3_SoW.b9_2_mzCDYXs[5] top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock DFN1 D b9_2_mzCDYXs_RNO[5] 9.461 -2.306 iice_inst_0.b3_SoW.b9_2_mzCDYXs[6] top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock DFN1 D b9_2_mzCDYXs_RNO[6] 9.461 -2.306 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b7_nYhI39s[2] top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock DFN1 D b7_nYhI39s_5[2] 9.427 -2.023 iice_inst_0.b3_SoW.b9_2_mzCDYXs[4] top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock DFN1 D b9_2_mzCDYXs_RNO[4] 9.461 -1.496 iice_inst_0.b3_SoW.b9_2_mzCDYXs[0] top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock DFN1 D N_5 9.461 -1.020 iice_inst_0.b3_SoW.b9_2_mzCDYXs[1] top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock DFN1 D b9_2_mzCDYXs_RNO[1] 9.461 -1.020 ================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.573 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.427 - Propagation time: 13.227 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -3.801 Number of logic level(s): 8 Starting point: iice_inst_0.b8_12m_IFLY.b5_nUTGT.b13_nAzGfFM_sLsv3[3] / Q Ending point: iice_inst_0.b8_12m_IFLY.b5_nUTGT.b7_nYhI39s[5] / D The start point is clocked by top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------- iice_inst_0.b8_12m_IFLY.b5_nUTGT.b13_nAzGfFM_sLsv3[3] DFN1C1 Q Out 0.737 0.737 - b13_nAzGfFM_sLsv3[3] Net - - 1.639 - 8 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b3_nfs_RNINCPA[0] OR3 C In - 2.376 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.b3_nfs_RNINCPA[0] OR3 Y Out 0.751 3.127 - G_18_2 Net - - 0.322 - 1 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b3_nfs_RNIGSRE[3] OR3 C In - 3.448 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.b3_nfs_RNIGSRE[3] OR3 Y Out 0.751 4.199 - N_1_0_i_0_0 Net - - 0.322 - 1 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b3_nfs_RNIIDDH1[3] OR2A A In - 4.520 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.b3_nfs_RNIIDDH1[3] OR2A Y Out 0.466 4.986 - N_2_0 Net - - 2.082 - 14 iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_24 OA1B C In - 7.068 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_24 OA1B Y Out 0.487 7.555 - DWACT_ADD_CI_0_g_array_1_0[0] Net - - 0.806 - 3 iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_36 AO1 B In - 8.361 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_36 AO1 Y Out 0.598 8.959 - DWACT_ADD_CI_0_g_array_2_0[0] Net - - 0.806 - 3 iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_30 AO13 B In - 9.765 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_30 AO13 Y Out 0.933 10.699 - DWACT_ADD_CI_0_g_array_12_1_0[0] Net - - 0.322 - 1 iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_21_0 XNOR3 C In - 11.020 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_21_0 XNOR3 Y Out 0.985 12.006 - un1_b7_nYhI39s_6_0[5] Net - - 0.322 - 1 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b7_nYhI39s_RNO[5] MX2 A In - 12.327 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.b7_nYhI39s_RNO[5] MX2 Y Out 0.579 12.906 - b7_nYhI39s_5[5] Net - - 0.322 - 1 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b7_nYhI39s[5] DFN1 D In - 13.227 - ========================================================================================================================= Total path delay (propagation time + setup) of 13.801 is 6.859(49.7%) logic and 6.941(50.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 0.573 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.427 - Propagation time: 12.998 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -3.571 Number of logic level(s): 8 Starting point: iice_inst_0.b8_12m_IFLY.b5_nUTGT.b10_nYhI3_umjB / Q Ending point: iice_inst_0.b8_12m_IFLY.b5_nUTGT.b7_nYhI39s[5] / D The start point is clocked by top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------ iice_inst_0.b8_12m_IFLY.b5_nUTGT.b10_nYhI3_umjB DFN1 Q Out 0.580 0.580 - b10_nYhI3_umjB Net - - 1.708 - 10 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b11_nUTGT_khWqH.b8_vABZ3qsY_RNIUE2L AO1D C In - 2.289 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.b11_nUTGT_khWqH.b8_vABZ3qsY_RNIUE2L AO1D Y Out 0.655 2.944 - G_17_0 Net - - 0.322 - 1 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b13_nAzGfFM_sLsv3_RNI2HH21[3] AO1D C In - 3.266 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.b13_nAzGfFM_sLsv3_RNI2HH21[3] AO1D Y Out 0.655 3.921 - G_17_1 Net - - 0.322 - 1 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b3_nfs_RNIIDDH1[3] OR2A B In - 4.242 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.b3_nfs_RNIIDDH1[3] OR2A Y Out 0.514 4.757 - N_2_0 Net - - 2.082 - 14 iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_24 OA1B C In - 6.839 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_24 OA1B Y Out 0.487 7.325 - DWACT_ADD_CI_0_g_array_1_0[0] Net - - 0.806 - 3 iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_36 AO1 B In - 8.132 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_36 AO1 Y Out 0.598 8.730 - DWACT_ADD_CI_0_g_array_2_0[0] Net - - 0.806 - 3 iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_30 AO13 B In - 9.536 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_30 AO13 Y Out 0.933 10.469 - DWACT_ADD_CI_0_g_array_12_1_0[0] Net - - 0.322 - 1 iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_21_0 XNOR3 C In - 10.791 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_21_0 XNOR3 Y Out 0.985 11.776 - un1_b7_nYhI39s_6_0[5] Net - - 0.322 - 1 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b7_nYhI39s_RNO[5] MX2 A In - 12.098 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.b7_nYhI39s_RNO[5] MX2 Y Out 0.579 12.676 - b7_nYhI39s_5[5] Net - - 0.322 - 1 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b7_nYhI39s[5] DFN1 D In - 12.998 - ==================================================================================================================================== Total path delay (propagation time + setup) of 13.571 is 6.560(48.3%) logic and 7.011(51.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 0.573 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.427 - Propagation time: 12.909 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -3.483 Number of logic level(s): 8 Starting point: iice_inst_0.b8_12m_IFLY.b5_nUTGT.b13_nAzGfFM_sLsv3[3] / Q Ending point: iice_inst_0.b8_12m_IFLY.b5_nUTGT.b7_nYhI39s[5] / D The start point is clocked by top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------- iice_inst_0.b8_12m_IFLY.b5_nUTGT.b13_nAzGfFM_sLsv3[3] DFN1C1 Q Out 0.737 0.737 - b13_nAzGfFM_sLsv3[3] Net - - 1.639 - 8 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b11_nUTGT_khWqH.b8_vABZ3qsY_RNIUE2L AO1D A In - 2.376 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.b11_nUTGT_khWqH.b8_vABZ3qsY_RNIUE2L AO1D Y Out 0.480 2.855 - G_17_0 Net - - 0.322 - 1 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b13_nAzGfFM_sLsv3_RNI2HH21[3] AO1D C In - 3.177 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.b13_nAzGfFM_sLsv3_RNI2HH21[3] AO1D Y Out 0.655 3.832 - G_17_1 Net - - 0.322 - 1 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b3_nfs_RNIIDDH1[3] OR2A B In - 4.154 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.b3_nfs_RNIIDDH1[3] OR2A Y Out 0.514 4.668 - N_2_0 Net - - 2.082 - 14 iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_24 OA1B C In - 6.750 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_24 OA1B Y Out 0.487 7.237 - DWACT_ADD_CI_0_g_array_1_0[0] Net - - 0.806 - 3 iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_36 AO1 B In - 8.043 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_36 AO1 Y Out 0.598 8.641 - DWACT_ADD_CI_0_g_array_2_0[0] Net - - 0.806 - 3 iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_30 AO13 B In - 9.447 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_30 AO13 Y Out 0.933 10.381 - DWACT_ADD_CI_0_g_array_12_1_0[0] Net - - 0.322 - 1 iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_21_0 XNOR3 C In - 10.702 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_21_0 XNOR3 Y Out 0.985 11.688 - un1_b7_nYhI39s_6_0[5] Net - - 0.322 - 1 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b7_nYhI39s_RNO[5] MX2 A In - 12.009 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.b7_nYhI39s_RNO[5] MX2 Y Out 0.579 12.588 - b7_nYhI39s_5[5] Net - - 0.322 - 1 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b7_nYhI39s[5] DFN1 D In - 12.909 - ===================================================================================================================================== Total path delay (propagation time + setup) of 13.483 is 6.541(48.5%) logic and 6.941(51.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 0.573 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.427 - Propagation time: 12.892 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -3.465 Number of logic level(s): 8 Starting point: iice_inst_0.b8_12m_IFLY.b5_nUTGT.b13_nAzGfFM_sLsv3[3] / Q Ending point: iice_inst_0.b8_12m_IFLY.b5_nUTGT.b7_nYhI39s[6] / D The start point is clocked by top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------- iice_inst_0.b8_12m_IFLY.b5_nUTGT.b13_nAzGfFM_sLsv3[3] DFN1C1 Q Out 0.737 0.737 - b13_nAzGfFM_sLsv3[3] Net - - 1.639 - 8 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b3_nfs_RNINCPA[0] OR3 C In - 2.376 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.b3_nfs_RNINCPA[0] OR3 Y Out 0.751 3.127 - G_18_2 Net - - 0.322 - 1 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b3_nfs_RNIGSRE[3] OR3 C In - 3.448 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.b3_nfs_RNIGSRE[3] OR3 Y Out 0.751 4.199 - N_1_0_i_0_0 Net - - 0.322 - 1 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b3_nfs_RNIIDDH1[3] OR2A A In - 4.520 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.b3_nfs_RNIIDDH1[3] OR2A Y Out 0.466 4.986 - N_2_0 Net - - 2.082 - 14 iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_24 OA1B C In - 7.068 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_24 OA1B Y Out 0.487 7.555 - DWACT_ADD_CI_0_g_array_1_0[0] Net - - 0.806 - 3 iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_36 AO1 B In - 8.361 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_36 AO1 Y Out 0.598 8.959 - DWACT_ADD_CI_0_g_array_2_0[0] Net - - 0.806 - 3 iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_32 AO1 B In - 9.765 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_32 AO1 Y Out 0.598 10.363 - DWACT_ADD_CI_0_g_array_11_0[0] Net - - 0.322 - 1 iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_22_0 XNOR3 C In - 10.685 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_22_0 XNOR3 Y Out 0.985 11.670 - un1_b7_nYhI39s_6_0[6] Net - - 0.322 - 1 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b7_nYhI39s_RNO[6] MX2 A In - 11.992 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.b7_nYhI39s_RNO[6] MX2 Y Out 0.579 12.570 - b7_nYhI39s_5[6] Net - - 0.322 - 1 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b7_nYhI39s[6] DFN1 D In - 12.892 - ========================================================================================================================= Total path delay (propagation time + setup) of 13.465 is 6.524(48.5%) logic and 6.941(51.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 0.573 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.427 - Propagation time: 12.819 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -3.392 Number of logic level(s): 8 Starting point: iice_inst_0.b8_12m_IFLY.b5_nUTGT.b13_nAzGfFM_sLsv3[3] / Q Ending point: iice_inst_0.b8_12m_IFLY.b5_nUTGT.b7_nYhI39s[5] / D The start point is clocked by top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by top_level|mss_top_0.MSS_CCC_0.mss_top_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------- iice_inst_0.b8_12m_IFLY.b5_nUTGT.b13_nAzGfFM_sLsv3[3] DFN1C1 Q Out 0.737 0.737 - b13_nAzGfFM_sLsv3[3] Net - - 1.639 - 8 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b3_nfs_RNINCPA[0] OR3 C In - 2.376 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.b3_nfs_RNINCPA[0] OR3 Y Out 0.751 3.127 - G_18_2 Net - - 0.322 - 1 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b3_nfs_RNIGSRE[3] OR3 C In - 3.448 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.b3_nfs_RNIGSRE[3] OR3 Y Out 0.751 4.199 - N_1_0_i_0_0 Net - - 0.322 - 1 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b3_nfs_RNIIDDH1[3] OR2A A In - 4.520 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.b3_nfs_RNIIDDH1[3] OR2A Y Out 0.466 4.986 - N_2_0 Net - - 2.082 - 14 iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_35_0 ZOR3 B In - 7.068 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_35_0 ZOR3 Y Out 0.939 8.007 - G_35_0 Net - - 0.322 - 1 iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_36 AO1 A In - 8.328 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_36 AO1 Y Out 0.520 8.848 - DWACT_ADD_CI_0_g_array_2_0[0] Net - - 0.806 - 3 iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_30 AO13 B In - 9.654 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_30 AO13 Y Out 0.636 10.290 - DWACT_ADD_CI_0_g_array_12_1_0[0] Net - - 0.322 - 1 iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_21_0 XNOR3 C In - 10.612 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.un1_b7_nYhI39s_6.G_21_0 XNOR3 Y Out 0.985 11.597 - un1_b7_nYhI39s_6_0[5] Net - - 0.322 - 1 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b7_nYhI39s_RNO[5] MX2 A In - 11.919 - iice_inst_0.b8_12m_IFLY.b5_nUTGT.b7_nYhI39s_RNO[5] MX2 Y Out 0.579 12.497 - b7_nYhI39s_5[5] Net - - 0.322 - 1 iice_inst_0.b8_12m_IFLY.b5_nUTGT.b7_nYhI39s[5] DFN1 D In - 12.819 - ========================================================================================================================= Total path delay (propagation time + setup) of 13.392 is 6.936(51.8%) logic and 6.456(48.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------- mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPSEL mss_top_0_MSS_MASTER_APB_PSELx 0.000 -2.204 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPENABLE CoreAPB3_0_APBmslave0_PENABLE 0.000 -2.169 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPADDR[11] mss_top_0_MSS_MASTER_APB_PADDR_\[11\] 0.000 -1.962 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPADDR[10] mss_top_0_MSS_MASTER_APB_PADDR_\[10\] 0.000 -1.943 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPADDR[8] mss_top_0_MSS_MASTER_APB_PADDR_\[8\] 0.000 -1.928 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPADDR[9] mss_top_0_MSS_MASTER_APB_PADDR_\[9\] 0.000 -1.804 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPWRITE CoreAPB3_0_APBmslave0_PWRITE 0.000 -0.141 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPADDR[2] mss_top_0_MSS_MASTER_APB_PADDR_\[2\] 0.000 1.849 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPADDR[3] mss_top_0_MSS_MASTER_APB_PADDR_\[3\] 0.000 2.000 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPWDATA[0] MSSPWDATA[0] 0.000 7.370 ================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------- mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPRDATA[0] rx_data_reg_RNIAQRN7[0] 10.000 -2.204 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPRDATA[1] rx_data_reg_RNI1Q5Q7[1] 10.000 -2.204 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPRDATA[2] rx_data_reg_RNIOA8U7[2] 10.000 -2.204 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPRDATA[7] rx_data_reg_RNI2T7N7[7] 10.000 -2.204 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPRDATA[4] rx_data_reg_RNICARQ5[3] 10.000 -1.921 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPRDATA[5] rx_data_reg_RNIDARQ5[2] 10.000 -1.921 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPRDATA[6] rx_data_reg_RNIEARQ5[1] 10.000 -1.921 mss_top_0.MSS_ADLIB_INST System MSS_APB MSSPRDATA[3] rx_data_reg_RNIBARQ5[3] 10.000 -1.780 CORESPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.rx_data_waiting System DFN1E1C0 E un1_rx_reg_re 9.392 0.599 CORESPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.tx_reg_empty System DFN1E1P0 E un1_tx_reg_we 9.392 3.439 ================================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 10.000 - Propagation time: 12.204 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -2.204 Number of logic level(s): 7 Starting point: mss_top_0.MSS_ADLIB_INST / MSSPSEL Ending point: mss_top_0.MSS_ADLIB_INST / MSSPRDATA[2] The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- mss_top_0.MSS_ADLIB_INST MSS_APB MSSPSEL Out 0.000 0.000 - mss_top_0_MSS_MASTER_APB_PSELx Net - - 0.322 - 1 CORESPI_0.cpu_re_1_2 NOR2A A In - 0.322 - CORESPI_0.cpu_re_1_2 NOR2A Y Out 0.627 0.949 - cpu_re_1_2 Net - - 0.322 - 1 CORESPI_0.cpu_re_1 OR3C C In - 1.270 - CORESPI_0.cpu_re_1 OR3C Y Out 0.641 1.912 - cpu_re_1_i Net - - 1.184 - 4 CORESPI_0.cpu_re NOR2 B In - 3.095 - CORESPI_0.cpu_re NOR2 Y Out 0.514 3.610 - cpu_re Net - - 2.037 - 13 CORESPI_0.ucorespi_sfr.rx_reg_re OR2B B In - 5.647 - CORESPI_0.ucorespi_sfr.rx_reg_re OR2B Y Out 0.627 6.274 - rx_reg_re Net - - 1.708 - 10 CORESPI_0.ucorespi_sfr.control_reg_RNIUHPS1_0[5] NOR2 A In - 7.982 - CORESPI_0.ucorespi_sfr.control_reg_RNIUHPS1_0[5] NOR2 Y Out 0.363 8.346 - data_out_1 Net - - 1.639 - 8 CORESPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.rx_data_reg_RNI1EQR3[2] AOI1B B In - 9.985 - CORESPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.rx_data_reg_RNI1EQR3[2] AOI1B Y Out 0.911 10.895 - data_out_0_iv_0[2] Net - - 0.322 - 1 CORESPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.rx_data_reg_RNIOA8U7[2] OR3C C In - 11.217 - CORESPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.rx_data_reg_RNIOA8U7[2] OR3C Y Out 0.666 11.882 - rx_data_reg_RNIOA8U7[2] Net - - 0.322 - 1 mss_top_0.MSS_ADLIB_INST MSS_APB MSSPRDATA[2] In - 12.204 - ================================================================================================================================================== Total path delay (propagation time + setup) of 12.204 is 4.350(35.6%) logic and 7.854(64.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 10.000 - Propagation time: 12.204 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -2.204 Number of logic level(s): 7 Starting point: mss_top_0.MSS_ADLIB_INST / MSSPSEL Ending point: mss_top_0.MSS_ADLIB_INST / MSSPRDATA[7] The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- mss_top_0.MSS_ADLIB_INST MSS_APB MSSPSEL Out 0.000 0.000 - mss_top_0_MSS_MASTER_APB_PSELx Net - - 0.322 - 1 CORESPI_0.cpu_re_1_2 NOR2A A In - 0.322 - CORESPI_0.cpu_re_1_2 NOR2A Y Out 0.627 0.949 - cpu_re_1_2 Net - - 0.322 - 1 CORESPI_0.cpu_re_1 OR3C C In - 1.270 - CORESPI_0.cpu_re_1 OR3C Y Out 0.641 1.912 - cpu_re_1_i Net - - 1.184 - 4 CORESPI_0.cpu_re NOR2 B In - 3.095 - CORESPI_0.cpu_re NOR2 Y Out 0.514 3.610 - cpu_re Net - - 2.037 - 13 CORESPI_0.ucorespi_sfr.rx_reg_re OR2B B In - 5.647 - CORESPI_0.ucorespi_sfr.rx_reg_re OR2B Y Out 0.627 6.274 - rx_reg_re Net - - 1.708 - 10 CORESPI_0.ucorespi_sfr.control_reg_RNIUHPS1_0[5] NOR2 A In - 7.982 - CORESPI_0.ucorespi_sfr.control_reg_RNIUHPS1_0[5] NOR2 Y Out 0.363 8.346 - data_out_1 Net - - 1.639 - 8 CORESPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.rx_data_reg_RNIFO1U3[7] AOI1B B In - 9.985 - CORESPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.rx_data_reg_RNIFO1U3[7] AOI1B Y Out 0.911 10.895 - data_out_0_iv_1[7] Net - - 0.322 - 1 CORESPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.rx_data_reg_RNI2T7N7[7] OR3C C In - 11.217 - CORESPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.rx_data_reg_RNI2T7N7[7] OR3C Y Out 0.666 11.882 - rx_data_reg_RNI2T7N7[7] Net - - 0.322 - 1 mss_top_0.MSS_ADLIB_INST MSS_APB MSSPRDATA[7] In - 12.204 - ================================================================================================================================================== Total path delay (propagation time + setup) of 12.204 is 4.350(35.6%) logic and 7.854(64.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 10.000 - Propagation time: 12.204 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -2.204 Number of logic level(s): 7 Starting point: mss_top_0.MSS_ADLIB_INST / MSSPSEL Ending point: mss_top_0.MSS_ADLIB_INST / MSSPRDATA[1] The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- mss_top_0.MSS_ADLIB_INST MSS_APB MSSPSEL Out 0.000 0.000 - mss_top_0_MSS_MASTER_APB_PSELx Net - - 0.322 - 1 CORESPI_0.cpu_re_1_2 NOR2A A In - 0.322 - CORESPI_0.cpu_re_1_2 NOR2A Y Out 0.627 0.949 - cpu_re_1_2 Net - - 0.322 - 1 CORESPI_0.cpu_re_1 OR3C C In - 1.270 - CORESPI_0.cpu_re_1 OR3C Y Out 0.641 1.912 - cpu_re_1_i Net - - 1.184 - 4 CORESPI_0.cpu_re NOR2 B In - 3.095 - CORESPI_0.cpu_re NOR2 Y Out 0.514 3.610 - cpu_re Net - - 2.037 - 13 CORESPI_0.ucorespi_sfr.rx_reg_re OR2B B In - 5.647 - CORESPI_0.ucorespi_sfr.rx_reg_re OR2B Y Out 0.627 6.274 - rx_reg_re Net - - 1.708 - 10 CORESPI_0.ucorespi_sfr.control_reg_RNIUHPS1_0[5] NOR2 A In - 7.982 - CORESPI_0.ucorespi_sfr.control_reg_RNIUHPS1_0[5] NOR2 Y Out 0.363 8.346 - data_out_1 Net - - 1.639 - 8 CORESPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.rx_data_reg_RNIFO1U3[1] AOI1B B In - 9.985 - CORESPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.rx_data_reg_RNIFO1U3[1] AOI1B Y Out 0.911 10.895 - data_out_0_iv_1[1] Net - - 0.322 - 1 CORESPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.rx_data_reg_RNI1Q5Q7[1] OR3C C In - 11.217 - CORESPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.rx_data_reg_RNI1Q5Q7[1] OR3C Y Out 0.666 11.882 - rx_data_reg_RNI1Q5Q7[1] Net - - 0.322 - 1 mss_top_0.MSS_ADLIB_INST MSS_APB MSSPRDATA[1] In - 12.204 - ================================================================================================================================================== Total path delay (propagation time + setup) of 12.204 is 4.350(35.6%) logic and 7.854(64.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 10.000 - Propagation time: 12.204 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -2.204 Number of logic level(s): 7 Starting point: mss_top_0.MSS_ADLIB_INST / MSSPSEL Ending point: mss_top_0.MSS_ADLIB_INST / MSSPRDATA[0] The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- mss_top_0.MSS_ADLIB_INST MSS_APB MSSPSEL Out 0.000 0.000 - mss_top_0_MSS_MASTER_APB_PSELx Net - - 0.322 - 1 CORESPI_0.cpu_re_1_2 NOR2A A In - 0.322 - CORESPI_0.cpu_re_1_2 NOR2A Y Out 0.627 0.949 - cpu_re_1_2 Net - - 0.322 - 1 CORESPI_0.cpu_re_1 OR3C C In - 1.270 - CORESPI_0.cpu_re_1 OR3C Y Out 0.641 1.912 - cpu_re_1_i Net - - 1.184 - 4 CORESPI_0.cpu_re NOR2 B In - 3.095 - CORESPI_0.cpu_re NOR2 Y Out 0.514 3.610 - cpu_re Net - - 2.037 - 13 CORESPI_0.ucorespi_sfr.rx_reg_re OR2B B In - 5.647 - CORESPI_0.ucorespi_sfr.rx_reg_re OR2B Y Out 0.627 6.274 - rx_reg_re Net - - 1.708 - 10 CORESPI_0.ucorespi_sfr.control_reg_RNIUHPS1_0[5] NOR2 A In - 7.982 - CORESPI_0.ucorespi_sfr.control_reg_RNIUHPS1_0[5] NOR2 Y Out 0.363 8.346 - data_out_1 Net - - 1.639 - 8 CORESPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.rx_data_reg_RNITDQR3[0] AOI1B B In - 9.985 - CORESPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.rx_data_reg_RNITDQR3[0] AOI1B Y Out 0.911 10.895 - data_out_0_iv_0[0] Net - - 0.322 - 1 CORESPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.rx_data_reg_RNIAQRN7[0] OR3C C In - 11.217 - CORESPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.rx_data_reg_RNIAQRN7[0] OR3C Y Out 0.666 11.882 - rx_data_reg_RNIAQRN7[0] Net - - 0.322 - 1 mss_top_0.MSS_ADLIB_INST MSS_APB MSSPRDATA[0] In - 12.204 - ================================================================================================================================================== Total path delay (propagation time + setup) of 12.204 is 4.350(35.6%) logic and 7.854(64.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 10.000 - Propagation time: 12.169 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -2.169 Number of logic level(s): 7 Starting point: mss_top_0.MSS_ADLIB_INST / MSSPENABLE Ending point: mss_top_0.MSS_ADLIB_INST / MSSPRDATA[2] The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- mss_top_0.MSS_ADLIB_INST MSS_APB MSSPENABLE Out 0.000 0.000 - CoreAPB3_0_APBmslave0_PENABLE Net - - 0.322 - 1 CORESPI_0.cpu_re_1_0 NOR2A A In - 0.322 - CORESPI_0.cpu_re_1_0 NOR2A Y Out 0.627 0.949 - cpu_re_1_0 Net - - 0.322 - 1 CORESPI_0.cpu_re_1 OR3C B In - 1.270 - CORESPI_0.cpu_re_1 OR3C Y Out 0.607 1.877 - cpu_re_1_i Net - - 1.184 - 4 CORESPI_0.cpu_re NOR2 B In - 3.061 - CORESPI_0.cpu_re NOR2 Y Out 0.514 3.575 - cpu_re Net - - 2.037 - 13 CORESPI_0.ucorespi_sfr.rx_reg_re OR2B B In - 5.612 - CORESPI_0.ucorespi_sfr.rx_reg_re OR2B Y Out 0.627 6.239 - rx_reg_re Net - - 1.708 - 10 CORESPI_0.ucorespi_sfr.control_reg_RNIUHPS1_0[5] NOR2 A In - 7.948 - CORESPI_0.ucorespi_sfr.control_reg_RNIUHPS1_0[5] NOR2 Y Out 0.363 8.311 - data_out_1 Net - - 1.639 - 8 CORESPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.rx_data_reg_RNI1EQR3[2] AOI1B B In - 9.950 - CORESPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.rx_data_reg_RNI1EQR3[2] AOI1B Y Out 0.911 10.861 - data_out_0_iv_0[2] Net - - 0.322 - 1 CORESPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.rx_data_reg_RNIOA8U7[2] OR3C C In - 11.182 - CORESPI_0.ucorespi_sfr.genblk10\.genblk11\.u_slave.rx_data_reg_RNIOA8U7[2] OR3C Y Out 0.666 11.848 - rx_data_reg_RNIOA8U7[2] Net - - 0.322 - 1 mss_top_0.MSS_ADLIB_INST MSS_APB MSSPRDATA[2] In - 12.169 - ================================================================================================================================================== Total path delay (propagation time + setup) of 12.169 is 4.315(35.5%) logic and 7.854(64.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Target Part: AFS090_FBGA256_Std Report for cell top_level.verilog Core Cell usage: cell count area count*area AND2 5 1.0 5.0 AO1 25 1.0 25.0 AO13 2 1.0 2.0 AO1A 2 1.0 2.0 AO1B 1 1.0 1.0 AO1D 3 1.0 3.0 AOI1 1 1.0 1.0 AOI1B 27 1.0 27.0 AX1B 4 1.0 4.0 BUFF 2 1.0 2.0 CLKINT 3 0.0 0.0 GND 29 0.0 0.0 INV 2 1.0 2.0 MSSINT 1 0.0 0.0 MSS_APB 1 0.0 0.0 MSS_CCC 1 0.0 0.0 MX2 102 1.0 102.0 MX2C 6 1.0 6.0 NOR2 15 1.0 15.0 NOR2A 20 1.0 20.0 NOR2B 51 1.0 51.0 NOR3 1 1.0 1.0 NOR3A 8 1.0 8.0 NOR3B 18 1.0 18.0 NOR3C 16 1.0 16.0 OA1 2 1.0 2.0 OA1B 4 1.0 4.0 OAI1 6 1.0 6.0 OR2 10 1.0 10.0 OR2A 10 1.0 10.0 OR2B 21 1.0 21.0 OR3 7 1.0 7.0 OR3A 3 1.0 3.0 OR3B 17 1.0 17.0 OR3C 27 1.0 27.0 VCC 29 0.0 0.0 XA1 1 1.0 1.0 XA1A 5 1.0 5.0 XA1B 3 1.0 3.0 XNOR2 5 1.0 5.0 XNOR3 5 1.0 5.0 XO1 1 1.0 1.0 XOR2 8 1.0 8.0 XOR3 1 1.0 1.0 ZOR3 2 1.0 2.0 ZOR3I 4 1.0 4.0 DFN1 96 1.0 96.0 DFN1C0 3 1.0 3.0 DFN1C1 16 1.0 16.0 DFN1E0 38 1.0 38.0 DFN1E0C0 1 1.0 1.0 DFN1E1 40 1.0 40.0 DFN1E1C0 42 1.0 42.0 DFN1E1C1 1 1.0 1.0 DFN1E1P0 2 1.0 2.0 DFN1P0 1 1.0 1.0 DFN1P1 1 1.0 1.0 RAM512X18 1 0.0 0.0 ----- ---------- TOTAL 759 694.0 IO Cell usage: cell count BIBUF_MSS 21 BIBUF_OPEND_MSS 4 INBUF 3 INBUF_MSS 9 MSS_XTLOSC 1 OUTBUF 1 OUTBUF_MSS 40 TRIBUFF_MSS 2 UJTAG 1 ----- TOTAL 82 Core Cells : 694 of 2304 (30%) IO Cells : 82 of 75 (109%) RAM/ROM Usage Summary Block Rams : 1 of 6 (16%) Mapper successful! Process took 0h:00m:02s realtime, 0h:00m:02s cputime # Tue Aug 17 14:54:09 2010 ###########################################################] $ Running Identify Instrumentor. See log file: @N: : identify.log | #Tue Aug 17 14:59:29 2010