#-- Synopsys, Inc.
#-- Version D-2009.12A
#-- Project file D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\synthesis\synthesis_1\run_options.txt
#-- Written on Tue Aug 17 14:54:00 2010


#project files
add_file -verilog "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/component/Actel/SmartFusionMSS/MSS/2.2.101/mss_comps.v"
add_file -verilog "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/component/work/mss_top/MSS_CCC_0/mss_top_tmp_MSS_CCC_0_MSS_CCC.v"
add_file -verilog "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/component/work/mss_top/mss_top.v"
add_file -verilog "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/component/Actel/DirectCore/CORESPI/3.0.156/rtl/vlog/core/spi_master.v"
add_file -verilog "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/component/Actel/DirectCore/CORESPI/3.0.156/rtl/vlog/core/spi_slave.v"
add_file -verilog "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/component/Actel/DirectCore/CORESPI/3.0.156/rtl/vlog/core/corespi_sfr.v"
add_file -verilog "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/component/Actel/DirectCore/CORESPI/3.0.156/rtl/vlog/core/corespi.v"
add_file -verilog -lib COREAPB3_LIB "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/component/Actel/DirectCore/CoreAPB3/3.0.103/rtl/vlog/core/coreapb3_muxptob3.v"
add_file -verilog -lib COREAPB3_LIB "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/component/Actel/DirectCore/CoreAPB3/3.0.103/rtl/vlog/core/coreapb3.v"
add_file -verilog "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/component/work/top_level/top_level.v"


#implementation: "synthesis_1"
impl -add synthesis_1 -type fpga

#
#implementation attributes

set_option -vlog_std v2001

#par_1 attributes
set_option -job par_1 -add par
set_option -job par_1 -option run_backannotation 0

#device options
set_option -technology Fusion
set_option -part AFS090
set_option -package FBGA256
set_option -speed_grade Std
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top_level"

# mapper_options
set_option -frequency 100.000
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -identify_debug_mode 1

# Actel 500K
set_option -run_prop_extract 1
set_option -maxfan 24
set_option -maxfan_hard3 0
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -report_path 0
set_option -opcond COMWC
set_option -update_models_cp 0
set_option -preserve_registers 0

# Actel 500K
set_option -globalthreshold 50

# NFilter
set_option -popfeed 0
set_option -constprop 0
set_option -createhierarchy 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./synthesis_1/top_level.edn"
impl -active "synthesis_1"
