"D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/component/Actel/SmartFusionMSS/MSS/2.2.101/mss_comps.v" "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/synthesis/synthesis_1/instr_sources/Actel/SmartFusionMSS/MSS/2.2.101/mss_comps.v"
"D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/component/work/mss_top/MSS_CCC_0/mss_top_tmp_MSS_CCC_0_MSS_CCC.v" "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/synthesis/synthesis_1/instr_sources/work/mss_top/MSS_CCC_0/mss_top_tmp_MSS_CCC_0_MSS_CCC.v"
"D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/component/work/mss_top/mss_top.v" "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/synthesis/synthesis_1/instr_sources/work/mss_top/mss_top.v"
"D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/component/Actel/DirectCore/CORESPI/3.0.156/rtl/vlog/core/spi_master.v" "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/synthesis/synthesis_1/instr_sources/Actel/DirectCore/CORESPI/3.0.156/rtl/vlog/core/spi_master.v"
"D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/component/Actel/DirectCore/CORESPI/3.0.156/rtl/vlog/core/spi_slave.v" "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/synthesis/synthesis_1/instr_sources/Actel/DirectCore/CORESPI/3.0.156/rtl/vlog/core/spi_slave.v"
"D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/component/Actel/DirectCore/CORESPI/3.0.156/rtl/vlog/core/corespi_sfr.v" "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/synthesis/synthesis_1/instr_sources/Actel/DirectCore/CORESPI/3.0.156/rtl/vlog/core/corespi_sfr.v"
"D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/component/Actel/DirectCore/CORESPI/3.0.156/rtl/vlog/core/corespi.v" "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/synthesis/synthesis_1/instr_sources/Actel/DirectCore/CORESPI/3.0.156/rtl/vlog/core/corespi.v"
"D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/component/Actel/DirectCore/CoreAPB3/3.0.103/rtl/vlog/core/coreapb3_muxptob3.v" "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/synthesis/synthesis_1/instr_sources/Actel/DirectCore/CoreAPB3/3.0.103/rtl/vlog/core/coreapb3_muxptob3.v"
"D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/component/Actel/DirectCore/CoreAPB3/3.0.103/rtl/vlog/core/coreapb3.v" "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/synthesis/synthesis_1/instr_sources/Actel/DirectCore/CoreAPB3/3.0.103/rtl/vlog/core/coreapb3.v"
"D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/component/work/top_level/top_level.v" "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/synthesis/synthesis_1/instr_sources/work/top_level/top_level.v"
