@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 
@N: MF547 |Generated clock conversion disabled 
@N: MO106 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":217:8:217:11|Found ROM, 'sck_enable', 11 words by 1 bits 
@N: BN362 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":421:4:421:9|Removing sequential instance rx_shift_enable2 of view:PrimLib.dffr(prim) in hierarchy view:work.spi_master(verilog) because there are no references to its outputs 
@N: BN362 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":457:4:457:9|Removing sequential instance SPI_0.ucorespi_sfr.genblk4\.u_master.tx_shift_reg[7] of view:PrimLib.dffr(prim) in hierarchy view:work.top_level(verilog) because there are no references to its outputs 
@N: BN362 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":457:4:457:9|Removing sequential instance SPI_0.ucorespi_sfr.genblk4\.u_master.tx_shift_reg[6] of view:PrimLib.dffr(prim) in hierarchy view:work.top_level(verilog) because there are no references to its outputs 
@N: BN362 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":457:4:457:9|Removing sequential instance SPI_0.ucorespi_sfr.genblk4\.u_master.tx_shift_reg[5] of view:PrimLib.dffr(prim) in hierarchy view:work.top_level(verilog) because there are no references to its outputs 
@N: BN362 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":457:4:457:9|Removing sequential instance SPI_0.ucorespi_sfr.genblk4\.u_master.tx_shift_reg[4] of view:PrimLib.dffr(prim) in hierarchy view:work.top_level(verilog) because there are no references to its outputs 
@N: BN362 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":457:4:457:9|Removing sequential instance SPI_0.ucorespi_sfr.genblk4\.u_master.tx_shift_reg[3] of view:PrimLib.dffr(prim) in hierarchy view:work.top_level(verilog) because there are no references to its outputs 
@N: BN362 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":457:4:457:9|Removing sequential instance SPI_0.ucorespi_sfr.genblk4\.u_master.tx_shift_reg[2] of view:PrimLib.dffr(prim) in hierarchy view:work.top_level(verilog) because there are no references to its outputs 
@N: BN362 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":457:4:457:9|Removing sequential instance SPI_0.ucorespi_sfr.genblk4\.u_master.tx_shift_reg[1] of view:PrimLib.dffr(prim) in hierarchy view:work.top_level(verilog) because there are no references to its outputs 
@N: BN362 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":457:4:457:9|Removing sequential instance SPI_0.ucorespi_sfr.genblk4\.u_master.tx_shift_reg[0] of view:PrimLib.dffr(prim) in hierarchy view:work.top_level(verilog) because there are no references to its outputs 
@N: BN362 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":161:4:161:9|Removing sequential instance SPI_0.ucorespi_sfr.genblk4\.u_master.tsck of view:PrimLib.dffr(prim) in hierarchy view:work.top_level(verilog) because there are no references to its outputs 
@N: BN362 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":457:4:457:9|Removing sequential instance SPI_0.ucorespi_sfr.genblk4\.u_master.mosi of view:PrimLib.dffr(prim) in hierarchy view:work.top_level(verilog) because there are no references to its outputs 
@N: FP130 |Promoting Net SPI_0.ucorespi_sfr.control_reg[5] on CLKINT  I_70 
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
