Timing Report Min Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Mon Jan 02 11:57:46 2012


Design: top_level
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                10.413
Frequency (MHz):            96.034
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                9.710
Frequency (MHz):            102.987
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        5.718
External Hold (ns):         -1.709
Min Clock-To-Out (ns):      4.120
Max Clock-To-Out (ns):      9.461

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.661
External Hold (ns):         1.288
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_macclk
Period (ns):                25.000
Frequency (MHz):            40.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[4]
  Delay (ns):                  3.854
  Slack (ns):
  Arrival (ns):                3.854
  Required (ns):
  Hold (ns):                   1.313

Path 2
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[1]
  Delay (ns):                  4.071
  Slack (ns):
  Arrival (ns):                4.071
  Required (ns):
  Hold (ns):                   1.334

Path 3
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[5]
  Delay (ns):                  4.100
  Slack (ns):
  Arrival (ns):                4.100
  Required (ns):
  Hold (ns):                   1.313

Path 4
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[2]
  Delay (ns):                  4.228
  Slack (ns):
  Arrival (ns):                4.228
  Required (ns):
  Hold (ns):                   1.335

Path 5
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0]
  Delay (ns):                  4.257
  Slack (ns):
  Arrival (ns):                4.257
  Required (ns):
  Hold (ns):                   1.335


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[4]
  data arrival time                              3.854
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     1.282          cell: ADLIB:MSS_APB_IP
  1.282                        mss_top_0/MSS_ADLIB_INST/U_CORE:MSSPWRITE (r)
               +     0.061          net: mss_top_0/MSS_ADLIB_INST/MSSPWRITEINT_NET
  1.343                        mss_top_0/MSS_ADLIB_INST/U_42:PIN3INT (r)
               +     0.040          cell: ADLIB:MSS_IF
  1.383                        mss_top_0/MSS_ADLIB_INST/U_42:PIN3 (r)
               +     0.573          net: CoreAPB3_0_APBmslave0_PWRITE
  1.956                        SPI_0/cpu_re_0:C (r)
               +     0.297          cell: ADLIB:NOR3
  2.253                        SPI_0/cpu_re_0:Y (f)
               +     0.142          net: SPI_0/cpu_re_0
  2.395                        SPI_0/cpu_re:A (f)
               +     0.199          cell: ADLIB:OR3A
  2.594                        SPI_0/cpu_re:Y (r)
               +     0.138          net: SPI_0/cpu_re
  2.732                        SPI_0/ucorespi_sfr/genblk6.u_slave/rx_data_reg_RNIDLMK3[27]:B (r)
               +     0.202          cell: ADLIB:NOR3A
  2.934                        SPI_0/ucorespi_sfr/genblk6.u_slave/rx_data_reg_RNIDLMK3[27]:Y (f)
               +     0.629          net: SPI_0_ucorespi_sfr_N_75_i_0
  3.563                        mss_top_0/MSS_ADLIB_INST/U_38:PIN5 (f)
               +     0.046          cell: ADLIB:MSS_IF
  3.609                        mss_top_0/MSS_ADLIB_INST/U_38:PIN5INT (f)
               +     0.245          net: mss_top_0/MSS_ADLIB_INST/MSSPRDATA[4]INT_NET
  3.854                        mss_top_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[4] (f)
                                    
  3.854                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_fabric_interface_clock
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     1.313          Library hold time: ADLIB:MSS_APB_IP
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[4]


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        SPI_0/ucorespi_sfr/genblk6.u_slave/i_ss/U1:CLK
  To:                          SPI_0/ucorespi_sfr/genblk6.u_slave/di_ss:D
  Delay (ns):                  0.662
  Slack (ns):
  Arrival (ns):                1.002
  Required (ns):
  Hold (ns):                   0.000

Path 2
  From:                        SPI_0/ucorespi_sfr/genblk6.u_slave/rx_data_reg[22]/U1:CLK
  To:                          SPI_0/ucorespi_sfr/genblk6.u_slave/rx_data_reg[22]/U1:D
  Delay (ns):                  0.790
  Slack (ns):
  Arrival (ns):                1.159
  Required (ns):
  Hold (ns):                   0.000

Path 3
  From:                        SPI_0/ucorespi_sfr/genblk6.u_slave/rx_data_reg[13]/U1:CLK
  To:                          SPI_0/ucorespi_sfr/genblk6.u_slave/rx_data_reg[13]/U1:D
  Delay (ns):                  0.792
  Slack (ns):
  Arrival (ns):                1.161
  Required (ns):
  Hold (ns):                   0.000

Path 4
  From:                        SPI_0/ucorespi_sfr/genblk6.u_slave/rx_data_reg[10]/U1:CLK
  To:                          SPI_0/ucorespi_sfr/genblk6.u_slave/rx_data_reg[10]/U1:D
  Delay (ns):                  0.792
  Slack (ns):
  Arrival (ns):                1.161
  Required (ns):
  Hold (ns):                   0.000

Path 5
  From:                        SPI_0/ucorespi_sfr/genblk6.u_slave/rx_data_reg[17]/U1:CLK
  To:                          SPI_0/ucorespi_sfr/genblk6.u_slave/rx_data_reg[17]/U1:D
  Delay (ns):                  0.792
  Slack (ns):
  Arrival (ns):                1.161
  Required (ns):
  Hold (ns):                   0.000


Expanded Path 1
  From: SPI_0/ucorespi_sfr/genblk6.u_slave/i_ss/U1:CLK
  To: SPI_0/ucorespi_sfr/genblk6.u_slave/di_ss:D
  data arrival time                              1.002
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.340          net: FAB_CLK
  0.340                        SPI_0/ucorespi_sfr/genblk6.u_slave/i_ss/U1:CLK (r)
               +     0.249          cell: ADLIB:DFN1P0
  0.589                        SPI_0/ucorespi_sfr/genblk6.u_slave/i_ss/U1:Q (r)
               +     0.413          net: SPI_0/ucorespi_sfr/genblk6_u_slave/i_ss
  1.002                        SPI_0/ucorespi_sfr/genblk6.u_slave/di_ss:D (r)
                                    
  1.002                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  N/C                          mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.354          net: FAB_CLK
  N/C                          SPI_0/ucorespi_sfr/genblk6.u_slave/di_ss:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          SPI_0/ucorespi_sfr/genblk6.u_slave/di_ss:D


END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        s_mosi
  To:                          SPI_0/ucorespi_sfr/genblk6.u_slave/t_mosi/U1:D
  Delay (ns):                  2.096
  Slack (ns):
  Arrival (ns):                2.096
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -1.709

Path 2
  From:                        s_ss
  To:                          SPI_0/ucorespi_sfr/genblk6.u_slave/t_ss:D
  Delay (ns):                  2.350
  Slack (ns):
  Arrival (ns):                2.350
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -1.951

Path 3
  From:                        s_sck
  To:                          SPI_0/ucorespi_sfr/genblk6.u_slave/i_sck/U1:D
  Delay (ns):                  2.739
  Slack (ns):
  Arrival (ns):                2.739
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -2.333


Expanded Path 1
  From: s_mosi
  To: SPI_0/ucorespi_sfr/genblk6.u_slave/t_mosi/U1:D
  data arrival time                              2.096
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        s_mosi (f)
               +     0.000          net: s_mosi
  0.000                        s_mosi_pad/U0/U0:PAD (f)
               +     0.277          cell: ADLIB:IOPAD_IN
  0.277                        s_mosi_pad/U0/U0:Y (f)
               +     0.000          net: s_mosi_pad/U0/NET1
  0.277                        s_mosi_pad/U0/U1:YIN (f)
               +     0.017          cell: ADLIB:IOIN_IB
  0.294                        s_mosi_pad/U0/U1:Y (f)
               +     1.385          net: s_mosi_c
  1.679                        SPI_0/ucorespi_sfr/genblk6.u_slave/t_mosi/U0:A (f)
               +     0.269          cell: ADLIB:MX2
  1.948                        SPI_0/ucorespi_sfr/genblk6.u_slave/t_mosi/U0:Y (f)
               +     0.148          net: SPI_0/ucorespi_sfr/genblk6_u_slave/t_mosi/Y
  2.096                        SPI_0/ucorespi_sfr/genblk6.u_slave/t_mosi/U1:D (f)
                                    
  2.096                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  N/C                          mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.387          net: FAB_CLK
  N/C                          SPI_0/ucorespi_sfr/genblk6.u_slave/t_mosi/U1:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          SPI_0/ucorespi_sfr/genblk6.u_slave/t_mosi/U1:D


END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        SPI_0/ucorespi_sfr/genblk6.u_slave/rxtx_shift_reg[31]/U1:CLK
  To:                          s_miso
  Delay (ns):                  3.780
  Slack (ns):
  Arrival (ns):                4.120
  Required (ns):
  Clock to Out (ns):           4.120


Expanded Path 1
  From: SPI_0/ucorespi_sfr/genblk6.u_slave/rxtx_shift_reg[31]/U1:CLK
  To: s_miso
  data arrival time                              4.120
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.340          net: FAB_CLK
  0.340                        SPI_0/ucorespi_sfr/genblk6.u_slave/rxtx_shift_reg[31]/U1:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  0.589                        SPI_0/ucorespi_sfr/genblk6.u_slave/rxtx_shift_reg[31]/U1:Q (r)
               +     2.164          net: s_miso_c
  2.753                        s_miso_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  3.032                        s_miso_pad/U0/U1:DOUT (r)
               +     0.000          net: s_miso_pad/U0/NET1
  3.032                        s_miso_pad/U0/U0:D (r)
               +     1.088          cell: ADLIB:IOPAD_TRI
  4.120                        s_miso_pad/U0/U0:PAD (r)
               +     0.000          net: s_miso
  4.120                        s_miso (r)
                                    
  4.120                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
                                    
  N/C                          s_miso (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.277
  Slack (ns):
  Arrival (ns):                0.277
  Required (ns):
  Hold (ns):                   1.294
  External Hold (ns):          1.288


Expanded Path 1
  From: MSS_RESET_N
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.277
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        mss_top_0/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.277          cell: ADLIB:IOPAD_IN
  0.277                        mss_top_0/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: mss_top_0/MSS_RESET_0_MSS_RESET_N_Y
  0.277                        mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.277                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.271          net: mss_top_0/GLA0
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.294          Library hold time: ADLIB:MSS_APB_IP
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_macclk

Info: The maximum frequency of this clock domain is limited by the period of pin mss_top_0/MSS_ADLIB_INST/U_CORE:MACCLKCCC

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

