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                            Global Usage Report
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Product: Designer
Release: v10.0
Version: 10.0.9.37
Date: Mon Jan 02 11:57:38 2012
Design Name: top_level  Family: SmartFusion  Die: A2F500M3G  Package: 484 FBGA
Design State: Post-Layout

The following nets have been routed to a chip global resource:

    Fanout            Name
    ----------------------
    155               Net   : FAB_CLK
                      Driver: mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1
    68                Net   : SPI_0/ucorespi_sfr/control_reg[5]
                      Driver: SPI_0/ucorespi_sfr/control_reg_RNIA8U[5]/U_CLKSRC/U_GL




