-- tb_temp_usb_slave.vhd

-- TB_EBI2_slave.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library smartfusion;

entity tb_temp_usb_slave is
end;

architecture tb_temp_usb_slave of tb_temp_usb_slave is 

  component usb_slave is
  port (USB_CLK           : in std_logic;
		RESET_N           : in std_logic;
        R_W_N             : in std_logic;
        USB_DATA_PAD      : inout std_logic_vector(7 downto 0);
        HCLK              : in    std_logic;
        HTRANS            : out   std_logic_vector(1 downto 0);
        HSIZE             : out   std_logic_vector(1 downto 0);
        HWRITE            : out   std_logic;
        HWDATA            : out   std_logic_vector(31 downto 0);
        HADDR             : out   std_logic_vector(31 downto 0);
        HMASTLOCK         : out   std_logic;
        HREADY            : out   std_logic;
        HSEL              : out   std_logic;
        HREADYOUT         : in    std_logic;
        HRESP             : in    std_logic;
        HRDATA            : in    std_logic_vector(31 downto 0);
        FABINT            : out   std_logic;
        SEND_DATA_BIT     : out   std_logic;
        FIFO_EMPTY_BIT    : out   std_logic;
        FIFO_DATA         : out   std_logic_vector(7 downto 0);
        USB_CLK_OUT       : out   std_logic
        );
    end component;

 component BIBUF_LVCMOS33U is
    port (D     : in std_logic;
          E     : in std_logic;
          Y     : out std_logic;
          PAD   : inout std_logic
         );	
	end component;
  --signal status_interrupt : std_logic;
  signal  USB_CLK  : std_logic := '1';
  signal  HCLK     : std_logic := '0';
  signal  RESET_N  : std_logic := '0';
  signal  R_W_N    : std_logic := '1';
  signal  DATA     : std_logic_vector(7 downto 0) :=(others => ('0'));
  signal  USB_DATA_PAD     : std_logic_vector(7 downto 0) :=(others => ('0'));
  signal      HTRANS            :    std_logic_vector(1 downto 0);
  signal      HSIZE             :    std_logic_vector(1 downto 0);
  signal      HWRITE            :    std_logic;
  signal      HWDATA            :    std_logic_vector(31 downto 0);
  signal      HADDR             :    std_logic_vector(31 downto 0);
  signal      HMASTLOCK         :    std_logic;
  signal      HREADY            :    std_logic;
  signal      HSEL              :    std_logic;
  signal      HREADYOUT         :     std_logic := '1';
  signal      HRESP             :     std_logic;
  signal      HRDATA            :     std_logic_vector(31 downto 0);
  signal      FABINT            :     std_logic;
  signal      SEND_DATA_BIT     :     std_logic;
  signal      FIFO_EMPTY_BIT    :     std_logic;
  signal      FIFO_DATA         :     std_logic_vector(7 downto 0);


  signal tb_op_enable           :     std_logic;
  signal USB_CLK_OUT            :     std_logic;
  
begin
 --TB_GEN: for i in 0 to 7 generate
   --    TB_DATA_PINS : BIBUF_LVCMOS33U port map(D           => DATA(i),
     --                                       E           => tb_op_enable,
       --                                     Y           => open,
         --                                   PAD         => USB_DATA_PAD(i)
           --                                ); 
	--end generate TB_GEN;
   DUT:usb_slave
   port map(
     USB_CLK => USB_CLK,
     HCLK    => HCLK,   
	 RESET_N => RESET_N,
	 R_W_N    => R_W_N,
     USB_DATA_PAD    => DATA,
     HTRANS            =>HTRANS,
     HSIZE             =>HSIZE,
     HWRITE            =>HWRITE,
     HWDATA            =>HWDATA,
     HADDR             =>HADDR,
     HMASTLOCK         =>HMASTLOCK,
     HREADY            =>HREADY,
     HSEL              =>HSEL,
     HREADYOUT         =>HREADYOUT,
     HRESP             =>HRESP,
     HRDATA            =>HRDATA,
     FABINT            => FABINT,
     SEND_DATA_BIT     => SEND_DATA_BIT,
     FIFO_EMPTY_BIT    => FIFO_EMPTY_BIT,
     FIFO_DATA         => FIFO_DATA,
     USB_CLK_OUT       => USB_CLK_OUT
  );


			 
   --REF_CLK <= not REF_CLK after 100 ns;
     HCLK <= not HCLK after 6.25 ns;
       --HCLK <= not HCLK after 1 ns;   
   WR_PROC: process
   begin
     wait for 750 ns;
     RESET_N <='1';
     wait for 750 ns;
     tb_op_enable <= '1';
     R_W_N <= '0';
     DATA <= conv_std_logic_vector(1,8);
     wait for 20 ns; 
     USB_CLK <= not USB_CLK;
     wait for 20 ns; 
     USB_CLK <= not USB_CLK;
     for i in 2 to 2048 loop
       --W_ADDR <= conv_std_logic_vector(i,11);
       wait for 20 ns; 
       USB_CLK <= not USB_CLK;
       DATA <= conv_std_logic_vector(i,8);
       wait for 20 ns; 
       USB_CLK <= not USB_CLK;
     end loop;
     wait for 1ms;
     for i in 2 to 2048 loop
       --W_ADDR <= conv_std_logic_vector(i,11);
       wait for 20 ns; 
       USB_CLK <= not USB_CLK;
       DATA <= conv_std_logic_vector(i,8);
       wait for 20 ns; 
       USB_CLK <= not USB_CLK;
     end loop;

      wait;
   end process;

   --RD_PROC: process
   --begin
     --wait until INTRPT'event and INTRPT = '1';
     --for i in 0 to 1023 loop
       --tb_op_enable <= '1';
	   --wait until HCLK'event and HCLK = '1';
       --PWRITE <= '0';
       --PSEL <= '1';
       --wait until HCLK'event and HCLK = '1';
       --PENABLE <= '1';
       --wait until HCLK'event and HCLK = '1';
       --PENABLE <= '0';
       --PWRITE <= '1';
       --PSEL <= '0';
       --wait for 1 ns;
     --end loop;
      --wait for 1 ns;
   --end process;
      
end;