-- tb_temp_usb_slave.vhd

-- TB_EBI2_slave.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library smartfusion;

entity tb_temp_usb_slave is
end;

architecture tb_temp_usb_slave of tb_temp_usb_slave is 

  component usb_slave is
    port (USB_CLK  : in    std_logic;
          HCLK     : in std_logic;
	      RESET_N  : in std_logic;
          R_W_N    : in std_logic;
          USB_DATA_PAD      : in std_logic_vector(7 downto 0);
          W_ADDR   : in std_logic_vector(10 downto 0)
         );
    end component;

 component BIBUF_LVCMOS33U is
    port (D     : in std_logic;
          E     : in std_logic;
          Y     : out std_logic;
          PAD   : inout std_logic
         );	
	end component;
  signal status_interrupt : std_logic;
  signal  USB_CLK  : std_logic := '0';
  signal  HCLK     : std_logic := '0';
  signal  RESET_N  : std_logic := '0';
  signal  R_W_N    : std_logic := '1';
  signal  W_ADDR     : std_logic_vector(10 downto 0);
  signal  DATA     : std_logic_vector(7 downto 0) :=(others => ('0'));
  signal  USB_DATA_PAD     : std_logic_vector(7 downto 0) :=(others => ('0'));

  signal tb_op_enable : std_logic;
  
begin
 --TB_GEN: for i in 0 to 7 generate
   --    TB_DATA_PINS : BIBUF_LVCMOS33U port map(D           => DATA(i),
     --                                       E           => tb_op_enable,
       --                                     Y           => open,
         --                                   PAD         => USB_DATA_PAD(i)
           --                                ); 
	--end generate TB_GEN;
   DUT:usb_slave
   port map(
     USB_CLK => USB_CLK,
     HCLK    => HCLK,   
	 RESET_N => RESET_N,
	 R_W_N    => R_W_N,
     USB_DATA_PAD    => DATA,
     W_ADDR    => W_ADDR
  );


			 
   --REF_CLK <= not REF_CLK after 100 ns;
 
   
   INPUT_PROC: process
   begin
     wait for 750 ns;
     RESET_N <='1';
     for i in 0 to 512 loop
       tb_op_enable <= '1';
	   USB_CLK <= not USB_CLK;
       W_ADDR <= conv_std_logic_vector(i,11);
	   R_W_N <= '0';
       DATA <= conv_std_logic_vector(i,8);
       wait for 40 ns; 
       USB_CLK <= not USB_CLK;
       wait for 40 ns;
     end loop;
       --USB_CLK <= not USB_CLK;
       --wait for 40 ns;
     for i in 10 to 512 loop
       tb_op_enable <= '0';
	   USB_CLK <= not USB_CLK;
       W_ADDR <= conv_std_logic_vector(i,11);
	   R_W_N <= '1';
       --DATA <= conv_std_logic_vector(i,8);
       wait for 40 ns; 
       USB_CLK <= not USB_CLK;
       wait for 40 ns;
     end loop;
     wait;
   end process;
      
end;