-- Version: 9.0 SPC 9.0.1.10

library ieee;
use ieee.std_logic_1164.all;
library smartfusion;
use smartfusion.all;

entity usbee_top_level is

    port( MAC_MDIO       : inout std_logic := 'Z';
          MAC_CRSDV      : in    std_logic;
          MAC_RXER       : in    std_logic;
          MAC_TXEN       : out   std_logic;
          MAC_MDC        : out   std_logic;
          EMC_CLK        : out   std_logic;
          EMC_CS0_N      : out   std_logic;
          EMC_CS1_N      : out   std_logic;
          EMC_OEN0_N     : out   std_logic;
          EMC_OEN1_N     : out   std_logic;
          EMC_RW_N       : out   std_logic;
          UART_1_TXD     : out   std_logic;
          UART_1_RXD     : in    std_logic;
          UART_0_TXD     : out   std_logic;
          UART_0_RXD     : in    std_logic;
          I2C_0_SCL      : inout std_logic := 'Z';
          I2C_0_SDA      : inout std_logic := 'Z';
          SPI_1_DO       : out   std_logic;
          SPI_1_SS       : inout std_logic := 'Z';
          SPI_1_CLK      : inout std_logic := 'Z';
          SPI_1_DI       : in    std_logic;
          SPI_0_DO       : out   std_logic;
          SPI_0_CLK      : inout std_logic := 'Z';
          SPI_0_SS       : inout std_logic := 'Z';
          SPI_0_DI       : in    std_logic;
          I2C_1_SDA      : inout std_logic := 'Z';
          I2C_1_SCL      : inout std_logic := 'Z';
          MSS_RESET_N    : in    std_logic;
          MAINXIN        : in    std_logic;
          USB_CLK        : in    std_logic;
          IO_0_PADIN     : in    std_logic;
          IO_1_PADOUT    : out   std_logic;
          IO_15_PADOUT   : out   std_logic;
          IO_14_PADOUT   : out   std_logic;
          IO_13_PADOUT   : out   std_logic;
          IO_12_PADOUT   : out   std_logic;
          IO_11_PADOUT   : out   std_logic;
          IO_10_PADOUT   : out   std_logic;
          IO_9_PADOUT    : out   std_logic;
          IO_8_PADOUT    : out   std_logic;
          IO_6_PADOUT    : out   std_logic;
          IO_5_PADOUT    : out   std_logic;
          IO_4_PADOUT    : out   std_logic;
          IO_3_PADOUT    : out   std_logic;
          IO_2_PADOUT    : out   std_logic;
          FAB_CLK        : out   std_logic;
          MAC_RXD        : in    std_logic_vector(1 downto 0);
          MAC_TXD        : out   std_logic_vector(1 downto 0);
          EMC_DB         : inout std_logic_vector(15 downto 0) := (others => 'Z');
          EMC_AB         : out   std_logic_vector(25 downto 0);
          EMC_BYTEN      : out   std_logic_vector(1 downto 0);
          USB_DATA_PAD_0 : inout std_logic_vector(7 downto 0) := (others => 'Z')
        ; atck : IN std_logic; tms : IN std_logic; tdi : IN std_logic; trstb : IN std_logic; tdo : OUT std_logic);

end usbee_top_level;

architecture DEF_ARCH of usbee_top_level is 

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component usb_mss
    port( EMC_CLK      : out   std_logic;
          EMC_CS0_N    : out   std_logic;
          EMC_CS1_N    : out   std_logic;
          EMC_OEN0_N   : out   std_logic;
          EMC_OEN1_N   : out   std_logic;
          EMC_RW_N     : out   std_logic;
          UART_0_TXD   : out   std_logic;
          UART_0_RXD   : in    std_logic := 'U';
          UART_1_TXD   : out   std_logic;
          UART_1_RXD   : in    std_logic := 'U';
          I2C_1_SDA    : inout   std_logic;
          I2C_1_SCL    : inout   std_logic;
          SPI_1_DI     : in    std_logic := 'U';
          SPI_1_DO     : out   std_logic;
          SPI_1_CLK    : inout   std_logic;
          SPI_1_SS     : inout   std_logic;
          SPI_0_DI     : in    std_logic := 'U';
          SPI_0_DO     : out   std_logic;
          SPI_0_CLK    : inout   std_logic;
          SPI_0_SS     : inout   std_logic;
          I2C_0_SCL    : inout   std_logic;
          I2C_0_SDA    : inout   std_logic;
          MAC_MDIO     : inout   std_logic;
          MAC_CRSDV    : in    std_logic := 'U';
          MAC_RXER     : in    std_logic := 'U';
          MAC_TXEN     : out   std_logic;
          MAC_MDC      : out   std_logic;
          MSS_RESET_N  : in    std_logic := 'U';
          MAINXIN      : in    std_logic := 'U';
          FAB_CLK      : out   std_logic;
          FAB_LOCK     : out   std_logic;
          FABINT       : in    std_logic := 'U';
          FABHWRITE    : in    std_logic := 'U';
          FABHSEL      : in    std_logic := 'U';
          FABHMASTLOCK : in    std_logic := 'U';
          FABHREADY    : in    std_logic := 'U';
          FABHREADYOUT : out   std_logic;
          FABHRESP     : out   std_logic;
          IO_0_PADIN   : in    std_logic := 'U';
          IO_0_Y       : out   std_logic;
          IO_1_PADOUT  : out   std_logic;
          IO_15_PADOUT : out   std_logic;
          IO_14_PADOUT : out   std_logic;
          IO_13_PADOUT : out   std_logic;
          IO_12_PADOUT : out   std_logic;
          IO_11_PADOUT : out   std_logic;
          IO_10_PADOUT : out   std_logic;
          IO_9_PADOUT  : out   std_logic;
          IO_8_PADOUT  : out   std_logic;
          IO_6_PADOUT  : out   std_logic;
          IO_5_PADOUT  : out   std_logic;
          IO_4_PADOUT  : out   std_logic;
          IO_3_PADOUT  : out   std_logic;
          IO_2_PADOUT  : out   std_logic;
          IO_2_D       : in    std_logic := 'U';
          IO_5_D       : in    std_logic := 'U';
          IO_13_D      : in    std_logic := 'U';
          IO_10_D      : in    std_logic := 'U';
          IO_14_D      : in    std_logic := 'U';
          IO_6_D       : in    std_logic := 'U';
          IO_12_D      : in    std_logic := 'U';
          IO_3_D       : in    std_logic := 'U';
          IO_11_D      : in    std_logic := 'U';
          IO_15_D      : in    std_logic := 'U';
          IO_8_D       : in    std_logic := 'U';
          IO_4_D       : in    std_logic := 'U';
          IO_1_D       : in    std_logic := 'U';
          IO_9_D       : in    std_logic := 'U';
          EMC_DB       : inout   std_logic_vector(15 downto 0);
          EMC_AB       : out   std_logic_vector(25 downto 0);
          EMC_BYTEN    : out   std_logic_vector(1 downto 0);
          MAC_RXD      : in    std_logic_vector(1 downto 0) := (others => 'U');
          MAC_TXD      : out   std_logic_vector(1 downto 0);
          FABHADDR     : in    std_logic_vector(31 downto 0) := (others => 'U');
          FABHTRANS    : in    std_logic_vector(1 downto 0) := (others => 'U');
          FABHSIZE     : in    std_logic_vector(1 downto 0) := (others => 'U');
          FABHWDATA    : in    std_logic_vector(31 downto 0) := (others => 'U');
          FABHRDATA    : out   std_logic_vector(31 downto 0)
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component CLKBUF
    port( PAD : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

    signal FABHREADYOUT, FABHRESP, FABINT, \FAB_CLK\, 
        \FIFO_DATA_[7]\, \FIFO_DATA_[6]\, \FIFO_DATA_[5]\, 
        \FIFO_DATA_[4]\, \FIFO_DATA_[3]\, \FIFO_DATA_[2]\, 
        \FIFO_DATA_[1]\, \FIFO_DATA_[0]\, HWRITE, IO_0_Y_0, 
        \usb_mss_0_FABHRDATA_[31]\, \usb_mss_0_FABHRDATA_[30]\, 
        \usb_mss_0_FABHRDATA_[29]\, \usb_mss_0_FABHRDATA_[28]\, 
        \usb_mss_0_FABHRDATA_[27]\, \usb_mss_0_FABHRDATA_[26]\, 
        \usb_mss_0_FABHRDATA_[25]\, \usb_mss_0_FABHRDATA_[24]\, 
        \usb_mss_0_FABHRDATA_[23]\, \usb_mss_0_FABHRDATA_[22]\, 
        \usb_mss_0_FABHRDATA_[21]\, \usb_mss_0_FABHRDATA_[20]\, 
        \usb_mss_0_FABHRDATA_[19]\, \usb_mss_0_FABHRDATA_[18]\, 
        \usb_mss_0_FABHRDATA_[17]\, \usb_mss_0_FABHRDATA_[16]\, 
        \usb_mss_0_FABHRDATA_[15]\, \usb_mss_0_FABHRDATA_[14]\, 
        \usb_mss_0_FABHRDATA_[13]\, \usb_mss_0_FABHRDATA_[12]\, 
        \usb_mss_0_FABHRDATA_[11]\, \usb_mss_0_FABHRDATA_[10]\, 
        \usb_mss_0_FABHRDATA_[9]\, \usb_mss_0_FABHRDATA_[8]\, 
        \usb_mss_0_FABHRDATA_[7]\, \usb_mss_0_FABHRDATA_[6]\, 
        \usb_mss_0_FABHRDATA_[5]\, \usb_mss_0_FABHRDATA_[4]\, 
        \usb_mss_0_FABHRDATA_[3]\, \usb_mss_0_FABHRDATA_[2]\, 
        \usb_mss_0_FABHRDATA_[1]\, \usb_mss_0_FABHRDATA_[0]\, 
        usb_mss_0_FAB_LOCK, usb_slave_0_FIFO_EMPTY_BIT, 
        \usb_slave_0_HADDR_[31]\, \usb_slave_0_HADDR_[30]\, 
        \usb_slave_0_HADDR_[29]\, \usb_slave_0_HADDR_[28]\, 
        \usb_slave_0_HADDR_[27]\, \usb_slave_0_HADDR_[26]\, 
        \usb_slave_0_HADDR_[25]\, \usb_slave_0_HADDR_[24]\, 
        \usb_slave_0_HADDR_[23]\, \usb_slave_0_HADDR_[22]\, 
        \usb_slave_0_HADDR_[21]\, \usb_slave_0_HADDR_[20]\, 
        \usb_slave_0_HADDR_[19]\, \usb_slave_0_HADDR_[18]\, 
        \usb_slave_0_HADDR_[17]\, \usb_slave_0_HADDR_[16]\, 
        \usb_slave_0_HADDR_[15]\, \usb_slave_0_HADDR_[14]\, 
        \usb_slave_0_HADDR_[13]\, \usb_slave_0_HADDR_[12]\, 
        \usb_slave_0_HADDR_[11]\, \usb_slave_0_HADDR_[10]\, 
        \usb_slave_0_HADDR_[9]\, \usb_slave_0_HADDR_[8]\, 
        \usb_slave_0_HADDR_[7]\, \usb_slave_0_HADDR_[6]\, 
        \usb_slave_0_HADDR_[5]\, \usb_slave_0_HADDR_[4]\, 
        \usb_slave_0_HADDR_[3]\, \usb_slave_0_HADDR_[2]\, 
        \usb_slave_0_HADDR_[1]\, \usb_slave_0_HADDR_[0]\, 
        usb_slave_0_HMASTLOCK, usb_slave_0_HREADY, 
        usb_slave_0_HSEL, \usb_slave_0_HSIZE_[1]\, 
        \usb_slave_0_HSIZE_[0]\, \usb_slave_0_HTRANS_[1]\, 
        \usb_slave_0_HTRANS_[0]\, \usb_slave_0_HWDATA_[31]\, 
        \usb_slave_0_HWDATA_[30]\, \usb_slave_0_HWDATA_[29]\, 
        \usb_slave_0_HWDATA_[28]\, \usb_slave_0_HWDATA_[27]\, 
        \usb_slave_0_HWDATA_[26]\, \usb_slave_0_HWDATA_[25]\, 
        \usb_slave_0_HWDATA_[24]\, \usb_slave_0_HWDATA_[23]\, 
        \usb_slave_0_HWDATA_[22]\, \usb_slave_0_HWDATA_[21]\, 
        \usb_slave_0_HWDATA_[20]\, \usb_slave_0_HWDATA_[19]\, 
        \usb_slave_0_HWDATA_[18]\, \usb_slave_0_HWDATA_[17]\, 
        \usb_slave_0_HWDATA_[16]\, \usb_slave_0_HWDATA_[15]\, 
        \usb_slave_0_HWDATA_[14]\, \usb_slave_0_HWDATA_[13]\, 
        \usb_slave_0_HWDATA_[12]\, \usb_slave_0_HWDATA_[11]\, 
        \usb_slave_0_HWDATA_[10]\, \usb_slave_0_HWDATA_[9]\, 
        \usb_slave_0_HWDATA_[8]\, \usb_slave_0_HWDATA_[7]\, 
        \usb_slave_0_HWDATA_[6]\, \usb_slave_0_HWDATA_[5]\, 
        \usb_slave_0_HWDATA_[4]\, \usb_slave_0_HWDATA_[3]\, 
        \usb_slave_0_HWDATA_[2]\, \usb_slave_0_HWDATA_[1]\, 
        \usb_slave_0_HWDATA_[0]\, usb_slave_0_SEND_DATA_BIT, Y, 
        GND_net, VCC_net : std_logic;

COMPONENT comm_block PORT ( atck : IN std_logic; tms : IN std_logic; tdi : IN std_logic; trstb : IN std_logic; tdo : OUT std_logic; comm2iice_link_iice_0 : OUT std_logic_vector(0 TO 9); iice2comm_link_iice_0 : IN std_logic); END COMPONENT; attribute syn_noprune : boolean; attribute syn_noprune of comm_block_inst : label is true; SIGNAL downlink_14_a : std_logic_vector(0 TO 16); COMPONENT ldic1_0 PORT ( fabint : IN std_logic; usb_slave_0_fifo_empty_bit : IN std_logic; usb_slave_0_send_data_bit : IN std_logic; uplink_8 : OUT std_logic_vector(0 TO 19); downlink_14 : IN std_logic_vector(0 TO 16)); END COMPONENT; SIGNAL uplink_8_a : std_logic_vector(0 TO 19); SIGNAL comm2iice_link_iice_0_a_0 : std_logic_vector(0 TO 9); SIGNAL iice2comm_link_iice_0_a_0 : std_logic; COMPONENT iice_0 PORT ( comm2iice_link_iice_0 : IN std_logic_vector(0 TO 9); iice2comm_link_iice_0 : OUT std_logic; mdic_link : IN std_logic_vector(0 TO 19)); END COMPONENT; attribute syn_noprune of iice_inst_0 : label is true; begin 

    FAB_CLK <= \FAB_CLK\;

    \VCC\ : VCC
      port map(Y => VCC_net);
    
    usb_mss_0 : usb_mss
      port map(EMC_CLK => EMC_CLK, EMC_CS0_N => EMC_CS0_N, 
        EMC_CS1_N => EMC_CS1_N, EMC_OEN0_N => EMC_OEN0_N, 
        EMC_OEN1_N => EMC_OEN1_N, EMC_RW_N => EMC_RW_N, 
        UART_0_TXD => UART_0_TXD, UART_0_RXD => UART_0_RXD, 
        UART_1_TXD => UART_1_TXD, UART_1_RXD => UART_1_RXD, 
        I2C_1_SDA => I2C_1_SDA, I2C_1_SCL => I2C_1_SCL, SPI_1_DI
         => SPI_1_DI, SPI_1_DO => SPI_1_DO, SPI_1_CLK => 
        SPI_1_CLK, SPI_1_SS => SPI_1_SS, SPI_0_DI => SPI_0_DI, 
        SPI_0_DO => SPI_0_DO, SPI_0_CLK => SPI_0_CLK, SPI_0_SS
         => SPI_0_SS, I2C_0_SCL => I2C_0_SCL, I2C_0_SDA => 
        I2C_0_SDA, MAC_MDIO => MAC_MDIO, MAC_CRSDV => MAC_CRSDV, 
        MAC_RXER => MAC_RXER, MAC_TXEN => MAC_TXEN, MAC_MDC => 
        MAC_MDC, MSS_RESET_N => MSS_RESET_N, MAINXIN => MAINXIN, 
        FAB_CLK => \FAB_CLK\, FAB_LOCK => usb_mss_0_FAB_LOCK, 
        FABINT => FABINT, FABHWRITE => HWRITE, FABHSEL => 
        usb_slave_0_HSEL, FABHMASTLOCK => usb_slave_0_HMASTLOCK, 
        FABHREADY => usb_slave_0_HREADY, FABHREADYOUT => 
        FABHREADYOUT, FABHRESP => FABHRESP, IO_0_PADIN => 
        IO_0_PADIN, IO_0_Y => IO_0_Y_0, IO_1_PADOUT => 
        IO_1_PADOUT, IO_15_PADOUT => IO_15_PADOUT, IO_14_PADOUT
         => IO_14_PADOUT, IO_13_PADOUT => IO_13_PADOUT, 
        IO_12_PADOUT => IO_12_PADOUT, IO_11_PADOUT => 
        IO_11_PADOUT, IO_10_PADOUT => IO_10_PADOUT, IO_9_PADOUT
         => IO_9_PADOUT, IO_8_PADOUT => IO_8_PADOUT, IO_6_PADOUT
         => IO_6_PADOUT, IO_5_PADOUT => IO_5_PADOUT, IO_4_PADOUT
         => IO_4_PADOUT, IO_3_PADOUT => IO_3_PADOUT, IO_2_PADOUT
         => IO_2_PADOUT, IO_2_D => IO_0_Y_0, IO_5_D => 
        usb_slave_0_SEND_DATA_BIT, IO_13_D => \FIFO_DATA_[5]\, 
        IO_10_D => \FIFO_DATA_[2]\, IO_14_D => \FIFO_DATA_[6]\, 
        IO_6_D => FABINT, IO_12_D => \FIFO_DATA_[4]\, IO_3_D => 
        GND_net, IO_11_D => \FIFO_DATA_[3]\, IO_15_D => 
        \FIFO_DATA_[7]\, IO_8_D => \FIFO_DATA_[0]\, IO_4_D => 
        usb_slave_0_FIFO_EMPTY_BIT, IO_1_D => GND_net, IO_9_D => 
        \FIFO_DATA_[1]\, EMC_DB(15) => EMC_DB(15), EMC_DB(14) => 
        EMC_DB(14), EMC_DB(13) => EMC_DB(13), EMC_DB(12) => 
        EMC_DB(12), EMC_DB(11) => EMC_DB(11), EMC_DB(10) => 
        EMC_DB(10), EMC_DB(9) => EMC_DB(9), EMC_DB(8) => 
        EMC_DB(8), EMC_DB(7) => EMC_DB(7), EMC_DB(6) => EMC_DB(6), 
        EMC_DB(5) => EMC_DB(5), EMC_DB(4) => EMC_DB(4), EMC_DB(3)
         => EMC_DB(3), EMC_DB(2) => EMC_DB(2), EMC_DB(1) => 
        EMC_DB(1), EMC_DB(0) => EMC_DB(0), EMC_AB(25) => 
        EMC_AB(25), EMC_AB(24) => EMC_AB(24), EMC_AB(23) => 
        EMC_AB(23), EMC_AB(22) => EMC_AB(22), EMC_AB(21) => 
        EMC_AB(21), EMC_AB(20) => EMC_AB(20), EMC_AB(19) => 
        EMC_AB(19), EMC_AB(18) => EMC_AB(18), EMC_AB(17) => 
        EMC_AB(17), EMC_AB(16) => EMC_AB(16), EMC_AB(15) => 
        EMC_AB(15), EMC_AB(14) => EMC_AB(14), EMC_AB(13) => 
        EMC_AB(13), EMC_AB(12) => EMC_AB(12), EMC_AB(11) => 
        EMC_AB(11), EMC_AB(10) => EMC_AB(10), EMC_AB(9) => 
        EMC_AB(9), EMC_AB(8) => EMC_AB(8), EMC_AB(7) => EMC_AB(7), 
        EMC_AB(6) => EMC_AB(6), EMC_AB(5) => EMC_AB(5), EMC_AB(4)
         => EMC_AB(4), EMC_AB(3) => EMC_AB(3), EMC_AB(2) => 
        EMC_AB(2), EMC_AB(1) => EMC_AB(1), EMC_AB(0) => EMC_AB(0), 
        EMC_BYTEN(1) => EMC_BYTEN(1), EMC_BYTEN(0) => 
        EMC_BYTEN(0), MAC_RXD(1) => MAC_RXD(1), MAC_RXD(0) => 
        MAC_RXD(0), MAC_TXD(1) => MAC_TXD(1), MAC_TXD(0) => 
        MAC_TXD(0), FABHADDR(31) => \usb_slave_0_HADDR_[31]\, 
        FABHADDR(30) => \usb_slave_0_HADDR_[30]\, FABHADDR(29)
         => \usb_slave_0_HADDR_[29]\, FABHADDR(28) => 
        \usb_slave_0_HADDR_[28]\, FABHADDR(27) => 
        \usb_slave_0_HADDR_[27]\, FABHADDR(26) => 
        \usb_slave_0_HADDR_[26]\, FABHADDR(25) => 
        \usb_slave_0_HADDR_[25]\, FABHADDR(24) => 
        \usb_slave_0_HADDR_[24]\, FABHADDR(23) => 
        \usb_slave_0_HADDR_[23]\, FABHADDR(22) => 
        \usb_slave_0_HADDR_[22]\, FABHADDR(21) => 
        \usb_slave_0_HADDR_[21]\, FABHADDR(20) => 
        \usb_slave_0_HADDR_[20]\, FABHADDR(19) => 
        \usb_slave_0_HADDR_[19]\, FABHADDR(18) => 
        \usb_slave_0_HADDR_[18]\, FABHADDR(17) => 
        \usb_slave_0_HADDR_[17]\, FABHADDR(16) => 
        \usb_slave_0_HADDR_[16]\, FABHADDR(15) => 
        \usb_slave_0_HADDR_[15]\, FABHADDR(14) => 
        \usb_slave_0_HADDR_[14]\, FABHADDR(13) => 
        \usb_slave_0_HADDR_[13]\, FABHADDR(12) => 
        \usb_slave_0_HADDR_[12]\, FABHADDR(11) => 
        \usb_slave_0_HADDR_[11]\, FABHADDR(10) => 
        \usb_slave_0_HADDR_[10]\, FABHADDR(9) => 
        \usb_slave_0_HADDR_[9]\, FABHADDR(8) => 
        \usb_slave_0_HADDR_[8]\, FABHADDR(7) => 
        \usb_slave_0_HADDR_[7]\, FABHADDR(6) => 
        \usb_slave_0_HADDR_[6]\, FABHADDR(5) => 
        \usb_slave_0_HADDR_[5]\, FABHADDR(4) => 
        \usb_slave_0_HADDR_[4]\, FABHADDR(3) => 
        \usb_slave_0_HADDR_[3]\, FABHADDR(2) => 
        \usb_slave_0_HADDR_[2]\, FABHADDR(1) => 
        \usb_slave_0_HADDR_[1]\, FABHADDR(0) => 
        \usb_slave_0_HADDR_[0]\, FABHTRANS(1) => 
        \usb_slave_0_HTRANS_[1]\, FABHTRANS(0) => 
        \usb_slave_0_HTRANS_[0]\, FABHSIZE(1) => 
        \usb_slave_0_HSIZE_[1]\, FABHSIZE(0) => 
        \usb_slave_0_HSIZE_[0]\, FABHWDATA(31) => 
        \usb_slave_0_HWDATA_[31]\, FABHWDATA(30) => 
        \usb_slave_0_HWDATA_[30]\, FABHWDATA(29) => 
        \usb_slave_0_HWDATA_[29]\, FABHWDATA(28) => 
        \usb_slave_0_HWDATA_[28]\, FABHWDATA(27) => 
        \usb_slave_0_HWDATA_[27]\, FABHWDATA(26) => 
        \usb_slave_0_HWDATA_[26]\, FABHWDATA(25) => 
        \usb_slave_0_HWDATA_[25]\, FABHWDATA(24) => 
        \usb_slave_0_HWDATA_[24]\, FABHWDATA(23) => 
        \usb_slave_0_HWDATA_[23]\, FABHWDATA(22) => 
        \usb_slave_0_HWDATA_[22]\, FABHWDATA(21) => 
        \usb_slave_0_HWDATA_[21]\, FABHWDATA(20) => 
        \usb_slave_0_HWDATA_[20]\, FABHWDATA(19) => 
        \usb_slave_0_HWDATA_[19]\, FABHWDATA(18) => 
        \usb_slave_0_HWDATA_[18]\, FABHWDATA(17) => 
        \usb_slave_0_HWDATA_[17]\, FABHWDATA(16) => 
        \usb_slave_0_HWDATA_[16]\, FABHWDATA(15) => 
        \usb_slave_0_HWDATA_[15]\, FABHWDATA(14) => 
        \usb_slave_0_HWDATA_[14]\, FABHWDATA(13) => 
        \usb_slave_0_HWDATA_[13]\, FABHWDATA(12) => 
        \usb_slave_0_HWDATA_[12]\, FABHWDATA(11) => 
        \usb_slave_0_HWDATA_[11]\, FABHWDATA(10) => 
        \usb_slave_0_HWDATA_[10]\, FABHWDATA(9) => 
        \usb_slave_0_HWDATA_[9]\, FABHWDATA(8) => 
        \usb_slave_0_HWDATA_[8]\, FABHWDATA(7) => 
        \usb_slave_0_HWDATA_[7]\, FABHWDATA(6) => 
        \usb_slave_0_HWDATA_[6]\, FABHWDATA(5) => 
        \usb_slave_0_HWDATA_[5]\, FABHWDATA(4) => 
        \usb_slave_0_HWDATA_[4]\, FABHWDATA(3) => 
        \usb_slave_0_HWDATA_[3]\, FABHWDATA(2) => 
        \usb_slave_0_HWDATA_[2]\, FABHWDATA(1) => 
        \usb_slave_0_HWDATA_[1]\, FABHWDATA(0) => 
        \usb_slave_0_HWDATA_[0]\, FABHRDATA(31) => 
        \usb_mss_0_FABHRDATA_[31]\, FABHRDATA(30) => 
        \usb_mss_0_FABHRDATA_[30]\, FABHRDATA(29) => 
        \usb_mss_0_FABHRDATA_[29]\, FABHRDATA(28) => 
        \usb_mss_0_FABHRDATA_[28]\, FABHRDATA(27) => 
        \usb_mss_0_FABHRDATA_[27]\, FABHRDATA(26) => 
        \usb_mss_0_FABHRDATA_[26]\, FABHRDATA(25) => 
        \usb_mss_0_FABHRDATA_[25]\, FABHRDATA(24) => 
        \usb_mss_0_FABHRDATA_[24]\, FABHRDATA(23) => 
        \usb_mss_0_FABHRDATA_[23]\, FABHRDATA(22) => 
        \usb_mss_0_FABHRDATA_[22]\, FABHRDATA(21) => 
        \usb_mss_0_FABHRDATA_[21]\, FABHRDATA(20) => 
        \usb_mss_0_FABHRDATA_[20]\, FABHRDATA(19) => 
        \usb_mss_0_FABHRDATA_[19]\, FABHRDATA(18) => 
        \usb_mss_0_FABHRDATA_[18]\, FABHRDATA(17) => 
        \usb_mss_0_FABHRDATA_[17]\, FABHRDATA(16) => 
        \usb_mss_0_FABHRDATA_[16]\, FABHRDATA(15) => 
        \usb_mss_0_FABHRDATA_[15]\, FABHRDATA(14) => 
        \usb_mss_0_FABHRDATA_[14]\, FABHRDATA(13) => 
        \usb_mss_0_FABHRDATA_[13]\, FABHRDATA(12) => 
        \usb_mss_0_FABHRDATA_[12]\, FABHRDATA(11) => 
        \usb_mss_0_FABHRDATA_[11]\, FABHRDATA(10) => 
        \usb_mss_0_FABHRDATA_[10]\, FABHRDATA(9) => 
        \usb_mss_0_FABHRDATA_[9]\, FABHRDATA(8) => 
        \usb_mss_0_FABHRDATA_[8]\, FABHRDATA(7) => 
        \usb_mss_0_FABHRDATA_[7]\, FABHRDATA(6) => 
        \usb_mss_0_FABHRDATA_[6]\, FABHRDATA(5) => 
        \usb_mss_0_FABHRDATA_[5]\, FABHRDATA(4) => 
        \usb_mss_0_FABHRDATA_[4]\, FABHRDATA(3) => 
        \usb_mss_0_FABHRDATA_[3]\, FABHRDATA(2) => 
        \usb_mss_0_FABHRDATA_[2]\, FABHRDATA(1) => 
        \usb_mss_0_FABHRDATA_[1]\, FABHRDATA(0) => 
        \usb_mss_0_FABHRDATA_[0]\);
    
    \GND\ : GND
      port map(Y => GND_net);
    
    usb_slave_0 : entity work.usb_slave
      port map(USB_CLK => Y, RESET_N => usb_mss_0_FAB_LOCK, R_W_N
         => IO_0_Y_0, HCLK => \FAB_CLK\, HWRITE => HWRITE, 
        HMASTLOCK => usb_slave_0_HMASTLOCK, HREADY => 
        usb_slave_0_HREADY, HSEL => usb_slave_0_HSEL, HREADYOUT
         => FABHREADYOUT, HRESP => FABHRESP, FABINT => FABINT, 
        SEND_DATA_BIT => usb_slave_0_SEND_DATA_BIT, 
        FIFO_EMPTY_BIT => usb_slave_0_FIFO_EMPTY_BIT, 
        USB_DATA_PAD(7) => USB_DATA_PAD_0(7), USB_DATA_PAD(6) => 
        USB_DATA_PAD_0(6), USB_DATA_PAD(5) => USB_DATA_PAD_0(5), 
        USB_DATA_PAD(4) => USB_DATA_PAD_0(4), USB_DATA_PAD(3) => 
        USB_DATA_PAD_0(3), USB_DATA_PAD(2) => USB_DATA_PAD_0(2), 
        USB_DATA_PAD(1) => USB_DATA_PAD_0(1), USB_DATA_PAD(0) => 
        USB_DATA_PAD_0(0), HTRANS(1) => \usb_slave_0_HTRANS_[1]\, 
        HTRANS(0) => \usb_slave_0_HTRANS_[0]\, HSIZE(1) => 
        \usb_slave_0_HSIZE_[1]\, HSIZE(0) => 
        \usb_slave_0_HSIZE_[0]\, HWDATA(31) => 
        \usb_slave_0_HWDATA_[31]\, HWDATA(30) => 
        \usb_slave_0_HWDATA_[30]\, HWDATA(29) => 
        \usb_slave_0_HWDATA_[29]\, HWDATA(28) => 
        \usb_slave_0_HWDATA_[28]\, HWDATA(27) => 
        \usb_slave_0_HWDATA_[27]\, HWDATA(26) => 
        \usb_slave_0_HWDATA_[26]\, HWDATA(25) => 
        \usb_slave_0_HWDATA_[25]\, HWDATA(24) => 
        \usb_slave_0_HWDATA_[24]\, HWDATA(23) => 
        \usb_slave_0_HWDATA_[23]\, HWDATA(22) => 
        \usb_slave_0_HWDATA_[22]\, HWDATA(21) => 
        \usb_slave_0_HWDATA_[21]\, HWDATA(20) => 
        \usb_slave_0_HWDATA_[20]\, HWDATA(19) => 
        \usb_slave_0_HWDATA_[19]\, HWDATA(18) => 
        \usb_slave_0_HWDATA_[18]\, HWDATA(17) => 
        \usb_slave_0_HWDATA_[17]\, HWDATA(16) => 
        \usb_slave_0_HWDATA_[16]\, HWDATA(15) => 
        \usb_slave_0_HWDATA_[15]\, HWDATA(14) => 
        \usb_slave_0_HWDATA_[14]\, HWDATA(13) => 
        \usb_slave_0_HWDATA_[13]\, HWDATA(12) => 
        \usb_slave_0_HWDATA_[12]\, HWDATA(11) => 
        \usb_slave_0_HWDATA_[11]\, HWDATA(10) => 
        \usb_slave_0_HWDATA_[10]\, HWDATA(9) => 
        \usb_slave_0_HWDATA_[9]\, HWDATA(8) => 
        \usb_slave_0_HWDATA_[8]\, HWDATA(7) => 
        \usb_slave_0_HWDATA_[7]\, HWDATA(6) => 
        \usb_slave_0_HWDATA_[6]\, HWDATA(5) => 
        \usb_slave_0_HWDATA_[5]\, HWDATA(4) => 
        \usb_slave_0_HWDATA_[4]\, HWDATA(3) => 
        \usb_slave_0_HWDATA_[3]\, HWDATA(2) => 
        \usb_slave_0_HWDATA_[2]\, HWDATA(1) => 
        \usb_slave_0_HWDATA_[1]\, HWDATA(0) => 
        \usb_slave_0_HWDATA_[0]\, HADDR(31) => 
        \usb_slave_0_HADDR_[31]\, HADDR(30) => 
        \usb_slave_0_HADDR_[30]\, HADDR(29) => 
        \usb_slave_0_HADDR_[29]\, HADDR(28) => 
        \usb_slave_0_HADDR_[28]\, HADDR(27) => 
        \usb_slave_0_HADDR_[27]\, HADDR(26) => 
        \usb_slave_0_HADDR_[26]\, HADDR(25) => 
        \usb_slave_0_HADDR_[25]\, HADDR(24) => 
        \usb_slave_0_HADDR_[24]\, HADDR(23) => 
        \usb_slave_0_HADDR_[23]\, HADDR(22) => 
        \usb_slave_0_HADDR_[22]\, HADDR(21) => 
        \usb_slave_0_HADDR_[21]\, HADDR(20) => 
        \usb_slave_0_HADDR_[20]\, HADDR(19) => 
        \usb_slave_0_HADDR_[19]\, HADDR(18) => 
        \usb_slave_0_HADDR_[18]\, HADDR(17) => 
        \usb_slave_0_HADDR_[17]\, HADDR(16) => 
        \usb_slave_0_HADDR_[16]\, HADDR(15) => 
        \usb_slave_0_HADDR_[15]\, HADDR(14) => 
        \usb_slave_0_HADDR_[14]\, HADDR(13) => 
        \usb_slave_0_HADDR_[13]\, HADDR(12) => 
        \usb_slave_0_HADDR_[12]\, HADDR(11) => 
        \usb_slave_0_HADDR_[11]\, HADDR(10) => 
        \usb_slave_0_HADDR_[10]\, HADDR(9) => 
        \usb_slave_0_HADDR_[9]\, HADDR(8) => 
        \usb_slave_0_HADDR_[8]\, HADDR(7) => 
        \usb_slave_0_HADDR_[7]\, HADDR(6) => 
        \usb_slave_0_HADDR_[6]\, HADDR(5) => 
        \usb_slave_0_HADDR_[5]\, HADDR(4) => 
        \usb_slave_0_HADDR_[4]\, HADDR(3) => 
        \usb_slave_0_HADDR_[3]\, HADDR(2) => 
        \usb_slave_0_HADDR_[2]\, HADDR(1) => 
        \usb_slave_0_HADDR_[1]\, HADDR(0) => 
        \usb_slave_0_HADDR_[0]\, HRDATA(31) => 
        \usb_mss_0_FABHRDATA_[31]\, HRDATA(30) => 
        \usb_mss_0_FABHRDATA_[30]\, HRDATA(29) => 
        \usb_mss_0_FABHRDATA_[29]\, HRDATA(28) => 
        \usb_mss_0_FABHRDATA_[28]\, HRDATA(27) => 
        \usb_mss_0_FABHRDATA_[27]\, HRDATA(26) => 
        \usb_mss_0_FABHRDATA_[26]\, HRDATA(25) => 
        \usb_mss_0_FABHRDATA_[25]\, HRDATA(24) => 
        \usb_mss_0_FABHRDATA_[24]\, HRDATA(23) => 
        \usb_mss_0_FABHRDATA_[23]\, HRDATA(22) => 
        \usb_mss_0_FABHRDATA_[22]\, HRDATA(21) => 
        \usb_mss_0_FABHRDATA_[21]\, HRDATA(20) => 
        \usb_mss_0_FABHRDATA_[20]\, HRDATA(19) => 
        \usb_mss_0_FABHRDATA_[19]\, HRDATA(18) => 
        \usb_mss_0_FABHRDATA_[18]\, HRDATA(17) => 
        \usb_mss_0_FABHRDATA_[17]\, HRDATA(16) => 
        \usb_mss_0_FABHRDATA_[16]\, HRDATA(15) => 
        \usb_mss_0_FABHRDATA_[15]\, HRDATA(14) => 
        \usb_mss_0_FABHRDATA_[14]\, HRDATA(13) => 
        \usb_mss_0_FABHRDATA_[13]\, HRDATA(12) => 
        \usb_mss_0_FABHRDATA_[12]\, HRDATA(11) => 
        \usb_mss_0_FABHRDATA_[11]\, HRDATA(10) => 
        \usb_mss_0_FABHRDATA_[10]\, HRDATA(9) => 
        \usb_mss_0_FABHRDATA_[9]\, HRDATA(8) => 
        \usb_mss_0_FABHRDATA_[8]\, HRDATA(7) => 
        \usb_mss_0_FABHRDATA_[7]\, HRDATA(6) => 
        \usb_mss_0_FABHRDATA_[6]\, HRDATA(5) => 
        \usb_mss_0_FABHRDATA_[5]\, HRDATA(4) => 
        \usb_mss_0_FABHRDATA_[4]\, HRDATA(3) => 
        \usb_mss_0_FABHRDATA_[3]\, HRDATA(2) => 
        \usb_mss_0_FABHRDATA_[2]\, HRDATA(1) => 
        \usb_mss_0_FABHRDATA_[1]\, HRDATA(0) => 
        \usb_mss_0_FABHRDATA_[0]\, FIFO_DATA(7) => 
        \FIFO_DATA_[7]\, FIFO_DATA(6) => \FIFO_DATA_[6]\, 
        FIFO_DATA(5) => \FIFO_DATA_[5]\, FIFO_DATA(4) => 
        \FIFO_DATA_[4]\, FIFO_DATA(3) => \FIFO_DATA_[3]\, 
        FIFO_DATA(2) => \FIFO_DATA_[2]\, FIFO_DATA(1) => 
        \FIFO_DATA_[1]\, FIFO_DATA(0) => \FIFO_DATA_[0]\, uplink_13_a => downlink_14_a);
    
    CLKBUF_0 : CLKBUF
      port map(PAD => USB_CLK, Y => Y);
    

comm_block_inst : comm_block PORT MAP ( atck => atck, tms => tms, tdi => tdi, trstb => trstb, tdo => tdo, comm2iice_link_iice_0 => comm2iice_link_iice_0_a_0, iice2comm_link_iice_0 => iice2comm_link_iice_0_a_0); ldic1_inst_0 : ldic1_0 PORT MAP ( fabint => fabint, usb_slave_0_fifo_empty_bit => usb_slave_0_fifo_empty_bit, usb_slave_0_send_data_bit => usb_slave_0_send_data_bit, uplink_8 => uplink_8_a, downlink_14 => downlink_14_a); iice_inst_0 : iice_0 PORT MAP ( comm2iice_link_iice_0 => comm2iice_link_iice_0_a_0, iice2comm_link_iice_0 => iice2comm_link_iice_0_a_0, mdic_link => uplink_8_a); end DEF_ARCH; 
