@W: MO111 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\component\work\mss_top\mss_ccc_0\mss_top_tmp_mss_ccc_0_mss_ccc.v":64:7:64:18|Tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module mss_top_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\component\work\mss_top\mss_ccc_0\mss_top_tmp_mss_ccc_0_mss_ccc.v":63:7:63:20|Tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module mss_top_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\component\work\mss_top\mss_ccc_0\mss_top_tmp_mss_ccc_0_mss_ccc.v":62:7:62:18|Tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module mss_top_tmp_MSS_CCC_0_MSS_CCC) 
@W: MT462 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\component\work\mss_top\mss_ccc_0\mss_top_tmp_mss_ccc_0_mss_ccc.v":78:41:78:48|Net mss_top_0.MSS_ADLIB_INST_MACCLKCCC appears to be an unidentified clock source. Assuming default frequency. 
@W: MT462 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":218:12:362:22|Net SPI_0.ucorespi_sfr.genblk4\.u_master.un3_busy appears to be an unidentified clock source. Assuming default frequency. 
@W: MO161 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":436:4:436:9|Register bit rx_shift_reg[0] is always 0, optimizing ...
@W: MO161 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":436:4:436:9|Register bit rx_shift_reg[1] is always 0, optimizing ...
@W: MO161 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":481:4:481:9|Register bit rx_data_reg[0] is always 0, optimizing ...
@W: MO161 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":436:4:436:9|Register bit rx_shift_reg[2] is always 0, optimizing ...
@W: MO161 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":481:4:481:9|Register bit rx_data_reg[1] is always 0, optimizing ...
@W: MO161 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":436:4:436:9|Register bit rx_shift_reg[3] is always 0, optimizing ...
@W: MO161 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":481:4:481:9|Register bit rx_data_reg[2] is always 0, optimizing ...
@W: MO161 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":436:4:436:9|Register bit rx_shift_reg[4] is always 0, optimizing ...
@W: MO161 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":481:4:481:9|Register bit rx_data_reg[3] is always 0, optimizing ...
@W: MO161 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":436:4:436:9|Register bit rx_shift_reg[5] is always 0, optimizing ...
@W: MO161 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":481:4:481:9|Register bit rx_data_reg[4] is always 0, optimizing ...
@W: MO161 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":436:4:436:9|Register bit rx_shift_reg[6] is always 0, optimizing ...
@W: MO161 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":481:4:481:9|Register bit rx_data_reg[5] is always 0, optimizing ...
@W: MO161 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":436:4:436:9|Register bit rx_shift_reg[7] is always 0, optimizing ...
@W: MO161 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":481:4:481:9|Register bit rx_data_reg[6] is always 0, optimizing ...
@W: MO161 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\hdl\spi_master.v":481:4:481:9|Register bit rx_data_reg[7] is always 0, optimizing ...
@W: MT246 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\component\work\mss_top\mss_top.v":421:54:421:65|Blackbox TRIBUFF_MSS is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\component\work\mss_top\mss_top.v":418:11:418:22|Blackbox MSSINT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"c:\a2f_ac356_df\a2f500\ftdi\ftdi_spi\component\work\mss_top\mss_ccc_0\mss_top_tmp_mss_ccc_0_mss_ccc.v":96:15:96:22|Blackbox MSS_XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock mss_top|MSS_EMI_0_CLK_D_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:mss_top_0.MSS_EMI_0_CLK_D"
