/***********************************************************************************************
* Company: Actel Corporation
*
* File: main.c
* File history:
*      Revision: 1.0 Date: September 3, 2010
*
* Description:
*
* This software received the Fabric Interrupt.Then read the eSRAM and send the data via UART_0
* to Host PC.
*
* Author: Pavan Marisetti
*         pavan.marisetti@actel.com
*         Corporate Applications Engineering
*
************************************************************************************************/

#include "drivers/mss_uart/mss_uart.h"
#include "drivers/mss_watchdog/mss_watchdog.h"

#define  FABRIC_BASE_ADDR 0x40050000
/*******************************************************************************
 * DATA register:
 *------------------------------------------------------------------------------
 */
#define DATA_REG_OFFSET	0x00

/*******************************************************************************
 * CTRL2 register:
 *------------------------------------------------------------------------------
 */
#define CTRL2_REG_OFFSET	0x08
/*******************************************************************************
 * CTRL1 register:
 *------------------------------------------------------------------------------
 */
#define CTRL1_REG_OFFSET	0x04
#define DATA_REG_OFFSET	    0x00
uint32_t * read_data =0x20001000;
uint8_t * read_data_uart = 0x20001000;
uint32_t index = 0,j=0;
uint8_t rdata,status,wdata = 0XAA;

/***************************************************************
 Interrupt Handlers
***************************************************************/

#if 1
/* Fabric Interrupt Handler */

void Fabric_IRQHandler( void )
{

	//status = (*((uint8_t volatile *)(FABRIC_BASE_ADDR + CTRL2_REG_OFFSET)));
	//if(i<129)
	{
		(*((uint32_t volatile *)(FABRIC_BASE_ADDR + DATA_REG_OFFSET))) = 0xFFFFFFFF;
		read_data[index++] = (*((uint32_t volatile *)(FABRIC_BASE_ADDR + DATA_REG_OFFSET)));
	  (*((uint32_t volatile *)(FABRIC_BASE_ADDR + DATA_REG_OFFSET)))= 0xAAAAAAAA;
	}
	//else
	  //(*((uint8_t volatile *)(FABRIC_BASE_ADDR + DATA_REG_OFFSET)))= g_slave_rx_frame[j++];

    NVIC_ClearPendingIRQ( Fabric_IRQn );
}
#endif


int main()
{
	uint32_t IO_MUX_CONFIG,i;
	MSS_WD_disable();
    /* Enabling Fabric Interrupt*/
    NVIC_EnableIRQ(Fabric_IRQn);
    /* Initialize and configure UART0. */
    MSS_UART_init( &g_mss_uart0, 57600, (MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY));
    /* CONFIGURATION control reg 1
     * Interrupt [7]  = enabled      1
     * mode_select[6] = slave        0
     * order[5]       = MSB first    0
     * cpha[4]        =              0
     * cpol[3]        =              0
     * scks[2:0]      = no effect when configured in slave mode  0  */
    (*((uint8_t volatile *)(FABRIC_BASE_ADDR + CTRL1_REG_OFFSET)) = 0x80);
    /* CONFIGURATION control reg 2
    Bit(s) Name     Function
    7      enable   SPI enable bit Used as a synchronous enable for CoreSPI. The SPI interface ports are activated when this bit is set to logic 1. When
                    this bit is cleared to logic 0, all SPI interface ports (S_*, M_*) are either in input or inactive output states.
    6:1    Unused   Unused
    0      error    Error bit If this bit is at logic 1, it indicates that a character has been received before the previous character has been read from
                    the RX data register. */

    (*((uint8_t volatile *)(FABRIC_BASE_ADDR + CTRL2_REG_OFFSET)) = 0x80);

	  IO_MUX_CONFIG = (*((uint8_t volatile *)(0xE004218C)));
	  while(index <= 1343)
	    {
	    	;
	    }

	    for(i=0; i<30000; i++)
	    {
	    	;
	    }
        i= 252;
        j= 252;
	    MSS_UART_polled_tx( &g_mss_uart0, read_data_uart+268, i );
	    MSS_UART_polled_tx( &g_mss_uart0, read_data_uart+268+j, i );
	    MSS_UART_polled_tx( &g_mss_uart0, read_data_uart+268+2*j, i );
	    MSS_UART_polled_tx( &g_mss_uart0, read_data_uart+268+3*j, i );
	    MSS_UART_polled_tx( &g_mss_uart0, read_data_uart+268+4*j, i );
	    MSS_UART_polled_tx( &g_mss_uart0, read_data_uart+268+5*j, i );
	    MSS_UART_polled_tx( &g_mss_uart0, read_data_uart+268+6*j, i );
	    MSS_UART_polled_tx( &g_mss_uart0, read_data_uart+268+7*j, i );
	    MSS_UART_polled_tx( &g_mss_uart0, read_data_uart+268+8*j, i );
	    MSS_UART_polled_tx( &g_mss_uart0, read_data_uart+268+9*j, i );
	    MSS_UART_polled_tx( &g_mss_uart0, read_data_uart+268+10*j, i );
	    MSS_UART_polled_tx( &g_mss_uart0, read_data_uart+268+11*j, i );
	    MSS_UART_polled_tx( &g_mss_uart0, read_data_uart+268+12*j, i );
	    MSS_UART_polled_tx( &g_mss_uart0, read_data_uart+268+13*j, i );
	    MSS_UART_polled_tx( &g_mss_uart0, read_data_uart+268+14*j, i );
	    MSS_UART_polled_tx( &g_mss_uart0, read_data_uart+268+15*j, i );
	    MSS_UART_polled_tx( &g_mss_uart0, read_data_uart+268+16*j, i );
	    MSS_UART_polled_tx( &g_mss_uart0, read_data_uart+268+17*j, i );
	    MSS_UART_polled_tx( &g_mss_uart0, read_data_uart+268+18*j, i );
	    MSS_UART_polled_tx( &g_mss_uart0, read_data_uart+268+19*j, i );
	    MSS_UART_polled_tx( &g_mss_uart0, read_data_uart+268+20*j, i );
	    MSS_UART_polled_tx( &g_mss_uart0, read_data_uart+268+21*j, i );
	    MSS_UART_polled_tx( &g_mss_uart0, read_data_uart+268+22*j, i );


	  return 0;
}

