`

    #Build: Synplify Pro D-2009.12A, Build 040R, Jan 20 2010
    #install: C:\Actel\Libero_v9.0\Synopsys\synplify_D200912A
    #OS: Windows XP 5.1
    #Hostname: WXPL-MARISETTI1

    #Implementation: synthesis

    #Fri Jul 16 10:14:06 2010

    $ Start of Compile
    #Fri Jul 16 10:14:06 2010

    Synopsys VHDL Compiler, version comp475rc, Build 060R, built Jan 15 2010
    Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved

    @N:CD720 : std.vhd(123) | Setting time resolution to ns
    Top entity isn't set yet!
    @W:CD645 : Fifo_1024.vhd(5) | Ignoring undefined library smartfusion
    @W:CD643 : Fifo_1024.vhd(6) | Ignoring use clause - smartfusion not found ...
    @W:CD645 : usb_slave.vhd(8) | Ignoring undefined library smartfusion
    @W:CD643 : usb_slave.vhd(9) | Ignoring use clause - smartfusion not found ...
    VHDL syntax check successful!
    @N:CD630 : usb_slave.vhd(11) | Synthesizing work.usb_slave.usb_slave
    @N:CD233 : usb_slave.vhd(38) | Using sequential encoding for type ahb_master_states
    @N:CD231 : usb_slave.vhd(37) | Using onehot encoding for type fifo_read_states (idle="1000000")
    @W:CD280 : usb_slave.vhd(59) | Unbound component BIBUF_LVCMOS33U mapped to black box
    @N:CD630 : Fifo_1024.vhd(8) | Synthesizing work.fifo_1024.def_arch
    @W:CD280 : Fifo_1024.vhd(145) | Unbound component VCC mapped to black box
    @W:CD280 : Fifo_1024.vhd(149) | Unbound component GND mapped to black box
    @W:CD280 : Fifo_1024.vhd(18) | Unbound component XNOR3 mapped to black box
    @W:CD280 : Fifo_1024.vhd(22) | Unbound component INV mapped to black box
    @W:CD280 : Fifo_1024.vhd(26) | Unbound component DFN1C0 mapped to black box
    @W:CD280 : Fifo_1024.vhd(31) | Unbound component NOR3 mapped to black box
    @W:CD280 : Fifo_1024.vhd(35) | Unbound component AND2 mapped to black box
    @W:CD280 : Fifo_1024.vhd(39) | Unbound component AND3 mapped to black box
    @W:CD280 : Fifo_1024.vhd(43) | Unbound component XOR2 mapped to black box
    @W:CD280 : Fifo_1024.vhd(47) | Unbound component XNOR2 mapped to black box
    @W:CD280 : Fifo_1024.vhd(51) | Unbound component AO1 mapped to black box
    @W:CD280 : Fifo_1024.vhd(55) | Unbound component XOR3 mapped to black box
    @W:CD280 : Fifo_1024.vhd(59) | Unbound component DFN1E1C0 mapped to black box
    @W:CD280 : Fifo_1024.vhd(64) | Unbound component OR2 mapped to black box
    @W:CD280 : Fifo_1024.vhd(68) | Unbound component MX2 mapped to black box
    @W:CD280 : Fifo_1024.vhd(72) | Unbound component BUFF mapped to black box
    @W:CD280 : Fifo_1024.vhd(76) | Unbound component AO1C mapped to black box
    @W:CD280 : Fifo_1024.vhd(80) | Unbound component RAM4K9 mapped to black box
    @N:CD630 : Fifo_1024.vhd(80) | Synthesizing work.ram4k9.syn_black_box
    Post processing for work.ram4k9.syn_black_box
    @W:CD280 : Fifo_1024.vhd(96) | Unbound component AND2A mapped to black box
    @W:CD280 : Fifo_1024.vhd(100) | Unbound component NOR3A mapped to black box
    @W:CD280 : Fifo_1024.vhd(104) | Unbound component OR2A mapped to black box
    @W:CD280 : Fifo_1024.vhd(108) | Unbound component NAND3A mapped to black box
    @W:CD280 : Fifo_1024.vhd(112) | Unbound component OA1C mapped to black box
    @W:CD280 : Fifo_1024.vhd(116) | Unbound component OR3 mapped to black box
    @W:CD280 : Fifo_1024.vhd(120) | Unbound component NAND2 mapped to black box
    @W:CD280 : Fifo_1024.vhd(124) | Unbound component OA1A mapped to black box
    @W:CD280 : Fifo_1024.vhd(128) | Unbound component AOI1 mapped to black box
    @W:CD280 : Fifo_1024.vhd(132) | Unbound component DFN1P0 mapped to black box
    @W:CD280 : Fifo_1024.vhd(137) | Unbound component NOR2A mapped to black box
    @W:CD280 : Fifo_1024.vhd(141) | Unbound component DFN1 mapped to black box
    @N:CD630 : Fifo_1024.vhd(76) | Synthesizing work.ao1c.syn_black_box
    Post processing for work.ao1c.syn_black_box
    @N:CD630 : Fifo_1024.vhd(26) | Synthesizing work.dfn1c0.syn_black_box
    Post processing for work.dfn1c0.syn_black_box
    @N:CD630 : Fifo_1024.vhd(35) | Synthesizing work.and2.syn_black_box
    Post processing for work.and2.syn_black_box
    @N:CD630 : Fifo_1024.vhd(43) | Synthesizing work.xor2.syn_black_box
    Post processing for work.xor2.syn_black_box
    @N:CD630 : Fifo_1024.vhd(68) | Synthesizing work.mx2.syn_black_box
    Post processing for work.mx2.syn_black_box
    @N:CD630 : Fifo_1024.vhd(18) | Synthesizing work.xnor3.syn_black_box
    Post processing for work.xnor3.syn_black_box
    @N:CD630 : Fifo_1024.vhd(47) | Synthesizing work.xnor2.syn_black_box
    Post processing for work.xnor2.syn_black_box
    @N:CD630 : Fifo_1024.vhd(72) | Synthesizing work.buff.syn_black_box
    Post processing for work.buff.syn_black_box
    @N:CD630 : Fifo_1024.vhd(51) | Synthesizing work.ao1.syn_black_box
    Post processing for work.ao1.syn_black_box
    @N:CD630 : Fifo_1024.vhd(108) | Synthesizing work.nand3a.syn_black_box
    Post processing for work.nand3a.syn_black_box
    @N:CD630 : Fifo_1024.vhd(120) | Synthesizing work.nand2.syn_black_box
    Post processing for work.nand2.syn_black_box
    @N:CD630 : Fifo_1024.vhd(55) | Synthesizing work.xor3.syn_black_box
    Post processing for work.xor3.syn_black_box
    @N:CD630 : Fifo_1024.vhd(39) | Synthesizing work.and3.syn_black_box
    Post processing for work.and3.syn_black_box
    @N:CD630 : Fifo_1024.vhd(22) | Synthesizing work.inv.syn_black_box
    Post processing for work.inv.syn_black_box
    @N:CD630 : Fifo_1024.vhd(59) | Synthesizing work.dfn1e1c0.syn_black_box
    Post processing for work.dfn1e1c0.syn_black_box
    @N:CD630 : Fifo_1024.vhd(141) | Synthesizing work.dfn1.syn_black_box
    Post processing for work.dfn1.syn_black_box
    @N:CD630 : Fifo_1024.vhd(104) | Synthesizing work.or2a.syn_black_box
    Post processing for work.or2a.syn_black_box
    @N:CD630 : Fifo_1024.vhd(137) | Synthesizing work.nor2a.syn_black_box
    Post processing for work.nor2a.syn_black_box
    @N:CD630 : Fifo_1024.vhd(132) | Synthesizing work.dfn1p0.syn_black_box
    Post processing for work.dfn1p0.syn_black_box
    @N:CD630 : Fifo_1024.vhd(64) | Synthesizing work.or2.syn_black_box
    Post processing for work.or2.syn_black_box
    @N:CD630 : Fifo_1024.vhd(128) | Synthesizing work.aoi1.syn_black_box
    Post processing for work.aoi1.syn_black_box
    @N:CD630 : Fifo_1024.vhd(124) | Synthesizing work.oa1a.syn_black_box
    Post processing for work.oa1a.syn_black_box
    @N:CD630 : Fifo_1024.vhd(96) | Synthesizing work.and2a.syn_black_box
    Post processing for work.and2a.syn_black_box
    @N:CD630 : Fifo_1024.vhd(100) | Synthesizing work.nor3a.syn_black_box
    Post processing for work.nor3a.syn_black_box
    @N:CD630 : Fifo_1024.vhd(116) | Synthesizing work.or3.syn_black_box
    Post processing for work.or3.syn_black_box
    @N:CD630 : Fifo_1024.vhd(112) | Synthesizing work.oa1c.syn_black_box
    Post processing for work.oa1c.syn_black_box
    @N:CD630 : Fifo_1024.vhd(31) | Synthesizing work.nor3.syn_black_box
    Post processing for work.nor3.syn_black_box
    @N:CD630 : Fifo_1024.vhd(149) | Synthesizing work.gnd.syn_black_box
    Post processing for work.gnd.syn_black_box
    @N:CD630 : Fifo_1024.vhd(145) | Synthesizing work.vcc.syn_black_box
    Post processing for work.vcc.syn_black_box
    Post processing for work.fifo_1024.def_arch
    @W:CL168 : Fifo_1024.vhd(1833) | Pruning instance AND2_25 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1824) | Pruning instance MX2_1 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1784) | Pruning instance AND2_37 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1781) | Pruning instance XOR2_68 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1749) | Pruning instance AO1_37 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1717) | Pruning instance AO1_17 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1693) | Pruning instance AND2_53 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1580) | Pruning instance MX2_4 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1531) | Pruning instance DFN1_1 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1517) | Pruning instance AND2_45 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1515) | Pruning instance AND2_48 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1452) | Pruning instance AND2_77 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1429) | Pruning instance AND2_0 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1332) | Pruning instance AO1_26 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1263) | Pruning instance MX2_3 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1256) | Pruning instance AND2_27 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1234) | Pruning instance AND2_39 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1231) | Pruning instance DFN1C0_DVLDX - not in use ...
    @W:CL168 : Fifo_1024.vhd(1225) | Pruning instance MX2_7 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1200) | Pruning instance XOR2_65 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1195) | Pruning instance AND2_9 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1192) | Pruning instance MX2_6 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1152) | Pruning instance AND2_34 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1121) | Pruning instance AND2_52 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1072) | Pruning instance XOR2_79 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1054) | Pruning instance MX2_2 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1034) | Pruning instance AND2_13 - not in use ...
    @W:CL168 : Fifo_1024.vhd(988) | Pruning instance AND2_47 - not in use ...
    @W:CL168 : Fifo_1024.vhd(986) | Pruning instance AND2_64 - not in use ...
    @W:CL168 : Fifo_1024.vhd(979) | Pruning instance AND2_51 - not in use ...
    @W:CL168 : Fifo_1024.vhd(939) | Pruning instance AND2_79 - not in use ...
    @W:CL168 : Fifo_1024.vhd(916) | Pruning instance MX2_0 - not in use ...
    @W:CL168 : Fifo_1024.vhd(880) | Pruning instance XOR2_9 - not in use ...
    @W:CL168 : Fifo_1024.vhd(878) | Pruning instance AND2_26 - not in use ...
    @W:CL168 : Fifo_1024.vhd(812) | Pruning instance AND2_30 - not in use ...
    @W:CL168 : Fifo_1024.vhd(810) | Pruning instance AND2_3 - not in use ...
    @W:CL168 : Fifo_1024.vhd(786) | Pruning instance AND2_35 - not in use ...
    @W:CL168 : Fifo_1024.vhd(717) | Pruning instance AND2_31 - not in use ...
    @W:CL168 : Fifo_1024.vhd(703) | Pruning instance AND2_24 - not in use ...
    @W:CL168 : Fifo_1024.vhd(679) | Pruning instance AO1_14 - not in use ...
    @W:CL168 : Fifo_1024.vhd(660) | Pruning instance AND2_62 - not in use ...
    @W:CL168 : Fifo_1024.vhd(654) | Pruning instance XOR2_57 - not in use ...
    @W:CL168 : Fifo_1024.vhd(619) | Pruning instance AND2_43 - not in use ...
    @W:CL168 : Fifo_1024.vhd(615) | Pruning instance AND2_68 - not in use ...
    @W:CL168 : Fifo_1024.vhd(556) | Pruning instance AND2_57 - not in use ...
    @W:CL168 : Fifo_1024.vhd(533) | Pruning instance MX2_5 - not in use ...
    @W:CL168 : Fifo_1024.vhd(528) | Pruning instance AND2_61 - not in use ...
    @W:CL168 : Fifo_1024.vhd(526) | Pruning instance AND2_72 - not in use ...
    @W:CL168 : Fifo_1024.vhd(409) | Pruning instance AND2_18 - not in use ...
    @W:CL168 : Fifo_1024.vhd(386) | Pruning instance XOR2_38 - not in use ...
    @W:CL168 : Fifo_1024.vhd(353) | Pruning instance AND2_44 - not in use ...
    @W:CL168 : Fifo_1024.vhd(345) | Pruning instance AND2_71 - not in use ...
    @W:CL168 : Fifo_1024.vhd(305) | Pruning instance AND2_2 - not in use ...
    @N:CD630 : usb_slave.vhd(59) | Synthesizing work.bibuf_lvcmos33u.syn_black_box
    Post processing for work.bibuf_lvcmos33u.syn_black_box
    Post processing for work.usb_slave.usb_slave
    @A: : usb_slave.vhd(225) | Feedback mux created for signal ahb_states[1:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area
    @W:CL190 : usb_slave.vhd(225) | Optimizing register bit HTRANS(0) to a constant 0
    @W:CL260 : usb_slave.vhd(225) | Pruning Register bit 0 of HTRANS(1 downto 0)
    @N:CL201 : usb_slave.vhd(225) | Trying to extract state machine for register ahb_states
    @N:CL201 : usb_slave.vhd(148) | Trying to extract state machine for register data_states
    Extracted state machine for register data_states
    State machine has 7 reachable states with original encodings of:
       0000001
       0000010
       0000100
       0001000
       0010000
       0100000
       1000000
    @W:CL159 : usb_slave.vhd(26) | Input HRESP is unused
    @W:CL159 : usb_slave.vhd(27) | Input HRDATA is unused
    @END
    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Fri Jul 16 10:14:07 2010

    ###########################################################]
    Synopsys Actel Technology Mapper, Version map500act, Build 058R, Built Jan 18 2010 09:16:23
    Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved
    Product Version D-2009.12A
    @N:MF249 :  | Running in 32-bit mode.
    @N:MF258 :  | Gated clock conversion disabled

    Automatic dissolve at startup in view:work.usb_slave(usb_slave) of FIFO_INST(Fifo_1024)
    @N:BN116 : fifo_1024.vhd(1206) | Removing sequential instance FIFO_INST.DFN1C0_AFULL of view:smartfusion.DFN1C0(prim) because there are no references to its outputs
    @W:BN132 : usb_slave.vhd(225) | Removing sequential instance HWRITE,  because it is equivalent to instance HTRANS_1[1]

    Available hyper_sources - for debug and ip models
    	None Found

    Finished RTL optimizations (Time elapsed 0h:00m:02s; Memory used current: 56MB peak: 57MB)

    @N: : usb_slave.vhd(225) | Found counter in view:work.usb_slave(usb_slave) inst HADDR_TEMP[31:0]
    @N: : usb_slave.vhd(261) | Found counter in view:work.usb_slave(usb_slave) inst INTRPT_COUNT[7:0]
    Encoding state machine work.usb_slave(usb_slave)-data_states[0:6]
    original code -> new code
       0000001 -> 0000001
       0000010 -> 0000010
       0000100 -> 0000100
       0001000 -> 0001000
       0010000 -> 0010000
       0100000 -> 0100000
       1000000 -> 1000000
    Finished factoring (Time elapsed 0h:00m:02s; Memory used current: 56MB peak: 57MB)

    Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:02s; Memory used current: 56MB peak: 57MB)

    Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:02s; Memory used current: 56MB peak: 57MB)

    Starting Early Timing Optimization (Time elapsed 0h:00m:02s; Memory used current: 56MB peak: 57MB)

    Finished Early Timing Optimization (Time elapsed 0h:00m:03s; Memory used current: 57MB peak: 57MB)

    Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:03s; Memory used current: 56MB peak: 57MB)

    Finished preparing to map (Time elapsed 0h:00m:03s; Memory used current: 57MB peak: 58MB)

    High Fanout Net Report
    **********************

    Driver Instance / Pin Name     Fanout, notes
    ---------------------------------------------------------------
    HWRITE_0_sqmuxa_0_a3 / Y       34
    un1_data_states_1_0_a3 / Y     34
    HWDATA_0_sqmuxa_i / Y          32
    RESET_N_pad / Y                220 : 117 asynchronous set/reset
    ===============================================================

    @N:FP130 :  | Promoting Net RESET_N_c on CLKBUF  RESET_N_pad
    @N:FP130 :  | Promoting Net HCLK_c on CLKBUF  HCLK_pad
    Replicating Combinational Instance HWDATA_0_sqmuxa_i, fanout 32 segments 2
    Replicating Combinational Instance un1_data_states_1_0_a3, fanout 34 segments 2
    Replicating Combinational Instance HWRITE_0_sqmuxa_0_a3, fanout 34 segments 2
    Buffering FIFO_INST.WCLOCKP, fanout 47 segments 2
    Finished technology mapping (Time elapsed 0h:00m:04s; Memory used current: 57MB peak: 58MB)

    @A:BN291 : usb_slave.vhd(148) | Boundary register rd_en has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
    Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:04s; Memory used current: 58MB peak: 60MB)

    Added 1 Buffers
    Added 3 Cells via replication
    	Added 0 Sequential Cells via replication
    	Added 3 Combinational Cells via replication
    Finished restoring hierarchy (Time elapsed 0h:00m:04s; Memory used current: 58MB peak: 60MB)

    Writing Analyst data base Y:\Pavan M\USB\USBeee\Using_Fabric_Master\HW_USBee\synthesis\usb_slave.srm
    Finished Writing Netlist Databases (Time elapsed 0h:00m:04s; Memory used current: 58MB peak: 60MB)

    Writing EDIF Netlist and constraint files
    D-2009.12A
    Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:05s; Memory used current: 58MB peak: 60MB)

    @W:MT420 :  | Found inferred clock usb_slave|USB_CLK with period 10.00ns. A user-defined clock should be declared on object "p:USB_CLK"

    @W:MT420 :  | Found inferred clock usb_slave|HCLK with period 10.00ns. A user-defined clock should be declared on object "p:HCLK"

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Fri Jul 16 10:14:31 2010
    #

    Top view:               usb_slave
    Library name:           smartfusion
    Operating conditions:   COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree )
    Requested Frequency:    100.0 MHz
    Wire load mode:         top
    Wire load model:        smartfusion
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report estimates place and route data. Please look at the place and route timing report for final timing..

    @N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock..

    Performance Summary
    *******************

    Worst slack in design: -7.469

                          Requested     Estimated     Requested     Estimated                Clock        Clock
    Starting Clock        Frequency     Frequency     Period        Period        Slack      Type         Group
    -------------------------------------------------------------------------------------------------------------------------
    usb_slave|HCLK        100.0 MHz     57.2 MHz      10.000        17.469        -7.469     inferred     Inferred_clkgroup_1
    usb_slave|USB_CLK     100.0 MHz     72.2 MHz      10.000        13.848        -3.848     inferred     Inferred_clkgroup_0
    =========================================================================================================================

    Clock Relationships
    *******************

    Clocks                                |    rise  to  rise    |    fall  to  fall    |    rise  to  fall   |    fall  to  rise
    ------------------------------------------------------------------------------------------------------------------------------
    Starting           Ending             |  constraint  slack   |  constraint  slack   |  constraint  slack  |  constraint  slack
    ------------------------------------------------------------------------------------------------------------------------------
    usb_slave|USB_CLK  usb_slave|USB_CLK  |  No paths    -       |  10.000      -3.848  |  No paths    -      |  No paths    -
    usb_slave|USB_CLK  usb_slave|HCLK     |  No paths    -       |  No paths    -       |  No paths    -      |  Diff grp    -
    usb_slave|HCLK     usb_slave|USB_CLK  |  No paths    -       |  No paths    -       |  Diff grp    -      |  No paths    -
    usb_slave|HCLK     usb_slave|HCLK     |  10.000      -7.469  |  No paths    -       |  No paths    -      |  No paths    -
    ==============================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    		No IO constraint found

    ====================================
    Detailed Report for Clock: usb_slave|HCLK
    ====================================

    Starting Points with Worst Slack
    ********************************

                                          Starting                                                     Arrival
    Instance                              Reference          Type         Pin     Net                  Time        Slack
                                          Clock
    ---------------------------------------------------------------------------------------------------------------------
    FIFO_INST.DFN1P0_EMPTY                usb_slave|HCLK     DFN1P0       Q       FIFO_EMPTY_BIT_c     0.580       -7.469
    rd_en                                 usb_slave|HCLK     DFI1E1P0     QN      FIFO_INST.REP        0.737       -5.538
    FIFO_INST.DFN1C0_MEM_RADDR_1_inst     usb_slave|HCLK     DFN1C0       Q       MEM_RADDR_1_net      0.737       -4.855
    FIFO_INST.DFN1C0_MEM_RADDR_0_inst     usb_slave|HCLK     DFN1C0       Q       MEM_RADDR_0_net      0.737       -4.789
    FIFO_INST.DFN1C0_MEM_RADDR_2_inst     usb_slave|HCLK     DFN1C0       Q       MEM_RADDR_2_net      0.737       -4.435
    FIFO_INST.DFN1C0_MEM_RADDR_3_inst     usb_slave|HCLK     DFN1C0       Q       MEM_RADDR_3_net      0.737       -4.405
    FIFO_INST.DFN1C0_MEM_RADDR_4_inst     usb_slave|HCLK     DFN1C0       Q       MEM_RADDR_4_net      0.737       -3.180
    FIFO_INST.DFN1C0_MEM_RADDR_5_inst     usb_slave|HCLK     DFN1C0       Q       MEM_RADDR_5_net      0.737       -3.151
    FIFO_INST.DFN1C0_MEM_RADDR_6_inst     usb_slave|HCLK     DFN1C0       Q       MEM_RADDR_6_net      0.737       -3.151
    FIFO_INST.DFN1C0_MEM_RADDR_7_inst     usb_slave|HCLK     DFN1C0       Q       MEM_RADDR_7_net      0.737       -3.121
    =====================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                           Starting                                                      Required
    Instance                               Reference          Type       Pin     Net                     Time         Slack
                                           Clock
    ------------------------------------------------------------------------------------------------------------------------
    FIFO_INST.DFN1P0_EMPTY                 usb_slave|HCLK     DFN1P0     D       EMPTYINT                9.461        -7.469
    FIFO_INST.DFN1C0_RGRY_8_inst           usb_slave|HCLK     DFN1C0     D       XOR2_62_Y               9.461        -4.927
    FIFO_INST.DFN1C0_RGRY_9_inst           usb_slave|HCLK     DFN1C0     D       XOR2_34_Y               9.461        -4.927
    FIFO_INST.DFN1C0_RGRY_6_inst           usb_slave|HCLK     DFN1C0     D       XOR2_63_Y               9.461        -4.506
    FIFO_INST.DFN1C0_RGRY_10_inst          usb_slave|HCLK     DFN1C0     D       XOR2_75_Y               9.461        -4.478
    FIFO_INST.DFN1C0_RGRY_7_inst           usb_slave|HCLK     DFN1C0     D       XOR2_18_Y               9.461        -4.058
    FIFO_INST.DFN1C0_MEM_RADDR_9_inst      usb_slave|HCLK     DFN1C0     D       RBINNXTSHIFT_9_net      9.461        -3.668
    FIFO_INST.DFN1C0_MEM_RADDR_10_inst     usb_slave|HCLK     DFN1C0     D       RBINNXTSHIFT_10_net     9.461        -3.668
    FIFO_INST.DFN1C0_RGRY_5_inst           usb_slave|HCLK     DFN1C0     D       XOR2_78_Y               9.461        -3.587
    FIFO_INST.DFN1C0_RGRY_4_inst           usb_slave|HCLK     DFN1C0     D       XOR2_72_Y               9.461        -3.523
    ========================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            0.539
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.461

        - Propagation time:                      16.930
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     -7.469

        Number of logic level(s):                13
        Starting point:                          FIFO_INST.DFN1P0_EMPTY / Q
        Ending point:                            FIFO_INST.DFN1P0_EMPTY / D
        The start point is clocked by            usb_slave|HCLK [rising] on pin CLK
        The end   point is clocked by            usb_slave|HCLK [rising] on pin CLK

    Instance / Net                                    Pin      Pin               Arrival     No. of
    Name                                   Type       Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------
    FIFO_INST.DFN1P0_EMPTY                 DFN1P0     Q        Out     0.580     0.580       -
    FIFO_EMPTY_BIT_c                       Net        -        -       1.776     -           11
    FIFO_INST.NAND2_1                      NAND2      A        In      -         2.357       -
    FIFO_INST.NAND2_1                      NAND2      Y        Out     0.488     2.845       -
    NAND2_1_Y                              Net        -        -       0.322     -           1
    FIFO_INST.AND2_MEMORYRE                AND2       A        In      -         3.166       -
    FIFO_INST.AND2_MEMORYRE                AND2       Y        Out     0.514     3.681       -
    MEMORYRE                               Net        -        -       0.806     -           3
    FIFO_INST.AND2_74                      AND2       B        In      -         4.487       -
    FIFO_INST.AND2_74                      AND2       Y        Out     0.627     5.115       -
    AND2_74_Y                              Net        -        -       0.386     -           2
    FIFO_INST.AO1_20                       AO1        B        In      -         5.500       -
    FIFO_INST.AO1_20                       AO1        Y        Out     0.598     6.098       -
    AO1_20_Y                               Net        -        -       0.806     -           3
    FIFO_INST.AO1_21                       AO1        B        In      -         6.905       -
    FIFO_INST.AO1_21                       AO1        Y        Out     0.598     7.502       -
    AO1_21_Y                               Net        -        -       1.184     -           4
    FIFO_INST.AO1_0                        AO1        B        In      -         8.686       -
    FIFO_INST.AO1_0                        AO1        Y        Out     0.598     9.284       -
    AO1_0_Y                                Net        -        -       0.386     -           2
    FIFO_INST.AO1_22                       AO1        B        In      -         9.670       -
    FIFO_INST.AO1_22                       AO1        Y        Out     0.598     10.267      -
    AO1_22_Y                               Net        -        -       0.322     -           1
    FIFO_INST.XOR2_RBINNXTSHIFT_7_inst     XOR2       B        In      -         10.589      -
    FIFO_INST.XOR2_RBINNXTSHIFT_7_inst     XOR2       Y        Out     0.937     11.526      -
    RBINNXTSHIFT_7_net                     Net        -        -       1.184     -           4
    FIFO_INST.XNOR2_23                     XNOR2      A        In      -         12.709      -
    FIFO_INST.XNOR2_23                     XNOR2      Y        Out     0.488     13.198      -
    XNOR2_23_Y                             Net        -        -       0.322     -           1
    FIFO_INST.AND3_10                      AND3       B        In      -         13.519      -
    FIFO_INST.AND3_10                      AND3       Y        Out     0.624     14.143      -
    AND3_10_Y                              Net        -        -       0.322     -           1
    FIFO_INST.AND3_9                       AND3       A        In      -         14.464      -
    FIFO_INST.AND3_9                       AND3       Y        Out     0.525     14.989      -
    AND3_9_Y                               Net        -        -       0.322     -           1
    FIFO_INST.AND2_19                      AND2       A        In      -         15.311      -
    FIFO_INST.AND2_19                      AND2       Y        Out     0.488     15.799      -
    AND2_19_Y                              Net        -        -       0.322     -           1
    FIFO_INST.AND2_EMPTYINT                AND2       A        In      -         16.121      -
    FIFO_INST.AND2_EMPTYINT                AND2       Y        Out     0.488     16.609      -
    EMPTYINT                               Net        -        -       0.322     -           1
    FIFO_INST.DFN1P0_EMPTY                 DFN1P0     D        In      -         16.930      -
    ===================================================================================================
    Total path delay (propagation time + setup) of 17.469 is 8.691(49.7%) logic and 8.778(50.3%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      10.000
        - Setup time:                            0.539
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.461

        - Propagation time:                      16.473
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -7.012

        Number of logic level(s):                12
        Starting point:                          FIFO_INST.DFN1P0_EMPTY / Q
        Ending point:                            FIFO_INST.DFN1P0_EMPTY / D
        The start point is clocked by            usb_slave|HCLK [rising] on pin CLK
        The end   point is clocked by            usb_slave|HCLK [rising] on pin CLK

    Instance / Net                                    Pin      Pin               Arrival     No. of
    Name                                   Type       Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------
    FIFO_INST.DFN1P0_EMPTY                 DFN1P0     Q        Out     0.580     0.580       -
    FIFO_EMPTY_BIT_c                       Net        -        -       1.776     -           11
    FIFO_INST.NAND2_1                      NAND2      A        In      -         2.357       -
    FIFO_INST.NAND2_1                      NAND2      Y        Out     0.488     2.845       -
    NAND2_1_Y                              Net        -        -       0.322     -           1
    FIFO_INST.AND2_MEMORYRE                AND2       A        In      -         3.166       -
    FIFO_INST.AND2_MEMORYRE                AND2       Y        Out     0.514     3.681       -
    MEMORYRE                               Net        -        -       0.806     -           3
    FIFO_INST.AND2_74                      AND2       B        In      -         4.487       -
    FIFO_INST.AND2_74                      AND2       Y        Out     0.627     5.115       -
    AND2_74_Y                              Net        -        -       0.386     -           2
    FIFO_INST.AO1_20                       AO1        B        In      -         5.500       -
    FIFO_INST.AO1_20                       AO1        Y        Out     0.598     6.098       -
    AO1_20_Y                               Net        -        -       0.806     -           3
    FIFO_INST.AO1_21                       AO1        B        In      -         6.905       -
    FIFO_INST.AO1_21                       AO1        Y        Out     0.598     7.502       -
    AO1_21_Y                               Net        -        -       1.184     -           4
    FIFO_INST.AO1_42                       AO1        B        In      -         8.686       -
    FIFO_INST.AO1_42                       AO1        Y        Out     0.598     9.284       -
    AO1_42_Y                               Net        -        -       0.806     -           3
    FIFO_INST.XOR2_RBINNXTSHIFT_8_inst     XOR2       B        In      -         10.090      -
    FIFO_INST.XOR2_RBINNXTSHIFT_8_inst     XOR2       Y        Out     0.937     11.027      -
    RBINNXTSHIFT_8_net                     Net        -        -       1.184     -           4
    FIFO_INST.XNOR2_19                     XNOR2      A        In      -         12.211      -
    FIFO_INST.XNOR2_19                     XNOR2      Y        Out     0.488     12.699      -
    XNOR2_19_Y                             Net        -        -       0.322     -           1
    FIFO_INST.AND3_10                      AND3       C        In      -         13.020      -
    FIFO_INST.AND3_10                      AND3       Y        Out     0.666     13.686      -
    AND3_10_Y                              Net        -        -       0.322     -           1
    FIFO_INST.AND3_9                       AND3       A        In      -         14.007      -
    FIFO_INST.AND3_9                       AND3       Y        Out     0.525     14.532      -
    AND3_9_Y                               Net        -        -       0.322     -           1
    FIFO_INST.AND2_19                      AND2       A        In      -         14.854      -
    FIFO_INST.AND2_19                      AND2       Y        Out     0.488     15.342      -
    AND2_19_Y                              Net        -        -       0.322     -           1
    FIFO_INST.AND2_EMPTYINT                AND2       A        In      -         15.664      -
    FIFO_INST.AND2_EMPTYINT                AND2       Y        Out     0.488     16.152      -
    EMPTYINT                               Net        -        -       0.322     -           1
    FIFO_INST.DFN1P0_EMPTY                 DFN1P0     D        In      -         16.473      -
    ===================================================================================================
    Total path delay (propagation time + setup) of 17.012 is 8.135(47.8%) logic and 8.877(52.2%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      10.000
        - Setup time:                            0.539
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.461

        - Propagation time:                      16.129
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -6.668

        Number of logic level(s):                12
        Starting point:                          FIFO_INST.DFN1P0_EMPTY / Q
        Ending point:                            FIFO_INST.DFN1P0_EMPTY / D
        The start point is clocked by            usb_slave|HCLK [rising] on pin CLK
        The end   point is clocked by            usb_slave|HCLK [rising] on pin CLK

    Instance / Net                                    Pin      Pin               Arrival     No. of
    Name                                   Type       Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------
    FIFO_INST.DFN1P0_EMPTY                 DFN1P0     Q        Out     0.580     0.580       -
    FIFO_EMPTY_BIT_c                       Net        -        -       1.776     -           11
    FIFO_INST.NAND2_1                      NAND2      A        In      -         2.357       -
    FIFO_INST.NAND2_1                      NAND2      Y        Out     0.488     2.845       -
    NAND2_1_Y                              Net        -        -       0.322     -           1
    FIFO_INST.AND2_MEMORYRE                AND2       A        In      -         3.166       -
    FIFO_INST.AND2_MEMORYRE                AND2       Y        Out     0.514     3.681       -
    MEMORYRE                               Net        -        -       0.806     -           3
    FIFO_INST.AND2_74                      AND2       B        In      -         4.487       -
    FIFO_INST.AND2_74                      AND2       Y        Out     0.627     5.115       -
    AND2_74_Y                              Net        -        -       0.386     -           2
    FIFO_INST.AO1_20                       AO1        B        In      -         5.500       -
    FIFO_INST.AO1_20                       AO1        Y        Out     0.598     6.098       -
    AO1_20_Y                               Net        -        -       0.806     -           3
    FIFO_INST.AO1_21                       AO1        B        In      -         6.905       -
    FIFO_INST.AO1_21                       AO1        Y        Out     0.598     7.502       -
    AO1_21_Y                               Net        -        -       1.184     -           4
    FIFO_INST.AO1_6                        AO1        B        In      -         8.686       -
    FIFO_INST.AO1_6                        AO1        Y        Out     0.598     9.284       -
    AO1_6_Y                                Net        -        -       0.322     -           1
    FIFO_INST.XOR2_RBINNXTSHIFT_5_inst     XOR2       B        In      -         9.605       -
    FIFO_INST.XOR2_RBINNXTSHIFT_5_inst     XOR2       Y        Out     0.937     10.542      -
    RBINNXTSHIFT_5_net                     Net        -        -       1.184     -           4
    FIFO_INST.XNOR2_12                     XNOR2      A        In      -         11.726      -
    FIFO_INST.XNOR2_12                     XNOR2      Y        Out     0.488     12.214      -
    XNOR2_12_Y                             Net        -        -       0.322     -           1
    FIFO_INST.AND3_6                       AND3       C        In      -         12.535      -
    FIFO_INST.AND3_6                       AND3       Y        Out     0.666     13.201      -
    AND3_6_Y                               Net        -        -       0.322     -           1
    FIFO_INST.AND3_9                       AND3       C        In      -         13.523      -
    FIFO_INST.AND3_9                       AND3       Y        Out     0.666     14.188      -
    AND3_9_Y                               Net        -        -       0.322     -           1
    FIFO_INST.AND2_19                      AND2       A        In      -         14.510      -
    FIFO_INST.AND2_19                      AND2       Y        Out     0.488     14.998      -
    AND2_19_Y                              Net        -        -       0.322     -           1
    FIFO_INST.AND2_EMPTYINT                AND2       A        In      -         15.319      -
    FIFO_INST.AND2_EMPTYINT                AND2       Y        Out     0.488     15.808      -
    EMPTYINT                               Net        -        -       0.322     -           1
    FIFO_INST.DFN1P0_EMPTY                 DFN1P0     D        In      -         16.129      -
    ===================================================================================================
    Total path delay (propagation time + setup) of 16.668 is 8.275(49.6%) logic and 8.393(50.4%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      10.000
        - Setup time:                            0.539
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.461

        - Propagation time:                      15.912
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -6.451

        Number of logic level(s):                12
        Starting point:                          FIFO_INST.DFN1P0_EMPTY / Q
        Ending point:                            FIFO_INST.DFN1P0_EMPTY / D
        The start point is clocked by            usb_slave|HCLK [rising] on pin CLK
        The end   point is clocked by            usb_slave|HCLK [rising] on pin CLK

    Instance / Net                                    Pin      Pin               Arrival     No. of
    Name                                   Type       Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------
    FIFO_INST.DFN1P0_EMPTY                 DFN1P0     Q        Out     0.580     0.580       -
    FIFO_EMPTY_BIT_c                       Net        -        -       1.776     -           11
    FIFO_INST.NAND2_1                      NAND2      A        In      -         2.357       -
    FIFO_INST.NAND2_1                      NAND2      Y        Out     0.488     2.845       -
    NAND2_1_Y                              Net        -        -       0.322     -           1
    FIFO_INST.AND2_MEMORYRE                AND2       A        In      -         3.166       -
    FIFO_INST.AND2_MEMORYRE                AND2       Y        Out     0.514     3.681       -
    MEMORYRE                               Net        -        -       0.806     -           3
    FIFO_INST.AND2_74                      AND2       B        In      -         4.487       -
    FIFO_INST.AND2_74                      AND2       Y        Out     0.627     5.115       -
    AND2_74_Y                              Net        -        -       0.386     -           2
    FIFO_INST.AO1_20                       AO1        B        In      -         5.500       -
    FIFO_INST.AO1_20                       AO1        Y        Out     0.598     6.098       -
    AO1_20_Y                               Net        -        -       0.806     -           3
    FIFO_INST.AO1_21                       AO1        B        In      -         6.905       -
    FIFO_INST.AO1_21                       AO1        Y        Out     0.598     7.502       -
    AO1_21_Y                               Net        -        -       1.184     -           4
    FIFO_INST.AO1_0                        AO1        B        In      -         8.686       -
    FIFO_INST.AO1_0                        AO1        Y        Out     0.598     9.284       -
    AO1_0_Y                                Net        -        -       0.386     -           2
    FIFO_INST.XOR2_RBINNXTSHIFT_6_inst     XOR2       B        In      -         9.670       -
    FIFO_INST.XOR2_RBINNXTSHIFT_6_inst     XOR2       Y        Out     0.937     10.606      -
    RBINNXTSHIFT_6_net                     Net        -        -       1.184     -           4
    FIFO_INST.XNOR2_21                     XNOR2      A        In      -         11.790      -
    FIFO_INST.XNOR2_21                     XNOR2      Y        Out     0.488     12.278      -
    XNOR2_21_Y                             Net        -        -       0.322     -           1
    FIFO_INST.AND3_10                      AND3       A        In      -         12.600      -
    FIFO_INST.AND3_10                      AND3       Y        Out     0.525     13.124      -
    AND3_10_Y                              Net        -        -       0.322     -           1
    FIFO_INST.AND3_9                       AND3       A        In      -         13.446      -
    FIFO_INST.AND3_9                       AND3       Y        Out     0.525     13.971      -
    AND3_9_Y                               Net        -        -       0.322     -           1
    FIFO_INST.AND2_19                      AND2       A        In      -         14.292      -
    FIFO_INST.AND2_19                      AND2       Y        Out     0.488     14.781      -
    AND2_19_Y                              Net        -        -       0.322     -           1
    FIFO_INST.AND2_EMPTYINT                AND2       A        In      -         15.102      -
    FIFO_INST.AND2_EMPTYINT                AND2       Y        Out     0.488     15.590      -
    EMPTYINT                               Net        -        -       0.322     -           1
    FIFO_INST.DFN1P0_EMPTY                 DFN1P0     D        In      -         15.912      -
    ===================================================================================================
    Total path delay (propagation time + setup) of 16.451 is 7.994(48.6%) logic and 8.457(51.4%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      10.000
        - Setup time:                            0.573
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.427

        - Propagation time:                      15.645
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -6.218

        Number of logic level(s):                11
        Starting point:                          FIFO_INST.DFN1P0_EMPTY / Q
        Ending point:                            FIFO_INST.DFN1P0_EMPTY / D
        The start point is clocked by            usb_slave|HCLK [rising] on pin CLK
        The end   point is clocked by            usb_slave|HCLK [rising] on pin CLK

    Instance / Net                                    Pin      Pin               Arrival     No. of
    Name                                   Type       Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------
    FIFO_INST.DFN1P0_EMPTY                 DFN1P0     Q        Out     0.580     0.580       -
    FIFO_EMPTY_BIT_c                       Net        -        -       1.776     -           11
    FIFO_INST.NAND2_1                      NAND2      A        In      -         2.357       -
    FIFO_INST.NAND2_1                      NAND2      Y        Out     0.488     2.845       -
    NAND2_1_Y                              Net        -        -       0.322     -           1
    FIFO_INST.AND2_MEMORYRE                AND2       A        In      -         3.166       -
    FIFO_INST.AND2_MEMORYRE                AND2       Y        Out     0.514     3.681       -
    MEMORYRE                               Net        -        -       0.806     -           3
    FIFO_INST.AND2_74                      AND2       B        In      -         4.487       -
    FIFO_INST.AND2_74                      AND2       Y        Out     0.627     5.115       -
    AND2_74_Y                              Net        -        -       0.386     -           2
    FIFO_INST.AO1_20                       AO1        B        In      -         5.500       -
    FIFO_INST.AO1_20                       AO1        Y        Out     0.598     6.098       -
    AO1_20_Y                               Net        -        -       0.806     -           3
    FIFO_INST.AO1_21                       AO1        B        In      -         6.905       -
    FIFO_INST.AO1_21                       AO1        Y        Out     0.598     7.502       -
    AO1_21_Y                               Net        -        -       1.184     -           4
    FIFO_INST.AO1_42                       AO1        B        In      -         8.686       -
    FIFO_INST.AO1_42                       AO1        Y        Out     0.598     9.284       -
    AO1_42_Y                               Net        -        -       0.806     -           3
    FIFO_INST.AO1_31                       AO1        B        In      -         10.090      -
    FIFO_INST.AO1_31                       AO1        Y        Out     0.598     10.688      -
    AO1_31_Y                               Net        -        -       0.322     -           1
    FIFO_INST.XOR2_RBINNXTSHIFT_9_inst     XOR2       B        In      -         11.009      -
    FIFO_INST.XOR2_RBINNXTSHIFT_9_inst     XOR2       Y        Out     0.937     11.946      -
    RBINNXTSHIFT_9_net                     Net        -        -       1.184     -           4
    FIFO_INST.XNOR2_11                     XNOR2      A        In      -         13.130      -
    FIFO_INST.XNOR2_11                     XNOR2      Y        Out     0.408     13.538      -
    XNOR2_11_Y                             Net        -        -       0.322     -           1
    FIFO_INST.AND2_19                      AND2       B        In      -         13.860      -
    FIFO_INST.AND2_19                      AND2       Y        Out     0.627     14.487      -
    AND2_19_Y                              Net        -        -       0.322     -           1
    FIFO_INST.AND2_EMPTYINT                AND2       A        In      -         14.809      -
    FIFO_INST.AND2_EMPTYINT                AND2       Y        Out     0.514     15.323      -
    EMPTYINT                               Net        -        -       0.322     -           1
    FIFO_INST.DFN1P0_EMPTY                 DFN1P0     D        In      -         15.645      -
    ===================================================================================================
    Total path delay (propagation time + setup) of 16.218 is 7.662(47.2%) logic and 8.556(52.8%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: usb_slave|USB_CLK
    ====================================

    Starting Points with Worst Slack
    ********************************

                                          Starting                                                     Arrival
    Instance                              Reference             Type       Pin     Net                 Time        Slack
                                          Clock
    ---------------------------------------------------------------------------------------------------------------------
    FIFO_INST.DFN1C0_FULL                 usb_slave|USB_CLK     DFN1C0     Q       FIFO_FULL           0.737       -3.848
    FIFO_INST.DFN1C0_MEM_WADDR_1_inst     usb_slave|USB_CLK     DFN1C0     Q       MEM_WADDR_1_net     0.737       -3.163
    FIFO_INST.DFN1C0_MEM_WADDR_0_inst     usb_slave|USB_CLK     DFN1C0     Q       MEM_WADDR_0_net     0.737       -2.944
    FIFO_INST.DFN1C0_MEM_WADDR_2_inst     usb_slave|USB_CLK     DFN1C0     Q       MEM_WADDR_2_net     0.737       -2.742
    FIFO_INST.DFN1C0_MEM_WADDR_3_inst     usb_slave|USB_CLK     DFN1C0     Q       MEM_WADDR_3_net     0.737       -2.713
    FIFO_INST.DFN1C0_MEM_WADDR_5_inst     usb_slave|USB_CLK     DFN1C0     Q       MEM_WADDR_5_net     0.737       -2.372
    FIFO_INST.DFN1C0_MEM_WADDR_4_inst     usb_slave|USB_CLK     DFN1C0     Q       MEM_WADDR_4_net     0.737       -2.139
    FIFO_INST.DFN1C0_MEM_WADDR_7_inst     usb_slave|USB_CLK     DFN1C0     Q       MEM_WADDR_7_net     0.737       -2.084
    FIFO_INST.DFN1C0_MEM_WADDR_6_inst     usb_slave|USB_CLK     DFN1C0     Q       MEM_WADDR_6_net     0.737       -1.917
    FIFO_INST.DFN1C0_RGRYSYNC_10_inst     usb_slave|USB_CLK     DFN1C0     Q       RGRYSYNC_10_net     0.737       -0.533
    =====================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                           Starting                                                         Required
    Instance                               Reference             Type       Pin     Net                     Time         Slack
                                           Clock
    ---------------------------------------------------------------------------------------------------------------------------
    FIFO_INST.DFN1C0_FULL                  usb_slave|USB_CLK     DFN1C0     D       FULLINT                 9.461        -3.848
    FIFO_INST.DFN1C0_WGRY_9_inst           usb_slave|USB_CLK     DFN1C0     D       XOR2_15_Y               9.461        -2.998
    FIFO_INST.DFN1C0_WGRY_7_inst           usb_slave|USB_CLK     DFN1C0     D       XOR2_50_Y               9.461        -2.577
    FIFO_INST.DFN1C0_WGRY_8_inst           usb_slave|USB_CLK     DFN1C0     D       XOR2_52_Y               9.461        -2.549
    FIFO_INST.DFN1C0_WGRY_10_inst          usb_slave|USB_CLK     DFN1C0     D       XOR2_44_Y               9.461        -2.502
    FIFO_INST.DFN1C0_WGRY_6_inst           usb_slave|USB_CLK     DFN1C0     D       XOR2_41_Y               9.461        -2.129
    FIFO_INST.DFN1C0_MEM_WADDR_9_inst      usb_slave|USB_CLK     DFN1C0     D       WBINNXTSHIFT_9_net      9.461        -1.740
    FIFO_INST.DFN1C0_MEM_WADDR_10_inst     usb_slave|USB_CLK     DFN1C0     D       WBINNXTSHIFT_10_net     9.461        -1.693
    FIFO_INST.DFN1C0_WGRY_5_inst           usb_slave|USB_CLK     DFN1C0     D       XOR2_29_Y               9.461        -1.625
    FIFO_INST.DFN1C0_MEM_WADDR_7_inst      usb_slave|USB_CLK     DFN1C0     D       WBINNXTSHIFT_7_net      9.461        -1.319
    ===========================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            0.539
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.461

        - Propagation time:                      13.309
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -3.848

        Number of logic level(s):                10
        Starting point:                          FIFO_INST.DFN1C0_FULL / Q
        Ending point:                            FIFO_INST.DFN1C0_FULL / D
        The start point is clocked by            usb_slave|USB_CLK [falling] on pin CLK
        The end   point is clocked by            usb_slave|USB_CLK [falling] on pin CLK

    Instance / Net                             Pin      Pin               Arrival     No. of
    Name                            Type       Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------
    FIFO_INST.DFN1C0_FULL           DFN1C0     Q        Out     0.737     0.737       -
    FIFO_FULL                       Net        -        -       0.322     -           1
    FIFO_INST.NAND2_0               NAND2      A        In      -         1.058       -
    FIFO_INST.NAND2_0               NAND2      Y        Out     0.514     1.573       -
    NAND2_0_Y                       Net        -        -       1.184     -           4
    FIFO_INST.NAND2_0_RNISBRF       NOR3C      C        In      -         2.756       -
    FIFO_INST.NAND2_0_RNISBRF       NOR3C      Y        Out     0.666     3.422       -
    G_28_1                          Net        -        -       0.322     -           1
    FIFO_INST.XOR2_31_RNIBCNN       AO1        A        In      -         3.744       -
    FIFO_INST.XOR2_31_RNIBCNN       AO1        Y        Out     0.520     4.263       -
    AO1_1_Y_0                       Net        -        -       0.806     -           3
    FIFO_INST.XOR2_16_RNIKLL11      AO1        B        In      -         5.069       -
    FIFO_INST.XOR2_16_RNIKLL11      AO1        Y        Out     0.567     5.636       -
    AO1_44_Y_0                      Net        -        -       1.184     -           4
    FIFO_INST.XOR2_70_RNIU82I1      AO1        B        In      -         6.820       -
    FIFO_INST.XOR2_70_RNIU82I1      AO1        Y        Out     0.567     7.386       -
    AO1_36_Y_0                      Net        -        -       0.386     -           2
    FIFO_INST.AND2_63_RNI1GFR1      AO1        B        In      -         7.772       -
    FIFO_INST.AND2_63_RNI1GFR1      AO1        Y        Out     0.567     8.338       -
    AO1_18_Y_0                      Net        -        -       0.322     -           1
    FIFO_INST.XOR2_67_RNI524S1      XOR2       B        In      -         8.660       -
    FIFO_INST.XOR2_67_RNI524S1      XOR2       Y        Out     0.937     9.597       -
    WBINNXTSHIFT_7_net              Net        -        -       1.184     -           4
    FIFO_INST.DFN1C0_FULL_RNO_6     XOR2       A        In      -         10.780      -
    FIFO_INST.DFN1C0_FULL_RNO_6     XOR2       Y        Out     0.408     11.189      -
    N_1                             Net        -        -       0.322     -           1
    FIFO_INST.DFN1C0_FULL_RNO_2     XA1C       C        In      -         11.510      -
    FIFO_INST.DFN1C0_FULL_RNO_2     XA1C       Y        Out     0.490     12.000      -
    G_66_7                          Net        -        -       0.322     -           1
    FIFO_INST.DFN1C0_FULL_RNO       NOR3C      C        In      -         12.322      -
    FIFO_INST.DFN1C0_FULL_RNO       NOR3C      Y        Out     0.666     12.987      -
    FULLINT                         Net        -        -       0.322     -           1
    FIFO_INST.DFN1C0_FULL           DFN1C0     D        In      -         13.309      -
    ============================================================================================
    Total path delay (propagation time + setup) of 13.848 is 7.176(51.8%) logic and 6.672(48.2%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 2:
          Requested Period:                      10.000
        - Setup time:                            0.539
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.461

        - Propagation time:                      13.225
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -3.764

        Number of logic level(s):                10
        Starting point:                          FIFO_INST.DFN1C0_FULL / Q
        Ending point:                            FIFO_INST.DFN1C0_FULL / D
        The start point is clocked by            usb_slave|USB_CLK [falling] on pin CLK
        The end   point is clocked by            usb_slave|USB_CLK [falling] on pin CLK

    Instance / Net                              Pin      Pin               Arrival     No. of
    Name                             Type       Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------
    FIFO_INST.DFN1C0_FULL            DFN1C0     Q        Out     0.737     0.737       -
    FIFO_FULL                        Net        -        -       0.322     -           1
    FIFO_INST.NAND2_0                NAND2      A        In      -         1.058       -
    FIFO_INST.NAND2_0                NAND2      Y        Out     0.514     1.573       -
    NAND2_0_Y                        Net        -        -       1.184     -           4
    FIFO_INST.NAND2_0_RNISBRF        NOR3C      C        In      -         2.756       -
    FIFO_INST.NAND2_0_RNISBRF        NOR3C      Y        Out     0.666     3.422       -
    G_28_1                           Net        -        -       0.322     -           1
    FIFO_INST.XOR2_31_RNIBCNN        AO1        A        In      -         3.744       -
    FIFO_INST.XOR2_31_RNIBCNN        AO1        Y        Out     0.520     4.263       -
    AO1_1_Y_0                        Net        -        -       0.806     -           3
    FIFO_INST.XOR2_16_RNIKLL11       AO1        B        In      -         5.069       -
    FIFO_INST.XOR2_16_RNIKLL11       AO1        Y        Out     0.567     5.636       -
    AO1_44_Y_0                       Net        -        -       1.184     -           4
    FIFO_INST.XOR2_70_RNIU82I1       AO1        B        In      -         6.820       -
    FIFO_INST.XOR2_70_RNIU82I1       AO1        Y        Out     0.567     7.386       -
    AO1_36_Y_0                       Net        -        -       0.386     -           2
    FIFO_INST.XOR2_43_RNISQMI1       XOR2       B        In      -         7.772       -
    FIFO_INST.XOR2_43_RNISQMI1       XOR2       Y        Out     0.937     8.709       -
    WBINNXTSHIFT_6_net               Net        -        -       1.184     -           4
    FIFO_INST.DFN1C0_FULL_RNO_10     XOR2       A        In      -         9.892       -
    FIFO_INST.DFN1C0_FULL_RNO_10     XOR2       Y        Out     0.408     10.301      -
    N_1_23                           Net        -        -       0.322     -           1
    FIFO_INST.DFN1C0_FULL_RNO_4      XA1C       C        In      -         10.622      -
    FIFO_INST.DFN1C0_FULL_RNO_4      XA1C       Y        Out     0.490     11.112      -
    G_66_5                           Net        -        -       0.322     -           1
    FIFO_INST.DFN1C0_FULL_RNO_0      NOR3B      B        In      -         11.434      -
    FIFO_INST.DFN1C0_FULL_RNO_0      NOR3B      Y        Out     0.624     12.058      -
    G_66_6                           Net        -        -       0.322     -           1
    FIFO_INST.DFN1C0_FULL_RNO        NOR3C      A        In      -         12.379      -
    FIFO_INST.DFN1C0_FULL_RNO        NOR3C      Y        Out     0.525     12.904      -
    FULLINT                          Net        -        -       0.322     -           1
    FIFO_INST.DFN1C0_FULL            DFN1C0     D        In      -         13.225      -
    =============================================================================================
    Total path delay (propagation time + setup) of 13.764 is 7.092(51.5%) logic and 6.672(48.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 3:
          Requested Period:                      10.000
        - Setup time:                            0.573
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.427

        - Propagation time:                      13.113
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -3.686

        Number of logic level(s):                9
        Starting point:                          FIFO_INST.DFN1C0_FULL / Q
        Ending point:                            FIFO_INST.DFN1C0_FULL / D
        The start point is clocked by            usb_slave|USB_CLK [falling] on pin CLK
        The end   point is clocked by            usb_slave|USB_CLK [falling] on pin CLK

    Instance / Net                             Pin      Pin               Arrival     No. of
    Name                            Type       Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------
    FIFO_INST.DFN1C0_FULL           DFN1C0     Q        Out     0.737     0.737       -
    FIFO_FULL                       Net        -        -       0.322     -           1
    FIFO_INST.NAND2_0               NAND2      A        In      -         1.058       -
    FIFO_INST.NAND2_0               NAND2      Y        Out     0.514     1.573       -
    NAND2_0_Y                       Net        -        -       1.184     -           4
    FIFO_INST.NAND2_0_RNISBRF       NOR3C      C        In      -         2.756       -
    FIFO_INST.NAND2_0_RNISBRF       NOR3C      Y        Out     0.666     3.422       -
    G_28_1                          Net        -        -       0.322     -           1
    FIFO_INST.XOR2_31_RNIBCNN       AO1        A        In      -         3.744       -
    FIFO_INST.XOR2_31_RNIBCNN       AO1        Y        Out     0.520     4.263       -
    AO1_1_Y_0                       Net        -        -       0.806     -           3
    FIFO_INST.XOR2_16_RNIKLL11      AO1        B        In      -         5.069       -
    FIFO_INST.XOR2_16_RNIKLL11      AO1        Y        Out     0.567     5.636       -
    AO1_44_Y_0                      Net        -        -       1.184     -           4
    FIFO_INST.XOR2_55_RNI3DQ62      AO1        B        In      -         6.820       -
    FIFO_INST.XOR2_55_RNI3DQ62      AO1        Y        Out     0.567     7.386       -
    AO1_30_Y_0                      Net        -        -       0.806     -           3
    FIFO_INST.XOR2_19_RNIUDME2      AO1        B        In      -         8.193       -
    FIFO_INST.XOR2_19_RNIUDME2      AO1        Y        Out     0.567     8.759       -
    AO1_33_Y_0                      Net        -        -       0.322     -           1
    FIFO_INST.XOR2_1_RNIE6SG2       XOR2       B        In      -         9.081       -
    FIFO_INST.XOR2_1_RNIE6SG2       XOR2       Y        Out     0.937     10.017      -
    WBINNXTSHIFT_9_net              Net        -        -       1.184     -           4
    FIFO_INST.DFN1C0_FULL_RNO_2     XA1C       B        In      -         11.201      -
    FIFO_INST.DFN1C0_FULL_RNO_2     XA1C       Y        Out     0.627     11.828      -
    G_66_7                          Net        -        -       0.322     -           1
    FIFO_INST.DFN1C0_FULL_RNO       NOR3C      C        In      -         12.150      -
    FIFO_INST.DFN1C0_FULL_RNO       NOR3C      Y        Out     0.641     12.791      -
    FULLINT                         Net        -        -       0.322     -           1
    FIFO_INST.DFN1C0_FULL           DFN1C0     D        In      -         13.113      -
    ============================================================================================
    Total path delay (propagation time + setup) of 13.686 is 6.915(50.5%) logic and 6.771(49.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 4:
          Requested Period:                      10.000
        - Setup time:                            0.539
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.461

        - Propagation time:                      13.019
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -3.557

        Number of logic level(s):                9
        Starting point:                          FIFO_INST.DFN1C0_FULL / Q
        Ending point:                            FIFO_INST.DFN1C0_FULL / D
        The start point is clocked by            usb_slave|USB_CLK [falling] on pin CLK
        The end   point is clocked by            usb_slave|USB_CLK [falling] on pin CLK

    Instance / Net                             Pin      Pin               Arrival     No. of
    Name                            Type       Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------
    FIFO_INST.DFN1C0_FULL           DFN1C0     Q        Out     0.737     0.737       -
    FIFO_FULL                       Net        -        -       0.322     -           1
    FIFO_INST.NAND2_0               NAND2      A        In      -         1.058       -
    FIFO_INST.NAND2_0               NAND2      Y        Out     0.514     1.573       -
    NAND2_0_Y                       Net        -        -       1.184     -           4
    FIFO_INST.NAND2_0_RNISBRF       NOR3C      C        In      -         2.756       -
    FIFO_INST.NAND2_0_RNISBRF       NOR3C      Y        Out     0.666     3.422       -
    G_28_1                          Net        -        -       0.322     -           1
    FIFO_INST.XOR2_31_RNIBCNN       AO1        A        In      -         3.744       -
    FIFO_INST.XOR2_31_RNIBCNN       AO1        Y        Out     0.520     4.263       -
    AO1_1_Y_0                       Net        -        -       0.806     -           3
    FIFO_INST.XOR2_16_RNIKLL11      AO1        B        In      -         5.069       -
    FIFO_INST.XOR2_16_RNIKLL11      AO1        Y        Out     0.567     5.636       -
    AO1_44_Y_0                      Net        -        -       1.184     -           4
    FIFO_INST.XOR2_55_RNI3DQ62      AO1        B        In      -         6.820       -
    FIFO_INST.XOR2_55_RNI3DQ62      AO1        Y        Out     0.567     7.386       -
    AO1_30_Y_0                      Net        -        -       0.806     -           3
    FIFO_INST.XOR2_25_RNI1VE72      XOR2       B        In      -         8.193       -
    FIFO_INST.XOR2_25_RNI1VE72      XOR2       Y        Out     0.937     9.129       -
    WBINNXTSHIFT_8_net              Net        -        -       1.184     -           4
    FIFO_INST.DFN1C0_FULL_RNO_4     XA1C       B        In      -         10.313      -
    FIFO_INST.DFN1C0_FULL_RNO_4     XA1C       Y        Out     0.593     10.905      -
    G_66_5                          Net        -        -       0.322     -           1
    FIFO_INST.DFN1C0_FULL_RNO_0     NOR3B      B        In      -         11.227      -
    FIFO_INST.DFN1C0_FULL_RNO_0     NOR3B      Y        Out     0.624     11.851      -
    G_66_6                          Net        -        -       0.322     -           1
    FIFO_INST.DFN1C0_FULL_RNO       NOR3C      A        In      -         12.172      -
    FIFO_INST.DFN1C0_FULL_RNO       NOR3C      Y        Out     0.525     12.697      -
    FULLINT                         Net        -        -       0.322     -           1
    FIFO_INST.DFN1C0_FULL           DFN1C0     D        In      -         13.019      -
    ============================================================================================
    Total path delay (propagation time + setup) of 13.557 is 6.786(50.1%) logic and 6.771(49.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    Path information for path number 5:
          Requested Period:                      10.000
        - Setup time:                            0.539
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.461

        - Propagation time:                      12.909
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 -3.448

        Number of logic level(s):                9
        Starting point:                          FIFO_INST.DFN1C0_FULL / Q
        Ending point:                            FIFO_INST.DFN1C0_FULL / D
        The start point is clocked by            usb_slave|USB_CLK [falling] on pin CLK
        The end   point is clocked by            usb_slave|USB_CLK [falling] on pin CLK

    Instance / Net                             Pin      Pin               Arrival     No. of
    Name                            Type       Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------
    FIFO_INST.DFN1C0_FULL           DFN1C0     Q        Out     0.737     0.737       -
    FIFO_FULL                       Net        -        -       0.322     -           1
    FIFO_INST.NAND2_0               NAND2      A        In      -         1.058       -
    FIFO_INST.NAND2_0               NAND2      Y        Out     0.514     1.573       -
    NAND2_0_Y                       Net        -        -       1.184     -           4
    FIFO_INST.NAND2_0_RNISBRF       NOR3C      C        In      -         2.756       -
    FIFO_INST.NAND2_0_RNISBRF       NOR3C      Y        Out     0.666     3.422       -
    G_28_1                          Net        -        -       0.322     -           1
    FIFO_INST.XOR2_31_RNIBCNN       AO1        A        In      -         3.744       -
    FIFO_INST.XOR2_31_RNIBCNN       AO1        Y        Out     0.520     4.263       -
    AO1_1_Y_0                       Net        -        -       0.806     -           3
    FIFO_INST.XOR2_16_RNIKLL11      AO1        B        In      -         5.069       -
    FIFO_INST.XOR2_16_RNIKLL11      AO1        Y        Out     0.567     5.636       -
    AO1_44_Y_0                      Net        -        -       1.184     -           4
    FIFO_INST.XOR2_55_RNI3DQ62      AO1        B        In      -         6.820       -
    FIFO_INST.XOR2_55_RNI3DQ62      AO1        Y        Out     0.567     7.386       -
    AO1_30_Y_0                      Net        -        -       0.806     -           3
    FIFO_INST.AO1_23_RNILQBE2       AO1        A        In      -         8.193       -
    FIFO_INST.AO1_23_RNILQBE2       AO1        Y        Out     0.520     8.712       -
    AO1_9_Y_0                       Net        -        -       0.322     -           1
    FIFO_INST.XOR2_69_RNIRC0F2      XOR2       B        In      -         9.034       -
    FIFO_INST.XOR2_69_RNIRC0F2      XOR2       Y        Out     0.937     9.970       -
    WBINNXTSHIFT_10_net             Net        -        -       1.184     -           4
    FIFO_INST.DFN1C0_FULL_RNO_1     XOR2       A        In      -         11.154      -
    FIFO_INST.DFN1C0_FULL_RNO_1     XOR2       Y        Out     0.488     11.642      -
    XOR2_45_Y_0                     Net        -        -       0.322     -           1
    FIFO_INST.DFN1C0_FULL_RNO       NOR3C      B        In      -         11.964      -
    FIFO_INST.DFN1C0_FULL_RNO       NOR3C      Y        Out     0.624     12.588      -
    FULLINT                         Net        -        -       0.322     -           1
    FIFO_INST.DFN1C0_FULL           DFN1C0     D        In      -         12.909      -
    ============================================================================================
    Total path delay (propagation time + setup) of 13.448 is 6.677(49.6%) logic and 6.771(50.4%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    --------------------------------------------------------------------------------
    Target Part: A2F200M3F_FBGA256_Std
    Report for cell usb_slave.usb_slave
      Core Cell usage:
                  cell count     area count*area
                  AND2    29      1.0       29.0
                 AND2A     1      1.0        1.0
                  AND3     4      1.0        4.0
                   AO1    29      1.0       29.0
                  AO1A     1      1.0        1.0
                  AO1B    32      1.0       32.0
                  AO1C     4      1.0        4.0
                  AO1D     1      1.0        1.0
                   AX1    11      1.0       11.0
                  AX1A     1      1.0        1.0
                  AX1C    12      1.0       12.0
                  AX1E     1      1.0        1.0
                  BUFF     5      1.0        5.0
                   GND     2      0.0        0.0
                   INV     6      1.0        6.0
                   MX2     8      1.0        8.0
                  MX2B     1      1.0        1.0
                 NAND2     2      1.0        2.0
                  NOR2    10      1.0       10.0
                 NOR2A     5      1.0        5.0
                 NOR2B    29      1.0       29.0
                  NOR3     2      1.0        2.0
                 NOR3A    13      1.0       13.0
                 NOR3B    10      1.0       10.0
                 NOR3C    15      1.0       15.0
                  OA1B     2      1.0        2.0
                  OA1C     1      1.0        1.0
                   OR2     5      1.0        5.0
                  OR2A     2      1.0        2.0
                  OR2B    45      1.0       45.0
                   OR3     5      1.0        5.0
                  OR3A     1      1.0        1.0
                  OR3B     3      1.0        3.0
                  OR3C     3      1.0        3.0
                   VCC     2      0.0        0.0
                  XA1C     2      1.0        2.0
                 XNOR2    22      1.0       22.0
                 XNOR3    34      1.0       34.0
                  XOR2   104      1.0      104.0
                  XOR3    14      1.0       14.0

              DFI1E1P0     1      1.0        1.0
                  DFN1     1      1.0        1.0
                DFN1C0   106      1.0      106.0
              DFN1E0C0    34      1.0       34.0
                DFN1E1     2      1.0        2.0
              DFN1E1C0    57      1.0       57.0
              DFN1E1P0    15      1.0       15.0
                DFN1P0     3      1.0        3.0
                RAM4K9     2      0.0        0.0
                       -----          ----------
                 TOTAL   700               694.0

      IO Cell usage:
                  cell count
       BIBUF_LVCMOS33U     8
                CLKBUF     2
                 INBUF     3
                OUTBUF    75
                       -----
                 TOTAL    88

    Core Cells         : 694 of 4608 (15%)
    IO Cells           : 88 of 66 (133%)

      RAM/ROM Usage Summary
    Block Rams : 2 of 8 (25%)

    Mapper successful!
    Process took 0h:00m:13s realtime, 0h:00m:05s cputime
    # Fri Jul 16 10:14:31 2010

    ###########################################################]

`