-- Version: 9.0 SPC 9.0.1.10

library ieee;
use ieee.std_logic_1164.all;
library smartfusion;
use smartfusion.all;

entity Fifo_1024 is

    port( USB_DATA_OUT     : out   std_logic_vector(7 downto 0);
          USB_DATA_IN      : in    std_logic_vector(7 downto 0);
          R_W_N_c          : in    std_logic;
          REP              : in    std_logic;
          USB_CLK_c        : in    std_logic;
          Fifo_1024_VCC    : in    std_logic;
          FIFO_EMPTY_BIT_c : out   std_logic;
          Fifo_1024_GND    : in    std_logic;
          RESET_N_c        : in    std_logic;
          HCLK_c           : in    std_logic
        );

end Fifo_1024;

architecture DEF_ARCH of Fifo_1024 is 

  component XNOR3
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component AO1
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component AND3
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component XNOR2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component DFN1C0
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          CLR : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component AND2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component XOR2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component NOR3B
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component OR2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component BUFF
    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component NOR2B
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component NOR3C
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component RAM4K9
    generic (MEMORYFILE:string := "");

    port( ADDRA11 : in    std_logic := 'U';
          ADDRA10 : in    std_logic := 'U';
          ADDRA9  : in    std_logic := 'U';
          ADDRA8  : in    std_logic := 'U';
          ADDRA7  : in    std_logic := 'U';
          ADDRA6  : in    std_logic := 'U';
          ADDRA5  : in    std_logic := 'U';
          ADDRA4  : in    std_logic := 'U';
          ADDRA3  : in    std_logic := 'U';
          ADDRA2  : in    std_logic := 'U';
          ADDRA1  : in    std_logic := 'U';
          ADDRA0  : in    std_logic := 'U';
          ADDRB11 : in    std_logic := 'U';
          ADDRB10 : in    std_logic := 'U';
          ADDRB9  : in    std_logic := 'U';
          ADDRB8  : in    std_logic := 'U';
          ADDRB7  : in    std_logic := 'U';
          ADDRB6  : in    std_logic := 'U';
          ADDRB5  : in    std_logic := 'U';
          ADDRB4  : in    std_logic := 'U';
          ADDRB3  : in    std_logic := 'U';
          ADDRB2  : in    std_logic := 'U';
          ADDRB1  : in    std_logic := 'U';
          ADDRB0  : in    std_logic := 'U';
          DINA8   : in    std_logic := 'U';
          DINA7   : in    std_logic := 'U';
          DINA6   : in    std_logic := 'U';
          DINA5   : in    std_logic := 'U';
          DINA4   : in    std_logic := 'U';
          DINA3   : in    std_logic := 'U';
          DINA2   : in    std_logic := 'U';
          DINA1   : in    std_logic := 'U';
          DINA0   : in    std_logic := 'U';
          DINB8   : in    std_logic := 'U';
          DINB7   : in    std_logic := 'U';
          DINB6   : in    std_logic := 'U';
          DINB5   : in    std_logic := 'U';
          DINB4   : in    std_logic := 'U';
          DINB3   : in    std_logic := 'U';
          DINB2   : in    std_logic := 'U';
          DINB1   : in    std_logic := 'U';
          DINB0   : in    std_logic := 'U';
          WIDTHA0 : in    std_logic := 'U';
          WIDTHA1 : in    std_logic := 'U';
          WIDTHB0 : in    std_logic := 'U';
          WIDTHB1 : in    std_logic := 'U';
          PIPEA   : in    std_logic := 'U';
          PIPEB   : in    std_logic := 'U';
          WMODEA  : in    std_logic := 'U';
          WMODEB  : in    std_logic := 'U';
          BLKA    : in    std_logic := 'U';
          BLKB    : in    std_logic := 'U';
          WENA    : in    std_logic := 'U';
          WENB    : in    std_logic := 'U';
          CLKA    : in    std_logic := 'U';
          CLKB    : in    std_logic := 'U';
          RESET   : in    std_logic := 'U';
          DOUTA8  : out   std_logic;
          DOUTA7  : out   std_logic;
          DOUTA6  : out   std_logic;
          DOUTA5  : out   std_logic;
          DOUTA4  : out   std_logic;
          DOUTA3  : out   std_logic;
          DOUTA2  : out   std_logic;
          DOUTA1  : out   std_logic;
          DOUTA0  : out   std_logic;
          DOUTB8  : out   std_logic;
          DOUTB7  : out   std_logic;
          DOUTB6  : out   std_logic;
          DOUTB5  : out   std_logic;
          DOUTB4  : out   std_logic;
          DOUTB3  : out   std_logic;
          DOUTB2  : out   std_logic;
          DOUTB1  : out   std_logic;
          DOUTB0  : out   std_logic
        );
  end component;

  component DFN1E1C0
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          CLR : in    std_logic := 'U';
          E   : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component MX2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          S : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component AND2A
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component INV
    port( A : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component XOR3
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component AX1C
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component NAND2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component DFN1P0
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          PRE : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component DFN1
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component NOR3A
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component XA1C
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

    signal G_66_7, RBINSYNCSHIFT_9_net, WBINNXTSHIFT_9_net, N_1, 
        G_66_6, G_66_3, G_66_5, N_1_21, RBINSYNCSHIFT_8_net, 
        WBINNXTSHIFT_8_net, N_1_23, N_1_11_i, G_66_1, N_1_4, 
        N_1_6_i, N_1_10, N_1_15, G_50_1, G_40_0, AO1_7_Y_0, 
        G_50_0, XOR2_55_Y, AND2_63_Y, AND2_14_Y, G_36_0_2, 
        XNOR3_0_Y, G_36_0_0, N_1_6_i_0_4, RGRYSYNC_3_net, 
        RGRYSYNC_4_net, G_55_0, XOR2_66_Y, AND2_59_Y, AND2_11_Y, 
        G_49_2, XOR2_0_Y, G_49_1, XOR2_70_Y, G_54_0, G_61_0, 
        XOR2_74_Y, AND2_10_Y, AND2_6_Y, G_25_0_2, XNOR3_14_Y, 
        RGRYSYNC_7_net, G_25_0_0, RGRYSYNC_5_net, RGRYSYNC_6_net, 
        G_32_0_1, XNOR3_29_Y, RGRYSYNC_0_net, XNOR3_15_Y, G_60_0, 
        XOR2_16_Y, G_28_1, MEM_WADDR_0_net, WEP, NAND2_0_Y, 
        G_22_0, AO1_36_Y_0, AO1_44_Y_0, FULLINT, XOR2_45_Y_0, 
        AO1_1_Y_0, AO1_30_Y_0, XOR2_29_Y, WBINNXTSHIFT_6_net, 
        WBINNXTSHIFT_5_net, XOR2_41_Y, WBINNXTSHIFT_7_net, 
        XOR2_61_Y, WBINNXTSHIFT_4_net, WBINNXTSHIFT_3_net, 
        XOR2_53_Y, XOR2_50_Y, XOR2_52_Y, XOR2_15_Y, 
        WBINNXTSHIFT_10_net, XOR2_17_Y, WBINNXTSHIFT_2_net, 
        WBINNXTSHIFT_1_net, XOR2_26_Y, XOR2_67_Y, AO1_18_Y_0, 
        XOR2_69_Y, AO1_9_Y_0, XOR2_83_Y, AO1_13_Y_0, XOR2_11_Y, 
        AO1_19_Y_0, XOR2_43_Y, XOR2_77_Y, XOR2_25_Y, XOR2_1_Y, 
        AO1_33_Y_0, WBINNXTSHIFT_0_net, XOR2_56_Y, 
        RBINSYNCSHIFT_6_net, RBINSYNCSHIFT_5_net, 
        RBINSYNCSHIFT_2_net, RBINSYNCSHIFT_4_net, 
        RBINSYNCSHIFT_10_net, RBINSYNCSHIFT_7_net, XOR2_19_Y, 
        AND2_69_Y, AND2_70_Y, AO1_23_Y, XOR2_31_Y, AND2_54_Y, 
        N_1_10_0_2, RGRYSYNC_9_net, RGRYSYNC_8_net, 
        RGRYSYNC_10_net, RGRYSYNC_1_net, MEMORYWE, WCLOCKP_0, 
        WCLOCKP, WGRYSYNC_5_net, DFN1C0_18_Q, AND2_28_Y, 
        MEM_RADDR_8_net, XOR2_71_Y, XNOR3_6_Y, XNOR3_2_Y, 
        XNOR2_8_Y, RBINNXTSHIFT_1_net, WBINSYNCSHIFT_1_net, 
        MEM_WADDR_3_net, BUFF_1_Y, MEM_RADDR_9_net, 
        RBINNXTSHIFT_9_net, AO1_21_Y, AND2_23_Y, AO1_20_Y, 
        AO1_39_Y, RBINNXTSHIFT_2_net, XOR2_39_Y, DFN1C0_19_Q, 
        WBINSYNCSHIFT_6_net, WGRYSYNC_7_net, WGRYSYNC_6_net, 
        XNOR3_24_Y, NAND2_1_Y, MEM_WADDR_4_net, MEM_WADDR_6_net, 
        XNOR3_17_Y, WGRYSYNC_1_net, XOR3_1_Y, XNOR3_19_Y, 
        WGRY_4_net, AND2_21_Y, XOR2_14_Y, XOR2_73_Y, RGRY_0_net, 
        XOR2_12_Y, XNOR3_28_Y, MEM_RADDR_10_net, 
        RBINNXTSHIFT_10_net, WBINSYNCSHIFT_4_net, WGRYSYNC_4_net, 
        XOR3_4_Y, XNOR3_8_Y, MEM_RADDR_0_net, RBINNXTSHIFT_0_net, 
        MEM_WADDR_5_net, XOR2_28_Y, DFN1C0_13_Q, RGRY_3_net, 
        XOR2_80_Y, AND2_74_Y, MEM_WADDR_1_net, XNOR3_16_Y, 
        RAM4K9_1_DOUTA0, RAM4K9_1_DOUTA1, RAM4K9_1_DOUTA2, 
        RAM4K9_1_DOUTA3, RAM4K9_1_DOUTA4, RAM4K9_1_DOUTA5, 
        RAM4K9_1_DOUTA6, RAM4K9_1_DOUTA7, RAM4K9_1_DOUTA8, 
        RAM4K9_1_DOUTB0, RAM4K9_1_DOUTB1, RAM4K9_1_DOUTB2, 
        RAM4K9_1_DOUTB3, RAM4K9_1_DOUTB4, RAM4K9_1_DOUTB5, 
        RAM4K9_1_DOUTB6, RAM4K9_1_DOUTB7, RAM4K9_1_DOUTB8, 
        MEM_WADDR_2_net, MEM_WADDR_7_net, MEM_WADDR_8_net, 
        MEM_RADDR_1_net, MEM_RADDR_2_net, MEM_RADDR_3_net, 
        MEM_RADDR_4_net, MEM_RADDR_5_net, MEM_RADDR_6_net, 
        MEM_RADDR_7_net, OR2_3_Y, OR2_4_Y, WGRYSYNC_10_net, 
        WGRYSYNC_9_net, WGRYSYNC_8_net, QXI_4_net, 
        RAM4K9_0_DOUTB4, DFN1_0_Q, XNOR3_21_Y, XOR2_3_Y, XOR3_2_Y, 
        XOR2_49_Y, XNOR2_16_Y, RBINNXTSHIFT_3_net, 
        WBINSYNCSHIFT_3_net, WGRY_8_net, QXI_2_net, DVLDI, 
        AND2_42_Y, DFN1C0_14_Q, XNOR3_12_Y, WGRYSYNC_3_net, 
        WGRYSYNC_2_net, AND2_40_Y, XOR2_2_Y, AND2_17_Y, AND2_55_Y, 
        AND2_4_Y, DFN1C0_7_Q, RGRY_10_net, XOR2_75_Y, DFN1C0_1_Q, 
        RGRY_9_net, DFN1C0_21_Q, DFN1C0_5_Q, RGRY_2_net, 
        XNOR2_12_Y, RBINNXTSHIFT_5_net, WBINSYNCSHIFT_5_net, 
        DFN1C0_20_Q, RGRY_8_net, XNOR2_23_Y, RBINNXTSHIFT_7_net, 
        WBINSYNCSHIFT_7_net, XOR2_81_Y, XNOR3_23_Y, XNOR3_30_Y, 
        XOR2_6_Y, XNOR3_25_Y, MEM_WADDR_10_net, XOR2_76_Y, 
        AO1_22_Y, XOR2_78_Y, RBINNXTSHIFT_6_net, XOR3_6_Y, 
        XNOR3_27_Y, RGRYSYNC_2_net, DFN1C0_4_Q, QXI_3_net, 
        \FIFO_EMPTY_BIT_c\, EMPTYINT, WGRY_1_net, RAM4K9_0_DOUTB2, 
        AO1_25_Y, AO1_10_Y, AND2_65_Y, AO1_12_Y, AO1_45_Y, 
        XOR2_44_Y, INV_4_Y, MEMWENEG, XOR2_46_Y, AND2_60_Y, 
        AO1_6_Y, XOR3_5_Y, AND3_9_Y, AND3_10_Y, AND3_8_Y, 
        AND3_6_Y, WBINSYNCSHIFT_0_net, XNOR3_31_Y, XNOR3_11_Y, 
        XNOR3_20_Y, RGRY_7_net, XOR2_18_Y, WGRY_10_net, XOR2_37_Y, 
        XNOR3_10_Y, RGRY_5_net, DFN1C0_8_Q, XOR3_0_Y, DFN1C0_0_Q, 
        AND2_1_Y, AND2_38_Y, DFN1C0_17_Q, AO1_0_Y, AND2_20_Y, 
        WGRY_2_net, XOR2_4_Y, XNOR2_27_Y, RBINNXTSHIFT_4_net, 
        OR2_1_Y, BUFF_0_Y, AND2A_1_Y, RGRY_6_net, XOR2_63_Y, 
        DFN1C0_2_Q, WBINSYNCSHIFT_9_net, FIFO_FULL, XOR2_58_Y, 
        QXI_5_net, XOR2_24_Y, AND2_15_Y, XOR2_8_Y, AO1_41_Y, 
        QXI_7_net, RAM4K9_0_DOUTB7, DFN1C0_6_Q, MEM_WADDR_9_net, 
        XOR2_59_Y, XNOR2_15_Y, WBINSYNCSHIFT_2_net, WGRY_7_net, 
        XOR2_7_Y, MEMORYRE, RGRY_4_net, XOR2_72_Y, AND2_58_Y, 
        WGRY_5_net, XOR2_62_Y, RBINNXTSHIFT_8_net, WGRY_9_net, 
        XNOR3_18_Y, DFN1C0_3_Q, AO1_43_Y, WGRYSYNC_0_net, 
        DFN1C0_10_Q, DFN1C0_9_Q, WGRY_0_net, XOR2_22_Y, QXI_0_net, 
        XNOR3_9_Y, RAM4K9_0_DOUTB3, QXI_1_net, RAM4K9_0_DOUTB1, 
        AND2_19_Y, XNOR2_11_Y, DFN1C0_16_Q, XOR2_33_Y, XNOR2_13_Y, 
        XOR2_34_Y, MEMRENEG, XOR2_21_Y, QXI_6_net, WGRY_3_net, 
        DFN1C0_11_Q, RGRY_1_net, XNOR3_22_Y, XNOR2_25_Y, 
        READDOMAIN_WMSB, DFN1C0_12_Q, DFN1C0_15_Q, XNOR2_21_Y, 
        XNOR2_19_Y, XNOR3_5_Y, WBINSYNCSHIFT_8_net, XOR2_47_Y, 
        WGRY_6_net, INV_11_Y, AO1_42_Y, RAM4K9_0_DOUTB5, 
        RAM4K9_0_DOUTB0, XNOR3_13_Y, RAM4K9_0_DOUTA0, 
        RAM4K9_0_DOUTA1, RAM4K9_0_DOUTA2, RAM4K9_0_DOUTA3, 
        RAM4K9_0_DOUTA4, RAM4K9_0_DOUTA5, RAM4K9_0_DOUTA6, 
        RAM4K9_0_DOUTA7, RAM4K9_0_DOUTA8, RAM4K9_0_DOUTB6, 
        RAM4K9_0_DOUTB8, OR2_2_Y, XOR2_82_Y, AO1_31_Y, \GND\, 
        \VCC\, GND_net_1, VCC_net_1 : std_logic;

begin 

    FIFO_EMPTY_BIT_c <= \FIFO_EMPTY_BIT_c\;

    XNOR3_14 : XNOR3
      port map(A => RGRYSYNC_4_net, B => RGRYSYNC_3_net, C => 
        RGRYSYNC_2_net, Y => XNOR3_14_Y);
    
    AND2_11_RNI9F3F_0 : AO1
      port map(A => XOR2_66_Y, B => AND2_59_Y, C => AND2_11_Y, Y
         => AO1_7_Y_0);
    
    XNOR3_5 : XNOR3
      port map(A => WGRYSYNC_4_net, B => WGRYSYNC_3_net, C => 
        XNOR3_22_Y, Y => XNOR3_5_Y);
    
    AO1_23_RNILQBE2 : AO1
      port map(A => AO1_30_Y_0, B => AND2_70_Y, C => AO1_23_Y, Y
         => AO1_9_Y_0);
    
    AND3_6 : AND3
      port map(A => XNOR2_16_Y, B => XNOR2_27_Y, C => XNOR2_12_Y, 
        Y => AND3_6_Y);
    
    XNOR2_WBINSYNCSHIFT_3_inst : XNOR2
      port map(A => XNOR3_16_Y, B => XNOR3_5_Y, Y => 
        WBINSYNCSHIFT_3_net);
    
    DFN1C0_RGRY_4_inst : DFN1C0
      port map(D => XOR2_72_Y, CLK => HCLK_c, CLR => RESET_N_c, Q
         => RGRY_4_net);
    
    AND2_20 : AND2
      port map(A => XOR2_8_Y, B => XOR2_24_Y, Y => AND2_20_Y);
    
    XOR2_82 : XOR2
      port map(A => MEM_RADDR_9_net, B => Fifo_1024_GND, Y => 
        XOR2_82_Y);
    
    XNOR2_13 : XNOR2
      port map(A => RBINNXTSHIFT_0_net, B => WBINSYNCSHIFT_0_net, 
        Y => XNOR2_13_Y);
    
    AND2_11 : AND2
      port map(A => MEM_WADDR_5_net, B => Fifo_1024_GND, Y => 
        AND2_11_Y);
    
    XNOR3_25 : XNOR3
      port map(A => WGRYSYNC_4_net, B => WGRYSYNC_3_net, C => 
        WGRYSYNC_2_net, Y => XNOR3_25_Y);
    
    DFN1C0_FULL : DFN1C0
      port map(D => FULLINT, CLK => WCLOCKP_0, CLR => RESET_N_c, 
        Q => FIFO_FULL);
    
    XNOR2_RBINSYNCSHIFT_7_inst : XNOR2
      port map(A => RGRYSYNC_7_net, B => XNOR3_21_Y, Y => 
        RBINSYNCSHIFT_7_net);
    
    DFN1C0_17 : DFN1C0
      port map(D => WGRY_8_net, CLK => HCLK_c, CLR => RESET_N_c, 
        Q => DFN1C0_17_Q);
    
    XOR2_19 : XOR2
      port map(A => MEM_WADDR_8_net, B => Fifo_1024_GND, Y => 
        XOR2_19_Y);
    
    XOR2_1 : XOR2
      port map(A => MEM_WADDR_9_net, B => Fifo_1024_GND, Y => 
        XOR2_1_Y);
    
    AO1_31 : AO1
      port map(A => XOR2_14_Y, B => AO1_42_Y, C => AND2_28_Y, Y
         => AO1_31_Y);
    
    XNOR3_13 : XNOR3
      port map(A => WGRYSYNC_10_net, B => WGRYSYNC_9_net, C => 
        WGRYSYNC_8_net, Y => XNOR3_13_Y);
    
    DFN1C0_WGRYSYNC_4_inst : DFN1C0
      port map(D => DFN1C0_4_Q, CLK => HCLK_c, CLR => RESET_N_c, 
        Q => WGRYSYNC_4_net);
    
    DFN1C0_FULL_RNO_0 : NOR3B
      port map(A => G_66_3, B => G_66_5, C => N_1_21, Y => G_66_6);
    
    OR2_2 : OR2
      port map(A => BUFF_1_Y, B => MEMRENEG, Y => OR2_2_Y);
    
    XOR2_47 : XOR2
      port map(A => RBINNXTSHIFT_2_net, B => RBINNXTSHIFT_3_net, 
        Y => XOR2_47_Y);
    
    BUFF_READDOMAIN_WMSB : BUFF
      port map(A => WGRYSYNC_10_net, Y => READDOMAIN_WMSB);
    
    XNOR3_RBINSYNCSHIFT_2_inst : XNOR3
      port map(A => XNOR3_23_Y, B => XNOR3_2_Y, C => XNOR3_30_Y, 
        Y => RBINSYNCSHIFT_2_net);
    
    DFN1C0_9 : DFN1C0
      port map(D => WGRY_2_net, CLK => HCLK_c, CLR => RESET_N_c, 
        Q => DFN1C0_9_Q);
    
    AND2_15 : AND2
      port map(A => MEM_RADDR_5_net, B => Fifo_1024_GND, Y => 
        AND2_15_Y);
    
    AO1_25 : AO1
      port map(A => AND2_21_Y, B => AO1_42_Y, C => AO1_41_Y, Y
         => AO1_25_Y);
    
    DFN1C0_WGRY_8_inst : DFN1C0
      port map(D => XOR2_52_Y, CLK => WCLOCKP, CLR => RESET_N_c, 
        Q => WGRY_8_net);
    
    XOR2_70_RNI1491 : NOR2B
      port map(A => XOR2_66_Y, B => XOR2_70_Y, Y => G_49_1);
    
    DFN1C0_MEM_WADDR_2_inst : DFN1C0
      port map(D => WBINNXTSHIFT_2_net, CLK => WCLOCKP_0, CLR => 
        RESET_N_c, Q => MEM_WADDR_2_net);
    
    DFN1C0_11 : DFN1C0
      port map(D => RGRY_5_net, CLK => WCLOCKP_0, CLR => 
        RESET_N_c, Q => DFN1C0_11_Q);
    
    DFN1C0_0 : DFN1C0
      port map(D => RGRY_1_net, CLK => WCLOCKP_0, CLR => 
        RESET_N_c, Q => DFN1C0_0_Q);
    
    NAND2_0_RNISBRF : NOR3C
      port map(A => MEM_WADDR_0_net, B => WEP, C => NAND2_0_Y, Y
         => G_28_1);
    
    AND2_1 : AND2
      port map(A => MEM_RADDR_6_net, B => Fifo_1024_GND, Y => 
        AND2_1_Y);
    
    XNOR2_21 : XNOR2
      port map(A => RBINNXTSHIFT_6_net, B => WBINSYNCSHIFT_6_net, 
        Y => XNOR2_21_Y);
    
    RAM4K9_0 : RAM4K9
      port map(ADDRA11 => Fifo_1024_GND, ADDRA10 => Fifo_1024_GND, 
        ADDRA9 => Fifo_1024_GND, ADDRA8 => MEM_WADDR_8_net, 
        ADDRA7 => MEM_WADDR_7_net, ADDRA6 => MEM_WADDR_6_net, 
        ADDRA5 => MEM_WADDR_5_net, ADDRA4 => MEM_WADDR_4_net, 
        ADDRA3 => MEM_WADDR_3_net, ADDRA2 => MEM_WADDR_2_net, 
        ADDRA1 => MEM_WADDR_1_net, ADDRA0 => MEM_WADDR_0_net, 
        ADDRB11 => Fifo_1024_GND, ADDRB10 => Fifo_1024_GND, 
        ADDRB9 => Fifo_1024_GND, ADDRB8 => MEM_RADDR_8_net, 
        ADDRB7 => MEM_RADDR_7_net, ADDRB6 => MEM_RADDR_6_net, 
        ADDRB5 => MEM_RADDR_5_net, ADDRB4 => MEM_RADDR_4_net, 
        ADDRB3 => MEM_RADDR_3_net, ADDRB2 => MEM_RADDR_2_net, 
        ADDRB1 => MEM_RADDR_1_net, ADDRB0 => MEM_RADDR_0_net, 
        DINA8 => Fifo_1024_GND, DINA7 => USB_DATA_IN(7), DINA6
         => USB_DATA_IN(6), DINA5 => USB_DATA_IN(5), DINA4 => 
        USB_DATA_IN(4), DINA3 => USB_DATA_IN(3), DINA2 => 
        USB_DATA_IN(2), DINA1 => USB_DATA_IN(1), DINA0 => 
        USB_DATA_IN(0), DINB8 => Fifo_1024_GND, DINB7 => 
        Fifo_1024_GND, DINB6 => Fifo_1024_GND, DINB5 => 
        Fifo_1024_GND, DINB4 => Fifo_1024_GND, DINB3 => 
        Fifo_1024_GND, DINB2 => Fifo_1024_GND, DINB1 => 
        Fifo_1024_GND, DINB0 => Fifo_1024_GND, WIDTHA0 => 
        Fifo_1024_VCC, WIDTHA1 => Fifo_1024_VCC, WIDTHB0 => 
        Fifo_1024_VCC, WIDTHB1 => Fifo_1024_VCC, PIPEA => 
        Fifo_1024_GND, PIPEB => Fifo_1024_GND, WMODEA => 
        Fifo_1024_GND, WMODEB => Fifo_1024_GND, BLKA => OR2_1_Y, 
        BLKB => OR2_2_Y, WENA => Fifo_1024_GND, WENB => 
        Fifo_1024_VCC, CLKA => WCLOCKP, CLKB => HCLK_c, RESET => 
        RESET_N_c, DOUTA8 => RAM4K9_0_DOUTA8, DOUTA7 => 
        RAM4K9_0_DOUTA7, DOUTA6 => RAM4K9_0_DOUTA6, DOUTA5 => 
        RAM4K9_0_DOUTA5, DOUTA4 => RAM4K9_0_DOUTA4, DOUTA3 => 
        RAM4K9_0_DOUTA3, DOUTA2 => RAM4K9_0_DOUTA2, DOUTA1 => 
        RAM4K9_0_DOUTA1, DOUTA0 => RAM4K9_0_DOUTA0, DOUTB8 => 
        RAM4K9_0_DOUTB8, DOUTB7 => RAM4K9_0_DOUTB7, DOUTB6 => 
        RAM4K9_0_DOUTB6, DOUTB5 => RAM4K9_0_DOUTB5, DOUTB4 => 
        RAM4K9_0_DOUTB4, DOUTB3 => RAM4K9_0_DOUTB3, DOUTB2 => 
        RAM4K9_0_DOUTB2, DOUTB1 => RAM4K9_0_DOUTB1, DOUTB0 => 
        RAM4K9_0_DOUTB0);
    
    DFN1C0_20 : DFN1C0
      port map(D => WGRY_3_net, CLK => HCLK_c, CLR => RESET_N_c, 
        Q => DFN1C0_20_Q);
    
    AND2_10 : AND2
      port map(A => MEM_WADDR_2_net, B => Fifo_1024_GND, Y => 
        AND2_10_Y);
    
    DFN1E1C0_Q_2_inst : DFN1E1C0
      port map(D => QXI_2_net, CLK => HCLK_c, CLR => RESET_N_c, E
         => DVLDI, Q => USB_DATA_OUT(2));
    
    XOR2_63 : XOR2
      port map(A => RBINNXTSHIFT_6_net, B => RBINNXTSHIFT_7_net, 
        Y => XOR2_63_Y);
    
    MX2_QXI_7_inst : MX2
      port map(A => RAM4K9_0_DOUTB7, B => RAM4K9_1_DOUTB7, S => 
        DFN1_0_Q, Y => QXI_7_net);
    
    AND2_70 : AND2
      port map(A => XOR2_19_Y, B => XOR2_46_Y, Y => AND2_70_Y);
    
    DFN1C0_WGRY_7_inst : DFN1C0
      port map(D => XOR2_50_Y, CLK => WCLOCKP, CLR => RESET_N_c, 
        Q => WGRY_7_net);
    
    AND2A_1 : AND2A
      port map(A => \FIFO_EMPTY_BIT_c\, B => REP, Y => AND2A_1_Y);
    
    XOR2_70_RNIU82I1 : AO1
      port map(A => G_54_0, B => AO1_44_Y_0, C => G_55_0, Y => 
        AO1_36_Y_0);
    
    AO1_42 : AO1
      port map(A => AND2_58_Y, B => AO1_21_Y, C => AO1_10_Y, Y
         => AO1_42_Y);
    
    DFN1C0_RGRYSYNC_6_inst : DFN1C0
      port map(D => DFN1C0_15_Q, CLK => WCLOCKP, CLR => RESET_N_c, 
        Q => RGRYSYNC_6_net);
    
    XNOR2_WBINSYNCSHIFT_1_inst : XNOR2
      port map(A => XNOR3_25_Y, B => XNOR3_17_Y, Y => 
        WBINSYNCSHIFT_1_net);
    
    XOR2_25_RNI1VE72 : XOR2
      port map(A => XOR2_25_Y, B => AO1_30_Y_0, Y => 
        WBINNXTSHIFT_8_net);
    
    AND2_EMPTYINT : AND2
      port map(A => AND2_19_Y, B => XNOR2_25_Y, Y => EMPTYINT);
    
    XOR2_24 : XOR2
      port map(A => MEM_RADDR_5_net, B => Fifo_1024_GND, Y => 
        XOR2_24_Y);
    
    XNOR3_20 : XNOR3
      port map(A => WGRYSYNC_1_net, B => WGRYSYNC_0_net, C => 
        XOR3_5_Y, Y => XNOR3_20_Y);
    
    DFN1C0_MEM_WADDR_10_inst : DFN1C0
      port map(D => WBINNXTSHIFT_10_net, CLK => WCLOCKP_0, CLR
         => RESET_N_c, Q => MEM_WADDR_10_net);
    
    XOR2_21 : XOR2
      port map(A => MEM_RADDR_6_net, B => Fifo_1024_GND, Y => 
        XOR2_21_Y);
    
    DFN1C0_MEM_RADDR_0_inst : DFN1C0
      port map(D => RBINNXTSHIFT_0_net, CLK => HCLK_c, CLR => 
        RESET_N_c, Q => MEM_RADDR_0_net);
    
    XOR2_11_RNIEU701 : XOR2
      port map(A => XOR2_11_Y, B => AO1_19_Y_0, Y => 
        WBINNXTSHIFT_3_net);
    
    DFN1C0_MEM_WADDR_6_inst : DFN1C0
      port map(D => WBINNXTSHIFT_6_net, CLK => WCLOCKP_0, CLR => 
        RESET_N_c, Q => MEM_WADDR_6_net);
    
    XOR2_WBINSYNCSHIFT_9_inst : XOR2
      port map(A => WGRYSYNC_10_net, B => WGRYSYNC_9_net, Y => 
        WBINSYNCSHIFT_9_net);
    
    DFN1C0_RGRY_6_inst : DFN1C0
      port map(D => XOR2_63_Y, CLK => HCLK_c, CLR => RESET_N_c, Q
         => RGRY_6_net);
    
    DFN1C0_FULL_RNO_14 : XOR2
      port map(A => WBINNXTSHIFT_2_net, B => RBINSYNCSHIFT_2_net, 
        Y => N_1_15);
    
    DFN1E1C0_Q_5_inst : DFN1E1C0
      port map(D => QXI_5_net, CLK => HCLK_c, CLR => RESET_N_c, E
         => DVLDI, Q => USB_DATA_OUT(5));
    
    INV_11 : INV
      port map(A => MEM_RADDR_9_net, Y => INV_11_Y);
    
    XNOR3_9 : XNOR3
      port map(A => WGRYSYNC_10_net, B => WGRYSYNC_9_net, C => 
        WGRYSYNC_8_net, Y => XNOR3_9_Y);
    
    XNOR3_8 : XNOR3
      port map(A => WGRYSYNC_7_net, B => WGRYSYNC_6_net, C => 
        WGRYSYNC_5_net, Y => XNOR3_8_Y);
    
    WEBUBBLE_RNIB2V7 : NOR2B
      port map(A => WEP, B => MEM_WADDR_0_net, Y => G_22_0);
    
    DFN1C0_FULL_RNO_17 : XOR3
      port map(A => XNOR3_29_Y, B => RGRYSYNC_0_net, C => 
        XNOR3_15_Y, Y => G_32_0_1);
    
    XOR2_16 : XOR2
      port map(A => MEM_WADDR_2_net, B => Fifo_1024_GND, Y => 
        XOR2_16_Y);
    
    DFN1C0_4 : DFN1C0
      port map(D => WGRY_4_net, CLK => HCLK_c, CLR => RESET_N_c, 
        Q => DFN1C0_4_Q);
    
    OR2_4 : OR2
      port map(A => INV_11_Y, B => MEMRENEG, Y => OR2_4_Y);
    
    DFN1C0_14 : DFN1C0
      port map(D => WGRY_6_net, CLK => HCLK_c, CLR => RESET_N_c, 
        Q => DFN1C0_14_Q);
    
    XOR2_RBINNXTSHIFT_7_inst : XOR2
      port map(A => XOR2_76_Y, B => AO1_22_Y, Y => 
        RBINNXTSHIFT_7_net);
    
    AND2_65 : AND2
      port map(A => XOR2_59_Y, B => XOR2_3_Y, Y => AND2_65_Y);
    
    DFN1C0_WGRY_1_inst : DFN1C0
      port map(D => XOR2_28_Y, CLK => WCLOCKP, CLR => RESET_N_c, 
        Q => WGRY_1_net);
    
    DFN1C0_WGRY_3_inst_RNO : XOR2
      port map(A => WBINNXTSHIFT_4_net, B => WBINNXTSHIFT_3_net, 
        Y => XOR2_61_Y);
    
    MEMWEBUBBLE : INV
      port map(A => MEMORYWE, Y => MEMWENEG);
    
    AND2_6 : AND2
      port map(A => MEM_WADDR_3_net, B => Fifo_1024_GND, Y => 
        AND2_6_Y);
    
    DFN1C0_RGRYSYNC_9_inst : DFN1C0
      port map(D => DFN1C0_1_Q, CLK => WCLOCKP, CLR => RESET_N_c, 
        Q => RGRYSYNC_9_net);
    
    AND2_60 : AND2
      port map(A => MEM_WADDR_9_net, B => Fifo_1024_GND, Y => 
        AND2_60_Y);
    
    XNOR2_WBINSYNCSHIFT_7_inst : XNOR2
      port map(A => WGRYSYNC_7_net, B => XNOR3_9_Y, Y => 
        WBINSYNCSHIFT_7_net);
    
    NAND2_0_RNISBRF_0 : AX1C
      port map(A => NAND2_0_Y, B => WEP, C => MEM_WADDR_0_net, Y
         => WBINNXTSHIFT_0_net);
    
    DFN1C0_WGRYSYNC_1_inst : DFN1C0
      port map(D => DFN1C0_8_Q, CLK => HCLK_c, CLR => RESET_N_c, 
        Q => WGRYSYNC_1_net);
    
    DFN1E1C0_Q_0_inst : DFN1E1C0
      port map(D => QXI_0_net, CLK => HCLK_c, CLR => RESET_N_c, E
         => DVLDI, Q => USB_DATA_OUT(0));
    
    XOR2_33 : XOR2
      port map(A => WBINNXTSHIFT_0_net, B => WBINNXTSHIFT_1_net, 
        Y => XOR2_33_Y);
    
    XOR2_49 : XOR2
      port map(A => RBINNXTSHIFT_3_net, B => RBINNXTSHIFT_4_net, 
        Y => XOR2_49_Y);
    
    XNOR2_19 : XNOR2
      port map(A => RBINNXTSHIFT_8_net, B => WBINSYNCSHIFT_8_net, 
        Y => XNOR2_19_Y);
    
    XOR2_67_RNI524S1 : XOR2
      port map(A => XOR2_67_Y, B => AO1_18_Y_0, Y => 
        WBINNXTSHIFT_7_net);
    
    MX2_QXI_2_inst : MX2
      port map(A => RAM4K9_0_DOUTB2, B => RAM4K9_1_DOUTB2, S => 
        DFN1_0_Q, Y => QXI_2_net);
    
    XOR2_4 : XOR2
      port map(A => MEM_RADDR_1_net, B => Fifo_1024_GND, Y => 
        XOR2_4_Y);
    
    DFN1C0_WGRY_2_inst_RNO : XOR2
      port map(A => WBINNXTSHIFT_3_net, B => WBINNXTSHIFT_2_net, 
        Y => XOR2_17_Y);
    
    XOR2_55 : XOR2
      port map(A => MEM_WADDR_7_net, B => Fifo_1024_GND, Y => 
        XOR2_55_Y);
    
    DFN1C0_FULL_RNO_9 : XOR2
      port map(A => WBINNXTSHIFT_4_net, B => RBINSYNCSHIFT_4_net, 
        Y => N_1_4);
    
    AND3_10 : AND3
      port map(A => XNOR2_21_Y, B => XNOR2_23_Y, C => XNOR2_19_Y, 
        Y => AND3_10_Y);
    
    XOR2_72 : XOR2
      port map(A => RBINNXTSHIFT_4_net, B => RBINNXTSHIFT_5_net, 
        Y => XOR2_72_Y);
    
    XNOR3_RBINSYNCSHIFT_6_inst : XNOR3
      port map(A => RGRYSYNC_7_net, B => RGRYSYNC_6_net, C => 
        XNOR3_6_Y, Y => RBINSYNCSHIFT_6_net);
    
    GND_i : GND
      port map(Y => \GND\);
    
    DFN1C0_15 : DFN1C0
      port map(D => RGRY_6_net, CLK => WCLOCKP_0, CLR => 
        RESET_N_c, Q => DFN1C0_15_Q);
    
    DFN1C0_12 : DFN1C0
      port map(D => RGRY_7_net, CLK => WCLOCKP_0, CLR => 
        RESET_N_c, Q => DFN1C0_12_Q);
    
    XOR2_18 : XOR2
      port map(A => RBINNXTSHIFT_7_net, B => RBINNXTSHIFT_8_net, 
        Y => XOR2_18_Y);
    
    XNOR3_19 : XNOR3
      port map(A => WGRYSYNC_7_net, B => WGRYSYNC_6_net, C => 
        WGRYSYNC_5_net, Y => XNOR3_19_Y);
    
    XNOR3_WBINSYNCSHIFT_2_inst : XNOR3
      port map(A => XNOR3_13_Y, B => XNOR3_18_Y, C => XNOR3_12_Y, 
        Y => WBINSYNCSHIFT_2_net);
    
    VCC_i_0 : VCC
      port map(Y => VCC_net_1);
    
    DFN1C0_FULL_RNO_5 : XOR2
      port map(A => WBINNXTSHIFT_5_net, B => RBINSYNCSHIFT_5_net, 
        Y => N_1_21);
    
    XOR2_56_RNIDUBO : XOR2
      port map(A => XOR2_56_Y, B => AO1_1_Y_0, Y => 
        WBINNXTSHIFT_2_net);
    
    XNOR2_25 : XNOR2
      port map(A => RBINNXTSHIFT_10_net, B => READDOMAIN_WMSB, Y
         => XNOR2_25_Y);
    
    XNOR3_22 : XNOR3
      port map(A => WGRYSYNC_10_net, B => WGRYSYNC_9_net, C => 
        WGRYSYNC_8_net, Y => XNOR3_22_Y);
    
    XOR2_8 : XOR2
      port map(A => MEM_RADDR_4_net, B => Fifo_1024_GND, Y => 
        XOR2_8_Y);
    
    AO1_43 : AO1
      port map(A => XOR2_7_Y, B => AO1_20_Y, C => AND2_17_Y, Y
         => AO1_43_Y);
    
    XOR2_RBINNXTSHIFT_2_inst : XOR2
      port map(A => XOR2_39_Y, B => AO1_20_Y, Y => 
        RBINNXTSHIFT_2_net);
    
    XOR2_RBINNXTSHIFT_8_inst : XOR2
      port map(A => XOR2_71_Y, B => AO1_42_Y, Y => 
        RBINNXTSHIFT_8_net);
    
    MEMREBUBBLE : INV
      port map(A => MEMORYRE, Y => MEMRENEG);
    
    AND2_38 : AND2
      port map(A => MEM_RADDR_7_net, B => Fifo_1024_GND, Y => 
        AND2_38_Y);
    
    DFN1C0_RGRY_5_inst : DFN1C0
      port map(D => XOR2_78_Y, CLK => HCLK_c, CLR => RESET_N_c, Q
         => RGRY_5_net);
    
    XOR2_RBINNXTSHIFT_0_inst : XOR2
      port map(A => MEM_RADDR_0_net, B => MEMORYRE, Y => 
        RBINNXTSHIFT_0_net);
    
    XOR2_34 : XOR2
      port map(A => RBINNXTSHIFT_9_net, B => RBINNXTSHIFT_10_net, 
        Y => XOR2_34_Y);
    
    XOR2_16_RNI0491 : NOR2B
      port map(A => XOR2_16_Y, B => XOR2_74_Y, Y => G_60_0);
    
    XOR2_31 : XOR2
      port map(A => MEM_WADDR_1_net, B => Fifo_1024_GND, Y => 
        XOR2_31_Y);
    
    DFN1C0_RGRYSYNC_1_inst_RNILGFA : XOR2
      port map(A => RGRYSYNC_1_net, B => N_1_6_i_0_4, Y => 
        N_1_10_0_2);
    
    WEBUBBLE : INV
      port map(A => R_W_N_c, Y => WEP);
    
    DFN1C0_FULL_RNO_7 : XOR2
      port map(A => G_36_0_2, B => WBINNXTSHIFT_3_net, Y => 
        N_1_11_i);
    
    AND2_14 : AND2
      port map(A => MEM_WADDR_7_net, B => Fifo_1024_GND, Y => 
        AND2_14_Y);
    
    XOR2_RBINNXTSHIFT_10_inst : XOR2
      port map(A => XOR2_6_Y, B => AO1_25_Y, Y => 
        RBINNXTSHIFT_10_net);
    
    DFN1C0_RGRYSYNC_5_inst : DFN1C0
      port map(D => DFN1C0_11_Q, CLK => WCLOCKP, CLR => RESET_N_c, 
        Q => RGRYSYNC_5_net);
    
    INV_4 : INV
      port map(A => MEM_WADDR_9_net, Y => INV_4_Y);
    
    DFN1C0_WGRYSYNC_2_inst : DFN1C0
      port map(D => DFN1C0_9_Q, CLK => HCLK_c, CLR => RESET_N_c, 
        Q => WGRYSYNC_2_net);
    
    DFN1C0_WGRYSYNC_0_inst : DFN1C0
      port map(D => DFN1C0_10_Q, CLK => HCLK_c, CLR => RESET_N_c, 
        Q => WGRYSYNC_0_net);
    
    XOR2_77 : XOR2
      port map(A => MEM_WADDR_4_net, B => Fifo_1024_GND, Y => 
        XOR2_77_Y);
    
    AND2_74 : AND2
      port map(A => MEM_RADDR_0_net, B => MEMORYRE, Y => 
        AND2_74_Y);
    
    AND3_8 : AND3
      port map(A => XNOR2_13_Y, B => XNOR2_8_Y, C => XNOR2_15_Y, 
        Y => AND3_8_Y);
    
    DFN1C0_MEM_WADDR_5_inst : DFN1C0
      port map(D => WBINNXTSHIFT_5_net, CLK => WCLOCKP_0, CLR => 
        RESET_N_c, Q => MEM_WADDR_5_net);
    
    XOR3_4 : XOR3
      port map(A => WGRYSYNC_10_net, B => WGRYSYNC_9_net, C => 
        WGRYSYNC_8_net, Y => XOR3_4_Y);
    
    MX2_QXI_3_inst : MX2
      port map(A => RAM4K9_0_DOUTB3, B => RAM4K9_1_DOUTB3, S => 
        DFN1_0_Q, Y => QXI_3_net);
    
    XOR2_46 : XOR2
      port map(A => MEM_WADDR_9_net, B => Fifo_1024_GND, Y => 
        XOR2_46_Y);
    
    XNOR3_WBINSYNCSHIFT_0_inst : XNOR3
      port map(A => XNOR3_31_Y, B => XNOR3_11_Y, C => XNOR3_20_Y, 
        Y => WBINSYNCSHIFT_0_net);
    
    XNOR2_11 : XNOR2
      port map(A => RBINNXTSHIFT_9_net, B => WBINSYNCSHIFT_9_net, 
        Y => XNOR2_11_Y);
    
    XOR2_75 : XOR2
      port map(A => RBINNXTSHIFT_10_net, B => Fifo_1024_GND, Y
         => XOR2_75_Y);
    
    XOR2_70_RNIBMH91 : AO1
      port map(A => XOR2_70_Y, B => AO1_44_Y_0, C => AND2_59_Y, Y
         => AO1_13_Y_0);
    
    XOR2_19_RNIUDME2 : AO1
      port map(A => XOR2_19_Y, B => AO1_30_Y_0, C => AND2_69_Y, Y
         => AO1_33_Y_0);
    
    DFN1C0_RGRY_9_inst : DFN1C0
      port map(D => XOR2_34_Y, CLK => HCLK_c, CLR => RESET_N_c, Q
         => RGRY_9_net);
    
    VCC_i : VCC
      port map(Y => \VCC\);
    
    XOR2_55_RNIHE34 : NOR3C
      port map(A => XOR2_55_Y, B => XOR2_0_Y, C => G_49_1, Y => 
        G_49_2);
    
    DFN1C0_WGRY_6_inst_RNO : XOR2
      port map(A => WBINNXTSHIFT_7_net, B => WBINNXTSHIFT_6_net, 
        Y => XOR2_41_Y);
    
    DFN1C0_RGRY_2_inst : DFN1C0
      port map(D => XOR2_47_Y, CLK => HCLK_c, CLR => RESET_N_c, Q
         => RGRY_2_net);
    
    XOR2_RBINNXTSHIFT_1_inst : XOR2
      port map(A => XOR2_80_Y, B => AND2_74_Y, Y => 
        RBINNXTSHIFT_1_net);
    
    XOR2_59 : XOR2
      port map(A => MEM_RADDR_6_net, B => Fifo_1024_GND, Y => 
        XOR2_59_Y);
    
    XOR2_55_RNIU8111 : AO1
      port map(A => G_40_0, B => AO1_7_Y_0, C => G_50_0, Y => 
        G_50_1);
    
    AND2_23 : AND2
      port map(A => XOR2_7_Y, B => XOR2_2_Y, Y => AND2_23_Y);
    
    DFN1E1C0_Q_1_inst : DFN1E1C0
      port map(D => QXI_1_net, CLK => HCLK_c, CLR => RESET_N_c, E
         => DVLDI, Q => USB_DATA_OUT(1));
    
    DFN1C0_MEM_RADDR_7_inst : DFN1C0
      port map(D => RBINNXTSHIFT_7_net, CLK => HCLK_c, CLR => 
        RESET_N_c, Q => MEM_RADDR_7_net);
    
    DFN1C0_16 : DFN1C0
      port map(D => WGRY_9_net, CLK => HCLK_c, CLR => RESET_N_c, 
        Q => DFN1C0_16_Q);
    
    XNOR3_11 : XNOR3
      port map(A => WGRYSYNC_4_net, B => WGRYSYNC_3_net, C => 
        WGRYSYNC_2_net, Y => XNOR3_11_Y);
    
    DFN1C0_MEM_WADDR_4_inst : DFN1C0
      port map(D => WBINNXTSHIFT_4_net, CLK => WCLOCKP_0, CLR => 
        RESET_N_c, Q => MEM_WADDR_4_net);
    
    XOR3_WBINSYNCSHIFT_8_inst : XOR3
      port map(A => WGRYSYNC_10_net, B => WGRYSYNC_9_net, C => 
        WGRYSYNC_8_net, Y => WBINSYNCSHIFT_8_net);
    
    DFN1C0_WGRY_3_inst : DFN1C0
      port map(D => XOR2_61_Y, CLK => WCLOCKP, CLR => RESET_N_c, 
        Q => WGRY_3_net);
    
    AND2_19 : AND2
      port map(A => AND3_9_Y, B => XNOR2_11_Y, Y => AND2_19_Y);
    
    DFN1C0_MEM_WADDR_8_inst : DFN1C0
      port map(D => WBINNXTSHIFT_8_net, CLK => WCLOCKP_0, CLR => 
        RESET_N_c, Q => MEM_WADDR_8_net);
    
    DFN1C0_6 : DFN1C0
      port map(D => RGRY_10_net, CLK => WCLOCKP_0, CLR => 
        RESET_N_c, Q => DFN1C0_6_Q);
    
    XOR2_22 : XOR2
      port map(A => RBINNXTSHIFT_1_net, B => RBINNXTSHIFT_2_net, 
        Y => XOR2_22_Y);
    
    XNOR3_27 : XNOR3
      port map(A => RGRYSYNC_7_net, B => RGRYSYNC_6_net, C => 
        RGRYSYNC_5_net, Y => XNOR3_27_Y);
    
    DFN1E1C0_Q_4_inst : DFN1E1C0
      port map(D => QXI_4_net, CLK => HCLK_c, CLR => RESET_N_c, E
         => DVLDI, Q => USB_DATA_OUT(4));
    
    DFN1C0_10 : DFN1C0
      port map(D => WGRY_0_net, CLK => HCLK_c, CLR => RESET_N_c, 
        Q => DFN1C0_10_Q);
    
    XOR2_31_RNIBCNN : AO1
      port map(A => G_28_1, B => XOR2_31_Y, C => AND2_54_Y, Y => 
        AO1_1_Y_0);
    
    XNOR3_31 : XNOR3
      port map(A => WGRYSYNC_7_net, B => WGRYSYNC_6_net, C => 
        WGRYSYNC_5_net, Y => XNOR3_31_Y);
    
    XOR2_83_RNID86A1 : XOR2
      port map(A => XOR2_83_Y, B => AO1_13_Y_0, Y => 
        WBINNXTSHIFT_5_net);
    
    XNOR3_WBINSYNCSHIFT_6_inst : XNOR3
      port map(A => WGRYSYNC_7_net, B => WGRYSYNC_6_net, C => 
        XNOR3_24_Y, Y => WBINSYNCSHIFT_6_net);
    
    DFN1C0_WGRY_8_inst_RNO : XOR2
      port map(A => WBINNXTSHIFT_9_net, B => WBINNXTSHIFT_8_net, 
        Y => XOR2_52_Y);
    
    DFN1C0_MEM_RADDR_6_inst : DFN1C0
      port map(D => RBINNXTSHIFT_6_net, CLK => HCLK_c, CLR => 
        RESET_N_c, Q => MEM_RADDR_6_net);
    
    XNOR2_WBINSYNCSHIFT_5_inst : XNOR2
      port map(A => XOR3_0_Y, B => XNOR3_10_Y, Y => 
        WBINSYNCSHIFT_5_net);
    
    DFN1C0_3 : DFN1C0
      port map(D => RGRY_4_net, CLK => WCLOCKP_0, CLR => 
        RESET_N_c, Q => DFN1C0_3_Q);
    
    XNOR3_18 : XNOR3
      port map(A => WGRYSYNC_7_net, B => WGRYSYNC_6_net, C => 
        WGRYSYNC_5_net, Y => XNOR3_18_Y);
    
    DFN1E1C0_Q_7_inst : DFN1E1C0
      port map(D => QXI_7_net, CLK => HCLK_c, CLR => RESET_N_c, E
         => DVLDI, Q => USB_DATA_OUT(7));
    
    XOR3_RBINSYNCSHIFT_8_inst : XOR3
      port map(A => RGRYSYNC_10_net, B => RGRYSYNC_9_net, C => 
        RGRYSYNC_8_net, Y => RBINSYNCSHIFT_8_net);
    
    DFN1C0_FULL_RNO : NOR3C
      port map(A => G_66_6, B => XOR2_45_Y_0, C => G_66_7, Y => 
        FULLINT);
    
    XNOR3_24 : XNOR3
      port map(A => WGRYSYNC_10_net, B => WGRYSYNC_9_net, C => 
        WGRYSYNC_8_net, Y => XNOR3_24_Y);
    
    AND2_63_RNI1GFR1 : AO1
      port map(A => XOR2_0_Y, B => AO1_36_Y_0, C => AND2_63_Y, Y
         => AO1_18_Y_0);
    
    XOR2_62 : XOR2
      port map(A => RBINNXTSHIFT_8_net, B => RBINNXTSHIFT_9_net, 
        Y => XOR2_62_Y);
    
    DFN1C0_18 : DFN1C0
      port map(D => WGRY_5_net, CLK => HCLK_c, CLR => RESET_N_c, 
        Q => DFN1C0_18_Q);
    
    AND2_58 : AND2
      port map(A => AND2_20_Y, B => AND2_65_Y, Y => AND2_58_Y);
    
    AND2_55 : AND2
      port map(A => MEM_RADDR_3_net, B => Fifo_1024_GND, Y => 
        AND2_55_Y);
    
    XNOR3_6 : XNOR3
      port map(A => RGRYSYNC_10_net, B => RGRYSYNC_9_net, C => 
        RGRYSYNC_8_net, Y => XNOR3_6_Y);
    
    DFN1C0_RGRYSYNC_8_inst : DFN1C0
      port map(D => DFN1C0_19_Q, CLK => WCLOCKP, CLR => RESET_N_c, 
        Q => RGRYSYNC_8_net);
    
    XOR2_RBINNXTSHIFT_3_inst : XOR2
      port map(A => XOR2_37_Y, B => AO1_43_Y, Y => 
        RBINNXTSHIFT_3_net);
    
    DFN1C0_2 : DFN1C0
      port map(D => WGRY_10_net, CLK => HCLK_c, CLR => RESET_N_c, 
        Q => DFN1C0_2_Q);
    
    WCLKBUBBLE_RNI2U84 : BUFF
      port map(A => WCLOCKP, Y => WCLOCKP_0);
    
    DFN1C0_WGRY_5_inst_RNO : XOR2
      port map(A => WBINNXTSHIFT_6_net, B => WBINNXTSHIFT_5_net, 
        Y => XOR2_29_Y);
    
    DFN1C0_RGRYSYNC_3_inst : DFN1C0
      port map(D => DFN1C0_13_Q, CLK => WCLOCKP, CLR => RESET_N_c, 
        Q => RGRYSYNC_3_net);
    
    AND2_69 : AND2
      port map(A => MEM_WADDR_8_net, B => Fifo_1024_GND, Y => 
        AND2_69_Y);
    
    DFN1C0_RGRY_8_inst : DFN1C0
      port map(D => XOR2_62_Y, CLK => HCLK_c, CLR => RESET_N_c, Q
         => RGRY_8_net);
    
    AND2_MEMORYRE : AND2
      port map(A => NAND2_1_Y, B => REP, Y => MEMORYRE);
    
    XOR2_7 : XOR2
      port map(A => MEM_RADDR_2_net, B => Fifo_1024_GND, Y => 
        XOR2_7_Y);
    
    XOR2_56 : XOR2
      port map(A => MEM_WADDR_2_net, B => Fifo_1024_GND, Y => 
        XOR2_56_Y);
    
    XOR2_14 : XOR2
      port map(A => MEM_RADDR_8_net, B => Fifo_1024_GND, Y => 
        XOR2_14_Y);
    
    XNOR3_23 : XNOR3
      port map(A => RGRYSYNC_10_net, B => RGRYSYNC_9_net, C => 
        RGRYSYNC_8_net, Y => XNOR3_23_Y);
    
    XOR2_11 : XOR2
      port map(A => MEM_WADDR_3_net, B => Fifo_1024_GND, Y => 
        XOR2_11_Y);
    
    DFN1C0_FULL_RNO_13 : XOR3
      port map(A => WBINNXTSHIFT_0_net, B => G_32_0_1, C => 
        N_1_10_0_2, Y => N_1_10);
    
    DFN1C0_7 : DFN1C0
      port map(D => WGRY_7_net, CLK => HCLK_c, CLR => RESET_N_c, 
        Q => DFN1C0_7_Q);
    
    XOR3_6 : XOR3
      port map(A => RGRYSYNC_10_net, B => RGRYSYNC_9_net, C => 
        RGRYSYNC_8_net, Y => XOR3_6_Y);
    
    XOR2_25 : XOR2
      port map(A => MEM_WADDR_8_net, B => Fifo_1024_GND, Y => 
        XOR2_25_Y);
    
    XNOR2_15 : XNOR2
      port map(A => RBINNXTSHIFT_2_net, B => WBINSYNCSHIFT_2_net, 
        Y => XNOR2_15_Y);
    
    AO1_22 : AO1
      port map(A => XOR2_59_Y, B => AO1_0_Y, C => AND2_1_Y, Y => 
        AO1_22_Y);
    
    DFN1C0_RGRY_7_inst : DFN1C0
      port map(D => XOR2_18_Y, CLK => HCLK_c, CLR => RESET_N_c, Q
         => RGRY_7_net);
    
    DFN1C0_FULL_RNO_12 : XOR3
      port map(A => N_1_10_0_2, B => G_25_0_2, C => 
        WBINNXTSHIFT_1_net, Y => N_1_6_i);
    
    BUFF_0 : BUFF
      port map(A => MEM_WADDR_9_net, Y => BUFF_0_Y);
    
    DFN1C0_RGRYSYNC_7_inst : DFN1C0
      port map(D => DFN1C0_12_Q, CLK => WCLOCKP, CLR => RESET_N_c, 
        Q => RGRYSYNC_7_net);
    
    DFN1C0_WGRYSYNC_6_inst : DFN1C0
      port map(D => DFN1C0_14_Q, CLK => HCLK_c, CLR => RESET_N_c, 
        Q => WGRYSYNC_6_net);
    
    DFN1C0_MEM_RADDR_3_inst : DFN1C0
      port map(D => RBINNXTSHIFT_3_net, CLK => HCLK_c, CLR => 
        RESET_N_c, Q => MEM_RADDR_3_net);
    
    XOR2_43_RNISQMI1 : XOR2
      port map(A => XOR2_43_Y, B => AO1_36_Y_0, Y => 
        WBINNXTSHIFT_6_net);
    
    AO1_6 : AO1
      port map(A => XOR2_8_Y, B => AO1_21_Y, C => AND2_4_Y, Y => 
        AO1_6_Y);
    
    AO1_41 : AO1
      port map(A => XOR2_73_Y, B => AND2_28_Y, C => AND2_40_Y, Y
         => AO1_41_Y);
    
    XOR2_26_RNIRTFG : AX1C
      port map(A => NAND2_0_Y, B => G_22_0, C => XOR2_26_Y, Y => 
        WBINNXTSHIFT_1_net);
    
    XNOR3_15 : XNOR3
      port map(A => RGRYSYNC_7_net, B => RGRYSYNC_6_net, C => 
        RGRYSYNC_5_net, Y => XNOR3_15_Y);
    
    DFN1C0_FULL_RNO_1 : XOR2
      port map(A => WBINNXTSHIFT_10_net, B => 
        RBINSYNCSHIFT_10_net, Y => XOR2_45_Y_0);
    
    MEMWEBUBBLE_RNO : NOR2B
      port map(A => WEP, B => NAND2_0_Y, Y => MEMORYWE);
    
    XOR2_67 : XOR2
      port map(A => MEM_WADDR_7_net, B => Fifo_1024_GND, Y => 
        XOR2_67_Y);
    
    DFN1C0_WGRY_0_inst : DFN1C0
      port map(D => XOR2_33_Y, CLK => WCLOCKP, CLR => RESET_N_c, 
        Q => WGRY_0_net);
    
    DFN1C0_WGRY_10_inst : DFN1C0
      port map(D => XOR2_44_Y, CLK => WCLOCKP, CLR => RESET_N_c, 
        Q => WGRY_10_net);
    
    DFN1C0_FULL_RNO_10 : XOR2
      port map(A => WBINNXTSHIFT_6_net, B => RBINSYNCSHIFT_6_net, 
        Y => N_1_23);
    
    AND2_63 : AND2
      port map(A => MEM_WADDR_6_net, B => Fifo_1024_GND, Y => 
        AND2_63_Y);
    
    AO1_12 : AO1
      port map(A => XOR2_24_Y, B => AND2_4_Y, C => AND2_15_Y, Y
         => AO1_12_Y);
    
    XOR2_77_RNIP7A21 : XOR2
      port map(A => XOR2_77_Y, B => AO1_44_Y_0, Y => 
        WBINNXTSHIFT_4_net);
    
    DFN1C0_WGRY_4_inst : DFN1C0
      port map(D => XOR2_53_Y, CLK => WCLOCKP, CLR => RESET_N_c, 
        Q => WGRY_4_net);
    
    DFN1C0_RGRY_1_inst : DFN1C0
      port map(D => XOR2_22_Y, CLK => HCLK_c, CLR => RESET_N_c, Q
         => RGRY_1_net);
    
    XOR2_58 : XOR2
      port map(A => MEM_RADDR_4_net, B => Fifo_1024_GND, Y => 
        XOR2_58_Y);
    
    XOR2_43 : XOR2
      port map(A => MEM_WADDR_6_net, B => Fifo_1024_GND, Y => 
        XOR2_43_Y);
    
    DFN1C0_MEM_WADDR_1_inst : DFN1C0
      port map(D => WBINNXTSHIFT_1_net, CLK => WCLOCKP_0, CLR => 
        RESET_N_c, Q => MEM_WADDR_1_net);
    
    MX2_QXI_1_inst : MX2
      port map(A => RAM4K9_0_DOUTB1, B => RAM4K9_1_DOUTB1, S => 
        DFN1_0_Q, Y => QXI_1_net);
    
    WCLKBUBBLE : INV
      port map(A => USB_CLK_c, Y => WCLOCKP);
    
    MX2_QXI_6_inst : MX2
      port map(A => RAM4K9_0_DOUTB6, B => RAM4K9_1_DOUTB6, S => 
        DFN1_0_Q, Y => QXI_6_net);
    
    XOR2_RBINNXTSHIFT_9_inst : XOR2
      port map(A => XOR2_82_Y, B => AO1_31_Y, Y => 
        RBINNXTSHIFT_9_net);
    
    NAND2_0 : NAND2
      port map(A => FIFO_FULL, B => Fifo_1024_VCC, Y => NAND2_0_Y);
    
    DFN1C0_MEM_RADDR_10_inst : DFN1C0
      port map(D => RBINNXTSHIFT_10_net, CLK => HCLK_c, CLR => 
        RESET_N_c, Q => MEM_RADDR_10_net);
    
    XNOR3_0 : XNOR3
      port map(A => RGRYSYNC_7_net, B => RGRYSYNC_6_net, C => 
        RGRYSYNC_5_net, Y => XNOR3_0_Y);
    
    DFN1E1C0_Q_3_inst : DFN1E1C0
      port map(D => QXI_3_net, CLK => HCLK_c, CLR => RESET_N_c, E
         => DVLDI, Q => USB_DATA_OUT(3));
    
    DFN1C0_RGRYSYNC_4_inst : DFN1C0
      port map(D => DFN1C0_3_Q, CLK => WCLOCKP, CLR => RESET_N_c, 
        Q => RGRYSYNC_4_net);
    
    DFN1C0_FULL_RNO_3 : NOR3B
      port map(A => N_1_11_i, B => G_66_1, C => N_1_4, Y => 
        G_66_3);
    
    XOR2_RBINNXTSHIFT_4_inst : XOR2
      port map(A => XOR2_58_Y, B => AO1_21_Y, Y => 
        RBINNXTSHIFT_4_net);
    
    XOR2_76 : XOR2
      port map(A => MEM_RADDR_7_net, B => Fifo_1024_GND, Y => 
        XOR2_76_Y);
    
    DFN1C0_WGRYSYNC_9_inst : DFN1C0
      port map(D => DFN1C0_16_Q, CLK => HCLK_c, CLR => RESET_N_c, 
        Q => WGRYSYNC_9_net);
    
    DFN1C0_MEM_RADDR_5_inst : DFN1C0
      port map(D => RBINNXTSHIFT_5_net, CLK => HCLK_c, CLR => 
        RESET_N_c, Q => MEM_RADDR_5_net);
    
    DFN1C0_DVLDI : DFN1C0
      port map(D => AND2A_1_Y, CLK => HCLK_c, CLR => RESET_N_c, Q
         => DVLDI);
    
    XNOR3_RBINSYNCSHIFT_4_inst : XNOR3
      port map(A => RGRYSYNC_4_net, B => XOR3_6_Y, C => 
        XNOR3_27_Y, Y => RBINSYNCSHIFT_4_net);
    
    OR2_1 : OR2
      port map(A => BUFF_0_Y, B => MEMWENEG, Y => OR2_1_Y);
    
    XOR2_83 : XOR2
      port map(A => MEM_WADDR_5_net, B => Fifo_1024_GND, Y => 
        XOR2_83_Y);
    
    XNOR2_27 : XNOR2
      port map(A => RBINNXTSHIFT_4_net, B => WBINSYNCSHIFT_4_net, 
        Y => XNOR2_27_Y);
    
    DFN1C0_RGRY_10_inst : DFN1C0
      port map(D => XOR2_75_Y, CLK => HCLK_c, CLR => RESET_N_c, Q
         => RGRY_10_net);
    
    AO1_20 : AO1
      port map(A => XOR2_4_Y, B => AND2_74_Y, C => AND2_42_Y, Y
         => AO1_20_Y);
    
    DFN1C0_MEM_WADDR_9_inst : DFN1C0
      port map(D => WBINNXTSHIFT_9_net, CLK => WCLOCKP_0, CLR => 
        RESET_N_c, Q => MEM_WADDR_9_net);
    
    GND_i_0 : GND
      port map(Y => GND_net_1);
    
    AO1_0 : AO1
      port map(A => AND2_20_Y, B => AO1_21_Y, C => AO1_12_Y, Y
         => AO1_0_Y);
    
    XOR3_0 : XOR3
      port map(A => WGRYSYNC_10_net, B => WGRYSYNC_9_net, C => 
        WGRYSYNC_8_net, Y => XOR3_0_Y);
    
    AO1_45 : AO1
      port map(A => XOR2_3_Y, B => AND2_1_Y, C => AND2_38_Y, Y
         => AO1_45_Y);
    
    XOR2_2 : XOR2
      port map(A => MEM_RADDR_3_net, B => Fifo_1024_GND, Y => 
        XOR2_2_Y);
    
    DFN1C0_MEM_WADDR_0_inst : DFN1C0
      port map(D => WBINNXTSHIFT_0_net, CLK => WCLOCKP_0, CLR => 
        RESET_N_c, Q => MEM_WADDR_0_net);
    
    DFN1C0_8 : DFN1C0
      port map(D => WGRY_1_net, CLK => HCLK_c, CLR => RESET_N_c, 
        Q => DFN1C0_8_Q);
    
    XNOR3_10 : XNOR3
      port map(A => WGRYSYNC_7_net, B => WGRYSYNC_6_net, C => 
        WGRYSYNC_5_net, Y => XNOR3_10_Y);
    
    XOR2_37 : XOR2
      port map(A => MEM_RADDR_3_net, B => Fifo_1024_GND, Y => 
        XOR2_37_Y);
    
    XNOR2_RBINSYNCSHIFT_5_inst : XNOR2
      port map(A => XOR3_2_Y, B => XNOR3_28_Y, Y => 
        RBINSYNCSHIFT_5_net);
    
    DFN1C0_FULL_RNO_18 : XOR2
      port map(A => RGRYSYNC_5_net, B => RGRYSYNC_6_net, Y => 
        G_25_0_0);
    
    XOR3_5 : XOR3
      port map(A => WGRYSYNC_10_net, B => WGRYSYNC_9_net, C => 
        WGRYSYNC_8_net, Y => XOR3_5_Y);
    
    AND3_9 : AND3
      port map(A => AND3_10_Y, B => AND3_8_Y, C => AND3_6_Y, Y
         => AND3_9_Y);
    
    AO1_23 : AO1
      port map(A => XOR2_46_Y, B => AND2_69_Y, C => AND2_60_Y, Y
         => AO1_23_Y);
    
    AND2_11_RNI9F3F : AO1
      port map(A => XOR2_66_Y, B => AND2_59_Y, C => AND2_11_Y, Y
         => G_55_0);
    
    OR2_3 : OR2
      port map(A => INV_4_Y, B => MEMWENEG, Y => OR2_3_Y);
    
    XOR2_44 : XOR2
      port map(A => WBINNXTSHIFT_10_net, B => Fifo_1024_GND, Y
         => XOR2_44_Y);
    
    AO1_10 : AO1
      port map(A => AND2_65_Y, B => AO1_12_Y, C => AO1_45_Y, Y
         => AO1_10_Y);
    
    XNOR3_30 : XNOR3
      port map(A => RGRYSYNC_4_net, B => RGRYSYNC_3_net, C => 
        RGRYSYNC_2_net, Y => XNOR3_30_Y);
    
    MX2_QXI_5_inst : MX2
      port map(A => RAM4K9_0_DOUTB5, B => RAM4K9_1_DOUTB5, S => 
        DFN1_0_Q, Y => QXI_5_net);
    
    XOR2_80 : XOR2
      port map(A => MEM_RADDR_1_net, B => Fifo_1024_GND, Y => 
        XOR2_80_Y);
    
    DFN1P0_EMPTY : DFN1P0
      port map(D => EMPTYINT, CLK => HCLK_c, PRE => RESET_N_c, Q
         => \FIFO_EMPTY_BIT_c\);
    
    XNOR3_29 : XNOR3
      port map(A => RGRYSYNC_4_net, B => RGRYSYNC_3_net, C => 
        RGRYSYNC_2_net, Y => XNOR3_29_Y);
    
    DFN1C0_WGRY_9_inst_RNO : XOR2
      port map(A => WBINNXTSHIFT_10_net, B => WBINNXTSHIFT_9_net, 
        Y => XOR2_15_Y);
    
    XOR2_78 : XOR2
      port map(A => RBINNXTSHIFT_5_net, B => RBINNXTSHIFT_6_net, 
        Y => XOR2_78_Y);
    
    XOR2_69_RNIRC0F2 : XOR2
      port map(A => XOR2_69_Y, B => AO1_9_Y_0, Y => 
        WBINNXTSHIFT_10_net);
    
    XOR2_69 : XOR2
      port map(A => MEM_WADDR_10_net, B => Fifo_1024_GND, Y => 
        XOR2_69_Y);
    
    AND2_17 : AND2
      port map(A => MEM_RADDR_2_net, B => Fifo_1024_GND, Y => 
        AND2_17_Y);
    
    DFN1C0_WGRY_6_inst : DFN1C0
      port map(D => XOR2_41_Y, CLK => WCLOCKP, CLR => RESET_N_c, 
        Q => WGRY_6_net);
    
    XOR2_6 : XOR2
      port map(A => MEM_RADDR_10_net, B => Fifo_1024_GND, Y => 
        XOR2_6_Y);
    
    DFN1C0_RGRYSYNC_10_inst : DFN1C0
      port map(D => DFN1C0_6_Q, CLK => WCLOCKP, CLR => RESET_N_c, 
        Q => RGRYSYNC_10_net);
    
    AND2_54 : AND2
      port map(A => MEM_WADDR_1_net, B => Fifo_1024_GND, Y => 
        AND2_54_Y);
    
    DFN1C0_MEM_WADDR_3_inst : DFN1C0
      port map(D => WBINNXTSHIFT_3_net, CLK => WCLOCKP_0, CLR => 
        RESET_N_c, Q => MEM_WADDR_3_net);
    
    XOR2_81 : XOR2
      port map(A => MEM_RADDR_5_net, B => Fifo_1024_GND, Y => 
        XOR2_81_Y);
    
    XNOR2_23 : XNOR2
      port map(A => RBINNXTSHIFT_7_net, B => WBINSYNCSHIFT_7_net, 
        Y => XNOR2_23_Y);
    
    DFN1C0_WGRYSYNC_5_inst : DFN1C0
      port map(D => DFN1C0_18_Q, CLK => HCLK_c, CLR => RESET_N_c, 
        Q => WGRYSYNC_5_net);
    
    XOR2_55_RNI3DQ62 : AO1
      port map(A => G_49_2, B => AO1_44_Y_0, C => G_50_1, Y => 
        AO1_30_Y_0);
    
    DFN1C0_19 : DFN1C0
      port map(D => RGRY_8_net, CLK => WCLOCKP_0, CLR => 
        RESET_N_c, Q => DFN1C0_19_Q);
    
    DFN1C0_RGRYSYNC_8_inst_RNI7HI7 : XOR3
      port map(A => RGRYSYNC_9_net, B => RGRYSYNC_8_net, C => 
        RGRYSYNC_10_net, Y => N_1_6_i_0_4);
    
    XOR2_55_RNIGAQ2 : NOR2B
      port map(A => XOR2_0_Y, B => XOR2_55_Y, Y => G_40_0);
    
    DFN1_0 : DFN1
      port map(D => MEM_RADDR_9_net, CLK => HCLK_c, Q => DFN1_0_Q);
    
    AND2_6_RNI95L8 : AO1
      port map(A => XOR2_74_Y, B => AND2_10_Y, C => AND2_6_Y, Y
         => G_61_0);
    
    XOR2_12 : XOR2
      port map(A => RBINNXTSHIFT_0_net, B => RBINNXTSHIFT_1_net, 
        Y => XOR2_12_Y);
    
    XNOR2_12 : XNOR2
      port map(A => RBINNXTSHIFT_5_net, B => WBINSYNCSHIFT_5_net, 
        Y => XNOR2_12_Y);
    
    DFN1C0_WGRY_7_inst_RNO : XOR2
      port map(A => WBINNXTSHIFT_8_net, B => WBINNXTSHIFT_7_net, 
        Y => XOR2_50_Y);
    
    DFN1C0_5 : DFN1C0
      port map(D => RGRY_2_net, CLK => WCLOCKP_0, CLR => 
        RESET_N_c, Q => DFN1C0_5_Q);
    
    DFN1C0_21 : DFN1C0
      port map(D => RGRY_0_net, CLK => WCLOCKP_0, CLR => 
        RESET_N_c, Q => DFN1C0_21_Q);
    
    AND2_14_RNI5F3F : AO1
      port map(A => XOR2_55_Y, B => AND2_63_Y, C => AND2_14_Y, Y
         => G_50_0);
    
    DFN1C0_RGRYSYNC_1_inst : DFN1C0
      port map(D => DFN1C0_0_Q, CLK => WCLOCKP, CLR => RESET_N_c, 
        Q => RGRYSYNC_1_net);
    
    XOR2_26 : XOR2
      port map(A => MEM_WADDR_1_net, B => Fifo_1024_GND, Y => 
        XOR2_26_Y);
    
    DFN1C0_1 : DFN1C0
      port map(D => RGRY_9_net, CLK => WCLOCKP_0, CLR => 
        RESET_N_c, Q => DFN1C0_1_Q);
    
    MX2_QXI_4_inst : MX2
      port map(A => RAM4K9_0_DOUTB4, B => RAM4K9_1_DOUTB4, S => 
        DFN1_0_Q, Y => QXI_4_net);
    
    AND2_59 : AND2
      port map(A => MEM_WADDR_4_net, B => Fifo_1024_GND, Y => 
        AND2_59_Y);
    
    DFN1C0_MEM_RADDR_2_inst : DFN1C0
      port map(D => RBINNXTSHIFT_2_net, CLK => HCLK_c, CLR => 
        RESET_N_c, Q => MEM_RADDR_2_net);
    
    DFN1C0_FULL_RNO_16 : XOR3
      port map(A => XNOR3_14_Y, B => RGRYSYNC_7_net, C => 
        G_25_0_0, Y => G_25_0_2);
    
    AND2_4 : AND2
      port map(A => MEM_RADDR_4_net, B => Fifo_1024_GND, Y => 
        AND2_4_Y);
    
    XNOR3_12 : XNOR3
      port map(A => WGRYSYNC_4_net, B => WGRYSYNC_3_net, C => 
        WGRYSYNC_2_net, Y => XNOR3_12_Y);
    
    AO1_39 : AO1
      port map(A => XOR2_2_Y, B => AND2_17_Y, C => AND2_55_Y, Y
         => AO1_39_Y);
    
    AND2_40 : AND2
      port map(A => MEM_RADDR_9_net, B => Fifo_1024_GND, Y => 
        AND2_40_Y);
    
    DFN1C0_RGRY_3_inst : DFN1C0
      port map(D => XOR2_49_Y, CLK => HCLK_c, CLR => RESET_N_c, Q
         => RGRY_3_net);
    
    DFN1C0_MEM_RADDR_1_inst : DFN1C0
      port map(D => RBINNXTSHIFT_1_net, CLK => HCLK_c, CLR => 
        RESET_N_c, Q => MEM_RADDR_1_net);
    
    AND2_42 : AND2
      port map(A => MEM_RADDR_1_net, B => Fifo_1024_GND, Y => 
        AND2_42_Y);
    
    BUFF_RBINSYNCSHIFT_10_inst : BUFF
      port map(A => RGRYSYNC_10_net, Y => RBINSYNCSHIFT_10_net);
    
    XOR2_1_RNIE6SG2 : XOR2
      port map(A => XOR2_1_Y, B => AO1_33_Y_0, Y => 
        WBINNXTSHIFT_9_net);
    
    XNOR2_16 : XNOR2
      port map(A => RBINNXTSHIFT_3_net, B => WBINSYNCSHIFT_3_net, 
        Y => XNOR2_16_Y);
    
    XOR3_2 : XOR3
      port map(A => RGRYSYNC_10_net, B => RGRYSYNC_9_net, C => 
        RGRYSYNC_8_net, Y => XOR3_2_Y);
    
    XOR2_39 : XOR2
      port map(A => MEM_RADDR_2_net, B => Fifo_1024_GND, Y => 
        XOR2_39_Y);
    
    XOR2_RBINSYNCSHIFT_9_inst : XOR2
      port map(A => RGRYSYNC_10_net, B => RGRYSYNC_9_net, Y => 
        RBINSYNCSHIFT_9_net);
    
    XOR2_3 : XOR2
      port map(A => MEM_RADDR_7_net, B => Fifo_1024_GND, Y => 
        XOR2_3_Y);
    
    DFN1C0_FULL_RNO_11 : XOR3
      port map(A => XNOR3_0_Y, B => G_36_0_0, C => N_1_6_i_0_4, Y
         => G_36_0_2);
    
    XOR3_1 : XOR3
      port map(A => WGRYSYNC_10_net, B => WGRYSYNC_9_net, C => 
        WGRYSYNC_8_net, Y => XOR3_1_Y);
    
    XNOR3_21 : XNOR3
      port map(A => RGRYSYNC_10_net, B => RGRYSYNC_9_net, C => 
        RGRYSYNC_8_net, Y => XNOR3_21_Y);
    
    RAM4K9_1 : RAM4K9
      port map(ADDRA11 => Fifo_1024_GND, ADDRA10 => Fifo_1024_GND, 
        ADDRA9 => Fifo_1024_GND, ADDRA8 => MEM_WADDR_8_net, 
        ADDRA7 => MEM_WADDR_7_net, ADDRA6 => MEM_WADDR_6_net, 
        ADDRA5 => MEM_WADDR_5_net, ADDRA4 => MEM_WADDR_4_net, 
        ADDRA3 => MEM_WADDR_3_net, ADDRA2 => MEM_WADDR_2_net, 
        ADDRA1 => MEM_WADDR_1_net, ADDRA0 => MEM_WADDR_0_net, 
        ADDRB11 => Fifo_1024_GND, ADDRB10 => Fifo_1024_GND, 
        ADDRB9 => Fifo_1024_GND, ADDRB8 => MEM_RADDR_8_net, 
        ADDRB7 => MEM_RADDR_7_net, ADDRB6 => MEM_RADDR_6_net, 
        ADDRB5 => MEM_RADDR_5_net, ADDRB4 => MEM_RADDR_4_net, 
        ADDRB3 => MEM_RADDR_3_net, ADDRB2 => MEM_RADDR_2_net, 
        ADDRB1 => MEM_RADDR_1_net, ADDRB0 => MEM_RADDR_0_net, 
        DINA8 => Fifo_1024_GND, DINA7 => USB_DATA_IN(7), DINA6
         => USB_DATA_IN(6), DINA5 => USB_DATA_IN(5), DINA4 => 
        USB_DATA_IN(4), DINA3 => USB_DATA_IN(3), DINA2 => 
        USB_DATA_IN(2), DINA1 => USB_DATA_IN(1), DINA0 => 
        USB_DATA_IN(0), DINB8 => Fifo_1024_GND, DINB7 => 
        Fifo_1024_GND, DINB6 => Fifo_1024_GND, DINB5 => 
        Fifo_1024_GND, DINB4 => Fifo_1024_GND, DINB3 => 
        Fifo_1024_GND, DINB2 => Fifo_1024_GND, DINB1 => 
        Fifo_1024_GND, DINB0 => Fifo_1024_GND, WIDTHA0 => 
        Fifo_1024_VCC, WIDTHA1 => Fifo_1024_VCC, WIDTHB0 => 
        Fifo_1024_VCC, WIDTHB1 => Fifo_1024_VCC, PIPEA => 
        Fifo_1024_GND, PIPEB => Fifo_1024_GND, WMODEA => 
        Fifo_1024_GND, WMODEB => Fifo_1024_GND, BLKA => OR2_3_Y, 
        BLKB => OR2_4_Y, WENA => Fifo_1024_GND, WENB => 
        Fifo_1024_VCC, CLKA => WCLOCKP, CLKB => HCLK_c, RESET => 
        RESET_N_c, DOUTA8 => RAM4K9_1_DOUTA8, DOUTA7 => 
        RAM4K9_1_DOUTA7, DOUTA6 => RAM4K9_1_DOUTA6, DOUTA5 => 
        RAM4K9_1_DOUTA5, DOUTA4 => RAM4K9_1_DOUTA4, DOUTA3 => 
        RAM4K9_1_DOUTA3, DOUTA2 => RAM4K9_1_DOUTA2, DOUTA1 => 
        RAM4K9_1_DOUTA1, DOUTA0 => RAM4K9_1_DOUTA0, DOUTB8 => 
        RAM4K9_1_DOUTB8, DOUTB7 => RAM4K9_1_DOUTB7, DOUTB6 => 
        RAM4K9_1_DOUTB6, DOUTB5 => RAM4K9_1_DOUTB5, DOUTB4 => 
        RAM4K9_1_DOUTB4, DOUTB3 => RAM4K9_1_DOUTB3, DOUTB2 => 
        RAM4K9_1_DOUTB2, DOUTB1 => RAM4K9_1_DOUTB1, DOUTB0 => 
        RAM4K9_1_DOUTB0);
    
    DFN1C0_MEM_RADDR_8_inst : DFN1C0
      port map(D => RBINNXTSHIFT_8_net, CLK => HCLK_c, CLR => 
        RESET_N_c, Q => MEM_RADDR_8_net);
    
    MX2_QXI_0_inst : MX2
      port map(A => RAM4K9_0_DOUTB0, B => RAM4K9_1_DOUTB0, S => 
        DFN1_0_Q, Y => QXI_0_net);
    
    XOR2_66 : XOR2
      port map(A => MEM_WADDR_5_net, B => Fifo_1024_GND, Y => 
        XOR2_66_Y);
    
    XNOR3_16 : XNOR3
      port map(A => WGRYSYNC_7_net, B => WGRYSYNC_6_net, C => 
        WGRYSYNC_5_net, Y => XNOR3_16_Y);
    
    XOR2_RBINNXTSHIFT_6_inst : XOR2
      port map(A => XOR2_21_Y, B => AO1_0_Y, Y => 
        RBINNXTSHIFT_6_net);
    
    XOR2_73 : XOR2
      port map(A => MEM_RADDR_9_net, B => Fifo_1024_GND, Y => 
        XOR2_73_Y);
    
    DFN1C0_13 : DFN1C0
      port map(D => RGRY_3_net, CLK => WCLOCKP_0, CLR => 
        RESET_N_c, Q => DFN1C0_13_Q);
    
    XNOR3_WBINSYNCSHIFT_4_inst : XNOR3
      port map(A => WGRYSYNC_4_net, B => XOR3_4_Y, C => XNOR3_8_Y, 
        Y => WBINSYNCSHIFT_4_net);
    
    XOR2_28 : XOR2
      port map(A => WBINNXTSHIFT_1_net, B => WBINNXTSHIFT_2_net, 
        Y => XOR2_28_Y);
    
    DFN1C0_WGRY_5_inst : DFN1C0
      port map(D => XOR2_29_Y, CLK => WCLOCKP, CLR => RESET_N_c, 
        Q => WGRY_5_net);
    
    DFN1C0_FULL_RNO_8 : NOR3A
      port map(A => N_1_6_i, B => N_1_10, C => N_1_15, Y => 
        G_66_1);
    
    XOR2_RBINNXTSHIFT_5_inst : XOR2
      port map(A => XOR2_81_Y, B => AO1_6_Y, Y => 
        RBINNXTSHIFT_5_net);
    
    XOR2_16_RNILCJV : AO1
      port map(A => XOR2_16_Y, B => AO1_1_Y_0, C => AND2_10_Y, Y
         => AO1_19_Y_0);
    
    XOR2_16_RNIKLL11 : AO1
      port map(A => G_60_0, B => AO1_1_Y_0, C => G_61_0, Y => 
        AO1_44_Y_0);
    
    DFN1C0_RGRYSYNC_2_inst : DFN1C0
      port map(D => DFN1C0_5_Q, CLK => WCLOCKP, CLR => RESET_N_c, 
        Q => RGRYSYNC_2_net);
    
    DFN1C0_RGRYSYNC_0_inst : DFN1C0
      port map(D => DFN1C0_21_Q, CLK => WCLOCKP_0, CLR => 
        RESET_N_c, Q => RGRYSYNC_0_net);
    
    DFN1C0_WGRYSYNC_8_inst : DFN1C0
      port map(D => DFN1C0_17_Q, CLK => HCLK_c, CLR => RESET_N_c, 
        Q => WGRYSYNC_8_net);
    
    DFN1C0_FULL_RNO_15 : XOR2
      port map(A => RGRYSYNC_3_net, B => RGRYSYNC_4_net, Y => 
        G_36_0_0);
    
    XNOR3_28 : XNOR3
      port map(A => RGRYSYNC_7_net, B => RGRYSYNC_6_net, C => 
        RGRYSYNC_5_net, Y => XNOR3_28_Y);
    
    DFN1C0_MEM_WADDR_7_inst : DFN1C0
      port map(D => WBINNXTSHIFT_7_net, CLK => WCLOCKP_0, CLR => 
        RESET_N_c, Q => MEM_WADDR_7_net);
    
    DFN1C0_WGRYSYNC_3_inst : DFN1C0
      port map(D => DFN1C0_20_Q, CLK => HCLK_c, CLR => RESET_N_c, 
        Q => WGRYSYNC_3_net);
    
    AND2_21 : AND2
      port map(A => XOR2_14_Y, B => XOR2_73_Y, Y => AND2_21_Y);
    
    DFN1C0_FULL_RNO_4 : XA1C
      port map(A => RBINSYNCSHIFT_8_net, B => WBINNXTSHIFT_8_net, 
        C => N_1_23, Y => G_66_5);
    
    DFN1E1C0_Q_6_inst : DFN1E1C0
      port map(D => QXI_6_net, CLK => HCLK_c, CLR => RESET_N_c, E
         => DVLDI, Q => USB_DATA_OUT(6));
    
    XOR2_0 : XOR2
      port map(A => MEM_WADDR_6_net, B => Fifo_1024_GND, Y => 
        XOR2_0_Y);
    
    XNOR3_17 : XNOR3
      port map(A => WGRYSYNC_1_net, B => XOR3_1_Y, C => 
        XNOR3_19_Y, Y => XNOR3_17_Y);
    
    XOR2_70 : XOR2
      port map(A => MEM_WADDR_4_net, B => Fifo_1024_GND, Y => 
        XOR2_70_Y);
    
    NAND2_1 : NAND2
      port map(A => \FIFO_EMPTY_BIT_c\, B => Fifo_1024_VCC, Y => 
        NAND2_1_Y);
    
    DFN1C0_MEM_RADDR_4_inst : DFN1C0
      port map(D => RBINNXTSHIFT_4_net, CLK => HCLK_c, CLR => 
        RESET_N_c, Q => MEM_RADDR_4_net);
    
    DFN1C0_FULL_RNO_6 : XOR2
      port map(A => WBINNXTSHIFT_7_net, B => RBINSYNCSHIFT_7_net, 
        Y => N_1);
    
    DFN1C0_WGRY_9_inst : DFN1C0
      port map(D => XOR2_15_Y, CLK => WCLOCKP, CLR => RESET_N_c, 
        Q => WGRY_9_net);
    
    DFN1C0_MEM_RADDR_9_inst : DFN1C0
      port map(D => RBINNXTSHIFT_9_net, CLK => HCLK_c, CLR => 
        RESET_N_c, Q => MEM_RADDR_9_net);
    
    DFN1C0_WGRY_2_inst : DFN1C0
      port map(D => XOR2_17_Y, CLK => WCLOCKP, CLR => RESET_N_c, 
        Q => WGRY_2_net);
    
    DFN1C0_FULL_RNO_2 : XA1C
      port map(A => RBINSYNCSHIFT_9_net, B => WBINNXTSHIFT_9_net, 
        C => N_1, Y => G_66_7);
    
    DFN1C0_WGRY_4_inst_RNO : XOR2
      port map(A => WBINNXTSHIFT_5_net, B => WBINNXTSHIFT_4_net, 
        Y => XOR2_53_Y);
    
    DFN1C0_WGRYSYNC_7_inst : DFN1C0
      port map(D => DFN1C0_7_Q, CLK => HCLK_c, CLR => RESET_N_c, 
        Q => WGRYSYNC_7_net);
    
    DFN1C0_WGRYSYNC_10_inst : DFN1C0
      port map(D => DFN1C0_2_Q, CLK => HCLK_c, CLR => RESET_N_c, 
        Q => WGRYSYNC_10_net);
    
    AO1_21 : AO1
      port map(A => AND2_23_Y, B => AO1_20_Y, C => AO1_39_Y, Y
         => AO1_21_Y);
    
    XOR2_70_RNI1491_0 : NOR2B
      port map(A => XOR2_66_Y, B => XOR2_70_Y, Y => G_54_0);
    
    BUFF_1 : BUFF
      port map(A => MEM_RADDR_9_net, Y => BUFF_1_Y);
    
    XOR2_74 : XOR2
      port map(A => MEM_WADDR_3_net, B => Fifo_1024_GND, Y => 
        XOR2_74_Y);
    
    XNOR3_2 : XNOR3
      port map(A => RGRYSYNC_7_net, B => RGRYSYNC_6_net, C => 
        RGRYSYNC_5_net, Y => XNOR3_2_Y);
    
    XNOR2_8 : XNOR2
      port map(A => RBINNXTSHIFT_1_net, B => WBINSYNCSHIFT_1_net, 
        Y => XNOR2_8_Y);
    
    XOR2_71 : XOR2
      port map(A => MEM_RADDR_8_net, B => Fifo_1024_GND, Y => 
        XOR2_71_Y);
    
    AND2_28 : AND2
      port map(A => MEM_RADDR_8_net, B => Fifo_1024_GND, Y => 
        AND2_28_Y);
    
    DFN1C0_RGRY_0_inst : DFN1C0
      port map(D => XOR2_12_Y, CLK => HCLK_c, CLR => RESET_N_c, Q
         => RGRY_0_net);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library smartfusion;
use smartfusion.all;

entity usb_slave is

    port( USB_CLK        : in    std_logic;
          RESET_N        : in    std_logic;
          R_W_N          : in    std_logic;
          USB_DATA_PAD   : inout std_logic_vector(7 downto 0) := (others => 'Z');
          HCLK           : in    std_logic;
          HTRANS         : out   std_logic_vector(1 downto 0);
          HSIZE          : out   std_logic_vector(1 downto 0);
          HWRITE         : out   std_logic;
          HWDATA         : out   std_logic_vector(31 downto 0);
          HADDR          : out   std_logic_vector(31 downto 0);
          HMASTLOCK      : out   std_logic;
          HREADY         : out   std_logic;
          HSEL           : out   std_logic;
          HREADYOUT      : in    std_logic;
          HRESP          : in    std_logic;
          HRDATA         : in    std_logic_vector(31 downto 0);
          FABINT         : out   std_logic;
          SEND_DATA_BIT  : out   std_logic;
          FIFO_EMPTY_BIT : out   std_logic
        );

end usb_slave;

architecture DEF_ARCH of usb_slave is 

  component DFN1E1C0
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          CLR : in    std_logic := 'U';
          E   : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component XOR2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component OUTBUF
    port( D   : in    std_logic := 'U';
          PAD : out   std_logic
        );
  end component;

  component OA1B
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component NOR2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component DFN1E1
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          E   : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component DFN1E0C0
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          CLR : in    std_logic := 'U';
          E   : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component DFN1C0
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          CLR : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component OR2B
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component NOR3A
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component AX1C
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component DFN1E1P0
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          PRE : in    std_logic := 'U';
          E   : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component AO1B
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component NOR2B
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component DFI1E1P0
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          E   : in    std_logic := 'U';
          PRE : in    std_logic := 'U';
          QN  : out   std_logic
        );
  end component;

  component AO1A
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component MX2B
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          S : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component NOR3C
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component OR3
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component OR2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component OR2A
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component AX1
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component NOR2A
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component XNOR2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component AND2
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component AX1E
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component DFN1P0
    port( D   : in    std_logic := 'U';
          CLK : in    std_logic := 'U';
          PRE : in    std_logic := 'U';
          Q   : out   std_logic
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component AX1A
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component BIBUF_LVCMOS33U
    port( PAD : inout   std_logic;
          D   : in    std_logic := 'U';
          E   : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component OA1C
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component AO1D
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component NOR3B
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component CLKBUF
    port( PAD : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component INBUF
    port( PAD : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component AO1C
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component OR3B
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component OR3C
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component NOR3
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

  component Fifo_1024
    port( USB_DATA_OUT     : out   std_logic_vector(7 downto 0);
          USB_DATA_IN      : in    std_logic_vector(7 downto 0) := (others => 'U');
          R_W_N_c          : in    std_logic := 'U';
          REP              : in    std_logic := 'U';
          USB_CLK_c        : in    std_logic := 'U';
          Fifo_1024_VCC    : in    std_logic := 'U';
          FIFO_EMPTY_BIT_c : out   std_logic;
          Fifo_1024_GND    : in    std_logic := 'U';
          RESET_N_c        : in    std_logic := 'U';
          HCLK_c           : in    std_logic := 'U'
        );
  end component;

  component OR3A
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

    signal \USB_DATA_OUT[1]\, \USB_DATA_IN[1]\, 
        \USB_DATA_OUT[2]\, \USB_DATA_IN[2]\, \USB_DATA_OUT[3]\, 
        \USB_DATA_IN[3]\, \USB_DATA_OUT[4]\, \USB_DATA_IN[4]\, 
        \USB_DATA_OUT[7]\, \USB_DATA_IN[7]\, \USB_DATA_OUT[5]\, 
        \USB_DATA_IN[5]\, \USB_DATA_OUT[6]\, \USB_DATA_IN[6]\, 
        \USB_DATA_OUT[0]\, \USB_DATA_IN[0]\, 
        \ahb_states[0]_net_1\, \ahb_states[1]_net_1\, 
        \data_states[6]_net_1\, \data_states[0]_net_1\, 
        \data_states[3]_net_1\, \data_states[2]_net_1\, 
        \data_states[1]_net_1\, \INTRPT_COUNT[0]_net_1\, 
        \INTRPT_COUNT[1]_net_1\, \INTRPT_COUNT[2]_net_1\, 
        \INTRPT_COUNT[3]_net_1\, \INTRPT_COUNT[4]_net_1\, 
        \INTRPT_COUNT[5]_net_1\, \INTRPT_COUNT[6]_net_1\, 
        \INTRPT_COUNT[7]_net_1\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[1]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[5]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[9]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[11]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[13]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[17]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[21]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[25]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[27]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[29]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[30]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[31]\, 
        \usb_32bit_data[8]_net_1\, \usb_32bit_data[9]_net_1\, 
        \usb_32bit_data[10]_net_1\, \usb_32bit_data[11]_net_1\, 
        \usb_32bit_data[12]_net_1\, \usb_32bit_data[13]_net_1\, 
        \usb_32bit_data[14]_net_1\, \usb_32bit_data[15]_net_1\, 
        \usb_32bit_data[16]_net_1\, \usb_32bit_data[17]_net_1\, 
        \usb_32bit_data[18]_net_1\, \usb_32bit_data[19]_net_1\, 
        \usb_32bit_data[20]_net_1\, \usb_32bit_data[21]_net_1\, 
        \usb_32bit_data[22]_net_1\, \usb_32bit_data[23]_net_1\, 
        \usb_32bit_data[24]_net_1\, \usb_32bit_data[25]_net_1\, 
        \usb_32bit_data[26]_net_1\, \usb_32bit_data[27]_net_1\, 
        \usb_32bit_data[28]_net_1\, \usb_32bit_data[29]_net_1\, 
        \usb_32bit_data[30]_net_1\, \usb_32bit_data[31]_net_1\, 
        \usb_32bit_data[0]_net_1\, \usb_32bit_data[1]_net_1\, 
        \usb_32bit_data[2]_net_1\, \usb_32bit_data[3]_net_1\, 
        \usb_32bit_data[4]_net_1\, \usb_32bit_data[5]_net_1\, 
        \usb_32bit_data[6]_net_1\, \usb_32bit_data[7]_net_1\, 
        \eight_bit_to_32bit_collection.data_count_3[1]\, 
        \data_count[0]_net_1\, \data_count[1]_net_1\, 
        \data_states[5]_net_1\, \data_states[4]_net_1\, 
        \FIFO_INST.REP\, HADDR_TEMPe, HADDR_TEMP_n2, 
        HADDR_TEMP_n3, HADDR_TEMP_n4, HADDR_TEMP_n5, 
        HADDR_TEMP_n6, HADDR_TEMP_n7, HADDR_TEMP_n8, 
        HADDR_TEMP_n9, HADDR_TEMP_n12, HADDR_TEMP_n13, 
        HADDR_TEMP_n14, HADDR_TEMP_n15, HADDR_TEMP_n16, 
        HADDR_TEMP_n17, HADDR_TEMP_n18, HADDR_TEMP_n19, 
        HADDR_TEMP_n20, HADDR_TEMP_n21, HADDR_TEMP_n22, 
        HADDR_TEMP_n23, HADDR_TEMP_n24, HADDR_TEMP_n25, 
        HADDR_TEMP_n26, HADDR_TEMP_n27, HADDR_TEMP_n28, 
        HADDR_TEMP_n29, HADDR_TEMP_n30, HADDR_TEMP_n31, 
        \HADDR_TEMP_RNO[0]_net_1\, \data_states_ns[3]\, 
        \data_states_ns[4]\, \data_states_ns[5]\, 
        \data_states_ns[6]\, \data_states_RNI04S6_0[5]_net_1\, 
        \data_states_ns[1]\, \data_states_ns[0]\, N_4, N_14, N_16, 
        N_18, N_20, N_22, N_24, N_26, N_28, HADDR_TEMP_c1, 
        HADDR_TEMP_c2, HADDR_TEMP_c4, HADDR_TEMP_c5, 
        HADDR_TEMP_c7, HADDR_TEMP_c11, HADDR_TEMP_c15, 
        HADDR_TEMP_c20, HADDR_TEMP_c25, \USB_DATA_OUT_m[1]\, 
        \USB_DATA_OUT_m[5]\, N_359, \USB_DATA_OUT_m_0[1]\, 
        \USB_DATA_OUT_m_0[3]\, \USB_DATA_OUT_m_0[5]\, N_358, 
        \USB_DATA_OUT_m_1[1]\, \USB_DATA_OUT_m_1[5]\, N_357, 
        \USB_DATA_OUT_m_2[1]\, \USB_DATA_OUT_m_2[3]\, 
        \USB_DATA_OUT_m_2[5]\, \USB_DATA_OUT_m_2[6]\, N_362, 
        \USB_DATA_OUT_m_2[7]\, 
        \eight_bit_to_32bit_collection.data_count_3.DWACT_ADD_CI_0_TMP[0]\, 
        \eight_bit_to_32bit_collection.data_count_3.DWACT_ADD_CI_0_partial_sum[0]\, 
        USB_CLK_c, RESET_N_c, R_W_N_c, HCLK_c, HWRITE_c_c, 
        \HWDATA_c[0]\, \HWDATA_c[1]\, \HWDATA_c[2]\, 
        \HWDATA_c[3]\, \HWDATA_c[4]\, \HWDATA_c[5]\, 
        \HWDATA_c[6]\, \HWDATA_c[7]\, \HWDATA_c[8]\, 
        \HWDATA_c[9]\, \HWDATA_c[10]\, \HWDATA_c[11]\, 
        \HWDATA_c[12]\, \HWDATA_c[13]\, \HWDATA_c[14]\, 
        \HWDATA_c[15]\, \HWDATA_c[16]\, \HWDATA_c[17]\, 
        \HWDATA_c[18]\, \HWDATA_c[19]\, \HWDATA_c[20]\, 
        \HWDATA_c[21]\, \HWDATA_c[22]\, \HWDATA_c[23]\, 
        \HWDATA_c[24]\, \HWDATA_c[25]\, \HWDATA_c[26]\, 
        \HWDATA_c[27]\, \HWDATA_c[28]\, \HWDATA_c[29]\, 
        \HWDATA_c[30]\, \HWDATA_c[31]\, \HADDR_TEMP_c[0]\, 
        \HADDR_TEMP_c[1]\, \HADDR_TEMP_c[2]\, \HADDR_TEMP_c[3]\, 
        \HADDR_TEMP_c[4]\, \HADDR_TEMP_c[5]\, \HADDR_TEMP_c[6]\, 
        \HADDR_TEMP_c[7]\, \HADDR_TEMP_c[8]\, \HADDR_TEMP_c[9]\, 
        \HADDR_TEMP_c[10]\, \HADDR_TEMP_c[11]\, 
        \HADDR_TEMP_c[12]\, \HADDR_TEMP_c[13]\, 
        \HADDR_TEMP_c[14]\, \HADDR_TEMP_c[15]\, 
        \HADDR_TEMP_c[16]\, \HADDR_TEMP_c[17]\, 
        \HADDR_TEMP_c[18]\, \HADDR_TEMP_c[19]\, 
        \HADDR_TEMP_c[20]\, \HADDR_TEMP_c[21]\, 
        \HADDR_TEMP_c[22]\, \HADDR_TEMP_c[23]\, 
        \HADDR_TEMP_c[24]\, \HADDR_TEMP_c[25]\, 
        \HADDR_TEMP_c[26]\, \HADDR_TEMP_c[27]\, 
        \HADDR_TEMP_c[28]\, \HADDR_TEMP_c[29]\, 
        \HADDR_TEMP_c[30]\, \HADDR_TEMP_c[31]\, \GND\, \VCC\, 
        HREADYOUT_c, FABINT_c, send_data_c, FIFO_EMPTY_BIT_c, 
        N_366, N_360, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[15]\, 
        \USB_DATA_OUT_m_0[7]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[14]\, 
        \USB_DATA_OUT_m_0[6]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[12]\, 
        \USB_DATA_OUT_m_0[4]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[2]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[6]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[10]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[22]\, 
        \USB_DATA_OUT_m[2]\, \USB_DATA_OUT_m[6]\, 
        \USB_DATA_OUT_m[7]\, \USB_DATA_OUT_m_0[2]\, 
        \USB_DATA_OUT_m_1[6]\, N_370, N_372, N_368, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[23]\, 
        \USB_DATA_OUT_m_1[7]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[20]\, 
        \USB_DATA_OUT_m_1[4]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[19]\, 
        \USB_DATA_OUT_m_1[3]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[18]\, 
        \USB_DATA_OUT_m_1[2]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[16]\, 
        \USB_DATA_OUT_m_1[0]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[8]\, 
        \USB_DATA_OUT_m_0[0]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[7]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[4]\, 
        \USB_DATA_OUT_m[4]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[3]\, 
        \USB_DATA_OUT_m[3]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[0]\, 
        \USB_DATA_OUT_m[0]\, \un1_data_states_2[0]\, 
        \USB_DATA_OUT_m_2[2]\, un1_intrpt_count_1, N_8, N_29, 
        N_30, N_32, N_63, N_64, N_67, N_40, N_43_i, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[28]\, 
        \USB_DATA_OUT_m_2[4]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[26]\, 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[24]\, 
        \USB_DATA_OUT_m_2[0]\, HADDR_TEMP_n1, \ahb_states_6[1]\, 
        HADDR_TEMP_c20_m6_0_a2_4, HADDR_TEMP_c11_m6_0_a2_0, 
        HADDR_TEMP_c11_m6_0_a2_1, HADDR_TEMP_c11_m6_0_a2_3, 
        \INTRPT_COUNT_RNIPB76[2]_net_1\, 
        HADDR_TEMP_c11_m6_0_a2_4_2, HADDR_TEMP_c27_m6_0_a2_5, 
        HADDR_TEMP_c27_m6_0_a2_7, HADDR_TEMP_c17_m6_0_a2_7, 
        HADDR_TEMP_c22_m2_0_a2_1, HADDR_TEMP_c3_s, 
        HADDR_TEMP_c13_s_0, HADDR_TEMP_c17_m6_0_a2_7_1, 
        HADDR_TEMP_c13_s_0_0, HADDR_TEMP_c11_m6_0_a2_3_0, 
        HADDR_TEMP_c23_1, HADDR_TEMP_c18_0, HADDR_TEMP_c15_s_0, 
        HADDR_TEMP_n11_0_N_10_i_i_0, HADDR_TEMP_n10_0_N_10_i_i_0, 
        HADDR_TEMP_c11_m6_0_a2_4_2_0, 
        HADDR_TEMP_c11_m6_0_a2_4_2_1, INTRPT_COUNT_e0_i_a2_0, 
        INTRPT_COUNT_e0_i_a2_1, INTRPT_COUNT_e0_i_a2_2, 
        HADDR_TEMP_c27_m6_0_a2_5_1, HADDR_TEMP_c27_m6_0_a2_5_3, 
        INTRPT_COUNT_n5_0_i_o2_m1_0_a2_0, 
        INTRPT_COUNT_n5_0_i_o2_m1_0_a2_1, INTRPT_COUNT_e0_i_a3_0, 
        HADDR_TEMP_c20_m6_0_a2_4_0, HADDR_TEMP_c20_m6_0_a2_4_3, 
        HADDR_TEMP_c20_m6_0_a2_4_4, HADDR_TEMP_c22_m2_0_a2_1_0, 
        HADDR_TEMP_c17_m6_0_a2_7_2, HADDR_TEMP_c17_m6_0_a2_7_4, 
        HADDR_TEMP_c17_m6_0_a2_7_5, HADDR_TEMP_c4_0, 
        HADDR_TEMP_n10_0_m3_i_o2_2, HADDR_TEMP_n10_0_m3_i_o2_3, 
        HADDR_TEMP_n11_0_m3_i_o2_0, HADDR_TEMP_n11_0_m3_i_o2_1, 
        HADDR_TEMP_n11_0_m3_i_o2_2, HADDR_TEMP_n11_0_m3_i_o2_4, 
        HADDR_TEMP_c29_0_0, HADDR_TEMP_c11_m6_0_a2_0_0, 
        HADDR_TEMP_c23_1_0, HADDR_TEMP_c7_0, 
        HADDR_TEMP_c25_m4_0_a2_0, HADDR_TEMP_c25_m4_0_a2_1, 
        HADDR_TEMP_c25_m4_0_a2_3, HADDR_TEMP_c25_m4_0_a2_5, 
        HADDR_TEMP_c25_m4_0_a2_6, HADDR_TEMP_c28_0, 
        HADDR_TEMP_c30_0, HADDR_TEMP_c27_m6_0_a2_0, 
        HADDR_TEMP_c14_0, HADDR_TEMP_c19_0, HADDR_TEMP_c24_0, 
        HADDR_TEMP_c22_m2_0_a2_0, HADDR_TEMP_c29_0_1, 
        HADDR_TEMP_c15_1, INTRPT_COUNT_n6_0_i_0, 
        INTRPT_COUNT_n5_0_i_0, INTRPT_COUNT_n4_0_i_0, 
        INTRPT_COUNT_n3_0_i_0, INTRPT_COUNT_n2_0_i_0, 
        INTRPT_COUNT_n1_0_i_0, N_4_0, N_361_0, HADDR_TEMPe_0, 
        GND_net_1, VCC_net_1 : std_logic;

    for all : Fifo_1024
	Use entity work.Fifo_1024(DEF_ARCH);
begin 


    \usb_32bit_data[30]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[30]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => 
        \data_states_RNI04S6_0[5]_net_1\, Q => 
        \usb_32bit_data[30]_net_1\);
    
    \HADDR_TEMP_RNO[8]\ : XOR2
      port map(A => \HADDR_TEMP_c[8]\, B => HADDR_TEMP_c7, Y => 
        HADDR_TEMP_n8);
    
    \HADDR_pad[10]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[10]\, PAD => HADDR(10));
    
    FIFO_EMPTY_BIT_pad : OUTBUF
      port map(D => FIFO_EMPTY_BIT_c, PAD => FIFO_EMPTY_BIT);
    
    \HADDR_TEMP[20]\ : DFN1E1C0
      port map(D => HADDR_TEMP_n20, CLK => HCLK_c, CLR => 
        RESET_N_c, E => HADDR_TEMPe_0, Q => \HADDR_TEMP_c[20]\);
    
    \HWDATA_pad[1]\ : OUTBUF
      port map(D => \HWDATA_c[1]\, PAD => HWDATA(1));
    
    \HADDR_pad[25]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[25]\, PAD => HADDR(25));
    
    FABINT_RNO : OA1B
      port map(A => \INTRPT_COUNT[5]_net_1\, B => N_32, C => 
        send_data_c, Y => un1_intrpt_count_1);
    
    \INTRPT_COUNT_RNILE22_0[4]\ : NOR2
      port map(A => \INTRPT_COUNT[3]_net_1\, B => 
        \INTRPT_COUNT[4]_net_1\, Y => INTRPT_COUNT_e0_i_a2_2);
    
    \ahb_states[0]\ : DFN1E1
      port map(D => HADDR_TEMPe, CLK => HCLK_c, E => RESET_N_c, Q
         => \ahb_states[0]_net_1\);
    
    \HADDR_TEMP_RNO[3]\ : XOR2
      port map(A => \HADDR_TEMP_c[3]\, B => HADDR_TEMP_c2, Y => 
        HADDR_TEMP_n3);
    
    \HWDATA_pad[24]\ : OUTBUF
      port map(D => \HWDATA_c[24]\, PAD => HWDATA(24));
    
    \HADDR_pad[7]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[7]\, PAD => HADDR(7));
    
    \HWDATA[5]\ : DFN1E0C0
      port map(D => \usb_32bit_data[5]_net_1\, CLK => HCLK_c, CLR
         => RESET_N_c, E => N_4, Q => \HWDATA_c[5]\);
    
    \data_states[2]\ : DFN1C0
      port map(D => \data_states_ns[4]\, CLK => HCLK_c, CLR => 
        RESET_N_c, Q => \data_states[2]_net_1\);
    
    \HADDR_TEMP_RNI7R47[5]\ : OR2B
      port map(A => \HADDR_TEMP_c[5]\, B => \HADDR_TEMP_c[6]\, Y
         => HADDR_TEMP_c11_m6_0_a2_4_2_1);
    
    \HADDR_TEMP_RNI3HEL[5]\ : OR2B
      port map(A => \HADDR_TEMP_c[5]\, B => HADDR_TEMP_c4, Y => 
        HADDR_TEMP_c5);
    
    \HADDR_pad[11]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[11]\, PAD => HADDR(11));
    
    \ahb_states_RNIE2JA[0]\ : NOR3A
      port map(A => send_data_c, B => \ahb_states[1]_net_1\, C
         => \ahb_states[0]_net_1\, Y => HADDR_TEMPe);
    
    \HADDR_TEMP_RNO[10]\ : AX1C
      port map(A => HADDR_TEMP_c4, B => 
        HADDR_TEMP_n10_0_m3_i_o2_3, C => \HADDR_TEMP_c[10]\, Y
         => HADDR_TEMP_n10_0_N_10_i_i_0);
    
    \HADDR_TEMP[2]\ : DFN1E1P0
      port map(D => HADDR_TEMP_n2, CLK => HCLK_c, PRE => 
        RESET_N_c, E => HADDR_TEMPe, Q => \HADDR_TEMP_c[2]\);
    
    \usb_32bit_data_RNO[19]\ : AO1B
      port map(A => \usb_32bit_data[19]_net_1\, B => N_357, C => 
        \USB_DATA_OUT_m_1[3]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[19]\);
    
    \HADDR_TEMP_RNI7GBI1[23]\ : NOR2B
      port map(A => \HADDR_TEMP_c[23]\, B => 
        HADDR_TEMP_c22_m2_0_a2_1, Y => HADDR_TEMP_c23_1_0);
    
    \HADDR_TEMP_RNI3ARF[22]\ : NOR2B
      port map(A => \HADDR_TEMP_c[22]\, B => \HADDR_TEMP_c[21]\, 
        Y => HADDR_TEMP_c22_m2_0_a2_1_0);
    
    \usb_32bit_data_RNO_0[11]\ : OR2B
      port map(A => \data_states[2]_net_1\, B => 
        \USB_DATA_OUT[3]\, Y => \USB_DATA_OUT_m_0[3]\);
    
    rd_en : DFI1E1P0
      port map(D => FIFO_EMPTY_BIT_c, CLK => HCLK_c, E => 
        \un1_data_states_2[0]\, PRE => RESET_N_c, QN => 
        \FIFO_INST.REP\);
    
    \HADDR_TEMP_RNO_1[11]\ : NOR2B
      port map(A => \HADDR_TEMP_c[9]\, B => \HADDR_TEMP_c[5]\, Y
         => HADDR_TEMP_n11_0_m3_i_o2_1);
    
    \ahb_states_RNO[1]\ : AO1A
      port map(A => HREADYOUT_c, B => \ahb_states[1]_net_1\, C
         => \ahb_states[0]_net_1\, Y => \ahb_states_6[1]\);
    
    \usb_32bit_data[24]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[24]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => 
        \data_states_RNI04S6_0[5]_net_1\, Q => 
        \usb_32bit_data[24]_net_1\);
    
    \usb_32bit_data_RNO_0[5]\ : OR2B
      port map(A => \data_states[3]_net_1\, B => 
        \USB_DATA_OUT[5]\, Y => \USB_DATA_OUT_m[5]\);
    
    rd_en_RNO : MX2B
      port map(A => \data_states_ns[0]\, B => FIFO_EMPTY_BIT_c, S
         => \data_states[6]_net_1\, Y => \un1_data_states_2[0]\);
    
    HWRITE_pad : OUTBUF
      port map(D => HWRITE_c_c, PAD => HWRITE);
    
    \usb_32bit_data_RNO_0[16]\ : OR2B
      port map(A => \data_states[1]_net_1\, B => 
        \USB_DATA_OUT[0]\, Y => \USB_DATA_OUT_m_1[0]\);
    
    \usb_32bit_data_RNO[15]\ : AO1B
      port map(A => \usb_32bit_data[15]_net_1\, B => N_358, C => 
        \USB_DATA_OUT_m_0[7]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[15]\);
    
    \HADDR_TEMP_RNIF7L71[21]\ : NOR3C
      port map(A => HADDR_TEMP_c25_m4_0_a2_0, B => 
        \HADDR_TEMP_c[21]\, C => HADDR_TEMP_c25_m4_0_a2_1, Y => 
        HADDR_TEMP_c25_m4_0_a2_3);
    
    \data_states_RNINVQ6[1]\ : OR3
      port map(A => \data_states[1]_net_1\, B => 
        \data_states[2]_net_1\, C => \data_states[3]_net_1\, Y
         => N_362);
    
    HREADYOUT_pad_RNIKP46_0 : OR2B
      port map(A => \ahb_states[1]_net_1\, B => HREADYOUT_c, Y
         => N_4);
    
    \HADDR_TEMP_RNISPHN1[26]\ : NOR3C
      port map(A => HADDR_TEMP_c25_m4_0_a2_1, B => 
        HADDR_TEMP_c27_m6_0_a2_5_1, C => 
        HADDR_TEMP_c27_m6_0_a2_5_3, Y => HADDR_TEMP_c27_m6_0_a2_5);
    
    \INTRPT_COUNT_RNO_0[0]\ : OR2
      port map(A => \INTRPT_COUNT[1]_net_1\, B => send_data_c, Y
         => INTRPT_COUNT_e0_i_a3_0);
    
    \data_states[1]\ : DFN1C0
      port map(D => \data_states_ns[5]\, CLK => HCLK_c, CLR => 
        RESET_N_c, Q => \data_states[1]_net_1\);
    
    \data_states_RNIKJQ6[1]\ : OR3
      port map(A => \data_states[0]_net_1\, B => 
        \data_states[2]_net_1\, C => \data_states[1]_net_1\, Y
         => N_359);
    
    \usb_32bit_data_RNO_0[30]\ : OR2B
      port map(A => \data_states[0]_net_1\, B => 
        \USB_DATA_OUT[6]\, Y => \USB_DATA_OUT_m_2[6]\);
    
    \usb_32bit_data_RNO[11]\ : AO1B
      port map(A => \usb_32bit_data[11]_net_1\, B => N_358, C => 
        \USB_DATA_OUT_m_0[3]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[11]\);
    
    \INTRPT_COUNT[7]\ : DFN1C0
      port map(D => N_28, CLK => HCLK_c, CLR => RESET_N_c, Q => 
        \INTRPT_COUNT[7]_net_1\);
    
    \usb_32bit_data[8]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[8]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => 
        \data_states_RNI04S6_0[5]_net_1\, Q => 
        \usb_32bit_data[8]_net_1\);
    
    \HWDATA_pad[31]\ : OUTBUF
      port map(D => \HWDATA_c[31]\, PAD => HWDATA(31));
    
    \HADDR_TEMP_RNO[9]\ : AX1C
      port map(A => HADDR_TEMP_c7, B => \HADDR_TEMP_c[8]\, C => 
        \HADDR_TEMP_c[9]\, Y => HADDR_TEMP_n9);
    
    \HADDR_pad[17]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[17]\, PAD => HADDR(17));
    
    \HADDR_TEMP_RNIG3SH[4]\ : NOR2B
      port map(A => HADDR_TEMP_c4_0, B => HADDR_TEMP_c1, Y => 
        HADDR_TEMP_c4);
    
    \HWDATA_pad[13]\ : OUTBUF
      port map(D => \HWDATA_c[13]\, PAD => HWDATA(13));
    
    \INTRPT_COUNT_RNIOL33[2]\ : OR2A
      port map(A => \INTRPT_COUNT[2]_net_1\, B => N_29, Y => N_30);
    
    \usb_32bit_data_RNO_0[21]\ : OR2B
      port map(A => \data_states[1]_net_1\, B => 
        \USB_DATA_OUT[5]\, Y => \USB_DATA_OUT_m_1[5]\);
    
    \usb_32bit_data_RNO_0[2]\ : OR2B
      port map(A => \data_states[3]_net_1\, B => 
        \USB_DATA_OUT[2]\, Y => \USB_DATA_OUT_m[2]\);
    
    \usb_32bit_data_RNO_0[3]\ : OR2B
      port map(A => \data_states[3]_net_1\, B => 
        \USB_DATA_OUT[3]\, Y => \USB_DATA_OUT_m[3]\);
    
    \HWDATA[2]\ : DFN1E0C0
      port map(D => \usb_32bit_data[2]_net_1\, CLK => HCLK_c, CLR
         => RESET_N_c, E => N_4, Q => \HWDATA_c[2]\);
    
    \HADDR_TEMP_RNID1QN[27]\ : NOR3C
      port map(A => \HADDR_TEMP_c[25]\, B => \HADDR_TEMP_c[27]\, 
        C => \HADDR_TEMP_c[21]\, Y => HADDR_TEMP_c27_m6_0_a2_5_3);
    
    \usb_32bit_data[0]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[0]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => N_361_0, Q => 
        \usb_32bit_data[0]_net_1\);
    
    \HADDR_TEMP_RNO[2]\ : XOR2
      port map(A => \HADDR_TEMP_c[2]\, B => HADDR_TEMP_c1, Y => 
        HADDR_TEMP_n2);
    
    \HWDATA_pad[3]\ : OUTBUF
      port map(D => \HWDATA_c[3]\, PAD => HWDATA(3));
    
    \HADDR_TEMP_RNO[20]\ : AX1
      port map(A => HADDR_TEMP_c15_s_0, B => HADDR_TEMP_c19_0, C
         => \HADDR_TEMP_c[20]\, Y => HADDR_TEMP_n20);
    
    \usb_32bit_data[10]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[10]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => N_361_0, Q => 
        \usb_32bit_data[10]_net_1\);
    
    \HADDR_TEMP[13]\ : DFN1E1P0
      port map(D => HADDR_TEMP_n13, CLK => HCLK_c, PRE => 
        RESET_N_c, E => HADDR_TEMPe_0, Q => \HADDR_TEMP_c[13]\);
    
    \usb_32bit_data_RNO_0[26]\ : OR2B
      port map(A => \data_states[0]_net_1\, B => 
        \USB_DATA_OUT[2]\, Y => \USB_DATA_OUT_m_2[2]\);
    
    \HADDR_TEMP[15]\ : DFN1E1C0
      port map(D => HADDR_TEMP_n15, CLK => HCLK_c, CLR => 
        RESET_N_c, E => HADDR_TEMPe_0, Q => \HADDR_TEMP_c[15]\);
    
    \HADDR_TEMP_RNIV1RF[11]\ : OR2B
      port map(A => \HADDR_TEMP_c[11]\, B => \HADDR_TEMP_c[10]\, 
        Y => HADDR_TEMP_c11_m6_0_a2_0);
    
    \HADDR_pad[6]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[6]\, PAD => HADDR(6));
    
    \usb_32bit_data_RNO_0[8]\ : OR2B
      port map(A => \data_states[2]_net_1\, B => 
        \USB_DATA_OUT[0]\, Y => \USB_DATA_OUT_m_0[0]\);
    
    \usb_32bit_data_RNO_0[15]\ : OR2B
      port map(A => \data_states[2]_net_1\, B => 
        \USB_DATA_OUT[7]\, Y => \USB_DATA_OUT_m_0[7]\);
    
    \HADDR_TEMP_RNIB8QP3[23]\ : NOR2A
      port map(A => HADDR_TEMP_c23_1_0, B => 
        HADDR_TEMP_c20_m6_0_a2_4, Y => HADDR_TEMP_c23_1);
    
    \HADDR_TEMP[30]\ : DFN1E1C0
      port map(D => HADDR_TEMP_n30, CLK => HCLK_c, CLR => 
        RESET_N_c, E => HADDR_TEMPe, Q => \HADDR_TEMP_c[30]\);
    
    \HTRANS_pad[0]\ : OUTBUF
      port map(D => \GND\, PAD => HTRANS(0));
    
    \HADDR_pad[16]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[16]\, PAD => HADDR(16));
    
    \HWDATA_pad[9]\ : OUTBUF
      port map(D => \HWDATA_c[9]\, PAD => HWDATA(9));
    
    \HADDR_pad[18]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[18]\, PAD => HADDR(18));
    
    \HWDATA_pad[5]\ : OUTBUF
      port map(D => \HWDATA_c[5]\, PAD => HWDATA(5));
    
    \INTRPT_COUNT_RNO_0[1]\ : XNOR2
      port map(A => \INTRPT_COUNT[0]_net_1\, B => 
        \INTRPT_COUNT[1]_net_1\, Y => INTRPT_COUNT_n1_0_i_0);
    
    \eight_bit_to_32bit_collection.data_count_3_I_1\ : AND2
      port map(A => \data_count[0]_net_1\, B => N_361_0, Y => 
        \eight_bit_to_32bit_collection.data_count_3.DWACT_ADD_CI_0_TMP[0]\);
    
    \usb_32bit_data_RNO_0[18]\ : OR2B
      port map(A => \data_states[1]_net_1\, B => 
        \USB_DATA_OUT[2]\, Y => \USB_DATA_OUT_m_1[2]\);
    
    \ahb_states_RNIE2JA_0[0]\ : NOR3A
      port map(A => send_data_c, B => \ahb_states[1]_net_1\, C
         => \ahb_states[0]_net_1\, Y => HADDR_TEMPe_0);
    
    \HWDATA[3]\ : DFN1E0C0
      port map(D => \usb_32bit_data[3]_net_1\, CLK => HCLK_c, CLR
         => RESET_N_c, E => N_4, Q => \HWDATA_c[3]\);
    
    \HADDR_TEMP_RNI2UAJ2[15]\ : NOR3A
      port map(A => HADDR_TEMP_c15_1, B => 
        HADDR_TEMP_c11_m6_0_a2_3, C => HADDR_TEMP_c15_s_0, Y => 
        HADDR_TEMP_c15);
    
    \usb_32bit_data[29]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[29]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => 
        \data_states_RNI04S6_0[5]_net_1\, Q => 
        \usb_32bit_data[29]_net_1\);
    
    \HADDR_pad[13]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[13]\, PAD => HADDR(13));
    
    \HADDR_TEMP[14]\ : DFN1E1P0
      port map(D => HADDR_TEMP_n14, CLK => HCLK_c, PRE => 
        RESET_N_c, E => HADDR_TEMPe_0, Q => \HADDR_TEMP_c[14]\);
    
    \HADDR_TEMP_RNICCJS[6]\ : NOR2
      port map(A => HADDR_TEMP_c7_0, B => HADDR_TEMP_c5, Y => 
        HADDR_TEMP_c7);
    
    \HADDR_pad[19]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[19]\, PAD => HADDR(19));
    
    \INTRPT_COUNT_RNO_0[7]\ : AX1E
      port map(A => \INTRPT_COUNT[6]_net_1\, B => 
        \INTRPT_COUNT_RNIPB76[2]_net_1\, C => 
        \INTRPT_COUNT[7]_net_1\, Y => N_43_i);
    
    \usb_32bit_data_RNO_0[25]\ : OR2B
      port map(A => \data_states[0]_net_1\, B => 
        \USB_DATA_OUT[1]\, Y => \USB_DATA_OUT_m_2[1]\);
    
    \HWDATA_pad[10]\ : OUTBUF
      port map(D => \HWDATA_c[10]\, PAD => HWDATA(10));
    
    \HWDATA[17]\ : DFN1E0C0
      port map(D => \usb_32bit_data[17]_net_1\, CLK => HCLK_c, 
        CLR => RESET_N_c, E => N_4_0, Q => \HWDATA_c[17]\);
    
    \HADDR_TEMP_RNI66M02[21]\ : NOR3C
      port map(A => HADDR_TEMP_c11_m6_0_a2_4_2, B => 
        HADDR_TEMP_c25_m4_0_a2_3, C => HADDR_TEMP_c2, Y => 
        HADDR_TEMP_c25_m4_0_a2_5);
    
    \HADDR_TEMP_RNI1BIQ[7]\ : OR2B
      port map(A => HADDR_TEMP_c11_m6_0_a2_3_0, B => 
        HADDR_TEMP_c11_m6_0_a2_1, Y => HADDR_TEMP_c11_m6_0_a2_3);
    
    \INTRPT_COUNT_RNO_0[3]\ : XOR2
      port map(A => \INTRPT_COUNT[3]_net_1\, B => N_30, Y => 
        INTRPT_COUNT_n3_0_i_0);
    
    \HADDR_TEMP[5]\ : DFN1E1P0
      port map(D => HADDR_TEMP_n5, CLK => HCLK_c, PRE => 
        RESET_N_c, E => HADDR_TEMPe, Q => \HADDR_TEMP_c[5]\);
    
    send_data_RNO : NOR2
      port map(A => \data_states[6]_net_1\, B => 
        \data_states[0]_net_1\, Y => N_360);
    
    \INTRPT_COUNT_RNO[3]\ : NOR3A
      port map(A => N_67, B => send_data_c, C => 
        INTRPT_COUNT_n3_0_i_0, Y => N_20);
    
    GND_i : GND
      port map(Y => \GND\);
    
    \usb_32bit_data_RNO_0[28]\ : OR2B
      port map(A => \data_states[0]_net_1\, B => 
        \USB_DATA_OUT[4]\, Y => \USB_DATA_OUT_m_2[4]\);
    
    \usb_32bit_data_RNO_0[7]\ : OR2B
      port map(A => \data_states[3]_net_1\, B => 
        \USB_DATA_OUT[7]\, Y => \USB_DATA_OUT_m[7]\);
    
    \HADDR_TEMP_RNI4TDA1[13]\ : NOR2
      port map(A => HADDR_TEMP_c13_s_0_0, B => 
        HADDR_TEMP_c11_m6_0_a2_3, Y => HADDR_TEMP_c13_s_0);
    
    \usb_32bit_data_RNO[0]\ : AO1B
      port map(A => \usb_32bit_data[0]_net_1\, B => N_359, C => 
        \USB_DATA_OUT_m[0]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[0]\);
    
    \HADDR_pad[22]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[22]\, PAD => HADDR(22));
    
    \data_states[6]\ : DFN1P0
      port map(D => \data_states_ns[0]\, CLK => HCLK_c, PRE => 
        RESET_N_c, Q => \data_states[6]_net_1\);
    
    VCC_i_0 : VCC
      port map(Y => VCC_net_1);
    
    \usb_32bit_data_RNO[9]\ : AO1B
      port map(A => \usb_32bit_data[9]_net_1\, B => N_358, C => 
        \USB_DATA_OUT_m_0[1]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[9]\);
    
    \usb_32bit_data[26]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[26]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => 
        \data_states_RNI04S6_0[5]_net_1\, Q => 
        \usb_32bit_data[26]_net_1\);
    
    HREADY_pad : OUTBUF
      port map(D => \VCC\, PAD => HREADY);
    
    \HADDR_TEMP_RNO_0[23]\ : NOR2A
      port map(A => HADDR_TEMP_c22_m2_0_a2_1, B => 
        HADDR_TEMP_c20_m6_0_a2_4, Y => HADDR_TEMP_c22_m2_0_a2_0);
    
    \usb_32bit_data_RNO_0[17]\ : OR2B
      port map(A => \data_states[1]_net_1\, B => 
        \USB_DATA_OUT[1]\, Y => \USB_DATA_OUT_m_1[1]\);
    
    \HWDATA_pad[22]\ : OUTBUF
      port map(D => \HWDATA_c[22]\, PAD => HWDATA(22));
    
    \HADDR_TEMP[9]\ : DFN1E1P0
      port map(D => HADDR_TEMP_n9, CLK => HCLK_c, PRE => 
        RESET_N_c, E => HADDR_TEMPe, Q => \HADDR_TEMP_c[9]\);
    
    FABINT_RNO_1 : OR3
      port map(A => \INTRPT_COUNT[0]_net_1\, B => 
        \INTRPT_COUNT[1]_net_1\, C => N_63, Y => N_64);
    
    \INTRPT_COUNT_RNO_0[4]\ : AX1A
      port map(A => N_30, B => \INTRPT_COUNT[3]_net_1\, C => 
        \INTRPT_COUNT[4]_net_1\, Y => INTRPT_COUNT_n4_0_i_0);
    
    \HADDR_pad[4]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[4]\, PAD => HADDR(4));
    
    \HWDATA_pad[16]\ : OUTBUF
      port map(D => \HWDATA_c[16]\, PAD => HWDATA(16));
    
    \HADDR_TEMP[7]\ : DFN1E1P0
      port map(D => HADDR_TEMP_n7, CLK => HCLK_c, PRE => 
        RESET_N_c, E => HADDR_TEMPe, Q => \HADDR_TEMP_c[7]\);
    
    \HSIZE_pad[0]\ : OUTBUF
      port map(D => \GND\, PAD => HSIZE(0));
    
    \HADDR_TEMP_RNO[13]\ : AX1
      port map(A => HADDR_TEMP_c11, B => \HADDR_TEMP_c[12]\, C
         => \HADDR_TEMP_c[13]\, Y => HADDR_TEMP_n13);
    
    \HADDR_TEMP[3]\ : DFN1E1P0
      port map(D => HADDR_TEMP_n3, CLK => HCLK_c, PRE => 
        RESET_N_c, E => HADDR_TEMPe, Q => \HADDR_TEMP_c[3]\);
    
    \INTRPT_COUNT_RNIFE22[0]\ : OR2B
      port map(A => \INTRPT_COUNT[1]_net_1\, B => 
        \INTRPT_COUNT[0]_net_1\, Y => N_29);
    
    \usb_32bit_data_RNO[22]\ : AO1B
      port map(A => \usb_32bit_data[22]_net_1\, B => N_357, C => 
        \USB_DATA_OUT_m_1[6]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[22]\);
    
    \HADDR_TEMP_RNIL7S61[11]\ : NOR3A
      port map(A => HADDR_TEMP_c11_m6_0_a2_1, B => 
        HADDR_TEMP_c17_m6_0_a2_7_1, C => HADDR_TEMP_c11_m6_0_a2_0, 
        Y => HADDR_TEMP_c17_m6_0_a2_7_5);
    
    \INTRPT_COUNT[4]\ : DFN1C0
      port map(D => N_22, CLK => HCLK_c, CLR => RESET_N_c, Q => 
        \INTRPT_COUNT[4]_net_1\);
    
    \HADDR_TEMP_RNIJ8NA[4]\ : NOR2B
      port map(A => \HADDR_TEMP_c[4]\, B => HADDR_TEMP_c3_s, Y
         => HADDR_TEMP_c4_0);
    
    \HADDR_TEMP_RNI7QRF[25]\ : NOR2B
      port map(A => \HADDR_TEMP_c[25]\, B => \HADDR_TEMP_c[22]\, 
        Y => HADDR_TEMP_c25_m4_0_a2_0);
    
    \HADDR_TEMP_RNO[18]\ : AX1
      port map(A => HADDR_TEMP_c15_s_0, B => 
        HADDR_TEMP_c17_m6_0_a2_7, C => \HADDR_TEMP_c[18]\, Y => 
        HADDR_TEMP_n18);
    
    \HADDR_TEMP_RNINU0P_0[1]\ : NOR2B
      port map(A => HADDR_TEMP_c11_m6_0_a2_4_2, B => 
        HADDR_TEMP_c2, Y => HADDR_TEMP_c11_m6_0_a2_0_0);
    
    \usb_32bit_data[25]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[25]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => 
        \data_states_RNI04S6_0[5]_net_1\, Q => 
        \usb_32bit_data[25]_net_1\);
    
    \GEN.4.DATA_PINS\ : BIBUF_LVCMOS33U
      port map(PAD => USB_DATA_PAD(4), D => \USB_DATA_OUT[4]\, E
         => R_W_N_c, Y => \USB_DATA_IN[4]\);
    
    \HADDR_TEMP[28]\ : DFN1E1C0
      port map(D => HADDR_TEMP_n28, CLK => HCLK_c, CLR => 
        RESET_N_c, E => HADDR_TEMPe, Q => \HADDR_TEMP_c[28]\);
    
    \INTRPT_COUNT_RNO_1[0]\ : OA1C
      port map(A => N_67, B => \INTRPT_COUNT[0]_net_1\, C => 
        send_data_c, Y => N_40);
    
    \INTRPT_COUNT_RNINE22[7]\ : NOR2
      port map(A => \INTRPT_COUNT[7]_net_1\, B => 
        \INTRPT_COUNT[2]_net_1\, Y => INTRPT_COUNT_e0_i_a2_1);
    
    \HADDR_TEMP_RNO[4]\ : AX1C
      port map(A => HADDR_TEMP_c1, B => HADDR_TEMP_c3_s, C => 
        \HADDR_TEMP_c[4]\, Y => HADDR_TEMP_n4);
    
    \eight_bit_to_32bit_collection.data_count_3_I_10\ : XOR2
      port map(A => \data_count[1]_net_1\, B => 
        \eight_bit_to_32bit_collection.data_count_3.DWACT_ADD_CI_0_TMP[0]\, 
        Y => \eight_bit_to_32bit_collection.data_count_3[1]\);
    
    \HWDATA[27]\ : DFN1E0C0
      port map(D => \usb_32bit_data[27]_net_1\, CLK => HCLK_c, 
        CLR => RESET_N_c, E => N_4, Q => \HWDATA_c[27]\);
    
    \INTRPT_COUNT_RNO_0[5]\ : AO1D
      port map(A => N_32, B => \INTRPT_COUNT[5]_net_1\, C => 
        \INTRPT_COUNT_RNIPB76[2]_net_1\, Y => 
        INTRPT_COUNT_n5_0_i_0);
    
    \HWDATA_pad[14]\ : OUTBUF
      port map(D => \HWDATA_c[14]\, PAD => HWDATA(14));
    
    \HWDATA[8]\ : DFN1E0C0
      port map(D => \usb_32bit_data[8]_net_1\, CLK => HCLK_c, CLR
         => RESET_N_c, E => N_4, Q => \HWDATA_c[8]\);
    
    \HSIZE_pad[1]\ : OUTBUF
      port map(D => \VCC\, PAD => HSIZE(1));
    
    \usb_32bit_data_RNO[2]\ : AO1B
      port map(A => \usb_32bit_data[2]_net_1\, B => N_359, C => 
        \USB_DATA_OUT_m[2]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[2]\);
    
    \usb_32bit_data[31]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[31]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => 
        \data_states_RNI04S6_0[5]_net_1\, Q => 
        \usb_32bit_data[31]_net_1\);
    
    \INTRPT_COUNT_RNO[5]\ : NOR3A
      port map(A => N_67, B => send_data_c, C => 
        INTRPT_COUNT_n5_0_i_0, Y => N_24);
    
    \HADDR_TEMP_RNICBL71[14]\ : NOR3B
      port map(A => HADDR_TEMP_c20_m6_0_a2_4_0, B => 
        \HADDR_TEMP_c[14]\, C => HADDR_TEMP_c13_s_0_0, Y => 
        HADDR_TEMP_c20_m6_0_a2_4_4);
    
    RESET_N_pad : CLKBUF
      port map(PAD => RESET_N, Y => RESET_N_c);
    
    HREADYOUT_pad : INBUF
      port map(PAD => HREADYOUT, Y => HREADYOUT_c);
    
    \INTRPT_COUNT_RNILE22[2]\ : NOR2B
      port map(A => \INTRPT_COUNT[5]_net_1\, B => 
        \INTRPT_COUNT[2]_net_1\, Y => 
        INTRPT_COUNT_n5_0_i_o2_m1_0_a2_0);
    
    \usb_32bit_data_RNO_0[27]\ : OR2B
      port map(A => \data_states[0]_net_1\, B => 
        \USB_DATA_OUT[3]\, Y => \USB_DATA_OUT_m_2[3]\);
    
    \HWDATA[18]\ : DFN1E0C0
      port map(D => \usb_32bit_data[18]_net_1\, CLK => HCLK_c, 
        CLR => RESET_N_c, E => N_4_0, Q => \HWDATA_c[18]\);
    
    \GEN.1.DATA_PINS\ : BIBUF_LVCMOS33U
      port map(PAD => USB_DATA_PAD(1), D => \USB_DATA_OUT[1]\, E
         => R_W_N_c, Y => \USB_DATA_IN[1]\);
    
    \HWDATA_pad[29]\ : OUTBUF
      port map(D => \HWDATA_c[29]\, PAD => HWDATA(29));
    
    VCC_i : VCC
      port map(Y => \VCC\);
    
    \HADDR_TEMP_RNI9ASF[15]\ : OR2B
      port map(A => \HADDR_TEMP_c[16]\, B => \HADDR_TEMP_c[15]\, 
        Y => HADDR_TEMP_c17_m6_0_a2_7_1);
    
    \HADDR_TEMP[19]\ : DFN1E1C0
      port map(D => HADDR_TEMP_n19, CLK => HCLK_c, CLR => 
        RESET_N_c, E => HADDR_TEMPe_0, Q => \HADDR_TEMP_c[19]\);
    
    \data_states[0]\ : DFN1C0
      port map(D => \data_states_ns[6]\, CLK => HCLK_c, CLR => 
        RESET_N_c, Q => \data_states[0]_net_1\);
    
    \HWDATA[15]\ : DFN1E0C0
      port map(D => \usb_32bit_data[15]_net_1\, CLK => HCLK_c, 
        CLR => RESET_N_c, E => N_4_0, Q => \HWDATA_c[15]\);
    
    \HADDR_TEMP[21]\ : DFN1E1C0
      port map(D => HADDR_TEMP_n21, CLK => HCLK_c, CLR => 
        RESET_N_c, E => HADDR_TEMPe_0, Q => \HADDR_TEMP_c[21]\);
    
    \HADDR_TEMP_RNO[31]\ : AX1C
      port map(A => HADDR_TEMP_c27_m6_0_a2_7, B => 
        HADDR_TEMP_c30_0, C => \HADDR_TEMP_c[31]\, Y => 
        HADDR_TEMP_n31);
    
    \HADDR_TEMP[27]\ : DFN1E1C0
      port map(D => HADDR_TEMP_n27, CLK => HCLK_c, CLR => 
        RESET_N_c, E => HADDR_TEMPe, Q => \HADDR_TEMP_c[27]\);
    
    \HADDR_pad[1]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[1]\, PAD => HADDR(1));
    
    \HADDR_TEMP[6]\ : DFN1E1P0
      port map(D => HADDR_TEMP_n6, CLK => HCLK_c, PRE => 
        RESET_N_c, E => HADDR_TEMPe, Q => \HADDR_TEMP_c[6]\);
    
    \data_states_RNO[2]\ : AO1C
      port map(A => FIFO_EMPTY_BIT_c, B => \data_states[3]_net_1\, 
        C => N_368, Y => \data_states_ns[4]\);
    
    \HADDR_TEMP_RNO[23]\ : AX1
      port map(A => HADDR_TEMP_c15_s_0, B => 
        HADDR_TEMP_c22_m2_0_a2_0, C => \HADDR_TEMP_c[23]\, Y => 
        HADDR_TEMP_n23);
    
    \HADDR_TEMP_RNO[1]\ : XOR2
      port map(A => \HADDR_TEMP_c[1]\, B => \HADDR_TEMP_c[0]\, Y
         => HADDR_TEMP_n1);
    
    \HWDATA[14]\ : DFN1E0C0
      port map(D => \usb_32bit_data[14]_net_1\, CLK => HCLK_c, 
        CLR => RESET_N_c, E => N_4_0, Q => \HWDATA_c[14]\);
    
    \usb_32bit_data_RNO[23]\ : AO1B
      port map(A => \usb_32bit_data[23]_net_1\, B => N_357, C => 
        \USB_DATA_OUT_m_1[7]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[23]\);
    
    \HADDR_pad[8]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[8]\, PAD => HADDR(8));
    
    \usb_32bit_data[2]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[2]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => 
        \data_states_RNI04S6_0[5]_net_1\, Q => 
        \usb_32bit_data[2]_net_1\);
    
    \HWDATA_pad[30]\ : OUTBUF
      port map(D => \HWDATA_c[30]\, PAD => HWDATA(30));
    
    \HADDR_TEMP_RNI3IRF[13]\ : OR2B
      port map(A => \HADDR_TEMP_c[13]\, B => \HADDR_TEMP_c[12]\, 
        Y => HADDR_TEMP_c13_s_0_0);
    
    HREADYOUT_pad_RNIKP46 : OR2B
      port map(A => \ahb_states[1]_net_1\, B => HREADYOUT_c, Y
         => N_4_0);
    
    \HADDR_TEMP_RNO[28]\ : AX1C
      port map(A => HADDR_TEMP_c27_m6_0_a2_7, B => 
        HADDR_TEMP_c27_m6_0_a2_0, C => \HADDR_TEMP_c[28]\, Y => 
        HADDR_TEMP_n28);
    
    \HADDR_pad[24]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[24]\, PAD => HADDR(24));
    
    \HADDR_TEMP_RNO[16]\ : XOR2
      port map(A => \HADDR_TEMP_c[16]\, B => HADDR_TEMP_c15, Y
         => HADDR_TEMP_n16);
    
    \HADDR_TEMP[12]\ : DFN1E1P0
      port map(D => HADDR_TEMP_n12, CLK => HCLK_c, PRE => 
        RESET_N_c, E => HADDR_TEMPe_0, Q => \HADDR_TEMP_c[12]\);
    
    \usb_32bit_data[18]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[18]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => N_361_0, Q => 
        \usb_32bit_data[18]_net_1\);
    
    \INTRPT_COUNT_RNO_0[2]\ : XNOR2
      port map(A => \INTRPT_COUNT[2]_net_1\, B => N_29, Y => 
        INTRPT_COUNT_n2_0_i_0);
    
    \INTRPT_COUNT_RNO[1]\ : NOR3A
      port map(A => N_67, B => send_data_c, C => 
        INTRPT_COUNT_n1_0_i_0, Y => N_16);
    
    \HADDR_TEMP_RNI4LDA1[22]\ : NOR3C
      port map(A => HADDR_TEMP_c11_m6_0_a2_3_0, B => 
        HADDR_TEMP_c22_m2_0_a2_1_0, C => HADDR_TEMP_c11_m6_0_a2_1, 
        Y => HADDR_TEMP_c22_m2_0_a2_1);
    
    \HADDR_TEMP_RNO_0[30]\ : NOR3A
      port map(A => HADDR_TEMP_c29_0_0, B => 
        HADDR_TEMP_c11_m6_0_a2_3, C => HADDR_TEMP_c20_m6_0_a2_4, 
        Y => HADDR_TEMP_c29_0_1);
    
    \usb_32bit_data_RNO[27]\ : AO1B
      port map(A => \usb_32bit_data[27]_net_1\, B => N_362, C => 
        \USB_DATA_OUT_m_2[3]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[27]\);
    
    send_data : DFN1E0C0
      port map(D => \data_states[0]_net_1\, CLK => HCLK_c, CLR
         => RESET_N_c, E => N_360, Q => send_data_c);
    
    \usb_32bit_data_RNO[24]\ : AO1B
      port map(A => \usb_32bit_data[24]_net_1\, B => N_362, C => 
        \USB_DATA_OUT_m_2[0]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[24]\);
    
    \HWDATA[4]\ : DFN1E0C0
      port map(D => \usb_32bit_data[4]_net_1\, CLK => HCLK_c, CLR
         => RESET_N_c, E => N_4, Q => \HWDATA_c[4]\);
    
    HMASTLOCK_pad : OUTBUF
      port map(D => \GND\, PAD => HMASTLOCK);
    
    \HWDATA_pad[25]\ : OUTBUF
      port map(D => \HWDATA_c[25]\, PAD => HWDATA(25));
    
    \data_states_RNO[1]\ : AO1C
      port map(A => FIFO_EMPTY_BIT_c, B => \data_states[2]_net_1\, 
        C => N_370, Y => \data_states_ns[5]\);
    
    \HWDATA[7]\ : DFN1E0C0
      port map(D => \usb_32bit_data[7]_net_1\, CLK => HCLK_c, CLR
         => RESET_N_c, E => N_4, Q => \HWDATA_c[7]\);
    
    \HADDR_pad[15]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[15]\, PAD => HADDR(15));
    
    \HADDR_TEMP[26]\ : DFN1E1C0
      port map(D => HADDR_TEMP_n26, CLK => HCLK_c, CLR => 
        RESET_N_c, E => HADDR_TEMPe, Q => \HADDR_TEMP_c[26]\);
    
    \HADDR_TEMP_RNIAM9E[3]\ : NOR2
      port map(A => HADDR_TEMP_c11_m6_0_a2_4_2_1, B => 
        HADDR_TEMP_c11_m6_0_a2_4_2_0, Y => 
        HADDR_TEMP_c11_m6_0_a2_4_2);
    
    \usb_32bit_data_RNO_0[13]\ : OR2B
      port map(A => \data_states[2]_net_1\, B => 
        \USB_DATA_OUT[5]\, Y => \USB_DATA_OUT_m_0[5]\);
    
    FABINT_pad : OUTBUF
      port map(D => FABINT_c, PAD => FABINT);
    
    \HWDATA_pad[27]\ : OUTBUF
      port map(D => \HWDATA_c[27]\, PAD => HWDATA(27));
    
    \HWDATA[0]\ : DFN1E0C0
      port map(D => \usb_32bit_data[0]_net_1\, CLK => HCLK_c, CLR
         => RESET_N_c, E => N_4_0, Q => \HWDATA_c[0]\);
    
    \data_states_RNO_0[1]\ : OR3B
      port map(A => \data_states[4]_net_1\, B => 
        \data_count[1]_net_1\, C => \data_count[0]_net_1\, Y => 
        N_370);
    
    \HADDR_TEMP_RNO[12]\ : XNOR2
      port map(A => \HADDR_TEMP_c[12]\, B => HADDR_TEMP_c11, Y
         => HADDR_TEMP_n12);
    
    \usb_32bit_data_RNO[26]\ : AO1B
      port map(A => \usb_32bit_data[26]_net_1\, B => N_362, C => 
        \USB_DATA_OUT_m_2[2]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[26]\);
    
    \usb_32bit_data_RNO[1]\ : AO1B
      port map(A => \usb_32bit_data[1]_net_1\, B => N_359, C => 
        \USB_DATA_OUT_m[1]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[1]\);
    
    \usb_32bit_data[12]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[12]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => N_361_0, Q => 
        \usb_32bit_data[12]_net_1\);
    
    \INTRPT_COUNT_RNI5C76[4]\ : OR3C
      port map(A => INTRPT_COUNT_e0_i_a2_1, B => 
        INTRPT_COUNT_e0_i_a2_0, C => INTRPT_COUNT_e0_i_a2_2, Y
         => N_63);
    
    \HWDATA[28]\ : DFN1E0C0
      port map(D => \usb_32bit_data[28]_net_1\, CLK => HCLK_c, 
        CLR => RESET_N_c, E => N_4, Q => \HWDATA_c[28]\);
    
    \INTRPT_COUNT_RNO[0]\ : OA1B
      port map(A => N_63, B => INTRPT_COUNT_e0_i_a3_0, C => N_40, 
        Y => N_14);
    
    \usb_32bit_data_RNO_0[10]\ : OR2B
      port map(A => \data_states[2]_net_1\, B => 
        \USB_DATA_OUT[2]\, Y => \USB_DATA_OUT_m_0[2]\);
    
    \usb_32bit_data[11]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[11]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => N_361_0, Q => 
        \usb_32bit_data[11]_net_1\);
    
    \HADDR_TEMP_RNIB5QN[13]\ : NOR3C
      port map(A => \HADDR_TEMP_c[17]\, B => \HADDR_TEMP_c[13]\, 
        C => \HADDR_TEMP_c[14]\, Y => HADDR_TEMP_c17_m6_0_a2_7_2);
    
    \HADDR_pad[0]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[0]\, PAD => HADDR(0));
    
    USB_CLK_pad : INBUF
      port map(PAD => USB_CLK, Y => USB_CLK_c);
    
    \usb_32bit_data[17]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[17]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => N_361_0, Q => 
        \usb_32bit_data[17]_net_1\);
    
    \HWDATA[11]\ : DFN1E0C0
      port map(D => \usb_32bit_data[11]_net_1\, CLK => HCLK_c, 
        CLR => RESET_N_c, E => N_4_0, Q => \HWDATA_c[11]\);
    
    \HWDATA[25]\ : DFN1E0C0
      port map(D => \usb_32bit_data[25]_net_1\, CLK => HCLK_c, 
        CLR => RESET_N_c, E => N_4, Q => \HWDATA_c[25]\);
    
    \HADDR_TEMP_RNO[26]\ : XOR2
      port map(A => \HADDR_TEMP_c[26]\, B => HADDR_TEMP_c25, Y
         => HADDR_TEMP_n26);
    
    \INTRPT_COUNT[5]\ : DFN1C0
      port map(D => N_24, CLK => HCLK_c, CLR => RESET_N_c, Q => 
        \INTRPT_COUNT[5]_net_1\);
    
    \HWDATA[24]\ : DFN1E0C0
      port map(D => \usb_32bit_data[24]_net_1\, CLK => HCLK_c, 
        CLR => RESET_N_c, E => N_4, Q => \HWDATA_c[24]\);
    
    \data_states[5]\ : DFN1C0
      port map(D => \data_states_ns[1]\, CLK => HCLK_c, CLR => 
        RESET_N_c, Q => \data_states[5]_net_1\);
    
    \HADDR_TEMP_RNO_0[15]\ : NOR2B
      port map(A => \HADDR_TEMP_c[14]\, B => HADDR_TEMP_c13_s_0, 
        Y => HADDR_TEMP_c14_0);
    
    \GEN.6.DATA_PINS\ : BIBUF_LVCMOS33U
      port map(PAD => USB_DATA_PAD(6), D => \USB_DATA_OUT[6]\, E
         => R_W_N_c, Y => \USB_DATA_IN[6]\);
    
    \HADDR_TEMP_RNI53123[14]\ : NOR2
      port map(A => HADDR_TEMP_c11_m6_0_a2_3, B => 
        HADDR_TEMP_c20_m6_0_a2_4, Y => HADDR_TEMP_c25_m4_0_a2_6);
    
    \HADDR_TEMP_RNO_0[10]\ : NOR3C
      port map(A => \HADDR_TEMP_c[7]\, B => \HADDR_TEMP_c[5]\, C
         => HADDR_TEMP_n10_0_m3_i_o2_2, Y => 
        HADDR_TEMP_n10_0_m3_i_o2_3);
    
    \HADDR_TEMP[31]\ : DFN1E1C0
      port map(D => HADDR_TEMP_n31, CLK => HCLK_c, CLR => 
        RESET_N_c, E => HADDR_TEMPe, Q => \HADDR_TEMP_c[31]\);
    
    \HADDR_TEMP_RNIO9JJ1[1]\ : OR2A
      port map(A => HADDR_TEMP_c11_m6_0_a2_0_0, B => 
        HADDR_TEMP_c11_m6_0_a2_3, Y => HADDR_TEMP_c11);
    
    \data_states_RNO_0[2]\ : OR3B
      port map(A => \data_count[0]_net_1\, B => 
        \data_states[4]_net_1\, C => \data_count[1]_net_1\, Y => 
        N_368);
    
    \HADDR_TEMP[10]\ : DFN1E1P0
      port map(D => HADDR_TEMP_n10_0_N_10_i_i_0, CLK => HCLK_c, 
        PRE => RESET_N_c, E => HADDR_TEMPe_0, Q => 
        \HADDR_TEMP_c[10]\);
    
    \usb_32bit_data[20]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[20]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => N_361_0, Q => 
        \usb_32bit_data[20]_net_1\);
    
    R_W_N_pad : INBUF
      port map(PAD => R_W_N, Y => R_W_N_c);
    
    \usb_32bit_data_RNO_0[23]\ : OR2B
      port map(A => \data_states[1]_net_1\, B => 
        \USB_DATA_OUT[7]\, Y => \USB_DATA_OUT_m_1[7]\);
    
    \HTRANS_1[1]\ : DFN1E0C0
      port map(D => HADDR_TEMPe, CLK => HCLK_c, CLR => RESET_N_c, 
        E => \ahb_states[1]_net_1\, Q => HWRITE_c_c);
    
    \HADDR_TEMP_RNO_0[28]\ : NOR2A
      port map(A => HADDR_TEMP_c27_m6_0_a2_5, B => 
        HADDR_TEMP_c11_m6_0_a2_3, Y => HADDR_TEMP_c27_m6_0_a2_0);
    
    \HADDR_TEMP_RNI8URF[26]\ : NOR2B
      port map(A => \HADDR_TEMP_c[26]\, B => \HADDR_TEMP_c[22]\, 
        Y => HADDR_TEMP_c27_m6_0_a2_5_1);
    
    \usb_32bit_data[13]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[13]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => N_361_0, Q => 
        \usb_32bit_data[13]_net_1\);
    
    \HADDR_pad[20]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[20]\, PAD => HADDR(20));
    
    \usb_32bit_data_RNO_0[12]\ : OR2B
      port map(A => \data_states[2]_net_1\, B => 
        \USB_DATA_OUT[4]\, Y => \USB_DATA_OUT_m_0[4]\);
    
    \usb_32bit_data_RNO_0[20]\ : OR2B
      port map(A => \data_states[1]_net_1\, B => 
        \USB_DATA_OUT[4]\, Y => \USB_DATA_OUT_m_1[4]\);
    
    \usb_32bit_data_RNO[12]\ : AO1B
      port map(A => \usb_32bit_data[12]_net_1\, B => N_358, C => 
        \USB_DATA_OUT_m_0[4]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[12]\);
    
    \HADDR_TEMP_RNIRMF03[14]\ : NOR2
      port map(A => HADDR_TEMP_c20_m6_0_a2_4, B => 
        HADDR_TEMP_c15_s_0, Y => HADDR_TEMP_c27_m6_0_a2_7);
    
    \data_states_RNI04S6_0[5]\ : NOR3
      port map(A => \data_states[4]_net_1\, B => 
        \data_states[5]_net_1\, C => \data_states[6]_net_1\, Y
         => \data_states_RNI04S6_0[5]_net_1\);
    
    \HWDATA[31]\ : DFN1E0C0
      port map(D => \usb_32bit_data[31]_net_1\, CLK => HCLK_c, 
        CLR => RESET_N_c, E => N_4, Q => \HWDATA_c[31]\);
    
    HSEL_pad : OUTBUF
      port map(D => \VCC\, PAD => HSEL);
    
    \HADDR_TEMP_RNO[22]\ : AX1C
      port map(A => HADDR_TEMP_c20, B => \HADDR_TEMP_c[21]\, C
         => \HADDR_TEMP_c[22]\, Y => HADDR_TEMP_n22);
    
    \HADDR_TEMP_RNI1R47[2]\ : NOR2B
      port map(A => \HADDR_TEMP_c[3]\, B => \HADDR_TEMP_c[2]\, Y
         => HADDR_TEMP_c3_s);
    
    \HWDATA_pad[7]\ : OUTBUF
      port map(D => \HWDATA_c[7]\, PAD => HWDATA(7));
    
    \INTRPT_COUNT[6]\ : DFN1C0
      port map(D => N_26, CLK => HCLK_c, CLR => RESET_N_c, Q => 
        \INTRPT_COUNT[6]_net_1\);
    
    \HADDR_TEMP[8]\ : DFN1E1P0
      port map(D => HADDR_TEMP_n8, CLK => HCLK_c, PRE => 
        RESET_N_c, E => HADDR_TEMPe, Q => \HADDR_TEMP_c[8]\);
    
    \usb_32bit_data_RNO[3]\ : AO1B
      port map(A => \usb_32bit_data[3]_net_1\, B => N_359, C => 
        \USB_DATA_OUT_m[3]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[3]\);
    
    \usb_32bit_data_RNO[30]\ : AO1B
      port map(A => \usb_32bit_data[30]_net_1\, B => N_362, C => 
        \USB_DATA_OUT_m_2[6]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[30]\);
    
    \HADDR_TEMP_RNIT05I2[18]\ : NOR2B
      port map(A => \HADDR_TEMP_c[18]\, B => 
        HADDR_TEMP_c17_m6_0_a2_7, Y => HADDR_TEMP_c18_0);
    
    \HADDR_pad[21]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[21]\, PAD => HADDR(21));
    
    \HWDATA[13]\ : DFN1E0C0
      port map(D => \usb_32bit_data[13]_net_1\, CLK => HCLK_c, 
        CLR => RESET_N_c, E => N_4_0, Q => \HWDATA_c[13]\);
    
    \INTRPT_COUNT_RNIKQ98[7]\ : OR3C
      port map(A => \INTRPT_COUNT[6]_net_1\, B => 
        \INTRPT_COUNT_RNIPB76[2]_net_1\, C => 
        \INTRPT_COUNT[7]_net_1\, Y => N_67);
    
    \usb_32bit_data[4]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[4]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => 
        \data_states_RNI04S6_0[5]_net_1\, Q => 
        \usb_32bit_data[4]_net_1\);
    
    \HWDATA_pad[21]\ : OUTBUF
      port map(D => \HWDATA_c[21]\, PAD => HWDATA(21));
    
    \usb_32bit_data_RNO[8]\ : AO1B
      port map(A => \usb_32bit_data[8]_net_1\, B => N_358, C => 
        \USB_DATA_OUT_m_0[0]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[8]\);
    
    \INTRPT_COUNT[2]\ : DFN1C0
      port map(D => N_18, CLK => HCLK_c, CLR => RESET_N_c, Q => 
        \INTRPT_COUNT[2]_net_1\);
    
    \GEN.7.DATA_PINS\ : BIBUF_LVCMOS33U
      port map(PAD => USB_DATA_PAD(7), D => \USB_DATA_OUT[7]\, E
         => R_W_N_c, Y => \USB_DATA_IN[7]\);
    
    \HWDATA_pad[28]\ : OUTBUF
      port map(D => \HWDATA_c[28]\, PAD => HWDATA(28));
    
    \HWDATA_pad[2]\ : OUTBUF
      port map(D => \HWDATA_c[2]\, PAD => HWDATA(2));
    
    \HADDR_TEMP[23]\ : DFN1E1C0
      port map(D => HADDR_TEMP_n23, CLK => HCLK_c, CLR => 
        RESET_N_c, E => HADDR_TEMPe_0, Q => \HADDR_TEMP_c[23]\);
    
    \usb_32bit_data_RNO_0[14]\ : OR2B
      port map(A => \data_states[2]_net_1\, B => 
        \USB_DATA_OUT[6]\, Y => \USB_DATA_OUT_m_0[6]\);
    
    \INTRPT_COUNT[1]\ : DFN1C0
      port map(D => N_16, CLK => HCLK_c, CLR => RESET_N_c, Q => 
        \INTRPT_COUNT[1]_net_1\);
    
    \data_states[3]\ : DFN1C0
      port map(D => \data_states_ns[3]\, CLK => HCLK_c, CLR => 
        RESET_N_c, Q => \data_states[3]_net_1\);
    
    \HWDATA[21]\ : DFN1E0C0
      port map(D => \usb_32bit_data[21]_net_1\, CLK => HCLK_c, 
        CLR => RESET_N_c, E => N_4_0, Q => \HWDATA_c[21]\);
    
    \HADDR_TEMP[25]\ : DFN1E1C0
      port map(D => HADDR_TEMP_n25, CLK => HCLK_c, CLR => 
        RESET_N_c, E => HADDR_TEMPe, Q => \HADDR_TEMP_c[25]\);
    
    \HWDATA_pad[12]\ : OUTBUF
      port map(D => \HWDATA_c[12]\, PAD => HWDATA(12));
    
    \HADDR_TEMP_RNIB9N25[21]\ : NOR2B
      port map(A => HADDR_TEMP_c25_m4_0_a2_6, B => 
        HADDR_TEMP_c25_m4_0_a2_5, Y => HADDR_TEMP_c25);
    
    \HADDR_TEMP_RNIAKNV[15]\ : NOR3B
      port map(A => \HADDR_TEMP_c[14]\, B => \HADDR_TEMP_c[15]\, 
        C => HADDR_TEMP_c13_s_0_0, Y => HADDR_TEMP_c15_1);
    
    \GEN.0.DATA_PINS\ : BIBUF_LVCMOS33U
      port map(PAD => USB_DATA_PAD(0), D => \USB_DATA_OUT[0]\, E
         => R_W_N_c, Y => \USB_DATA_IN[0]\);
    
    \HADDR_pad[2]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[2]\, PAD => HADDR(2));
    
    \data_states_RNO[3]\ : AO1C
      port map(A => FIFO_EMPTY_BIT_c, B => \data_states[0]_net_1\, 
        C => N_366, Y => \data_states_ns[3]\);
    
    \usb_32bit_data_RNO[28]\ : AO1B
      port map(A => \usb_32bit_data[28]_net_1\, B => N_362, C => 
        \USB_DATA_OUT_m_2[4]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[28]\);
    
    \HADDR_TEMP_RNI1AA31[12]\ : NOR3C
      port map(A => \HADDR_TEMP_c[7]\, B => \HADDR_TEMP_c[12]\, C
         => HADDR_TEMP_c17_m6_0_a2_7_2, Y => 
        HADDR_TEMP_c17_m6_0_a2_7_4);
    
    \HADDR_pad[9]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[9]\, PAD => HADDR(9));
    
    \data_states_RNIMRQ6[2]\ : OR3
      port map(A => \data_states[0]_net_1\, B => 
        \data_states[2]_net_1\, C => \data_states[3]_net_1\, Y
         => N_357);
    
    \usb_32bit_data_RNO_0[22]\ : OR2B
      port map(A => \data_states[1]_net_1\, B => 
        \USB_DATA_OUT[6]\, Y => \USB_DATA_OUT_m_1[6]\);
    
    \usb_32bit_data_RNO_0[4]\ : OR2B
      port map(A => \data_states[3]_net_1\, B => 
        \USB_DATA_OUT[4]\, Y => \USB_DATA_OUT_m[4]\);
    
    \usb_32bit_data[14]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[14]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => N_361_0, Q => 
        \usb_32bit_data[14]_net_1\);
    
    \HWDATA[16]\ : DFN1E0C0
      port map(D => \usb_32bit_data[16]_net_1\, CLK => HCLK_c, 
        CLR => RESET_N_c, E => N_4_0, Q => \HWDATA_c[16]\);
    
    \HTRANS_pad[1]\ : OUTBUF
      port map(D => HWRITE_c_c, PAD => HTRANS(1));
    
    \data_count[1]\ : DFN1C0
      port map(D => 
        \eight_bit_to_32bit_collection.data_count_3[1]\, CLK => 
        HCLK_c, CLR => RESET_N_c, Q => \data_count[1]_net_1\);
    
    FIFO_INST : Fifo_1024
      port map(USB_DATA_OUT(7) => \USB_DATA_OUT[7]\, 
        USB_DATA_OUT(6) => \USB_DATA_OUT[6]\, USB_DATA_OUT(5) => 
        \USB_DATA_OUT[5]\, USB_DATA_OUT(4) => \USB_DATA_OUT[4]\, 
        USB_DATA_OUT(3) => \USB_DATA_OUT[3]\, USB_DATA_OUT(2) => 
        \USB_DATA_OUT[2]\, USB_DATA_OUT(1) => \USB_DATA_OUT[1]\, 
        USB_DATA_OUT(0) => \USB_DATA_OUT[0]\, USB_DATA_IN(7) => 
        \USB_DATA_IN[7]\, USB_DATA_IN(6) => \USB_DATA_IN[6]\, 
        USB_DATA_IN(5) => \USB_DATA_IN[5]\, USB_DATA_IN(4) => 
        \USB_DATA_IN[4]\, USB_DATA_IN(3) => \USB_DATA_IN[3]\, 
        USB_DATA_IN(2) => \USB_DATA_IN[2]\, USB_DATA_IN(1) => 
        \USB_DATA_IN[1]\, USB_DATA_IN(0) => \USB_DATA_IN[0]\, 
        R_W_N_c => R_W_N_c, REP => \FIFO_INST.REP\, USB_CLK_c => 
        USB_CLK_c, Fifo_1024_VCC => \VCC\, FIFO_EMPTY_BIT_c => 
        FIFO_EMPTY_BIT_c, Fifo_1024_GND => \GND\, RESET_N_c => 
        RESET_N_c, HCLK_c => HCLK_c);
    
    \usb_32bit_data_RNO_0[31]\ : OR2B
      port map(A => \data_states[0]_net_1\, B => 
        \USB_DATA_OUT[7]\, Y => \USB_DATA_OUT_m_2[7]\);
    
    \HADDR_pad[27]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[27]\, PAD => HADDR(27));
    
    \HADDR_TEMP_RNO_0[29]\ : NOR3B
      port map(A => HADDR_TEMP_c27_m6_0_a2_5, B => 
        \HADDR_TEMP_c[28]\, C => HADDR_TEMP_c11_m6_0_a2_3, Y => 
        HADDR_TEMP_c28_0);
    
    \usb_32bit_data_RNO[13]\ : AO1B
      port map(A => \usb_32bit_data[13]_net_1\, B => N_358, C => 
        \USB_DATA_OUT_m_0[5]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[13]\);
    
    GND_i_0 : GND
      port map(Y => GND_net_1);
    
    \HADDR_TEMP_RNO[19]\ : AX1
      port map(A => HADDR_TEMP_c15_s_0, B => HADDR_TEMP_c18_0, C
         => \HADDR_TEMP_c[19]\, Y => HADDR_TEMP_n19);
    
    \HADDR_TEMP[24]\ : DFN1E1C0
      port map(D => HADDR_TEMP_n24, CLK => HCLK_c, CLR => 
        RESET_N_c, E => HADDR_TEMPe_0, Q => \HADDR_TEMP_c[24]\);
    
    \data_states_RNO_0[0]\ : OR3C
      port map(A => \data_count[0]_net_1\, B => 
        \data_states[4]_net_1\, C => \data_count[1]_net_1\, Y => 
        N_372);
    
    \INTRPT_COUNT_RNO[2]\ : NOR3B
      port map(A => N_67, B => INTRPT_COUNT_n2_0_i_0, C => 
        send_data_c, Y => N_18);
    
    \usb_32bit_data_RNO_0[0]\ : OR2B
      port map(A => \data_states[3]_net_1\, B => 
        \USB_DATA_OUT[0]\, Y => \USB_DATA_OUT_m[0]\);
    
    \data_states_RNO_0[3]\ : OR3A
      port map(A => \data_states[4]_net_1\, B => 
        \data_count[0]_net_1\, C => \data_count[1]_net_1\, Y => 
        N_366);
    
    \usb_32bit_data_RNO[4]\ : AO1B
      port map(A => \usb_32bit_data[4]_net_1\, B => N_359, C => 
        \USB_DATA_OUT_m[4]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[4]\);
    
    \HWDATA[1]\ : DFN1E0C0
      port map(D => \usb_32bit_data[1]_net_1\, CLK => HCLK_c, CLR
         => RESET_N_c, E => N_4_0, Q => \HWDATA_c[1]\);
    
    \HADDR_pad[3]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[3]\, PAD => HADDR(3));
    
    \HADDR_TEMP_RNO_0[31]\ : NOR3B
      port map(A => HADDR_TEMP_c29_0_0, B => \HADDR_TEMP_c[30]\, 
        C => HADDR_TEMP_c11_m6_0_a2_3, Y => HADDR_TEMP_c30_0);
    
    \usb_32bit_data_RNO_0[24]\ : OR2B
      port map(A => \data_states[0]_net_1\, B => 
        \USB_DATA_OUT[0]\, Y => \USB_DATA_OUT_m_2[0]\);
    
    \usb_32bit_data_RNO[17]\ : AO1B
      port map(A => \usb_32bit_data[17]_net_1\, B => N_357, C => 
        \USB_DATA_OUT_m_1[1]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[17]\);
    
    \HADDR_pad[30]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[30]\, PAD => HADDR(30));
    
    \INTRPT_COUNT[0]\ : DFN1C0
      port map(D => N_14, CLK => HCLK_c, CLR => RESET_N_c, Q => 
        \INTRPT_COUNT[0]_net_1\);
    
    \HADDR_TEMP_RNO_2[11]\ : NOR2B
      port map(A => \HADDR_TEMP_c[10]\, B => \HADDR_TEMP_c[6]\, Y
         => HADDR_TEMP_n11_0_m3_i_o2_0);
    
    \usb_32bit_data_RNO[14]\ : AO1B
      port map(A => \usb_32bit_data[14]_net_1\, B => N_358, C => 
        \USB_DATA_OUT_m_0[6]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[14]\);
    
    \HWDATA[23]\ : DFN1E0C0
      port map(D => \usb_32bit_data[23]_net_1\, CLK => HCLK_c, 
        CLR => RESET_N_c, E => N_4_0, Q => \HWDATA_c[23]\);
    
    \HWDATA_pad[19]\ : OUTBUF
      port map(D => \HWDATA_c[19]\, PAD => HWDATA(19));
    
    \data_states_RNI7A66[5]\ : NOR3A
      port map(A => FIFO_EMPTY_BIT_c, B => \data_states[4]_net_1\, 
        C => \data_states[5]_net_1\, Y => \data_states_ns[0]\);
    
    \HADDR_TEMP_RNO_0[25]\ : NOR2B
      port map(A => \HADDR_TEMP_c[24]\, B => HADDR_TEMP_c23_1, Y
         => HADDR_TEMP_c24_0);
    
    \HADDR_TEMP_RNO[14]\ : AX1
      port map(A => HADDR_TEMP_c15_s_0, B => HADDR_TEMP_c13_s_0, 
        C => \HADDR_TEMP_c[14]\, Y => HADDR_TEMP_n14);
    
    \GEN.2.DATA_PINS\ : BIBUF_LVCMOS33U
      port map(PAD => USB_DATA_PAD(2), D => \USB_DATA_OUT[2]\, E
         => R_W_N_c, Y => \USB_DATA_IN[2]\);
    
    \HADDR_TEMP_RNO[11]\ : AX1C
      port map(A => HADDR_TEMP_c4, B => 
        HADDR_TEMP_n11_0_m3_i_o2_4, C => \HADDR_TEMP_c[11]\, Y
         => HADDR_TEMP_n11_0_N_10_i_i_0);
    
    \usb_32bit_data_RNO[31]\ : AO1B
      port map(A => \usb_32bit_data[31]_net_1\, B => N_362, C => 
        \USB_DATA_OUT_m_2[7]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[31]\);
    
    \HWDATA_pad[0]\ : OUTBUF
      port map(D => \HWDATA_c[0]\, PAD => HWDATA(0));
    
    \HADDR_pad[26]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[26]\, PAD => HADDR(26));
    
    \HADDR_pad[12]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[12]\, PAD => HADDR(12));
    
    \INTRPT_COUNT_RNO[6]\ : NOR3A
      port map(A => N_67, B => send_data_c, C => 
        INTRPT_COUNT_n6_0_i_0, Y => N_26);
    
    \HADDR_TEMP_RNO_0[20]\ : NOR2B
      port map(A => \HADDR_TEMP_c[19]\, B => HADDR_TEMP_c18_0, Y
         => HADDR_TEMP_c19_0);
    
    \data_states_RNO[5]\ : NOR2A
      port map(A => \data_states[6]_net_1\, B => FIFO_EMPTY_BIT_c, 
        Y => \data_states_ns[1]\);
    
    \usb_32bit_data_RNO[20]\ : AO1B
      port map(A => \usb_32bit_data[20]_net_1\, B => N_357, C => 
        \USB_DATA_OUT_m_1[4]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[20]\);
    
    \HWDATA_pad[4]\ : OUTBUF
      port map(D => \HWDATA_c[4]\, PAD => HWDATA(4));
    
    \HADDR_TEMP[0]\ : DFN1P0
      port map(D => \HADDR_TEMP_RNO[0]_net_1\, CLK => HCLK_c, PRE
         => RESET_N_c, Q => \HADDR_TEMP_c[0]\);
    
    \HADDR_pad[31]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[31]\, PAD => HADDR(31));
    
    \ahb_states[1]\ : DFN1E1
      port map(D => \ahb_states_6[1]\, CLK => HCLK_c, E => 
        RESET_N_c, Q => \ahb_states[1]_net_1\);
    
    \HADDR_pad[28]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[28]\, PAD => HADDR(28));
    
    \HADDR_TEMP_RNO[30]\ : AX1
      port map(A => HADDR_TEMP_c15_s_0, B => HADDR_TEMP_c29_0_1, 
        C => \HADDR_TEMP_c[30]\, Y => HADDR_TEMP_n30);
    
    \HADDR_TEMP_RNO[0]\ : XOR2
      port map(A => HADDR_TEMPe_0, B => \HADDR_TEMP_c[0]\, Y => 
        \HADDR_TEMP_RNO[0]_net_1\);
    
    \usb_32bit_data_RNO[16]\ : AO1B
      port map(A => \usb_32bit_data[16]_net_1\, B => N_357, C => 
        \USB_DATA_OUT_m_1[0]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[16]\);
    
    \INTRPT_COUNT_RNO[7]\ : NOR3A
      port map(A => N_67, B => send_data_c, C => N_43_i, Y => 
        N_28);
    
    \HADDR_TEMP[4]\ : DFN1E1P0
      port map(D => HADDR_TEMP_n4, CLK => HCLK_c, PRE => 
        RESET_N_c, E => HADDR_TEMPe, Q => \HADDR_TEMP_c[4]\);
    
    \HADDR_TEMP_RNO[5]\ : XOR2
      port map(A => \HADDR_TEMP_c[5]\, B => HADDR_TEMP_c4, Y => 
        HADDR_TEMP_n5);
    
    \HADDR_TEMP_RNO[15]\ : AX1
      port map(A => HADDR_TEMP_c15_s_0, B => HADDR_TEMP_c14_0, C
         => \HADDR_TEMP_c[15]\, Y => HADDR_TEMP_n15);
    
    \GEN.3.DATA_PINS\ : BIBUF_LVCMOS33U
      port map(PAD => USB_DATA_PAD(3), D => \USB_DATA_OUT[3]\, E
         => R_W_N_c, Y => \USB_DATA_IN[3]\);
    
    \HWDATA[12]\ : DFN1E0C0
      port map(D => \usb_32bit_data[12]_net_1\, CLK => HCLK_c, 
        CLR => RESET_N_c, E => N_4_0, Q => \HWDATA_c[12]\);
    
    \HADDR_pad[23]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[23]\, PAD => HADDR(23));
    
    \HADDR_TEMP_RNIMH6A2[12]\ : NOR2B
      port map(A => HADDR_TEMP_c17_m6_0_a2_7_5, B => 
        HADDR_TEMP_c17_m6_0_a2_7_4, Y => HADDR_TEMP_c17_m6_0_a2_7);
    
    \HWDATA[26]\ : DFN1E0C0
      port map(D => \usb_32bit_data[26]_net_1\, CLK => HCLK_c, 
        CLR => RESET_N_c, E => N_4, Q => \HWDATA_c[26]\);
    
    \HADDR_TEMP_RNO[29]\ : AX1C
      port map(A => HADDR_TEMP_c27_m6_0_a2_7, B => 
        HADDR_TEMP_c28_0, C => \HADDR_TEMP_c[29]\, Y => 
        HADDR_TEMP_n29);
    
    \HADDR_pad[29]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[29]\, PAD => HADDR(29));
    
    \eight_bit_to_32bit_collection.data_count_3_I_8\ : XOR2
      port map(A => \data_count[0]_net_1\, B => N_361_0, Y => 
        \eight_bit_to_32bit_collection.data_count_3.DWACT_ADD_CI_0_partial_sum[0]\);
    
    \HADDR_TEMP_RNI9R47[6]\ : OR2B
      port map(A => \HADDR_TEMP_c[6]\, B => \HADDR_TEMP_c[7]\, Y
         => HADDR_TEMP_c7_0);
    
    \INTRPT_COUNT_RNIPB76[2]\ : NOR3B
      port map(A => INTRPT_COUNT_n5_0_i_o2_m1_0_a2_1, B => 
        INTRPT_COUNT_n5_0_i_o2_m1_0_a2_0, C => N_29, Y => 
        \INTRPT_COUNT_RNIPB76[2]_net_1\);
    
    \HADDR_TEMP_RNO_0[11]\ : NOR3C
      port map(A => HADDR_TEMP_n11_0_m3_i_o2_1, B => 
        HADDR_TEMP_n11_0_m3_i_o2_0, C => 
        HADDR_TEMP_n11_0_m3_i_o2_2, Y => 
        HADDR_TEMP_n11_0_m3_i_o2_4);
    
    \data_states[4]\ : DFN1C0
      port map(D => \data_states[5]_net_1\, CLK => HCLK_c, CLR
         => RESET_N_c, Q => \data_states[4]_net_1\);
    
    \usb_32bit_data[19]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[19]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => N_361_0, Q => 
        \usb_32bit_data[19]_net_1\);
    
    \HWDATA_pad[15]\ : OUTBUF
      port map(D => \HWDATA_c[15]\, PAD => HWDATA(15));
    
    \HADDR_TEMP_RNINU0P[1]\ : OR2B
      port map(A => HADDR_TEMP_c11_m6_0_a2_4_2, B => 
        HADDR_TEMP_c2, Y => HADDR_TEMP_c15_s_0);
    
    \GEN.5.DATA_PINS\ : BIBUF_LVCMOS33U
      port map(PAD => USB_DATA_PAD(5), D => \USB_DATA_OUT[5]\, E
         => R_W_N_c, Y => \USB_DATA_IN[5]\);
    
    \HWDATA_pad[23]\ : OUTBUF
      port map(D => \HWDATA_c[23]\, PAD => HWDATA(23));
    
    \HADDR_TEMP_RNI6QRF[20]\ : NOR2B
      port map(A => \HADDR_TEMP_c[20]\, B => \HADDR_TEMP_c[17]\, 
        Y => HADDR_TEMP_c20_m6_0_a2_4_0);
    
    \HADDR_TEMP_RNO[17]\ : AX1C
      port map(A => HADDR_TEMP_c15, B => \HADDR_TEMP_c[16]\, C
         => \HADDR_TEMP_c[17]\, Y => HADDR_TEMP_n17);
    
    \usb_32bit_data_RNO[29]\ : AO1B
      port map(A => \usb_32bit_data[29]_net_1\, B => N_362, C => 
        \USB_DATA_OUT_m_2[5]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[29]\);
    
    \HADDR_TEMP_RNIS12R3[14]\ : NOR2
      port map(A => HADDR_TEMP_c20_m6_0_a2_4, B => HADDR_TEMP_c11, 
        Y => HADDR_TEMP_c20);
    
    \usb_32bit_data[7]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[7]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => 
        \data_states_RNI04S6_0[5]_net_1\, Q => 
        \usb_32bit_data[7]_net_1\);
    
    \HADDR_TEMP_RNO[24]\ : AX1
      port map(A => HADDR_TEMP_c15_s_0, B => HADDR_TEMP_c23_1, C
         => \HADDR_TEMP_c[24]\, Y => HADDR_TEMP_n24);
    
    \HADDR_TEMP_RNIDR47[9]\ : NOR2B
      port map(A => \HADDR_TEMP_c[9]\, B => \HADDR_TEMP_c[8]\, Y
         => HADDR_TEMP_c11_m6_0_a2_1);
    
    \HADDR_TEMP_RNI3R47[3]\ : OR2B
      port map(A => \HADDR_TEMP_c[3]\, B => \HADDR_TEMP_c[4]\, Y
         => HADDR_TEMP_c11_m6_0_a2_4_2_0);
    
    \HWDATA_pad[17]\ : OUTBUF
      port map(D => \HWDATA_c[17]\, PAD => HWDATA(17));
    
    \HADDR_TEMP_RNO_1[10]\ : NOR3C
      port map(A => \HADDR_TEMP_c[9]\, B => \HADDR_TEMP_c[6]\, C
         => \HADDR_TEMP_c[8]\, Y => HADDR_TEMP_n10_0_m3_i_o2_2);
    
    \HADDR_TEMP_RNO[21]\ : XOR2
      port map(A => \HADDR_TEMP_c[21]\, B => HADDR_TEMP_c20, Y
         => HADDR_TEMP_n21);
    
    \usb_32bit_data[1]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[1]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => N_361_0, Q => 
        \usb_32bit_data[1]_net_1\);
    
    \HWDATA[10]\ : DFN1E0C0
      port map(D => \usb_32bit_data[10]_net_1\, CLK => HCLK_c, 
        CLR => RESET_N_c, E => N_4_0, Q => \HWDATA_c[10]\);
    
    \HWDATA[19]\ : DFN1E0C0
      port map(D => \usb_32bit_data[19]_net_1\, CLK => HCLK_c, 
        CLR => RESET_N_c, E => N_4_0, Q => \HWDATA_c[19]\);
    
    \usb_32bit_data_RNO[25]\ : AO1B
      port map(A => \usb_32bit_data[25]_net_1\, B => N_362, C => 
        \USB_DATA_OUT_m_2[1]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[25]\);
    
    \HADDR_TEMP_RNI7QRF[23]\ : NOR2B
      port map(A => \HADDR_TEMP_c[23]\, B => \HADDR_TEMP_c[24]\, 
        Y => HADDR_TEMP_c25_m4_0_a2_1);
    
    \usb_32bit_data[6]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[6]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => 
        \data_states_RNI04S6_0[5]_net_1\, Q => 
        \usb_32bit_data[6]_net_1\);
    
    \HADDR_TEMP_RNO[25]\ : AX1
      port map(A => HADDR_TEMP_c15_s_0, B => HADDR_TEMP_c24_0, C
         => \HADDR_TEMP_c[25]\, Y => HADDR_TEMP_n25);
    
    \data_count[0]\ : DFN1C0
      port map(D => 
        \eight_bit_to_32bit_collection.data_count_3.DWACT_ADD_CI_0_partial_sum[0]\, 
        CLK => HCLK_c, CLR => RESET_N_c, Q => 
        \data_count[0]_net_1\);
    
    \usb_32bit_data_RNO[21]\ : AO1B
      port map(A => \usb_32bit_data[21]_net_1\, B => N_357, C => 
        \USB_DATA_OUT_m_1[5]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[21]\);
    
    \usb_32bit_data[28]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[28]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => 
        \data_states_RNI04S6_0[5]_net_1\, Q => 
        \usb_32bit_data[28]_net_1\);
    
    \usb_32bit_data[5]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[5]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => 
        \data_states_RNI04S6_0[5]_net_1\, Q => 
        \usb_32bit_data[5]_net_1\);
    
    \HWDATA[22]\ : DFN1E0C0
      port map(D => \usb_32bit_data[22]_net_1\, CLK => HCLK_c, 
        CLR => RESET_N_c, E => N_4_0, Q => \HWDATA_c[22]\);
    
    \usb_32bit_data_RNO[5]\ : AO1B
      port map(A => \usb_32bit_data[5]_net_1\, B => N_359, C => 
        \USB_DATA_OUT_m[5]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[5]\);
    
    \usb_32bit_data[9]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[9]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => 
        \data_states_RNI04S6_0[5]_net_1\, Q => 
        \usb_32bit_data[9]_net_1\);
    
    \INTRPT_COUNT_RNID465[4]\ : NOR3B
      port map(A => \INTRPT_COUNT[3]_net_1\, B => 
        \INTRPT_COUNT[4]_net_1\, C => N_30, Y => N_32);
    
    \HADDR_TEMP[29]\ : DFN1E1P0
      port map(D => HADDR_TEMP_n29, CLK => HCLK_c, PRE => 
        RESET_N_c, E => HADDR_TEMPe, Q => \HADDR_TEMP_c[29]\);
    
    \INTRPT_COUNT_RNO_0[6]\ : XNOR2
      port map(A => \INTRPT_COUNT[6]_net_1\, B => 
        \INTRPT_COUNT_RNIPB76[2]_net_1\, Y => 
        INTRPT_COUNT_n6_0_i_0);
    
    \usb_32bit_data_RNO_0[6]\ : OR2B
      port map(A => \data_states[3]_net_1\, B => 
        \USB_DATA_OUT[6]\, Y => \USB_DATA_OUT_m[6]\);
    
    \usb_32bit_data[16]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[16]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => N_361_0, Q => 
        \usb_32bit_data[16]_net_1\);
    
    \INTRPT_COUNT_RNO[4]\ : NOR3A
      port map(A => N_67, B => send_data_c, C => 
        INTRPT_COUNT_n4_0_i_0, Y => N_22);
    
    \HADDR_TEMP[18]\ : DFN1E1C0
      port map(D => HADDR_TEMP_n18, CLK => HCLK_c, CLR => 
        RESET_N_c, E => HADDR_TEMPe_0, Q => \HADDR_TEMP_c[18]\);
    
    \HADDR_pad[14]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[14]\, PAD => HADDR(14));
    
    \HADDR_TEMP_RNID8NA[1]\ : NOR3C
      port map(A => \HADDR_TEMP_c[0]\, B => \HADDR_TEMP_c[1]\, C
         => \HADDR_TEMP_c[2]\, Y => HADDR_TEMP_c2);
    
    \usb_32bit_data_RNO[18]\ : AO1B
      port map(A => \usb_32bit_data[18]_net_1\, B => N_357, C => 
        \USB_DATA_OUT_m_1[2]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[18]\);
    
    \HWDATA[30]\ : DFN1E0C0
      port map(D => \usb_32bit_data[30]_net_1\, CLK => HCLK_c, 
        CLR => RESET_N_c, E => N_4, Q => \HWDATA_c[30]\);
    
    \HWDATA_pad[6]\ : OUTBUF
      port map(D => \HWDATA_c[6]\, PAD => HWDATA(6));
    
    \HWDATA[6]\ : DFN1E0C0
      port map(D => \usb_32bit_data[6]_net_1\, CLK => HCLK_c, CLR
         => RESET_N_c, E => N_4, Q => \HWDATA_c[6]\);
    
    \HADDR_TEMP_RNO[27]\ : AX1C
      port map(A => HADDR_TEMP_c25, B => \HADDR_TEMP_c[26]\, C
         => \HADDR_TEMP_c[27]\, Y => HADDR_TEMP_n27);
    
    \usb_32bit_data_RNO_0[1]\ : OR2B
      port map(A => \data_states[3]_net_1\, B => 
        \USB_DATA_OUT[1]\, Y => \USB_DATA_OUT_m[1]\);
    
    \FABINT\ : DFN1E1C0
      port map(D => un1_intrpt_count_1, CLK => HCLK_c, CLR => 
        RESET_N_c, E => N_8, Q => FABINT_c);
    
    \usb_32bit_data_RNO_0[19]\ : OR2B
      port map(A => \data_states[1]_net_1\, B => 
        \USB_DATA_OUT[3]\, Y => \USB_DATA_OUT_m_1[3]\);
    
    \usb_32bit_data[22]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[22]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => N_361_0, Q => 
        \usb_32bit_data[22]_net_1\);
    
    \data_states_RNI04S6[5]\ : NOR3
      port map(A => \data_states[4]_net_1\, B => 
        \data_states[5]_net_1\, C => \data_states[6]_net_1\, Y
         => N_361_0);
    
    \data_states_RNILNQ6[1]\ : OR3
      port map(A => \data_states[3]_net_1\, B => 
        \data_states[1]_net_1\, C => \data_states[0]_net_1\, Y
         => N_358);
    
    \usb_32bit_data_RNO_0[9]\ : OR2B
      port map(A => \data_states[2]_net_1\, B => 
        \USB_DATA_OUT[1]\, Y => \USB_DATA_OUT_m_0[1]\);
    
    \HADDR_TEMP_RNIOCPV[18]\ : NOR3B
      port map(A => \HADDR_TEMP_c[19]\, B => \HADDR_TEMP_c[18]\, 
        C => HADDR_TEMP_c17_m6_0_a2_7_1, Y => 
        HADDR_TEMP_c20_m6_0_a2_4_3);
    
    \INTRPT_COUNT_RNILE22[4]\ : NOR2B
      port map(A => \INTRPT_COUNT[3]_net_1\, B => 
        \INTRPT_COUNT[4]_net_1\, Y => 
        INTRPT_COUNT_n5_0_i_o2_m1_0_a2_1);
    
    \usb_32bit_data[21]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[21]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => N_361_0, Q => 
        \usb_32bit_data[21]_net_1\);
    
    \usb_32bit_data[27]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[27]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => 
        \data_states_RNI04S6_0[5]_net_1\, Q => 
        \usb_32bit_data[27]_net_1\);
    
    \HADDR_TEMP[22]\ : DFN1E1C0
      port map(D => HADDR_TEMP_n22, CLK => HCLK_c, CLR => 
        RESET_N_c, E => HADDR_TEMPe_0, Q => \HADDR_TEMP_c[22]\);
    
    \HWDATA_pad[20]\ : OUTBUF
      port map(D => \HWDATA_c[20]\, PAD => HWDATA(20));
    
    \HADDR_pad[5]\ : OUTBUF
      port map(D => \HADDR_TEMP_c[5]\, PAD => HADDR(5));
    
    \INTRPT_COUNT_RNIPE22[5]\ : NOR2
      port map(A => \INTRPT_COUNT[5]_net_1\, B => 
        \INTRPT_COUNT[6]_net_1\, Y => INTRPT_COUNT_e0_i_a2_0);
    
    \HWDATA_pad[8]\ : OUTBUF
      port map(D => \HWDATA_c[8]\, PAD => HWDATA(8));
    
    \HADDR_TEMP[11]\ : DFN1E1P0
      port map(D => HADDR_TEMP_n11_0_N_10_i_i_0, CLK => HCLK_c, 
        PRE => RESET_N_c, E => HADDR_TEMPe_0, Q => 
        \HADDR_TEMP_c[11]\);
    
    \data_states_RNO[0]\ : AO1C
      port map(A => FIFO_EMPTY_BIT_c, B => \data_states[1]_net_1\, 
        C => N_372, Y => \data_states_ns[6]\);
    
    \HWDATA_pad[11]\ : OUTBUF
      port map(D => \HWDATA_c[11]\, PAD => HWDATA(11));
    
    \HADDR_TEMP[17]\ : DFN1E1C0
      port map(D => HADDR_TEMP_n17, CLK => HCLK_c, CLR => 
        RESET_N_c, E => HADDR_TEMPe_0, Q => \HADDR_TEMP_c[17]\);
    
    \HWDATA[20]\ : DFN1E0C0
      port map(D => \usb_32bit_data[20]_net_1\, CLK => HCLK_c, 
        CLR => RESET_N_c, E => N_4_0, Q => \HWDATA_c[20]\);
    
    \usb_32bit_data[15]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[15]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => N_361_0, Q => 
        \usb_32bit_data[15]_net_1\);
    
    HCLK_pad : CLKBUF
      port map(PAD => HCLK, Y => HCLK_c);
    
    \HADDR_TEMP[1]\ : DFN1E1P0
      port map(D => HADDR_TEMP_n1, CLK => HCLK_c, PRE => 
        RESET_N_c, E => HADDR_TEMPe_0, Q => \HADDR_TEMP_c[1]\);
    
    \HWDATA_pad[18]\ : OUTBUF
      port map(D => \HWDATA_c[18]\, PAD => HWDATA(18));
    
    \HWDATA[29]\ : DFN1E0C0
      port map(D => \usb_32bit_data[29]_net_1\, CLK => HCLK_c, 
        CLR => RESET_N_c, E => N_4, Q => \HWDATA_c[29]\);
    
    \usb_32bit_data_RNO[7]\ : AO1B
      port map(A => \usb_32bit_data[7]_net_1\, B => N_359, C => 
        \USB_DATA_OUT_m[7]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[7]\);
    
    \HADDR_TEMP_RNO[7]\ : AX1
      port map(A => HADDR_TEMP_c5, B => \HADDR_TEMP_c[6]\, C => 
        \HADDR_TEMP_c[7]\, Y => HADDR_TEMP_n7);
    
    \HADDR_TEMP_RNI4OE72[14]\ : OR2B
      port map(A => HADDR_TEMP_c20_m6_0_a2_4_4, B => 
        HADDR_TEMP_c20_m6_0_a2_4_3, Y => HADDR_TEMP_c20_m6_0_a2_4);
    
    \HADDR_TEMP_RNO_3[11]\ : NOR2B
      port map(A => \HADDR_TEMP_c[7]\, B => \HADDR_TEMP_c[8]\, Y
         => HADDR_TEMP_n11_0_m3_i_o2_2);
    
    \HADDR_TEMP_RNITQ47[1]\ : NOR2B
      port map(A => \HADDR_TEMP_c[1]\, B => \HADDR_TEMP_c[0]\, Y
         => HADDR_TEMP_c1);
    
    \HADDR_TEMP_RNIDSE72[29]\ : NOR3C
      port map(A => HADDR_TEMP_c27_m6_0_a2_5, B => 
        \HADDR_TEMP_c[28]\, C => \HADDR_TEMP_c[29]\, Y => 
        HADDR_TEMP_c29_0_0);
    
    \HADDR_TEMP_RNO[6]\ : XNOR2
      port map(A => \HADDR_TEMP_c[6]\, B => HADDR_TEMP_c5, Y => 
        HADDR_TEMP_n6);
    
    \INTRPT_COUNT[3]\ : DFN1C0
      port map(D => N_20, CLK => HCLK_c, CLR => RESET_N_c, Q => 
        \INTRPT_COUNT[3]_net_1\);
    
    \usb_32bit_data_RNO[10]\ : AO1B
      port map(A => \usb_32bit_data[10]_net_1\, B => N_358, C => 
        \USB_DATA_OUT_m_0[2]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[10]\);
    
    SEND_DATA_BIT_pad : OUTBUF
      port map(D => send_data_c, PAD => SEND_DATA_BIT);
    
    \usb_32bit_data_RNO_0[29]\ : OR2B
      port map(A => \data_states[0]_net_1\, B => 
        \USB_DATA_OUT[5]\, Y => \USB_DATA_OUT_m_2[5]\);
    
    \usb_32bit_data[23]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[23]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => 
        \data_states_RNI04S6_0[5]_net_1\, Q => 
        \usb_32bit_data[23]_net_1\);
    
    FABINT_RNO_0 : OR3B
      port map(A => N_64, B => N_67, C => send_data_c, Y => N_8);
    
    \usb_32bit_data_RNO[6]\ : AO1B
      port map(A => \usb_32bit_data[6]_net_1\, B => N_359, C => 
        \USB_DATA_OUT_m[6]\, Y => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[6]\);
    
    \HWDATA[9]\ : DFN1E0C0
      port map(D => \usb_32bit_data[9]_net_1\, CLK => HCLK_c, CLR
         => RESET_N_c, E => N_4, Q => \HWDATA_c[9]\);
    
    \HWDATA_pad[26]\ : OUTBUF
      port map(D => \HWDATA_c[26]\, PAD => HWDATA(26));
    
    \usb_32bit_data[3]\ : DFN1E1C0
      port map(D => 
        \eight_bit_to_32bit_collection.usb_32bit_data_6[3]\, CLK
         => HCLK_c, CLR => RESET_N_c, E => 
        \data_states_RNI04S6_0[5]_net_1\, Q => 
        \usb_32bit_data[3]_net_1\);
    
    \HADDR_TEMP_RNIKFDJ[7]\ : NOR2A
      port map(A => \HADDR_TEMP_c[7]\, B => 
        HADDR_TEMP_c11_m6_0_a2_0, Y => HADDR_TEMP_c11_m6_0_a2_3_0);
    
    \HADDR_TEMP[16]\ : DFN1E1C0
      port map(D => HADDR_TEMP_n16, CLK => HCLK_c, CLR => 
        RESET_N_c, E => HADDR_TEMPe_0, Q => \HADDR_TEMP_c[16]\);
    

end DEF_ARCH; 
