----------------------------------------------------------------------
-- Created by Actel SmartDesign Thu Dec 29 14:20:47 2011
-- Testbench Template
-- This is a basic testbench that instantiates your design with basic 
-- clock and reset pins connected.  If your design has special
-- clock/reset or testbench driver requirements then you should 
-- copy this file and modify it. 
----------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench;

architecture behavioral of testbench is

    constant SYSCLK_PERIOD : time := 100 ns;

    signal SYSCLK : std_logic := '0';
    signal NSYSRESET : std_logic := '0';

    component usb_mss
        -- ports
        port( 
            -- Inputs
            MAINXIN : in std_logic;
            FABHWRITE : in std_logic;
            FABHSEL : in std_logic;
            FABHMASTLOCK : in std_logic;
            FABHREADY : in std_logic;
            FABINT : in std_logic;
            FABHADDR : in std_logic_vector(31 downto 0);
            FABHTRANS : in std_logic_vector(1 downto 0);
            FABHSIZE : in std_logic_vector(1 downto 0);
            FABHWDATA : in std_logic_vector(31 downto 0);
            UART_0_RXD : in std_logic;
            MSS_RESET_N : in std_logic;
            IO_0_PADIN : in std_logic;

            -- Outputs
            FAB_CLK : out std_logic;
            FABHREADYOUT : out std_logic;
            FABHRESP : out std_logic;
            IO_0_Y : out std_logic;
            M2F_RESET_N : out std_logic;
            FABHRDATA : out std_logic_vector(31 downto 0);
            UART_0_TXD : out std_logic;
            EMC_AB : out std_logic_vector(25 downto 0);
            EMC_BYTEN : out std_logic_vector(1 downto 0);
            EMC_CS0_N : out std_logic;
            EMC_CS1_N : out std_logic;
            EMC_OEN0_N : out std_logic;
            EMC_OEN1_N : out std_logic;
            EMC_CLK : out std_logic;
            EMC_RW_N : out std_logic;

            -- Inouts
            EMC_DB : inout std_logic_vector(15 downto 0)

        );
    end component;

begin

    process
        variable vhdl_initial : BOOLEAN := TRUE;

    begin
        if ( vhdl_initial ) then
            -- Assert Reset
            NSYSRESET <= '0';
            wait for ( SYSCLK_PERIOD * 10 );
            
            NSYSRESET <= '1';
            wait;
        end if;
    end process;

    -- 10MHz Clock Driver
    SYSCLK <= not SYSCLK after (SYSCLK_PERIOD / 2.0 );

    -- Instantiate Unit Under Test:  usb_mss
    usb_mss_0 : usb_mss
        -- port map
        port map( 
            -- Inputs
            MAINXIN => '0',
            FABHWRITE => '0',
            FABHSEL => '0',
            FABHMASTLOCK => '0',
            FABHREADY => '0',
            FABINT => '0',
            FABHADDR => (others=> '0'),
            FABHTRANS => (others=> '0'),
            FABHSIZE => (others=> '0'),
            FABHWDATA => (others=> '0'),
            UART_0_RXD => '0',
            MSS_RESET_N => NSYSRESET,
            IO_0_PADIN => '0',

            -- Outputs
            FAB_CLK =>  open,
            FABHREADYOUT =>  open,
            FABHRESP =>  open,
            IO_0_Y =>  open,
            M2F_RESET_N =>  open,
            FABHRDATA => open,
            UART_0_TXD =>  open,
            EMC_AB => open,
            EMC_BYTEN => open,
            EMC_CS0_N =>  open,
            EMC_CS1_N =>  open,
            EMC_OEN0_N =>  open,
            EMC_OEN1_N =>  open,
            EMC_CLK =>  open,
            EMC_RW_N =>  open,

            -- Inouts
            EMC_DB => open

        );

end behavioral;

