#  
# This is an automatically generated script file for loading the instrumented 
# design into Synplify. 
# 
add_file -vhdl -lib work  "//idm/CAE/pavan m/USB/USBeee/Using_Fabric_Master/HW_USBee/synthesis/synthesis_1/instr_sources/component/Actel/SmartFusionMSS/MSS/2.0.100/mss_comps.vhd"
add_file -vhdl -lib work  "//idm/CAE/pavan m/USB/USBeee/Using_Fabric_Master/HW_USBee/synthesis/synthesis_1/instr_sources/component/work/usb_mss/MSS_CCC_0/usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd"
add_file -vhdl -lib work  "//idm/CAE/pavan m/USB/USBeee/Using_Fabric_Master/HW_USBee/synthesis/synthesis_1/instr_sources/component/work/usb_mss/usb_mss.vhd"
add_file -vhdl -lib work  "//idm/CAE/pavan m/USB/USBeee/Using_Fabric_Master/HW_USBee/synthesis/synthesis_1/instr_sources/smartgen/Fifo_1024/Fifo_1024.vhd"
add_file -vhdl -lib work  "//idm/CAE/pavan m/USB/USBeee/Using_Fabric_Master/HW_USBee/synthesis/synthesis_1/instr_sources/hdl/usb_slave.vhd"
add_file -vhdl -lib work  "//idm/CAE/pavan m/USB/USBeee/Using_Fabric_Master/HW_USBee/synthesis/synthesis_1/instr_sources/component/work/usbee_top_level/usbee_top_level.vhd"
add_file "//idm/CAE/pavan m/USB/USBeee/Using_Fabric_Master/HW_USBee/synthesis/synthesis_1/instr_sources/syn_dics.vhd"
set_option -top_module work.usbee_top_level
set_option -technology PROASIC3E
set_option -dup 0
