#  
# This is an automatically generated script file for loading the instrumented 
# design into Synplify. 
# 
add_file -verilog  "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/synthesis/synthesis_1/instr_sources/Actel/SmartFusionMSS/MSS/2.2.101/mss_comps.v"
add_file -verilog  "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/synthesis/synthesis_1/instr_sources/work/mss_top/MSS_CCC_0/mss_top_tmp_MSS_CCC_0_MSS_CCC.v"
add_file -verilog  "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/synthesis/synthesis_1/instr_sources/work/mss_top/mss_top.v"
add_file -verilog  "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/synthesis/synthesis_1/instr_sources/Actel/DirectCore/CORESPI/3.0.156/rtl/vlog/core/spi_master.v"
add_file -verilog  "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/synthesis/synthesis_1/instr_sources/Actel/DirectCore/CORESPI/3.0.156/rtl/vlog/core/spi_slave.v"
add_file -verilog  "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/synthesis/synthesis_1/instr_sources/Actel/DirectCore/CORESPI/3.0.156/rtl/vlog/core/corespi_sfr.v"
add_file -verilog  "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/synthesis/synthesis_1/instr_sources/Actel/DirectCore/CORESPI/3.0.156/rtl/vlog/core/corespi.v"
add_file -verilog  "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/synthesis/synthesis_1/instr_sources/Actel/DirectCore/CoreAPB3/3.0.103/rtl/vlog/core/coreapb3_muxptob3.v"
add_file -verilog  "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/synthesis/synthesis_1/instr_sources/Actel/DirectCore/CoreAPB3/3.0.103/rtl/vlog/core/coreapb3.v"
add_file -verilog  "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/synthesis/synthesis_1/instr_sources/work/top_level/top_level.v"
add_file "D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/synthesis/synthesis_1/instr_sources/syn_dics.v"
set_option -top_module top_level
set_option -technology FUSION
set_option -include_path "./"
set_option -include_path "C:/Actel/Libero_v9.0/Synopsys/synplify_D200912A/lib"
set_option -vlog_std v2001
set_option -dup 0
