Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Mon Jan 02 11:57:45 2012


Design: top_level
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                10.413
Frequency (MHz):            96.034
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                9.710
Frequency (MHz):            102.987
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        5.718
External Hold (ns):         -1.709
Min Clock-To-Out (ns):      4.120
Max Clock-To-Out (ns):      9.461

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.661
External Hold (ns):         1.288
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_macclk
Period (ns):                25.000
Frequency (MHz):            40.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[3]
  Delay (ns):                  12.589
  Slack (ns):
  Arrival (ns):                12.589
  Required (ns):
  Setup (ns):                  -2.176
  Minimum Period (ns):         10.413

Path 2
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[7]
  Delay (ns):                  12.176
  Slack (ns):
  Arrival (ns):                12.176
  Required (ns):
  Setup (ns):                  -2.176
  Minimum Period (ns):         10.000

Path 3
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0]
  Delay (ns):                  12.162
  Slack (ns):
  Arrival (ns):                12.162
  Required (ns):
  Setup (ns):                  -2.178
  Minimum Period (ns):         9.984

Path 4
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[12]
  Delay (ns):                  12.159
  Slack (ns):
  Arrival (ns):                12.159
  Required (ns):
  Setup (ns):                  -2.181
  Minimum Period (ns):         9.978

Path 5
  From:                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[1]
  Delay (ns):                  12.148
  Slack (ns):
  Arrival (ns):                12.148
  Required (ns):
  Setup (ns):                  -2.177
  Minimum Period (ns):         9.971


Expanded Path 1
  From: mss_top_0/MSS_ADLIB_INST/U_CORE:GLB
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[3]
  data required time                             N/C
  data arrival time                          -   12.589
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.879          cell: ADLIB:MSS_APB_IP
  2.879                        mss_top_0/MSS_ADLIB_INST/U_CORE:MSSPADDR[2] (r)
               +     0.119          net: mss_top_0/MSS_ADLIB_INST/MSSPADDR[2]INT_NET
  2.998                        mss_top_0/MSS_ADLIB_INST/U_30:PIN3INT (r)
               +     0.086          cell: ADLIB:MSS_IF
  3.084                        mss_top_0/MSS_ADLIB_INST/U_30:PIN3 (r)
               +     2.560          net: mss_top_0_MSS_MASTER_APB_PADDR_[2]
  5.644                        SPI_0/ucorespi_sfr/data_out_m_i_a2_1[0]:B (r)
               +     0.468          cell: ADLIB:OR2A
  6.112                        SPI_0/ucorespi_sfr/data_out_m_i_a2_1[0]:Y (r)
               +     1.447          net: SPI_0/ucorespi_sfr/N_382
  7.559                        SPI_0/ucorespi_sfr/control_reg_RNI8GSH1[6]:C (r)
               +     0.698          cell: ADLIB:AO1
  8.257                        SPI_0/ucorespi_sfr/control_reg_RNI8GSH1[6]:Y (r)
               +     0.306          net: SPI_0/ucorespi_sfr/control_reg_RNI8GSH1[6]
  8.563                        SPI_0/ucorespi_sfr/control_reg_RNIEBLQ2[3]:B (r)
               +     0.568          cell: ADLIB:NOR3C
  9.131                        SPI_0/ucorespi_sfr/control_reg_RNIEBLQ2[3]:Y (r)
               +     1.181          net: SPI_0/ucorespi_sfr/data_out_m_i_1[3]
  10.312                       SPI_0/ucorespi_sfr/genblk6.u_slave/rx_data_reg_RNIODKP5[28]:A (r)
               +     0.606          cell: ADLIB:NOR3B
  10.918                       SPI_0/ucorespi_sfr/genblk6.u_slave/rx_data_reg_RNIODKP5[28]:Y (r)
               +     1.168          net: SPI_0_ucorespi_sfr_N_23_i_0
  12.086                       mss_top_0/MSS_ADLIB_INST/U_37:PIN6 (r)
               +     0.076          cell: ADLIB:MSS_IF
  12.162                       mss_top_0/MSS_ADLIB_INST/U_37:PIN6INT (r)
               +     0.427          net: mss_top_0/MSS_ADLIB_INST/MSSPRDATA[3]INT_NET
  12.589                       mss_top_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[3] (r)
                                    
  12.589                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_fabric_interface_clock
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               -    -2.176          Library setup time: ADLIB:MSS_APB_IP
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[3]


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        SPI_0/ucorespi_sfr/genblk6.u_slave/count[0]/U1:CLK
  To:                          SPI_0/ucorespi_sfr/genblk6.u_slave/rx_data_reg[24]/U1:D
  Delay (ns):                  9.209
  Slack (ns):
  Arrival (ns):                9.866
  Required (ns):
  Setup (ns):                  0.522
  Minimum Period (ns):         9.710

Path 2
  From:                        SPI_0/ucorespi_sfr/genblk6.u_slave/count[4]/U1:CLK
  To:                          SPI_0/ucorespi_sfr/genblk6.u_slave/rx_data_reg[24]/U1:D
  Delay (ns):                  8.910
  Slack (ns):
  Arrival (ns):                9.567
  Required (ns):
  Setup (ns):                  0.522
  Minimum Period (ns):         9.411

Path 3
  From:                        SPI_0/ucorespi_sfr/genblk4.u_master/state[3]:CLK
  To:                          SPI_0/ucorespi_sfr/genblk4.u_master/rx_error_i/U1:D
  Delay (ns):                  8.872
  Slack (ns):
  Arrival (ns):                9.566
  Required (ns):
  Setup (ns):                  0.522
  Minimum Period (ns):         9.382

Path 4
  From:                        SPI_0/ucorespi_sfr/genblk4.u_master/state[3]:CLK
  To:                          SPI_0/ucorespi_sfr/genblk4.u_master/rx_data_waiting/U1:D
  Delay (ns):                  8.764
  Slack (ns):
  Arrival (ns):                9.458
  Required (ns):
  Setup (ns):                  0.522
  Minimum Period (ns):         9.307

Path 5
  From:                        SPI_0/ucorespi_sfr/genblk6.u_slave/count[1]/U1:CLK
  To:                          SPI_0/ucorespi_sfr/genblk6.u_slave/rx_data_reg[24]/U1:D
  Delay (ns):                  8.771
  Slack (ns):
  Arrival (ns):                9.428
  Required (ns):
  Setup (ns):                  0.522
  Minimum Period (ns):         9.272


Expanded Path 1
  From: SPI_0/ucorespi_sfr/genblk6.u_slave/count[0]/U1:CLK
  To: SPI_0/ucorespi_sfr/genblk6.u_slave/rx_data_reg[24]/U1:D
  data required time                             N/C
  data arrival time                          -   9.866
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.657          net: FAB_CLK
  0.657                        SPI_0/ucorespi_sfr/genblk6.u_slave/count[0]/U1:CLK (r)
               +     0.671          cell: ADLIB:DFN1C0
  1.328                        SPI_0/ucorespi_sfr/genblk6.u_slave/count[0]/U1:Q (f)
               +     1.402          net: SPI_0/ucorespi_sfr/genblk6_u_slave/count[0]
  2.730                        SPI_0/ucorespi_sfr/genblk6.u_slave/count_RNIH6AI[5]:B (f)
               +     0.370          cell: ADLIB:NOR2A
  3.100                        SPI_0/ucorespi_sfr/genblk6.u_slave/count_RNIH6AI[5]:Y (r)
               +     0.305          net: SPI_0/ucorespi_sfr/genblk6_u_slave/rx_ready_0
  3.405                        SPI_0/ucorespi_sfr/genblk6.u_slave/count_RNIJJUM1[2]:B (r)
               +     0.652          cell: ADLIB:OR3C
  4.057                        SPI_0/ucorespi_sfr/genblk6.u_slave/count_RNIJJUM1[2]:Y (f)
               +     1.535          net: SPI_0/ucorespi_sfr/genblk6_u_slave/rx_ready
  5.592                        SPI_0/ucorespi_sfr/genblk6.u_slave/count_RNIJU3T1_0[2]:B (f)
               +     0.592          cell: ADLIB:NOR2
  6.184                        SPI_0/ucorespi_sfr/genblk6.u_slave/count_RNIJU3T1_0[2]:Y (r)
               +     3.047          net: SPI_0/ucorespi_sfr/genblk6_u_slave/rx_data_reg_0_sqmuxa_1
  9.231                        SPI_0/ucorespi_sfr/genblk6.u_slave/rx_data_reg[24]/U0:S (r)
               +     0.339          cell: ADLIB:MX2
  9.570                        SPI_0/ucorespi_sfr/genblk6.u_slave/rx_data_reg[24]/U0:Y (f)
               +     0.296          net: SPI_0/ucorespi_sfr/genblk6_u_slave/rx_data_reg[24]/Y
  9.866                        SPI_0/ucorespi_sfr/genblk6.u_slave/rx_data_reg[24]/U1:D (f)
                                    
  9.866                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  N/C                          mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.678          net: FAB_CLK
  N/C                          SPI_0/ucorespi_sfr/genblk6.u_slave/rx_data_reg[24]/U1:CLK (r)
               -     0.522          Library setup time: ADLIB:DFN1C0
  N/C                          SPI_0/ucorespi_sfr/genblk6.u_slave/rx_data_reg[24]/U1:D


END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        s_sck
  To:                          SPI_0/ucorespi_sfr/genblk6.u_slave/i_sck/U1:D
  Delay (ns):                  5.917
  Slack (ns):
  Arrival (ns):                5.917
  Required (ns):
  Setup (ns):                  0.490
  External Setup (ns):         5.718

Path 2
  From:                        s_ss
  To:                          SPI_0/ucorespi_sfr/genblk6.u_slave/t_ss:D
  Delay (ns):                  4.959
  Slack (ns):
  Arrival (ns):                4.959
  Required (ns):
  Setup (ns):                  0.522
  External Setup (ns):         4.803

Path 3
  From:                        s_mosi
  To:                          SPI_0/ucorespi_sfr/genblk6.u_slave/t_mosi/U1:D
  Delay (ns):                  4.588
  Slack (ns):
  Arrival (ns):                4.588
  Required (ns):
  Setup (ns):                  0.490
  External Setup (ns):         4.421


Expanded Path 1
  From: s_sck
  To: SPI_0/ucorespi_sfr/genblk6.u_slave/i_sck/U1:D
  data required time                             N/C
  data arrival time                          -   5.917
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        s_sck (r)
               +     0.000          net: s_sck
  0.000                        s_sck_pad/U0/U0:PAD (r)
               +     0.935          cell: ADLIB:IOPAD_IN
  0.935                        s_sck_pad/U0/U0:Y (r)
               +     0.000          net: s_sck_pad/U0/NET1
  0.935                        s_sck_pad/U0/U1:YIN (r)
               +     0.039          cell: ADLIB:IOIN_IB
  0.974                        s_sck_pad/U0/U1:Y (r)
               +     3.164          net: s_sck_c
  4.138                        SPI_0/ucorespi_sfr/genblk6.u_slave/i_sck_RNO:B (r)
               +     0.650          cell: ADLIB:XOR3
  4.788                        SPI_0/ucorespi_sfr/genblk6.u_slave/i_sck_RNO:Y (r)
               +     0.306          net: SPI_0/ucorespi_sfr/genblk6_u_slave/N_218_i
  5.094                        SPI_0/ucorespi_sfr/genblk6.u_slave/i_sck/U0:A (r)
               +     0.517          cell: ADLIB:MX2
  5.611                        SPI_0/ucorespi_sfr/genblk6.u_slave/i_sck/U0:Y (r)
               +     0.306          net: SPI_0/ucorespi_sfr/genblk6_u_slave/i_sck/Y
  5.917                        SPI_0/ucorespi_sfr/genblk6.u_slave/i_sck/U1:D (r)
                                    
  5.917                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  N/C                          mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.689          net: FAB_CLK
  N/C                          SPI_0/ucorespi_sfr/genblk6.u_slave/i_sck/U1:CLK (r)
               -     0.490          Library setup time: ADLIB:DFN1C0
  N/C                          SPI_0/ucorespi_sfr/genblk6.u_slave/i_sck/U1:D


END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        SPI_0/ucorespi_sfr/genblk6.u_slave/rxtx_shift_reg[31]/U1:CLK
  To:                          s_miso
  Delay (ns):                  8.767
  Slack (ns):
  Arrival (ns):                9.461
  Required (ns):
  Clock to Out (ns):           9.461


Expanded Path 1
  From: SPI_0/ucorespi_sfr/genblk6.u_slave/rxtx_shift_reg[31]/U1:CLK
  To: s_miso
  data required time                             N/C
  data arrival time                          -   9.461
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: mss_top_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        mss_top_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.694          net: FAB_CLK
  0.694                        SPI_0/ucorespi_sfr/genblk6.u_slave/rxtx_shift_reg[31]/U1:CLK (r)
               +     0.671          cell: ADLIB:DFN1C0
  1.365                        SPI_0/ucorespi_sfr/genblk6.u_slave/rxtx_shift_reg[31]/U1:Q (f)
               +     4.245          net: s_miso_c
  5.610                        s_miso_pad/U0/U1:D (f)
               +     0.600          cell: ADLIB:IOTRI_OB_EB
  6.210                        s_miso_pad/U0/U1:DOUT (f)
               +     0.000          net: s_miso_pad/U0/NET1
  6.210                        s_miso_pad/U0/U0:D (f)
               +     3.251          cell: ADLIB:IOPAD_TRI
  9.461                        s_miso_pad/U0/U0:PAD (f)
               +     0.000          net: s_miso
  9.461                        s_miso (f)
                                    
  9.461                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
                                    
  N/C                          s_miso (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.937
  Slack (ns):
  Arrival (ns):                0.937
  Required (ns):
  Setup (ns):                  -2.139
  External Setup (ns):         -1.661


Expanded Path 1
  From: MSS_RESET_N
  To: mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.937
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        mss_top_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.937          cell: ADLIB:IOPAD_IN
  0.937                        mss_top_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: mss_top_0/MSS_RESET_0_MSS_RESET_N_Y
  0.937                        mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.937                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          mss_top_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.459          net: mss_top_0/GLA0
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -2.139          Library setup time: ADLIB:MSS_APB_IP
  N/C                          mss_top_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_macclk

Info: The maximum frequency of this clock domain is limited by the period of pin mss_top_0/MSS_ADLIB_INST/U_CORE:MACCLKCCC

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_top_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

