@E: CG389 :"C:\A2F_AC356_DF\A2F500\FTDI\FTDI_SPI\component\work\top_level\top_level.v":546:8:546:10|Reference to undefined module VCC
@E: CG389 :"C:\A2F_AC356_DF\A2F500\FTDI\FTDI_SPI\component\work\mss_top\mss_top.v":177:8:177:10|Reference to undefined module VCC
@E: CG389 :"C:\A2F_AC356_DF\A2F500\FTDI\FTDI_SPI\component\work\mss_top\mss_top.v":177:8:177:10|Illegal or Unsupported Syntax within black box. Use: // synthesis translate_off {  unsupported Verilog } // synthesis translate_on 
@E: CG389 :"C:\A2F_AC356_DF\A2F500\FTDI\FTDI_SPI\component\work\mss_top\mss_top.v":177:8:177:10|Alternatively, set the builtin compiler directive IGNORE_VERILOG_BLACKBOX_GUTS in the Verilog tab of the UI or set `define IGNORE_VERILOG_BLACKBOX_GUTS in any Verilog file.
@E: CG389 :"C:\A2F_AC356_DF\A2F500\FTDI\FTDI_SPI\component\work\mss_top\mss_top.v":224:8:224:10|Reference to undefined module GND
@E: CG389 :"C:\A2F_AC356_DF\A2F500\FTDI\FTDI_SPI\component\work\mss_top\mss_top.v":224:8:224:10|Illegal or Unsupported Syntax within black box. Use: // synthesis translate_off {  unsupported Verilog } // synthesis translate_on 
@E: CG389 :"C:\A2F_AC356_DF\A2F500\FTDI\FTDI_SPI\component\work\mss_top\mss_top.v":224:8:224:10|Alternatively, set the builtin compiler directive IGNORE_VERILOG_BLACKBOX_GUTS in the Verilog tab of the UI or set `define IGNORE_VERILOG_BLACKBOX_GUTS in any Verilog file.
@E: CG389 :"C:\A2F_AC356_DF\A2F500\FTDI\FTDI_SPI\component\work\mss_top\MSS_CCC_0\mss_top_tmp_MSS_CCC_0_MSS_CCC.v":97:8:97:22|Reference to undefined module GND
@E: CG389 :"C:\A2F_AC356_DF\A2F500\FTDI\FTDI_SPI\component\work\mss_top\MSS_CCC_0\mss_top_tmp_MSS_CCC_0_MSS_CCC.v":97:8:97:22|Illegal or Unsupported Syntax within black box. Use: // synthesis translate_off {  unsupported Verilog } // synthesis translate_on 
@E: CG389 :"C:\A2F_AC356_DF\A2F500\FTDI\FTDI_SPI\component\work\mss_top\MSS_CCC_0\mss_top_tmp_MSS_CCC_0_MSS_CCC.v":97:8:97:22|Alternatively, set the builtin compiler directive IGNORE_VERILOG_BLACKBOX_GUTS in the Verilog tab of the UI or set `define IGNORE_VERILOG_BLACKBOX_GUTS in any Verilog file.
@E: CG389 :"C:\A2F_AC356_DF\A2F500\FTDI\FTDI_SPI\component\work\mss_top\MSS_CCC_0\mss_top_tmp_MSS_CCC_0_MSS_CCC.v":98:8:98:22|Reference to undefined module VCC
@E: CG389 :"C:\A2F_AC356_DF\A2F500\FTDI\FTDI_SPI\component\work\mss_top\MSS_CCC_0\mss_top_tmp_MSS_CCC_0_MSS_CCC.v":98:8:98:22|Illegal or Unsupported Syntax within black box. Use: // synthesis translate_off {  unsupported Verilog } // synthesis translate_on 
@E: CG389 :"C:\A2F_AC356_DF\A2F500\FTDI\FTDI_SPI\component\work\mss_top\MSS_CCC_0\mss_top_tmp_MSS_CCC_0_MSS_CCC.v":98:8:98:22|Alternatively, set the builtin compiler directive IGNORE_VERILOG_BLACKBOX_GUTS in the Verilog tab of the UI or set `define IGNORE_VERILOG_BLACKBOX_GUTS in any Verilog file.
@E: CG389 :"C:\A2F_AC356_DF\A2F500\FTDI\FTDI_SPI\component\work\top_level\top_level.v":659:8:659:10|Reference to undefined module GND

