-- Version: 9.0 SPC 9.0.1.10

library ieee;
use ieee.std_logic_1164.all;
library smartfusion;
use smartfusion.all;

entity Em_Fifo_256_32 is 
    port( DATA : in std_logic_vector(31 downto 0); Q : out 
        std_logic_vector(31 downto 0);WE, RE, WCLOCK, RCLOCK : 
        in std_logic;  FULL, EMPTY : out std_logic;  RESET : in 
        std_logic) ;
end Em_Fifo_256_32;


architecture DEF_ARCH of  Em_Fifo_256_32 is

    component OR2
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component INV
        port(A : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component NAND2A
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component NAND2
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component AND2
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component FIFO4K18
        port(AEVAL11, AEVAL10, AEVAL9, AEVAL8, AEVAL7, AEVAL6, 
        AEVAL5, AEVAL4, AEVAL3, AEVAL2, AEVAL1, AEVAL0, AFVAL11, 
        AFVAL10, AFVAL9, AFVAL8, AFVAL7, AFVAL6, AFVAL5, AFVAL4, 
        AFVAL3, AFVAL2, AFVAL1, AFVAL0, WD17, WD16, WD15, WD14, 
        WD13, WD12, WD11, WD10, WD9, WD8, WD7, WD6, WD5, WD4, WD3, 
        WD2, WD1, WD0, WW0, WW1, WW2, RW0, RW1, RW2, RPIPE, WEN, 
        REN, WBLK, RBLK, WCLK, RCLK, RESET, ESTOP, FSTOP : in 
        std_logic := 'U'; RD17, RD16, RD15, RD14, RD13, RD12, 
        RD11, RD10, RD9, RD8, RD7, RD6, RD5, RD4, RD3, RD2, RD1, 
        RD0, FULL, AFULL, EMPTY, AEMPTY : out std_logic) ;
    end component;

    component VCC
        port( Y : out std_logic);
    end component;

    component GND
        port( Y : out std_logic);
    end component;

    signal FULL_1_net, EMPTY_1_net, WEAP, WRITE_FSTOP_ENABLE, 
        WRITE_ENABLE_I, READ_ESTOP_ENABLE, READ_ENABLE_I, 
        FULLX_I_0_net, EMPTYX_I_0_net, FULLX_I_1_net, 
        EMPTYX_I_1_net, VCC_1_net, GND_1_net : std_logic ;
    begin   

    FULL <= FULL_1_net;
    
    EMPTY <= EMPTY_1_net;
    
    VCC_2_net : VCC port map(Y => VCC_1_net);
    GND_2_net : GND port map(Y => GND_1_net);
    OR2_EMPTY : OR2
      port map(A => EMPTYX_I_0_net, B => EMPTYX_I_1_net, Y => 
        EMPTY_1_net);
    REBUBBLEA : INV
      port map(A => RE, Y => WEAP);
    WRITE_AND : NAND2A
      port map(A => WE, B => WRITE_FSTOP_ENABLE, Y => 
        WRITE_ENABLE_I);
    OR2_FULL : OR2
      port map(A => FULLX_I_0_net, B => FULLX_I_1_net, Y => 
        FULL_1_net);
    READ_ESTOP_GATE : NAND2
      port map(A => EMPTY_1_net, B => VCC_1_net, Y => 
        READ_ESTOP_ENABLE);
    WRITE_FSTOP_GATE : NAND2
      port map(A => FULL_1_net, B => VCC_1_net, Y => 
        WRITE_FSTOP_ENABLE);
    READ_AND : AND2
      port map(A => WEAP, B => READ_ESTOP_ENABLE, Y => 
        READ_ENABLE_I);
    FIFOBLOCK_0_inst : FIFO4K18
      port map(AEVAL11 => GND_1_net, AEVAL10 => GND_1_net, 
        AEVAL9 => GND_1_net, AEVAL8 => GND_1_net, AEVAL7 => 
        GND_1_net, AEVAL6 => GND_1_net, AEVAL5 => GND_1_net, 
        AEVAL4 => GND_1_net, AEVAL3 => GND_1_net, AEVAL2 => 
        GND_1_net, AEVAL1 => GND_1_net, AEVAL0 => GND_1_net, 
        AFVAL11 => GND_1_net, AFVAL10 => GND_1_net, AFVAL9 => 
        GND_1_net, AFVAL8 => GND_1_net, AFVAL7 => GND_1_net, 
        AFVAL6 => GND_1_net, AFVAL5 => GND_1_net, AFVAL4 => 
        GND_1_net, AFVAL3 => GND_1_net, AFVAL2 => GND_1_net, 
        AFVAL1 => GND_1_net, AFVAL0 => GND_1_net, WD17 => 
        DATA(17), WD16 => DATA(16), WD15 => DATA(15), WD14 => 
        DATA(14), WD13 => DATA(13), WD12 => DATA(12), WD11 => 
        DATA(11), WD10 => DATA(10), WD9 => DATA(9), WD8 => 
        DATA(8), WD7 => DATA(7), WD6 => DATA(6), WD5 => DATA(5), 
        WD4 => DATA(4), WD3 => DATA(3), WD2 => DATA(2), WD1 => 
        DATA(1), WD0 => DATA(0), WW0 => GND_1_net, WW1 => 
        GND_1_net, WW2 => VCC_1_net, RW0 => GND_1_net, RW1 => 
        GND_1_net, RW2 => VCC_1_net, RPIPE => GND_1_net, WEN => 
        WRITE_ENABLE_I, REN => READ_ENABLE_I, WBLK => GND_1_net, 
        RBLK => GND_1_net, WCLK => WCLOCK, RCLK => RCLOCK, 
        RESET => RESET, ESTOP => VCC_1_net, FSTOP => VCC_1_net, 
        RD17 => Q(17), RD16 => Q(16), RD15 => Q(15), RD14 => 
        Q(14), RD13 => Q(13), RD12 => Q(12), RD11 => Q(11), 
        RD10 => Q(10), RD9 => Q(9), RD8 => Q(8), RD7 => Q(7), 
        RD6 => Q(6), RD5 => Q(5), RD4 => Q(4), RD3 => Q(3), 
        RD2 => Q(2), RD1 => Q(1), RD0 => Q(0), FULL => 
        FULLX_I_0_net, AFULL => OPEN , EMPTY => EMPTYX_I_0_net, 
        AEMPTY => OPEN );
    FIFOBLOCK_1_inst : FIFO4K18
      port map(AEVAL11 => GND_1_net, AEVAL10 => GND_1_net, 
        AEVAL9 => GND_1_net, AEVAL8 => GND_1_net, AEVAL7 => 
        GND_1_net, AEVAL6 => GND_1_net, AEVAL5 => GND_1_net, 
        AEVAL4 => GND_1_net, AEVAL3 => GND_1_net, AEVAL2 => 
        GND_1_net, AEVAL1 => GND_1_net, AEVAL0 => GND_1_net, 
        AFVAL11 => GND_1_net, AFVAL10 => GND_1_net, AFVAL9 => 
        GND_1_net, AFVAL8 => GND_1_net, AFVAL7 => GND_1_net, 
        AFVAL6 => GND_1_net, AFVAL5 => GND_1_net, AFVAL4 => 
        GND_1_net, AFVAL3 => GND_1_net, AFVAL2 => GND_1_net, 
        AFVAL1 => GND_1_net, AFVAL0 => GND_1_net, WD17 => 
        GND_1_net, WD16 => GND_1_net, WD15 => GND_1_net, WD14 => 
        GND_1_net, WD13 => DATA(31), WD12 => DATA(30), WD11 => 
        DATA(29), WD10 => DATA(28), WD9 => DATA(27), WD8 => 
        DATA(26), WD7 => DATA(25), WD6 => DATA(24), WD5 => 
        DATA(23), WD4 => DATA(22), WD3 => DATA(21), WD2 => 
        DATA(20), WD1 => DATA(19), WD0 => DATA(18), WW0 => 
        GND_1_net, WW1 => GND_1_net, WW2 => VCC_1_net, RW0 => 
        GND_1_net, RW1 => GND_1_net, RW2 => VCC_1_net, RPIPE => 
        GND_1_net, WEN => WRITE_ENABLE_I, REN => READ_ENABLE_I, 
        WBLK => GND_1_net, RBLK => GND_1_net, WCLK => WCLOCK, 
        RCLK => RCLOCK, RESET => RESET, ESTOP => VCC_1_net, 
        FSTOP => VCC_1_net, RD17 => OPEN , RD16 => OPEN , RD15 => 
        OPEN , RD14 => OPEN , RD13 => Q(31), RD12 => Q(30), 
        RD11 => Q(29), RD10 => Q(28), RD9 => Q(27), RD8 => Q(26), 
        RD7 => Q(25), RD6 => Q(24), RD5 => Q(23), RD4 => Q(22), 
        RD3 => Q(21), RD2 => Q(20), RD1 => Q(19), RD0 => Q(18), 
        FULL => FULLX_I_1_net, AFULL => OPEN , EMPTY => 
        EMPTYX_I_1_net, AEMPTY => OPEN );
end DEF_ARCH;
