`

    #Build: Synplify Pro D-2009.12A, Build 040R, Jan 20 2010
    #install: \\idm\tools\releases\production\Libero\Libero_90\PC_9_0_0_19_SPB\Synopsys\synplify_D200912A
    #OS: Windows XP 5.1
    #Hostname: WXPL-MARISETTI1

    #Implementation: synthesis_1

    #Sun Jul 18 21:43:58 2010

    $ Running Identify Instrumentor. See log file:
    @N: : identify.log |
    #Sun Jul 18 21:43:58 2010

    $ Start of Compile
    #Sun Jul 18 21:44:03 2010

    Synopsys VHDL Compiler, version comp475rc, Build 060R, built Jan 15 2010
    Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved

    @N:CD720 : std.vhd(123) | Setting time resolution to ns
    Top entity isn't set yet!
    @W:CD645 : Fifo_1024.vhd(5) | Ignoring undefined library smartfusion
    @W:CD643 : Fifo_1024.vhd(6) | Ignoring use clause - smartfusion not found ...
    @W:CD645 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(5) | Ignoring undefined library smartfusion
    @W:CD643 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(6) | Ignoring use clause - smartfusion not found ...
    @W:CD645 : usb_mss.vhd(5) | Ignoring undefined library smartfusion
    @W:CD643 : usb_mss.vhd(6) | Ignoring use clause - smartfusion not found ...
    @W:CD645 : usb_slave.vhd(8) | Ignoring undefined library smartfusion
    @W:CD643 : usb_slave.vhd(9) | Ignoring use clause - smartfusion not found ...
    @W:CD645 : usbee_top_level.vhd(5) | Ignoring undefined library smartfusion
    @W:CD643 : usbee_top_level.vhd(6) | Ignoring use clause - smartfusion not found ...
    @I:: "\\idm\CAE\pavan m\USB\USBeee\Using_Fabric_Master\HW_USBee\synthesis\synthesis_1\instr_sources\syn_dics.vhd"
    VHDL syntax check successful!
    File \\idm\CAE\pavan m\USB\USBeee\Using_Fabric_Master\HW_USBee\synthesis\synthesis_1\instr_sources\.filemap changed - recompiling
    File \\idm\CAE\pavan m\USB\USBeee\Using_Fabric_Master\HW_USBee\synthesis\synthesis_1\instr_sources\smartgen\Fifo_1024\Fifo_1024.vhd changed - recompiling
    File \\idm\CAE\pavan m\USB\USBeee\Using_Fabric_Master\HW_USBee\synthesis\synthesis_1\instr_sources\hdl\usb_slave.vhd changed - recompiling
    File \\idm\CAE\pavan m\USB\USBeee\Using_Fabric_Master\HW_USBee\synthesis\synthesis_1\instr_sources\component\work\usbee_top_level\usbee_top_level.vhd changed - recompiling
    File \\idm\CAE\pavan m\USB\USBeee\Using_Fabric_Master\HW_USBee\synthesis\synthesis_1\instr_sources\syn_dics.vhd changed - recompiling
    @N:CD630 : usbee_top_level.vhd(8) | Synthesizing work.usbee_top_level.def_arch
    @W:CD280 : usbee_top_level.vhd(68) | Unbound component VCC mapped to black box
    @W:CD280 : usbee_top_level.vhd(155) | Unbound component GND mapped to black box
    @W:CD280 : usbee_top_level.vhd(160) | Unbound component CLKBUF mapped to black box
    @N:CD630 : syn_dics.vhd(1790) | Synthesizing work.iice_0.structure
    @N:CD630 : syn_dics.vhd(1275) | Synthesizing work.b7_ofwnt9s.b3_vfw
    @N:CD630 : syn_dics.vhd(968) | Synthesizing work.b12_ofwnt9_wmeed.b3_joc
    Post processing for work.b12_ofwnt9_wmeed.b3_joc
    @N:CD630 : syn_dics.vhd(1217) | Synthesizing work.ram_block.struct
    @N:CD630 : syn_dics.vhd(1178) | Synthesizing work.ramsliceram_block.struct
    @N:CD630 : syn_dics.vhd(1026) | Synthesizing work.genericramram_block.struct
    @N:CD630 : syn_dics.vhd(1037) | Synthesizing work.ram512x18.syn_black_box
    Post processing for work.ram512x18.syn_black_box
    Post processing for work.genericramram_block.struct
    Post processing for work.ramsliceram_block.struct
    Post processing for work.ram_block.struct
    Post processing for work.b7_ofwnt9s.b3_vfw
    @N:CD630 : syn_dics.vhd(1534) | Synthesizing work.b3_ukr.b3_vcj
    @N:CD630 : syn_dics.vhd(1438) | Synthesizing work.b7_plf_6ln.b3_vcj
    Post processing for work.b7_plf_6ln.b3_vcj
    @N:CD630 : syn_dics.vhd(1483) | Synthesizing work.b12_nvmfl_la1xyh.b3_vcj
    Post processing for work.b12_nvmfl_la1xyh.b3_vcj
    Post processing for work.b3_ukr.b3_vcj
    @N:CD630 : syn_dics.vhd(1634) | Synthesizing work.b3_12m.b6_oczobx
    @W:CD638 : syn_dics.vhd(1698) | Signal b11_nutz3qm_tkl is undriven
    @N:CD630 : syn_dics.vhd(565) | Synthesizing work.b7_pffzrny.b6_oczobx
    @N:CD630 : syn_dics.vhd(492) | Synthesizing work.b5_nvmfl.b6_oczobx
    Post processing for work.b5_nvmfl.b6_oczobx
    @N:CD630 : syn_dics.vhd(526) | Synthesizing work.b11_psyil9s1fkt.b3_joc
    @N:CD630 : syn_dics.vhd(412) | Synthesizing work.b8_1lbcqdr1.b3_joc
    Post processing for work.b8_1lbcqdr1.b3_joc
    Post processing for work.b11_psyil9s1fkt.b3_joc
    Post processing for work.b7_pffzrny.b6_oczobx
    @N:CD630 : syn_dics.vhd(751) | Synthesizing work.b7_ocbylxc.b3_joc
    @W:CD274 : syn_dics.vhd(867) | Incomplete case statement - add more cases or a when others
    @N:CD630 : syn_dics.vhd(662) | Synthesizing work.b8_nr_ymqrg.b3_joc
    Post processing for work.b8_nr_ymqrg.b3_joc
    Post processing for work.b7_ocbylxc.b3_joc
    Post processing for work.b3_12m.b6_oczobx
    Post processing for work.iice_0.structure
    @N:CD630 : syn_dics.vhd(1739) | Synthesizing work.ldic1_0.structure
    Post processing for work.ldic1_0.structure
    @N:CD630 : syn_dics.vhd(243) | Synthesizing work.comm_block.b3_joc
    @N:CD630 : syn_dics.vhd(5) | Synthesizing work.b9_orbiwxaef.b3_vcj
    Post processing for work.b9_orbiwxaef.b3_vcj
    @N:CD630 : syn_dics.vhd(192) | Synthesizing work.b16_rcmi_qlx9_yhpm7y.b3_vcj
    Post processing for work.b16_rcmi_qlx9_yhpm7y.b3_vcj
    @N:CD630 : syn_dics.vhd(70) | Synthesizing work.jtag_interface.b3_vcj
    @W:CD434 : syn_dics.vhd(159) | Signal identify_clk2_no_clk_buffer_needed in the sensitivity list is not used in the process
    @W:CD434 : syn_dics.vhd(170) | Signal identify_clk2_no_clk_buffer_needed in the sensitivity list is not used in the process
    @W:CD638 : syn_dics.vhd(94) | Signal b14_gir9p_al2ezh2v is undriven
    @N:CD630 : syn_dics.vhd(110) | Synthesizing work.ujtag.syn_black_box
    Post processing for work.ujtag.syn_black_box
    Post processing for work.jtag_interface.b3_vcj
    Post processing for work.comm_block.b3_joc
    @N:CD630 : usbee_top_level.vhd(160) | Synthesizing work.clkbuf.syn_black_box
    Post processing for work.clkbuf.syn_black_box
    @N:CD630 : usb_slave.vhd(11) | Synthesizing work.usb_slave.usb_slave
    @N:CD233 : usb_slave.vhd(39) | Using sequential encoding for type ahb_master_states
    @N:CD231 : usb_slave.vhd(38) | Using onehot encoding for type fifo_read_states (idle="1000000")
    @W:CD280 : usb_slave.vhd(60) | Unbound component BIBUF_LVCMOS33U mapped to black box
    @N:CD630 : syn_dics.vhd(1758) | Synthesizing work.ldic4_0.structure
    Post processing for work.ldic4_0.structure
    @N:CD630 : Fifo_1024.vhd(8) | Synthesizing work.fifo_1024.def_arch
    @W:CD280 : Fifo_1024.vhd(18) | Unbound component XNOR3 mapped to black box
    @W:CD280 : Fifo_1024.vhd(22) | Unbound component INV mapped to black box
    @W:CD280 : Fifo_1024.vhd(26) | Unbound component DFN1C0 mapped to black box
    @W:CD280 : Fifo_1024.vhd(31) | Unbound component NOR3 mapped to black box
    @W:CD280 : Fifo_1024.vhd(35) | Unbound component AND2 mapped to black box
    @W:CD280 : Fifo_1024.vhd(39) | Unbound component AND3 mapped to black box
    @W:CD280 : Fifo_1024.vhd(43) | Unbound component XOR2 mapped to black box
    @W:CD280 : Fifo_1024.vhd(47) | Unbound component XNOR2 mapped to black box
    @W:CD280 : Fifo_1024.vhd(51) | Unbound component AO1 mapped to black box
    @W:CD280 : Fifo_1024.vhd(55) | Unbound component XOR3 mapped to black box
    @W:CD280 : Fifo_1024.vhd(59) | Unbound component DFN1E1C0 mapped to black box
    @W:CD280 : Fifo_1024.vhd(64) | Unbound component OR2 mapped to black box
    @W:CD280 : Fifo_1024.vhd(68) | Unbound component MX2 mapped to black box
    @W:CD280 : Fifo_1024.vhd(72) | Unbound component BUFF mapped to black box
    @W:CD280 : Fifo_1024.vhd(76) | Unbound component AO1C mapped to black box
    @W:CD280 : Fifo_1024.vhd(80) | Unbound component RAM4K9 mapped to black box
    @N:CD630 : Fifo_1024.vhd(80) | Synthesizing work.ram4k9.syn_black_box
    Post processing for work.ram4k9.syn_black_box
    @W:CD280 : Fifo_1024.vhd(96) | Unbound component AND2A mapped to black box
    @W:CD280 : Fifo_1024.vhd(100) | Unbound component NOR3A mapped to black box
    @W:CD280 : Fifo_1024.vhd(104) | Unbound component OR2A mapped to black box
    @W:CD280 : Fifo_1024.vhd(108) | Unbound component NAND3A mapped to black box
    @W:CD280 : Fifo_1024.vhd(112) | Unbound component OA1C mapped to black box
    @W:CD280 : Fifo_1024.vhd(116) | Unbound component OR3 mapped to black box
    @W:CD280 : Fifo_1024.vhd(120) | Unbound component NAND2 mapped to black box
    @W:CD280 : Fifo_1024.vhd(124) | Unbound component OA1A mapped to black box
    @W:CD280 : Fifo_1024.vhd(128) | Unbound component AOI1 mapped to black box
    @W:CD280 : Fifo_1024.vhd(132) | Unbound component DFN1P0 mapped to black box
    @W:CD280 : Fifo_1024.vhd(137) | Unbound component NOR2A mapped to black box
    @W:CD280 : Fifo_1024.vhd(141) | Unbound component DFN1 mapped to black box
    @N:CD630 : syn_dics.vhd(1775) | Synthesizing work.ldic5_0.structure
    Post processing for work.ldic5_0.structure
    @N:CD630 : Fifo_1024.vhd(76) | Synthesizing work.ao1c.syn_black_box
    Post processing for work.ao1c.syn_black_box
    @N:CD630 : Fifo_1024.vhd(26) | Synthesizing work.dfn1c0.syn_black_box
    Post processing for work.dfn1c0.syn_black_box
    @N:CD630 : Fifo_1024.vhd(35) | Synthesizing work.and2.syn_black_box
    Post processing for work.and2.syn_black_box
    @N:CD630 : Fifo_1024.vhd(43) | Synthesizing work.xor2.syn_black_box
    Post processing for work.xor2.syn_black_box
    @N:CD630 : Fifo_1024.vhd(68) | Synthesizing work.mx2.syn_black_box
    Post processing for work.mx2.syn_black_box
    @N:CD630 : Fifo_1024.vhd(18) | Synthesizing work.xnor3.syn_black_box
    Post processing for work.xnor3.syn_black_box
    @N:CD630 : Fifo_1024.vhd(47) | Synthesizing work.xnor2.syn_black_box
    Post processing for work.xnor2.syn_black_box
    @N:CD630 : Fifo_1024.vhd(72) | Synthesizing work.buff.syn_black_box
    Post processing for work.buff.syn_black_box
    @N:CD630 : Fifo_1024.vhd(51) | Synthesizing work.ao1.syn_black_box
    Post processing for work.ao1.syn_black_box
    @N:CD630 : Fifo_1024.vhd(108) | Synthesizing work.nand3a.syn_black_box
    Post processing for work.nand3a.syn_black_box
    @N:CD630 : Fifo_1024.vhd(120) | Synthesizing work.nand2.syn_black_box
    Post processing for work.nand2.syn_black_box
    @N:CD630 : Fifo_1024.vhd(55) | Synthesizing work.xor3.syn_black_box
    Post processing for work.xor3.syn_black_box
    @N:CD630 : Fifo_1024.vhd(39) | Synthesizing work.and3.syn_black_box
    Post processing for work.and3.syn_black_box
    @N:CD630 : Fifo_1024.vhd(22) | Synthesizing work.inv.syn_black_box
    Post processing for work.inv.syn_black_box
    @N:CD630 : Fifo_1024.vhd(59) | Synthesizing work.dfn1e1c0.syn_black_box
    Post processing for work.dfn1e1c0.syn_black_box
    @N:CD630 : Fifo_1024.vhd(141) | Synthesizing work.dfn1.syn_black_box
    Post processing for work.dfn1.syn_black_box
    @N:CD630 : Fifo_1024.vhd(104) | Synthesizing work.or2a.syn_black_box
    Post processing for work.or2a.syn_black_box
    @N:CD630 : Fifo_1024.vhd(137) | Synthesizing work.nor2a.syn_black_box
    Post processing for work.nor2a.syn_black_box
    @N:CD630 : Fifo_1024.vhd(132) | Synthesizing work.dfn1p0.syn_black_box
    Post processing for work.dfn1p0.syn_black_box
    @N:CD630 : Fifo_1024.vhd(64) | Synthesizing work.or2.syn_black_box
    Post processing for work.or2.syn_black_box
    @N:CD630 : Fifo_1024.vhd(128) | Synthesizing work.aoi1.syn_black_box
    Post processing for work.aoi1.syn_black_box
    @N:CD630 : Fifo_1024.vhd(124) | Synthesizing work.oa1a.syn_black_box
    Post processing for work.oa1a.syn_black_box
    @N:CD630 : Fifo_1024.vhd(96) | Synthesizing work.and2a.syn_black_box
    Post processing for work.and2a.syn_black_box
    @N:CD630 : Fifo_1024.vhd(100) | Synthesizing work.nor3a.syn_black_box
    Post processing for work.nor3a.syn_black_box
    @N:CD630 : Fifo_1024.vhd(116) | Synthesizing work.or3.syn_black_box
    Post processing for work.or3.syn_black_box
    @N:CD630 : Fifo_1024.vhd(112) | Synthesizing work.oa1c.syn_black_box
    Post processing for work.oa1c.syn_black_box
    @N:CD630 : Fifo_1024.vhd(31) | Synthesizing work.nor3.syn_black_box
    Post processing for work.nor3.syn_black_box
    @N:CD630 : usbee_top_level.vhd(155) | Synthesizing work.gnd.syn_black_box
    Post processing for work.gnd.syn_black_box
    @N:CD630 : usbee_top_level.vhd(68) | Synthesizing work.vcc.syn_black_box
    Post processing for work.vcc.syn_black_box
    Post processing for work.fifo_1024.def_arch
    @W:CL168 : Fifo_1024.vhd(1833) | Pruning instance AND2_25 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1824) | Pruning instance MX2_1 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1784) | Pruning instance AND2_37 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1781) | Pruning instance XOR2_68 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1749) | Pruning instance AO1_37 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1717) | Pruning instance AO1_17 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1693) | Pruning instance AND2_53 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1580) | Pruning instance MX2_4 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1531) | Pruning instance DFN1_1 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1517) | Pruning instance AND2_45 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1515) | Pruning instance AND2_48 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1452) | Pruning instance AND2_77 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1429) | Pruning instance AND2_0 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1332) | Pruning instance AO1_26 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1263) | Pruning instance MX2_3 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1256) | Pruning instance AND2_27 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1234) | Pruning instance AND2_39 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1231) | Pruning instance DFN1C0_DVLDX - not in use ...
    @W:CL168 : Fifo_1024.vhd(1225) | Pruning instance MX2_7 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1200) | Pruning instance XOR2_65 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1195) | Pruning instance AND2_9 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1192) | Pruning instance MX2_6 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1152) | Pruning instance AND2_34 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1121) | Pruning instance AND2_52 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1072) | Pruning instance XOR2_79 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1054) | Pruning instance MX2_2 - not in use ...
    @W:CL168 : Fifo_1024.vhd(1034) | Pruning instance AND2_13 - not in use ...
    @W:CL168 : Fifo_1024.vhd(988) | Pruning instance AND2_47 - not in use ...
    @W:CL168 : Fifo_1024.vhd(986) | Pruning instance AND2_64 - not in use ...
    @W:CL168 : Fifo_1024.vhd(979) | Pruning instance AND2_51 - not in use ...
    @W:CL168 : Fifo_1024.vhd(939) | Pruning instance AND2_79 - not in use ...
    @W:CL168 : Fifo_1024.vhd(916) | Pruning instance MX2_0 - not in use ...
    @W:CL168 : Fifo_1024.vhd(880) | Pruning instance XOR2_9 - not in use ...
    @W:CL168 : Fifo_1024.vhd(878) | Pruning instance AND2_26 - not in use ...
    @W:CL168 : Fifo_1024.vhd(812) | Pruning instance AND2_30 - not in use ...
    @W:CL168 : Fifo_1024.vhd(810) | Pruning instance AND2_3 - not in use ...
    @W:CL168 : Fifo_1024.vhd(786) | Pruning instance AND2_35 - not in use ...
    @W:CL168 : Fifo_1024.vhd(717) | Pruning instance AND2_31 - not in use ...
    @W:CL168 : Fifo_1024.vhd(703) | Pruning instance AND2_24 - not in use ...
    @W:CL168 : Fifo_1024.vhd(679) | Pruning instance AO1_14 - not in use ...
    @W:CL168 : Fifo_1024.vhd(660) | Pruning instance AND2_62 - not in use ...
    @W:CL168 : Fifo_1024.vhd(654) | Pruning instance XOR2_57 - not in use ...
    @W:CL168 : Fifo_1024.vhd(619) | Pruning instance AND2_43 - not in use ...
    @W:CL168 : Fifo_1024.vhd(615) | Pruning instance AND2_68 - not in use ...
    @W:CL168 : Fifo_1024.vhd(556) | Pruning instance AND2_57 - not in use ...
    @W:CL168 : Fifo_1024.vhd(533) | Pruning instance MX2_5 - not in use ...
    @W:CL168 : Fifo_1024.vhd(528) | Pruning instance AND2_61 - not in use ...
    @W:CL168 : Fifo_1024.vhd(526) | Pruning instance AND2_72 - not in use ...
    @W:CL168 : Fifo_1024.vhd(409) | Pruning instance AND2_18 - not in use ...
    @W:CL168 : Fifo_1024.vhd(386) | Pruning instance XOR2_38 - not in use ...
    @W:CL168 : Fifo_1024.vhd(353) | Pruning instance AND2_44 - not in use ...
    @W:CL168 : Fifo_1024.vhd(345) | Pruning instance AND2_71 - not in use ...
    @W:CL168 : Fifo_1024.vhd(305) | Pruning instance AND2_2 - not in use ...
    @N:CD630 : usb_slave.vhd(60) | Synthesizing work.bibuf_lvcmos33u.syn_black_box
    Post processing for work.bibuf_lvcmos33u.syn_black_box
    Post processing for work.usb_slave.usb_slave
    @A: : usb_slave.vhd(226) | Feedback mux created for signal ahb_states[1:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area
    @W:CL190 : usb_slave.vhd(226) | Optimizing register bit HSIZE(0) to a constant 0
    @W:CL190 : usb_slave.vhd(226) | Optimizing register bit HTRANS(0) to a constant 0
    @W:CL260 : usb_slave.vhd(226) | Pruning Register bit 0 of HSIZE(1 downto 0)
    @W:CL260 : usb_slave.vhd(226) | Pruning Register bit 0 of HTRANS(1 downto 0)
    @N:CD630 : usb_mss.vhd(8) | Synthesizing work.usb_mss.def_arch
    @N:CD630 : mss_comps.vhd(24) | Synthesizing work.outbuf_mss.def_arch
    Post processing for work.outbuf_mss.def_arch
    @N:CD630 : mss_comps.vhd(4) | Synthesizing work.inbuf_mss.def_arch
    Post processing for work.inbuf_mss.def_arch
    @N:CD630 : mss_comps.vhd(65) | Synthesizing work.bibuf_mss.def_arch
    Post processing for work.bibuf_mss.def_arch
    @N:CD630 : mss_comps.vhd(87) | Synthesizing work.bibuf_opend_mss.def_arch
    Post processing for work.bibuf_opend_mss.def_arch
    @N:CD630 : mss_comps.vhd(44) | Synthesizing work.tribuff_mss.def_arch
    Post processing for work.tribuff_mss.def_arch
    @N:CD630 : mss_comps.vhd(182) | Synthesizing work.mss_ahb.def_arch
    Post processing for work.mss_ahb.def_arch
    @N:CD630 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(8) | Synthesizing work.usb_mss_tmp_mss_ccc_0_mss_ccc.def_arch
    @N:CD630 : mss_comps.vhd(906) | Synthesizing work.mss_xtlosc.def_arch
    Post processing for work.mss_xtlosc.def_arch
    @N:CD630 : mss_comps.vhd(926) | Synthesizing work.mss_ccc.def_arch
    Post processing for work.mss_ccc.def_arch
    Post processing for work.usb_mss_tmp_mss_ccc_0_mss_ccc.def_arch
    Post processing for work.usb_mss.def_arch
    Post processing for work.usbee_top_level.def_arch
    @W:CL168 : usbee_top_level.vhd(229) | Pruning instance 	VCC - not in use ...
    @W:CL159 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(10) | Input CLKA is unused
    @W:CL159 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(11) | Input CLKA_PAD is unused
    @W:CL159 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(12) | Input CLKA_PADP is unused
    @W:CL159 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(13) | Input CLKA_PADN is unused
    @W:CL159 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(15) | Input CLKC is unused
    @W:CL159 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(16) | Input CLKC_PAD is unused
    @W:CL159 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(17) | Input CLKC_PADP is unused
    @W:CL159 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(18) | Input CLKC_PADN is unused
    @W:CL159 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(19) | Input FB_CLK is unused
    @W:CL159 : usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd(20) | Input MAC_CLK is unused
    @N:CL201 : usb_slave.vhd(226) | Trying to extract state machine for register ahb_states
    @N:CL201 : usb_slave.vhd(149) | Trying to extract state machine for register data_states
    Extracted state machine for register data_states
    State machine has 7 reachable states with original encodings of:
       0000001
       0000010
       0000100
       0001000
       0010000
       0100000
       1000000
    @W:CL159 : usb_slave.vhd(26) | Input HRESP is unused
    @W:CL159 : usb_slave.vhd(27) | Input HRDATA is unused
    @N:CL201 : syn_dics.vhd(849) | Trying to extract state machine for register b13_nAzGfFM_sLsv3
    Extracted state machine for register b13_nAzGfFM_sLsv3
    State machine has 6 reachable states with original encodings of:
       0000
       0001
       0010
       0011
       0100
       1101
    @W:CL249 : syn_dics.vhd(849) | Initial value is not supported on state machine b13_nAzGfFM_sLsv3
    @W:CL247 : syn_dics.vhd(567) | Input port bit 0 of b9_slyy_nrgd(0 to 19) is unused
    @W:CL246 : syn_dics.vhd(567) | Input port bits 2 to 19 of b9_slyy_nrgd(0 to 19) are unused
    @END
    Process took 0h:00m:02s realtime, 0h:00m:01s cputime
    # Sun Jul 18 21:44:06 2010

    ###########################################################]
    Synopsys Actel Technology Mapper, Version map500act, Build 058R, Built Jan 18 2010 09:16:23
    Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved
    Product Version D-2009.12A
    @N:MF249 :  | Running in 32-bit mode.
    @N:MF258 :  | Gated clock conversion disabled

    Automatic dissolve during optimization of view:work.Fifo_1024(def_arch) of ldic5_inst_0(ldic5_0)
    Automatic dissolve during optimization of view:work.usb_slave(usb_slave) of ldic4_inst_0(ldic4_0)
    Automatic dissolve during optimization of view:work.ram_block(struct) of ramSliceInst1(ramSliceram_block)
    Automatic dissolve during optimization of view:work.ram_block(struct) of ramSliceInst0(ramSliceram_block)
    Automatic dissolve during optimization of view:work.usbee_top_level(def_arch) of ldic1_inst_0(ldic1_0)
    Automatic dissolve at startup in view:work.usb_mss(def_arch) of MSS_CCC_0(usb_mss_tmp_MSS_CCC_0_MSS_CCC)
    Automatic dissolve at startup in view:work.usb_slave(usb_slave) of FIFO_INST(Fifo_1024)
    @N:BN116 : fifo_1024.vhd(1206) | Removing sequential instance FIFO_INST.DFN1C0_AFULL of view:PA3.DFN1C0(prim) because there are no references to its outputs
    Automatic dissolve at startup in view:work.comm_block(b3_joc) of b9_ORb_xNywD(b9_ORbIwXaEF)
    Automatic dissolve at startup in view:work.comm_block(b3_joc) of b7_Rcmi_ql(b16_Rcmi_qlx9_yHpm7y)
    Automatic dissolve at startup in view:work.b7_OCByLXC(b3_joc) of b11_nUTGT_khWqH(b8_nR_ymqrG)
    Automatic dissolve at startup in view:work.b7_PfFzrNY(b6_oczobx) of b5_PbrtL(b5_nvmFL)
    Automatic dissolve at startup in view:work.ram_block(struct) of ramSliceInst1.GenericRAMInst0(GenericRAMram_block_ramSliceInst1_GenericRAMInst0)
    Automatic dissolve at startup in view:work.ram_block(struct) of ramSliceInst0.GenericRAMInst0(GenericRAMram_block)
    Automatic dissolve at startup in view:work.b7_OFWNT9s(b3_vfw) of b3_SoW(ram_block)
    Automatic dissolve at startup in view:work.usbee_top_level(def_arch) of usb_mss_0(usb_mss)
    @W:BN132 : usb_slave.vhd(226) | Removing sequential instance usb_slave_0.HSIZE_1[1],  because it is equivalent to instance usb_slave_0.HTRANS_1[1]
    @W:BN132 : usb_slave.vhd(226) | Removing sequential instance usb_slave_0.HWRITE,  because it is equivalent to instance usb_slave_0.HTRANS_1[1]
    @W:BN132 : usb_slave.vhd(226) | Removing sequential instance usb_slave_0.HSEL,  because it is equivalent to instance usb_slave_0.HTRANS_1[1]

    Available hyper_sources - for debug and ip models
    	None Found

    Finished RTL optimizations (Time elapsed 0h:00m:02s; Memory used current: 57MB peak: 58MB)

    @N: : usb_slave.vhd(272) | Found counter in view:work.usb_slave(usb_slave) inst INTRPT_COUNT[7:0]
    @N: : usb_slave.vhd(226) | Found counter in view:work.usb_slave(usb_slave) inst HADDR_TEMP[31:0]
    Encoding state machine work.usb_slave(usb_slave)-data_states[0:6]
    original code -> new code
       0000001 -> 0000001
       0000010 -> 0000010
       0000100 -> 0000100
       0001000 -> 0001000
       0010000 -> 0010000
       0100000 -> 0100000
       1000000 -> 1000000
    Encoding state machine work.b7_OCByLXC(b3_joc)-b13_nAzGfFM_sLsv3[0:5]
    original code -> new code
       0000 -> 000001
       0001 -> 000010
       0010 -> 000100
       0011 -> 001000
       0100 -> 010000
       1101 -> 100000
    @W:MO129 : syn_dics.vhd(823) | Sequential instance iice_inst_0.b7_12mFLWM.b5_nUTGT.b3_nfs[1] has been reduced to a combinational gate by constant propagation
    @N: : syn_dics.vhd(1388) | Found counter in view:work.b7_OFWNT9s(b3_vfw) inst b9_v_mzCDYXs[6:0]
    @N: : syn_dics.vhd(1368) | Found counter in view:work.b7_OFWNT9s(b3_vfw) inst b9_2_mzCDYXs[6:0]
    Finished factoring (Time elapsed 0h:00m:03s; Memory used current: 58MB peak: 59MB)

    Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:03s; Memory used current: 58MB peak: 59MB)

    Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:03s; Memory used current: 58MB peak: 59MB)

    Starting Early Timing Optimization (Time elapsed 0h:00m:03s; Memory used current: 59MB peak: 59MB)

    Finished Early Timing Optimization (Time elapsed 0h:00m:03s; Memory used current: 59MB peak: 59MB)

    Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:03s; Memory used current: 58MB peak: 59MB)

    Finished preparing to map (Time elapsed 0h:00m:04s; Memory used current: 60MB peak: 61MB)

    High Fanout Net Report
    **********************

    Driver Instance / Pin Name                              Fanout, notes
    ----------------------------------------------------------------------------------------
    comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[5] / Q        34
    comm_block_inst.b9_ORb_xNywD.un1_b3_orb9 / Y            32
    comm_block_inst.jtag_block.jtagi.b10_nv_ywKMm9X / Y     91
    usb_mss_0.MSS_CCC_0.I_MSSCCC / LOCK                     220 : 117 asynchronous set/reset
    usb_slave_0.ahb_states[0] / Q                           34
    usb_slave_0.ahb_states_0_sqmuxa_1_0_a3 / Y              34
    usb_slave_0.un1_data_states_1_0_a3 / Y                  34
    ========================================================================================

    @N:FP130 :  | Promoting Net b3_PK3 on CLKINT  jtag_block\.jtagi.b3_PK3_inferred_clock
    @N:FP130 :  | Promoting Net comm2iice_link_iice_0_a_0[7] on CLKINT  I_44
    Buffering FAB_CLK_c, fanout 178 segments 8
    Replicating Combinational Instance usb_slave_0.un1_data_states_1_0_a3, fanout 34 segments 2
    Replicating Combinational Instance usb_slave_0.ahb_states_0_sqmuxa_1_0_a3, fanout 34 segments 2
    Buffering usb_slave_0.FIFO_INST.WCLOCKP, fanout 47 segments 2
    Replicating Sequential Instance usb_slave_0.ahb_states[0], fanout 35 segments 2
    Finished technology mapping (Time elapsed 0h:00m:04s; Memory used current: 60MB peak: 61MB)

    Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:04s; Memory used current: 60MB peak: 61MB)

    Added 8 Buffers
    Added 3 Cells via replication
    	Added 1 Sequential Cells via replication
    	Added 2 Combinational Cells via replication

    Added 8 Buffers
    Added 3 Cells via replication
    	Added 1 Sequential Cells via replication
    	Added 2 Combinational Cells via replication

    Added 8 Buffers
    Added 3 Cells via replication
    	Added 1 Sequential Cells via replication
    	Added 2 Combinational Cells via replication

    Added 8 Buffers
    Added 3 Cells via replication
    	Added 1 Sequential Cells via replication
    	Added 2 Combinational Cells via replication
    Finished restoring hierarchy (Time elapsed 0h:00m:04s; Memory used current: 61MB peak: 61MB)

    Writing Analyst data base \\idm\CAE\pavan m\USB\USBeee\Using_Fabric_Master\HW_USBee\synthesis\synthesis_1\usbee_top_level.srm
    Finished Writing Netlist Databases (Time elapsed 0h:00m:05s; Memory used current: 60MB peak: 61MB)

    Writing EDIF Netlist and constraint files
    D-2009.12A
    Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:05s; Memory used current: 61MB peak: 62MB)

    @W:MT420 :  | Found inferred clock usbee_top_level|USB_CLK with period 1000.00ns. A user-defined clock should be declared on object "p:USB_CLK"

    @W:MT420 :  | Found inferred clock usbee_top_level|atck with period 1000.00ns. A user-defined clock should be declared on object "p:atck"

    @W:MT420 :  | Found inferred clock usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock with period 1000.00ns. A user-defined clock should be declared on object "n:FAB_CLK"

    @W:MT420 :  | Found inferred clock jtag_interface|b3_PK3_inferred_clock with period 1000.00ns. A user-defined clock should be declared on object "n:comm_block_inst.jtag_block.jtagi.b3_PK3"

    @W:MT420 :  | Found inferred clock jtag_interface|b7_oSD_3vW_inferred_clock with period 1000.00ns. A user-defined clock should be declared on object "n:comm_block_inst.jtag_block.jtagi.b7_oSD_3vW"

    @W:MT420 :  | Found inferred clock jtag_interface|identify_clk2_no_clk_buffer_needed with period 1000.00ns. A user-defined clock should be declared on object "n:comm_block_inst.jtag_block.jtagi.identify_clk2_no_clk_buffer_needed"

    @W:MT246 : usb_mss.vhd(1236) | Blackbox OUTBUF_MSS is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT246 : usb_mss.vhd(1231) | Blackbox INBUF_MSS is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT246 : usb_mss.vhd(1220) | Blackbox BIBUF_MSS is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT246 : usb_mss.vhd(1157) | Blackbox BIBUF_OPEND_MSS is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT246 : usb_mss.vhd(1087) | Blackbox TRIBUFF_MSS is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT246 : usb_mss.vhd(763) | Blackbox MSS_AHB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT246 : usb_mss_tmp_mss_ccc_0_mss_ccc.vhd(139) | Blackbox MSS_XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT246 : usb_mss_tmp_mss_ccc_0_mss_ccc.vhd(101) | Blackbox MSS_CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Sun Jul 18 21:44:33 2010
    #

    Top view:               usbee_top_level
    Library name:           PA3
    Operating conditions:   COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree )
    Requested Frequency:    1.0 MHz
    Wire load mode:         top
    Wire load model:        proasic3e
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report estimates place and route data. Please look at the place and route timing report for final timing..

    @N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock..

    Performance Summary
    *******************

    Worst slack in design: 975.928

                                                                   Requested     Estimated     Requested     Estimated                 Clock        Clock
    Starting Clock                                                 Frequency     Frequency     Period        Period        Slack       Type         Group
    -------------------------------------------------------------------------------------------------------------------------------------------------------------------
    jtag_interface|b3_PK3_inferred_clock                           1.0 MHz       107.8 MHz     1000.000      9.275         990.725     inferred     Inferred_clkgroup_4
    jtag_interface|b7_oSD_3vW_inferred_clock                       1.0 MHz       589.6 MHz     1000.000      1.696         998.304     inferred     Inferred_clkgroup_5
    jtag_interface|identify_clk2_no_clk_buffer_needed              1.0 MHz       139.8 MHz     1000.000      7.153         992.847     inferred     Inferred_clkgroup_1
    usbee_top_level|USB_CLK                                        1.0 MHz       60.7 MHz      1000.000      16.463        983.537     inferred     Inferred_clkgroup_3
    usbee_top_level|atck                                           1.0 MHz       85.7 MHz      1000.000      11.672        988.328     inferred     Inferred_clkgroup_2
    usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock     1.0 MHz       41.5 MHz      1000.000      24.072        975.928     inferred     Inferred_clkgroup_0
    System                                                         1.0 MHz       460.3 MHz     1000.000      2.173         997.827     system       default_clkgroup
    ===================================================================================================================================================================

    Clock Relationships
    *******************

    Clocks                                                                                                                  |    rise  to  rise     |    fall  to  fall     |    rise  to  fall   |    fall  to  rise
    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                                                    Ending                                                      |  constraint  slack    |  constraint  slack    |  constraint  slack  |  constraint  slack
    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock  usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock  |  1000.000    975.928  |  No paths    -        |  No paths    -      |  No paths    -
    usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock  usbee_top_level|USB_CLK                                     |  No paths    -        |  No paths    -        |  Diff grp    -      |  No paths    -
    usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock  jtag_interface|b3_PK3_inferred_clock                        |  Diff grp    -        |  No paths    -        |  No paths    -      |  No paths    -
    jtag_interface|identify_clk2_no_clk_buffer_needed           usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock  |  Diff grp    -        |  No paths    -        |  No paths    -      |  No paths    -
    jtag_interface|identify_clk2_no_clk_buffer_needed           jtag_interface|identify_clk2_no_clk_buffer_needed           |  1000.000    992.847  |  No paths    -        |  No paths    -      |  No paths    -
    jtag_interface|identify_clk2_no_clk_buffer_needed           usbee_top_level|atck                                        |  No paths    -        |  No paths    -        |  Diff grp    -      |  No paths    -
    jtag_interface|identify_clk2_no_clk_buffer_needed           jtag_interface|b3_PK3_inferred_clock                        |  Diff grp    -        |  No paths    -        |  No paths    -      |  No paths    -
    usbee_top_level|atck                                        jtag_interface|identify_clk2_no_clk_buffer_needed           |  No paths    -        |  No paths    -        |  No paths    -      |  Diff grp    -
    usbee_top_level|atck                                        usbee_top_level|atck                                        |  No paths    -        |  1000.000    988.328  |  No paths    -      |  No paths    -
    usbee_top_level|atck                                        jtag_interface|b3_PK3_inferred_clock                        |  No paths    -        |  No paths    -        |  No paths    -      |  Diff grp    -
    usbee_top_level|atck                                        jtag_interface|b7_oSD_3vW_inferred_clock                    |  No paths    -        |  No paths    -        |  No paths    -      |  Diff grp    -
    usbee_top_level|USB_CLK                                     usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock  |  No paths    -        |  No paths    -        |  No paths    -      |  Diff grp    -
    usbee_top_level|USB_CLK                                     usbee_top_level|USB_CLK                                     |  No paths    -        |  1000.000    983.537  |  No paths    -      |  No paths    -
    jtag_interface|b3_PK3_inferred_clock                        usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock  |  Diff grp    -        |  No paths    -        |  No paths    -      |  No paths    -
    jtag_interface|b3_PK3_inferred_clock                        jtag_interface|identify_clk2_no_clk_buffer_needed           |  Diff grp    -        |  No paths    -        |  No paths    -      |  No paths    -
    jtag_interface|b3_PK3_inferred_clock                        usbee_top_level|atck                                        |  No paths    -        |  No paths    -        |  Diff grp    -      |  No paths    -
    jtag_interface|b3_PK3_inferred_clock                        jtag_interface|b3_PK3_inferred_clock                        |  1000.000    990.725  |  No paths    -        |  No paths    -      |  No paths    -
    jtag_interface|b7_oSD_3vW_inferred_clock                    jtag_interface|identify_clk2_no_clk_buffer_needed           |  Diff grp    -        |  No paths    -        |  No paths    -      |  No paths    -
    jtag_interface|b7_oSD_3vW_inferred_clock                    usbee_top_level|atck                                        |  No paths    -        |  No paths    -        |  Diff grp    -      |  No paths    -
    jtag_interface|b7_oSD_3vW_inferred_clock                    jtag_interface|b7_oSD_3vW_inferred_clock                    |  1000.000    998.304  |  No paths    -        |  No paths    -      |  No paths    -
    ==================================================================================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    		No IO constraint found

    ====================================
    Detailed Report for Clock: jtag_interface|b3_PK3_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                                              Starting                                                                            Arrival
    Instance                                                                  Reference                                Type          Pin      Net                 Time        Slack
                                                                              Clock
    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    iice_inst_0.b3_SoW.b3_SoW.ramSliceInst0.GenericRAMInst0.syn_block_ram     jtag_interface|b3_PK3_inferred_clock     RAM512X18     RD13     b7_vFW_PlM[13]      2.963       990.725
    iice_inst_0.b3_SoW.b3_SoW.ramSliceInst0.GenericRAMInst0.syn_block_ram     jtag_interface|b3_PK3_inferred_clock     RAM512X18     RD12     b7_vFW_PlM[12]      2.963       991.025
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[0]                                        jtag_interface|b3_PK3_inferred_clock     DFN1E0        Q        b9_v_mzCDYXs[0]     0.737       991.131
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[1]                                        jtag_interface|b3_PK3_inferred_clock     DFN1E0        Q        b9_v_mzCDYXs[1]     0.737       991.133
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[2]                                        jtag_interface|b3_PK3_inferred_clock     DFN1E0        Q        b9_v_mzCDYXs[2]     0.737       991.194
    iice_inst_0.b3_SoW.b3_SoW.ramSliceInst0.GenericRAMInst0.syn_block_ram     jtag_interface|b3_PK3_inferred_clock     RAM512X18     RD10     b7_vFW_PlM[10]      2.963       991.486
    iice_inst_0.b3_SoW.b3_SoW.ramSliceInst1.GenericRAMInst0.syn_block_ram     jtag_interface|b3_PK3_inferred_clock     RAM512X18     RD0      b7_vFW_PlM[18]      2.963       991.585
    iice_inst_0.b3_SoW.b3_SoW.ramSliceInst0.GenericRAMInst0.syn_block_ram     jtag_interface|b3_PK3_inferred_clock     RAM512X18     RD11     b7_vFW_PlM[11]      2.963       991.585
    iice_inst_0.b3_SoW.b3_SoW.ramSliceInst0.GenericRAMInst0.syn_block_ram     jtag_interface|b3_PK3_inferred_clock     RAM512X18     RD0      b7_vFW_PlM[0]       2.963       991.627
    iice_inst_0.b3_SoW.b3_SoW.ramSliceInst0.GenericRAMInst0.syn_block_ram     jtag_interface|b3_PK3_inferred_clock     RAM512X18     RD1      b7_vFW_PlM[1]       2.963       991.726
    =================================================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                        Starting                                                                        Required
    Instance                                            Reference                                Type       Pin     Net                 Time         Slack
                                                        Clock
    --------------------------------------------------------------------------------------------------------------------------------------------------------
    iice_inst_0.b3_SoW.b11_OFWNT9_X1eH.b6_yor0PD[7]     jtag_interface|b3_PK3_inferred_clock     DFN1E0     D       b6_yor0PD_5[7]      999.427      990.725
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[0]                  jtag_interface|b3_PK3_inferred_clock     DFN1E0     D       b9_v_mzCDYXs_n0     999.461      991.131
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[1]                  jtag_interface|b3_PK3_inferred_clock     DFN1E0     D       N_114               999.461      991.131
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[2]                  jtag_interface|b3_PK3_inferred_clock     DFN1E0     D       N_115               999.461      991.131
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[3]                  jtag_interface|b3_PK3_inferred_clock     DFN1E0     D       N_116               999.461      991.131
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[4]                  jtag_interface|b3_PK3_inferred_clock     DFN1E0     D       N_117               999.461      991.131
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[5]                  jtag_interface|b3_PK3_inferred_clock     DFN1E0     D       N_118               999.461      991.131
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[6]                  jtag_interface|b3_PK3_inferred_clock     DFN1E0     D       N_119               999.427      993.021
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[0]                  jtag_interface|b3_PK3_inferred_clock     DFN1E0     E       N_126               999.566      994.645
    iice_inst_0.b3_SoW.b9_v_mzCDYXs[1]                  jtag_interface|b3_PK3_inferred_clock     DFN1E0     E       N_126               999.566      994.645
    ========================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      1000.000
        - Setup time:                            0.573
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         999.427

        - Propagation time:                      8.702
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 990.725

        Number of logic level(s):                6
        Starting point:                          iice_inst_0.b3_SoW.b3_SoW.ramSliceInst0.GenericRAMInst0.syn_block_ram / RD13
        Ending point:                            iice_inst_0.b3_SoW.b11_OFWNT9_X1eH.b6_yor0PD[7] / D
        The start point is clocked by            jtag_interface|b3_PK3_inferred_clock [rising] on pin RCLK
        The end   point is clocked by            jtag_interface|b3_PK3_inferred_clock [rising] on pin CLK

    Instance / Net                                                                          Pin      Pin               Arrival     No. of
    Name                                                                      Type          Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------------------
    iice_inst_0.b3_SoW.b3_SoW.ramSliceInst0.GenericRAMInst0.syn_block_ram     RAM512X18     RD13     Out     2.963     2.963       -
    b7_vFW_PlM[13]                                                            Net           -        -       0.322     -           1
    iice_inst_0.b3_SoW.b11_OFWNT9_X1eH.b5_nvmFL\.b6_yor0PD_5_RNO_23[7]        OR2B          A        In      -         3.285       -
    iice_inst_0.b3_SoW.b11_OFWNT9_X1eH.b5_nvmFL\.b6_yor0PD_5_RNO_23[7]        OR2B          Y        Out     0.514     3.799       -
    b7_O2yyf_F[13]                                                            Net           -        -       0.322     -           1
    iice_inst_0.b3_SoW.b11_OFWNT9_X1eH.b5_nvmFL\.b6_yor0PD_5_RNO_22[7]        AOI1B         C        In      -         4.121       -
    iice_inst_0.b3_SoW.b11_OFWNT9_X1eH.b5_nvmFL\.b6_yor0PD_5_RNO_22[7]        AOI1B         Y        Out     0.398     4.519       -
    un2_b7_o2yyf_e_6                                                          Net           -        -       0.322     -           1
    iice_inst_0.b3_SoW.b11_OFWNT9_X1eH.b5_nvmFL\.b6_yor0PD_5_RNO_11[7]        NOR3C         C        In      -         4.840       -
    iice_inst_0.b3_SoW.b11_OFWNT9_X1eH.b5_nvmFL\.b6_yor0PD_5_RNO_11[7]        NOR3C         Y        Out     0.666     5.506       -
    un2_b7_o2yyf_e_12                                                         Net           -        -       0.322     -           1
    iice_inst_0.b3_SoW.b11_OFWNT9_X1eH.b5_nvmFL\.b6_yor0PD_5_RNO_2[7]         NOR3C         C        In      -         5.827       -
    iice_inst_0.b3_SoW.b11_OFWNT9_X1eH.b5_nvmFL\.b6_yor0PD_5_RNO_2[7]         NOR3C         Y        Out     0.666     6.493       -
    un2_b7_o2yyf_e_15                                                         Net           -        -       0.322     -           1
    iice_inst_0.b3_SoW.b11_OFWNT9_X1eH.b5_nvmFL\.b6_yor0PD_5_RNO[7]           OR3C          C        In      -         6.814       -
    iice_inst_0.b3_SoW.b11_OFWNT9_X1eH.b5_nvmFL\.b6_yor0PD_5_RNO[7]           OR3C          Y        Out     0.666     7.480       -
    un2_b7_o2yyf_e                                                            Net           -        -       0.322     -           1
    iice_inst_0.b3_SoW.b11_OFWNT9_X1eH.b5_nvmFL\.b6_yor0PD_5[7]               MX2           A        In      -         7.801       -
    iice_inst_0.b3_SoW.b11_OFWNT9_X1eH.b5_nvmFL\.b6_yor0PD_5[7]               MX2           Y        Out     0.579     8.380       -
    b6_yor0PD_5[7]                                                            Net           -        -       0.322     -           1
    iice_inst_0.b3_SoW.b11_OFWNT9_X1eH.b6_yor0PD[7]                           DFN1E0        D        In      -         8.702       -
    =========================================================================================================================================
    Total path delay (propagation time + setup) of 9.275 is 7.025(75.7%) logic and 2.250(24.3%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: jtag_interface|b7_oSD_3vW_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                   Starting                                                                            Arrival
    Instance                                       Reference                                    Type       Pin     Net                 Time        Slack
                                                   Clock
    ------------------------------------------------------------------------------------------------------------------------------------------------------
    comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[1]     jtag_interface|b7_oSD_3vW_inferred_clock     DFN1E1     Q       b9_OvyH3_saL[1]     0.737       998.304
    comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[2]     jtag_interface|b7_oSD_3vW_inferred_clock     DFN1E1     Q       b9_OvyH3_saL[2]     0.737       998.304
    comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[3]     jtag_interface|b7_oSD_3vW_inferred_clock     DFN1E1     Q       b9_OvyH3_saL[3]     0.737       998.304
    comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[4]     jtag_interface|b7_oSD_3vW_inferred_clock     DFN1E1     Q       b9_OvyH3_saL[4]     0.737       998.304
    comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[5]     jtag_interface|b7_oSD_3vW_inferred_clock     DFN1E1     Q       b9_OvyH3_saL[5]     0.737       998.304
    ======================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                   Starting                                                                            Required
    Instance                                       Reference                                    Type       Pin     Net                 Time         Slack
                                                   Clock
    -------------------------------------------------------------------------------------------------------------------------------------------------------
    comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[0]     jtag_interface|b7_oSD_3vW_inferred_clock     DFN1E1     D       b9_OvyH3_saL[1]     999.427      998.304
    comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[1]     jtag_interface|b7_oSD_3vW_inferred_clock     DFN1E1     D       b9_OvyH3_saL[2]     999.427      998.304
    comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[2]     jtag_interface|b7_oSD_3vW_inferred_clock     DFN1E1     D       b9_OvyH3_saL[3]     999.427      998.304
    comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[3]     jtag_interface|b7_oSD_3vW_inferred_clock     DFN1E1     D       b9_OvyH3_saL[4]     999.427      998.304
    comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[4]     jtag_interface|b7_oSD_3vW_inferred_clock     DFN1E1     D       b9_OvyH3_saL[5]     999.427      998.304
    =======================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      1000.000
        - Setup time:                            0.573
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         999.427

        - Propagation time:                      1.123
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 998.304

        Number of logic level(s):                0
        Starting point:                          comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[1] / Q
        Ending point:                            comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[0] / D
        The start point is clocked by            jtag_interface|b7_oSD_3vW_inferred_clock [rising] on pin CLK
        The end   point is clocked by            jtag_interface|b7_oSD_3vW_inferred_clock [rising] on pin CLK

    Instance / Net                                            Pin      Pin               Arrival     No. of
    Name                                           Type       Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------
    comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[1]     DFN1E1     Q        Out     0.737     0.737       -
    b9_OvyH3_saL[1]                                Net        -        -       0.386     -           2
    comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[0]     DFN1E1     D        In      -         1.123       -
    ===========================================================================================================
    Total path delay (propagation time + setup) of 1.696 is 1.310(77.3%) logic and 0.386(22.7%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: jtag_interface|identify_clk2_no_clk_buffer_needed
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                     Starting                                                                                          Arrival
    Instance                                         Reference                                             Type       Pin     Net                      Time        Slack
                                                     Clock
    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------
    comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[0]     jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1E0     Q       b11_uRrc_WYOFjZ[0]       0.737       992.847
    comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[1]     jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1E0     Q       b13_nvmFL_fx2rbuQ[0]     0.737       993.517
    comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[2]     jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1E0     Q       b13_nvmFL_fx2rbuQ[1]     0.580       993.763
    comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[3]     jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1E0     Q       b13_nvmFL_fx2rbuQ[2]     0.580       993.914
    comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[4]     jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1E0     Q       b13_nvmFL_fx2rbuQ[3]     0.737       994.087
    ======================================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                                  Starting                                                                                         Required
    Instance                                                      Reference                                             Type       Pin     Net                     Time         Slack
                                                                  Clock
    -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b11_nUTGT_khWqH.b3_nUT[0]     jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1E1     E       b15_nYhI39swMeEd_Mg     999.392      992.847
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b11_nUTGT_khWqH.b3_nUT[1]     jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1E1     E       b15_nYhI39swMeEd_Mg     999.392      992.847
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b11_nUTGT_khWqH.b3_nUT[2]     jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1E1     E       b15_nYhI39swMeEd_Mg     999.392      992.847
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b11_nUTGT_khWqH.b3_nUT[3]     jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1E1     E       b15_nYhI39swMeEd_Mg     999.392      992.847
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b11_nUTGT_khWqH.b3_nUT[4]     jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1E1     E       b15_nYhI39swMeEd_Mg     999.392      992.847
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b11_nUTGT_khWqH.b3_nUT[5]     jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1E1     E       b15_nYhI39swMeEd_Mg     999.392      992.847
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b11_nUTGT_khWqH.b3_nUT[6]     jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1E1     E       b15_nYhI39swMeEd_Mg     999.392      992.847
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b11_nUTGT_khWqH.b3_nfs[0]     jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1E1     E       b12_nUTQBgfDb_bd        999.392      993.512
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b11_nUTGT_khWqH.b3_nfs[1]     jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1E1     E       b12_nUTQBgfDb_bd        999.392      993.512
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b11_nUTGT_khWqH.b3_nfs[2]     jtag_interface|identify_clk2_no_clk_buffer_needed     DFN1E1     E       b12_nUTQBgfDb_bd        999.392      993.512
    ===================================================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      1000.000
        - Setup time:                            0.608
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         999.392

        - Propagation time:                      6.545
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 992.847

        Number of logic level(s):                3
        Starting point:                          comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[0] / Q
        Ending point:                            iice_inst_0.b7_12mFLWM.b5_nUTGT.b11_nUTGT_khWqH.b3_nUT[0] / E
        The start point is clocked by            jtag_interface|identify_clk2_no_clk_buffer_needed [rising] on pin CLK
        The end   point is clocked by            jtag_interface|identify_clk2_no_clk_buffer_needed [rising] on pin CLK

    Instance / Net                                                            Pin      Pin               Arrival     No. of
    Name                                                           Type       Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------------------------
    comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[0]                   DFN1E0     Q        Out     0.737     0.737       -
    b11_uRrc_WYOFjZ[0]                                             Net        -        -       0.322     -           1
    comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3_RNI37HR[0]           NOR2B      A        In      -         1.058       -
    comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3_RNI37HR[0]           NOR2B      Y        Out     0.514     1.573       -
    b11_uRrc_9urXBb[0]                                             Net        -        -       1.279     -           5
    iice_inst_0.b8_uKr_IFLY.b10_nvscB_rGsL.b9_nvmFLz_ab_0_a2_0     NOR3A      A        In      -         2.852       -
    iice_inst_0.b8_uKr_IFLY.b10_nvscB_rGsL.b9_nvmFLz_ab_0_a2_0     NOR3A      Y        Out     0.641     3.493       -
    N_26                                                           Net        -        -       0.806     -           3
    iice_inst_0.b8_uKr_IFLY.b10_nvscB_rGsL.b9_nvmFLP_ab0_0_a2      NOR3B      B        In      -         4.300       -
    iice_inst_0.b8_uKr_IFLY.b10_nvscB_rGsL.b9_nvmFLP_ab0_0_a2      NOR3B      Y        Out     0.607     4.906       -
    b15_nYhI39swMeEd_Mg                                            Net        -        -       1.639     -           8
    iice_inst_0.b7_12mFLWM.b5_nUTGT.b11_nUTGT_khWqH.b3_nUT[0]      DFN1E1     E        In      -         6.545       -
    ===========================================================================================================================
    Total path delay (propagation time + setup) of 7.153 is 3.107(43.4%) logic and 4.046(56.6%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: usbee_top_level|USB_CLK
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                      Starting                                                           Arrival
    Instance                                          Reference                   Type       Pin     Net                 Time        Slack
                                                      Clock
    ----------------------------------------------------------------------------------------------------------------------------------------
    usb_slave_0.FIFO_INST.DFN1C0_FULL                 usbee_top_level|USB_CLK     DFN1C0     Q       FIFO_FULL           0.580       983.537
    usb_slave_0.FIFO_INST.DFN1C0_MEM_WADDR_1_inst     usbee_top_level|USB_CLK     DFN1C0     Q       MEM_WADDR_1_net     0.737       984.696
    usb_slave_0.FIFO_INST.DFN1C0_MEM_WADDR_0_inst     usbee_top_level|USB_CLK     DFN1C0     Q       MEM_WADDR_0_net     0.737       984.762
    usb_slave_0.FIFO_INST.DFN1C0_MEM_WADDR_2_inst     usbee_top_level|USB_CLK     DFN1C0     Q       MEM_WADDR_2_net     0.737       985.117
    usb_slave_0.FIFO_INST.DFN1C0_MEM_WADDR_3_inst     usbee_top_level|USB_CLK     DFN1C0     Q       MEM_WADDR_3_net     0.737       985.146
    usb_slave_0.FIFO_INST.DFN1C0_MEM_WADDR_4_inst     usbee_top_level|USB_CLK     DFN1C0     Q       MEM_WADDR_4_net     0.737       986.372
    usb_slave_0.FIFO_INST.DFN1C0_MEM_WADDR_5_inst     usbee_top_level|USB_CLK     DFN1C0     Q       MEM_WADDR_5_net     0.737       986.401
    usb_slave_0.FIFO_INST.DFN1C0_MEM_WADDR_6_inst     usbee_top_level|USB_CLK     DFN1C0     Q       MEM_WADDR_6_net     0.737       986.401
    usb_slave_0.FIFO_INST.DFN1C0_MEM_WADDR_7_inst     usbee_top_level|USB_CLK     DFN1C0     Q       MEM_WADDR_7_net     0.737       986.431
    usb_slave_0.FIFO_INST.DFN1C0_RGRYSYNC_8_inst      usbee_top_level|USB_CLK     DFN1C0     Q       RGRYSYNC_8_net      0.737       988.914
    ========================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                       Starting                                                               Required
    Instance                                           Reference                   Type       Pin     Net                     Time         Slack
                                                       Clock
    ----------------------------------------------------------------------------------------------------------------------------------------------
    usb_slave_0.FIFO_INST.DFN1C0_FULL                  usbee_top_level|USB_CLK     DFN1C0     D       FULLINT                 999.461      983.537
    usb_slave_0.FIFO_INST.DFN1C0_WGRY_8_inst           usbee_top_level|USB_CLK     DFN1C0     D       XOR2_52_Y               999.461      986.528
    usb_slave_0.FIFO_INST.DFN1C0_WGRY_9_inst           usbee_top_level|USB_CLK     DFN1C0     D       XOR2_15_Y               999.461      986.528
    usb_slave_0.FIFO_INST.DFN1C0_WGRY_6_inst           usbee_top_level|USB_CLK     DFN1C0     D       XOR2_41_Y               999.461      986.949
    usb_slave_0.FIFO_INST.DFN1C0_WGRY_10_inst          usbee_top_level|USB_CLK     DFN1C0     D       XOR2_44_Y               999.461      986.976
    usb_slave_0.FIFO_INST.DFN1C0_WGRY_7_inst           usbee_top_level|USB_CLK     DFN1C0     D       XOR2_50_Y               999.461      987.397
    usb_slave_0.FIFO_INST.DFN1C0_MEM_WADDR_9_inst      usbee_top_level|USB_CLK     DFN1C0     D       WBINNXTSHIFT_9_net      999.461      987.786
    usb_slave_0.FIFO_INST.DFN1C0_MEM_WADDR_10_inst     usbee_top_level|USB_CLK     DFN1C0     D       WBINNXTSHIFT_10_net     999.461      987.786
    usb_slave_0.FIFO_INST.DFN1C0_WGRY_5_inst           usbee_top_level|USB_CLK     DFN1C0     D       XOR2_29_Y               999.461      987.868
    usb_slave_0.FIFO_INST.DFN1C0_WGRY_4_inst           usbee_top_level|USB_CLK     DFN1C0     D       XOR2_53_Y               999.461      987.932
    ==============================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      1000.000
        - Setup time:                            0.539
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         999.461

        - Propagation time:                      15.924
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 983.537

        Number of logic level(s):                13
        Starting point:                          usb_slave_0.FIFO_INST.DFN1C0_FULL / Q
        Ending point:                            usb_slave_0.FIFO_INST.DFN1C0_FULL / D
        The start point is clocked by            usbee_top_level|USB_CLK [falling] on pin CLK
        The end   point is clocked by            usbee_top_level|USB_CLK [falling] on pin CLK

    Instance / Net                                                Pin      Pin               Arrival     No. of
    Name                                               Type       Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------------
    usb_slave_0.FIFO_INST.DFN1C0_FULL                  DFN1C0     Q        Out     0.580     0.580       -
    FIFO_FULL                                          Net        -        -       0.322     -           1
    usb_slave_0.FIFO_INST.NAND2_0                      NAND2      A        In      -         0.902       -
    usb_slave_0.FIFO_INST.NAND2_0                      NAND2      Y        Out     0.488     1.390       -
    NAND2_0_Y                                          Net        -        -       0.322     -           1
    usb_slave_0.FIFO_INST.AND2_MEMORYWE                AND2       A        In      -         1.712       -
    usb_slave_0.FIFO_INST.AND2_MEMORYWE                AND2       Y        Out     0.514     2.226       -
    MEMORYWE                                           Net        -        -       0.806     -           3
    usb_slave_0.FIFO_INST.AND2_32                      AND2       B        In      -         3.033       -
    usb_slave_0.FIFO_INST.AND2_32                      AND2       Y        Out     0.627     3.660       -
    AND2_32_Y                                          Net        -        -       0.386     -           2
    usb_slave_0.FIFO_INST.AO1_1                        AO1        B        In      -         4.046       -
    usb_slave_0.FIFO_INST.AO1_1                        AO1        Y        Out     0.598     4.644       -
    AO1_1_Y                                            Net        -        -       0.806     -           3
    usb_slave_0.FIFO_INST.AO1_44                       AO1        B        In      -         5.450       -
    usb_slave_0.FIFO_INST.AO1_44                       AO1        Y        Out     0.598     6.048       -
    AO1_44_Y                                           Net        -        -       1.184     -           4
    usb_slave_0.FIFO_INST.AO1_36                       AO1        B        In      -         7.231       -
    usb_slave_0.FIFO_INST.AO1_36                       AO1        Y        Out     0.598     7.829       -
    AO1_36_Y                                           Net        -        -       0.386     -           2
    usb_slave_0.FIFO_INST.AO1_18                       AO1        B        In      -         8.215       -
    usb_slave_0.FIFO_INST.AO1_18                       AO1        Y        Out     0.598     8.813       -
    AO1_18_Y                                           Net        -        -       0.322     -           1
    usb_slave_0.FIFO_INST.XOR2_WBINNXTSHIFT_7_inst     XOR2       B        In      -         9.134       -
    usb_slave_0.FIFO_INST.XOR2_WBINNXTSHIFT_7_inst     XOR2       Y        Out     0.937     10.071      -
    WBINNXTSHIFT_7_net                                 Net        -        -       1.184     -           4
    usb_slave_0.FIFO_INST.XNOR2_9                      XNOR2      B        In      -         11.255      -
    usb_slave_0.FIFO_INST.XNOR2_9                      XNOR2      Y        Out     0.937     12.191      -
    XNOR2_9_Y                                          Net        -        -       0.322     -           1
    usb_slave_0.FIFO_INST.AND3_3                       AND3       B        In      -         12.513      -
    usb_slave_0.FIFO_INST.AND3_3                       AND3       Y        Out     0.624     13.137      -
    AND3_3_Y                                           Net        -        -       0.322     -           1
    usb_slave_0.FIFO_INST.AND3_1                       AND3       A        In      -         13.458      -
    usb_slave_0.FIFO_INST.AND3_1                       AND3       Y        Out     0.525     13.983      -
    AND3_1_Y                                           Net        -        -       0.322     -           1
    usb_slave_0.FIFO_INST.AND2_22                      AND2       A        In      -         14.304      -
    usb_slave_0.FIFO_INST.AND2_22                      AND2       Y        Out     0.488     14.793      -
    AND2_22_Y                                          Net        -        -       0.322     -           1
    usb_slave_0.FIFO_INST.AND2_FULLINT                 AND2       A        In      -         15.114      -
    usb_slave_0.FIFO_INST.AND2_FULLINT                 AND2       Y        Out     0.488     15.602      -
    FULLINT                                            Net        -        -       0.322     -           1
    usb_slave_0.FIFO_INST.DFN1C0_FULL                  DFN1C0     D        In      -         15.924      -
    ===============================================================================================================
    Total path delay (propagation time + setup) of 16.463 is 9.139(55.5%) logic and 7.324(44.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: usbee_top_level|atck
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                      Starting                                                       Arrival
    Instance                                          Reference                Type      Pin        Net              Time        Slack
                                                      Clock
    ------------------------------------------------------------------------------------------------------------------------------------
    comm_block_inst.jtag_block\.jtagi.b9_Rcmi_KsDw    usbee_top_level|atck     UJTAG     UIREG3     b6_uS_MrX[2]     2.211       988.328
    comm_block_inst.jtag_block\.jtagi.b9_Rcmi_KsDw    usbee_top_level|atck     UJTAG     UIREG4     b6_uS_MrX[3]     2.211       988.467
    comm_block_inst.jtag_block\.jtagi.b9_Rcmi_KsDw    usbee_top_level|atck     UJTAG     UIREG2     b6_uS_MrX[1]     2.211       988.526
    comm_block_inst.jtag_block\.jtagi.b9_Rcmi_KsDw    usbee_top_level|atck     UJTAG     UIREG1     b6_uS_MrX[0]     1.960       988.667
    comm_block_inst.jtag_block\.jtagi.b9_Rcmi_KsDw    usbee_top_level|atck     UJTAG     UIREG5     b6_uS_MrX[4]     2.211       988.667
    comm_block_inst.jtag_block\.jtagi.b9_Rcmi_KsDw    usbee_top_level|atck     UJTAG     UIREG6     b3_1Um           1.960       988.808
    ====================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                      Starting                                                  Required
    Instance                                          Reference                Type      Pin      Net           Time         Slack
                                                      Clock
    --------------------------------------------------------------------------------------------------------------------------------
    comm_block_inst.jtag_block\.jtagi.b9_Rcmi_KsDw    usbee_top_level|atck     UJTAG     UTDO     b6_PLF_Bq     998.279      988.328
    ================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      1000.000
        - Setup time:                            1.721
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         998.279

        - Propagation time:                      9.951
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 988.328

        Number of logic level(s):                6
        Starting point:                          comm_block_inst.jtag_block\.jtagi.b9_Rcmi_KsDw / UIREG3
        Ending point:                            comm_block_inst.jtag_block\.jtagi.b9_Rcmi_KsDw / UTDO
        The start point is clocked by            usbee_top_level|atck [falling] on pin TCK
        The end   point is clocked by            usbee_top_level|atck [falling] on pin TCK

    Instance / Net                                                        Pin        Pin               Arrival     No. of
    Name                                                        Type      Name       Dir     Delay     Time        Fan Out(s)
    -------------------------------------------------------------------------------------------------------------------------
    comm_block_inst.jtag_block\.jtagi.b9_Rcmi_KsDw              UJTAG     UIREG3     Out     2.211     2.211       -
    b6_uS_MrX[2]                                                Net       -          -       0.322     -           1
    comm_block_inst.jtag_block\.jtagi.b9_Rcmi_KsDw_RNISNG8      NOR2      B          In      -         2.532       -
    comm_block_inst.jtag_block\.jtagi.b9_Rcmi_KsDw_RNISNG8      NOR2      Y          Out     0.646     3.179       -
    b9_nv_cLqgOF_2                                              Net       -          -       0.386     -           2
    comm_block_inst.jtag_block\.jtagi.b9_Rcmi_KsDw_RNIK7IP_0    NOR3C     B          In      -         3.564       -
    comm_block_inst.jtag_block\.jtagi.b9_Rcmi_KsDw_RNIK7IP_0    NOR3C     Y          Out     0.624     4.188       -
    b9_nv_cLqgOF                                                Net       -          -       1.184     -           4
    comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3_RNI37HR[0]        NOR2B     B          In      -         5.372       -
    comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3_RNI37HR[0]        NOR2B     Y          Out     0.516     5.888       -
    b11_uRrc_9urXBb[0]                                          Net       -          -       1.279     -           5
    iice_inst_0.b8_uKr_IFLY.b11_uRrc_9urXBb_RNIJRAG2            NOR3C     C          In      -         7.167       -
    iice_inst_0.b8_uKr_IFLY.b11_uRrc_9urXBb_RNIJRAG2            NOR3C     Y          Out     0.666     7.833       -
    b3_PLF                                                      Net       -          -       0.322     -           1
    comm_block_inst.tdo_sig_RNISCN3                             MX2       A          In      -         8.154       -
    comm_block_inst.tdo_sig_RNISCN3                             MX2       Y          Out     0.568     8.723       -
    b9_PLF_TJkrj                                                Net       -          -       0.322     -           1
    comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL_RNI7MHV[0]          MX2       B          In      -         9.044       -
    comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL_RNI7MHV[0]          MX2       Y          Out     0.586     9.630       -
    b6_PLF_Bq                                                   Net       -          -       0.322     -           1
    comm_block_inst.jtag_block\.jtagi.b9_Rcmi_KsDw              UJTAG     UTDO       In      -         9.951       -
    =========================================================================================================================
    Total path delay (propagation time + setup) of 11.672 is 7.537(64.6%) logic and 4.135(35.4%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                  Starting                                                                                                         Arrival
    Instance                      Reference                                                      Type         Pin     Net                          Time        Slack
                                  Clock
    ------------------------------------------------------------------------------------------------------------------------------------------------------------------
    usb_slave_0.HADDR_TEMP[1]     usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock     DFN1E1C0     Q       Z\\usb_slave_0_HADDR_\[1\]\\ 0.580       975.928
    usb_slave_0.HADDR_TEMP[0]     usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock     DFN1C0       Q       Z\\usb_slave_0_HADDR_\[0\]\\ 0.580       975.932
    usb_slave_0.HADDR_TEMP[2]     usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock     DFN1E1C0     Q       Z\\usb_slave_0_HADDR_\[2\]\\ 0.580       976.264
    usb_slave_0.HADDR_TEMP[3]     usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock     DFN1E1C0     Q       Z\\usb_slave_0_HADDR_\[3\]\\ 0.580       977.458
    usb_slave_0.HADDR_TEMP[4]     usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock     DFN1E1C0     Q       Z\\usb_slave_0_HADDR_\[4\]\\ 0.580       977.694
    usb_slave_0.HADDR_TEMP[5]     usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock     DFN1E1C0     Q       Z\\usb_slave_0_HADDR_\[5\]\\ 0.580       978.888
    usb_slave_0.HADDR_TEMP[6]     usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock     DFN1E1C0     Q       Z\\usb_slave_0_HADDR_\[6\]\\ 0.580       979.124
    usb_slave_0.HADDR_TEMP[7]     usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock     DFN1E1C0     Q       Z\\usb_slave_0_HADDR_\[7\]\\ 0.580       980.318
    usb_slave_0.HADDR_TEMP[8]     usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock     DFN1E1C0     Q       Z\\usb_slave_0_HADDR_\[8\]\\ 0.580       980.555
    usb_slave_0.HADDR_TEMP[9]     usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock     DFN1E1C0     Q       Z\\usb_slave_0_HADDR_\[9\]\\ 0.580       981.749
    ==================================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                   Starting                                                                                               Required
    Instance                       Reference                                                      Type         Pin     Net                Time         Slack
                                   Clock
    ----------------------------------------------------------------------------------------------------------------------------------------------------------
    usb_slave_0.HADDR_TEMP[31]     usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock     DFN1E1C0     D       HADDR_TEMP_n31     999.461      975.928
    usb_slave_0.HADDR_TEMP[30]     usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock     DFN1E1P0     D       HADDR_TEMP_n30     999.427      976.455
    usb_slave_0.HADDR_TEMP[29]     usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock     DFN1E1P0     D       HADDR_TEMP_n29     999.427      977.329
    usb_slave_0.HADDR_TEMP[28]     usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock     DFN1E1P0     D       HADDR_TEMP_n28     999.531      977.882
    usb_slave_0.HADDR_TEMP[27]     usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock     DFN1E1C0     D       HADDR_TEMP_n27     999.461      978.294
    usb_slave_0.HADDR_TEMP[26]     usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock     DFN1E1C0     D       HADDR_TEMP_n26     999.461      979.242
    usb_slave_0.HADDR_TEMP[25]     usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock     DFN1E1C0     D       HADDR_TEMP_n25     999.461      979.724
    usb_slave_0.HADDR_TEMP[24]     usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock     DFN1E1C0     D       HADDR_TEMP_n24     999.461      980.673
    usb_slave_0.HADDR_TEMP[23]     usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock     DFN1E1C0     D       HADDR_TEMP_n23     999.461      981.154
    usb_slave_0.HADDR_TEMP[22]     usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock     DFN1E1C0     D       HADDR_TEMP_n22     999.461      982.103
    ==========================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      1000.000
        - Setup time:                            0.539
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         999.461

        - Propagation time:                      23.533
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     975.928

        Number of logic level(s):                16
        Starting point:                          usb_slave_0.HADDR_TEMP[1] / Q
        Ending point:                            usb_slave_0.HADDR_TEMP[31] / D
        The start point is clocked by            usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock [rising] on pin CLK
        The end   point is clocked by            usbee_top_level|usb_mss_0.MSS_CCC_0.FAB_CLK_inferred_clock [rising] on pin CLK

    Instance / Net                                       Pin      Pin               Arrival     No. of
    Name                                    Type         Name     Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------------------
    usb_slave_0.HADDR_TEMP[1]               DFN1E1C0     Q        Out     0.580     0.580       -
    Z\\usb_slave_0_HADDR_\[1\]\\            Net          -        -       1.184     -           4
    usb_slave_0.HADDR_TEMP_RNIASPM[2]       NOR3C        B        In      -         1.764       -
    usb_slave_0.HADDR_TEMP_RNIASPM[2]       NOR3C        Y        Out     0.624     2.388       -
    HADDR_TEMP_c2                           Net          -        -       0.806     -           3
    usb_slave_0.HADDR_TEMP_RNIBF061[4]      NOR3C        B        In      -         3.194       -
    usb_slave_0.HADDR_TEMP_RNIBF061[4]      NOR3C        Y        Out     0.624     3.818       -
    HADDR_TEMP_c4                           Net          -        -       0.806     -           3
    usb_slave_0.HADDR_TEMP_RNIG27L1[6]      NOR3C        B        In      -         4.625       -
    usb_slave_0.HADDR_TEMP_RNIG27L1[6]      NOR3C        Y        Out     0.624     5.248       -
    HADDR_TEMP_c6                           Net          -        -       0.806     -           3
    usb_slave_0.HADDR_TEMP_RNIPLD42[8]      NOR3C        B        In      -         6.055       -
    usb_slave_0.HADDR_TEMP_RNIPLD42[8]      NOR3C        Y        Out     0.624     6.679       -
    HADDR_TEMP_c8                           Net          -        -       0.806     -           3
    usb_slave_0.HADDR_TEMP_RNID2NH2[10]     NOR3C        B        In      -         7.485       -
    usb_slave_0.HADDR_TEMP_RNID2NH2[10]     NOR3C        Y        Out     0.624     8.109       -
    HADDR_TEMP_c10                          Net          -        -       0.806     -           3
    usb_slave_0.HADDR_TEMP_RNICK3T2[12]     NOR3C        B        In      -         8.915       -
    usb_slave_0.HADDR_TEMP_RNICK3T2[12]     NOR3C        Y        Out     0.624     9.539       -
    HADDR_TEMP_c12                          Net          -        -       0.806     -           3
    usb_slave_0.HADDR_TEMP_RNIFMG83[14]     NOR3C        B        In      -         10.346      -
    usb_slave_0.HADDR_TEMP_RNIFMG83[14]     NOR3C        Y        Out     0.624     10.970      -
    HADDR_TEMP_c14                          Net          -        -       0.806     -           3
    usb_slave_0.HADDR_TEMP_RNIM8UJ3[16]     NOR3C        B        In      -         11.776      -
    usb_slave_0.HADDR_TEMP_RNIM8UJ3[16]     NOR3C        Y        Out     0.624     12.400      -
    HADDR_TEMP_c16                          Net          -        -       0.806     -           3
    usb_slave_0.HADDR_TEMP_RNI1BCV3[18]     NOR3C        B        In      -         13.206      -
    usb_slave_0.HADDR_TEMP_RNI1BCV3[18]     NOR3C        Y        Out     0.624     13.830      -
    HADDR_TEMP_c18                          Net          -        -       0.806     -           3
    usb_slave_0.HADDR_TEMP_RNI7LPA4[20]     NOR3C        B        In      -         14.637      -
    usb_slave_0.HADDR_TEMP_RNI7LPA4[20]     NOR3C        Y        Out     0.624     15.261      -
    HADDR_TEMP_c20                          Net          -        -       0.806     -           3
    usb_slave_0.HADDR_TEMP_RNI876M4[22]     NOR3C        B        In      -         16.067      -
    usb_slave_0.HADDR_TEMP_RNI876M4[22]     NOR3C        Y        Out     0.624     16.691      -
    HADDR_TEMP_c22                          Net          -        -       0.806     -           3
    usb_slave_0.HADDR_TEMP_RNID9J15[24]     NOR3C        B        In      -         17.497      -
    usb_slave_0.HADDR_TEMP_RNID9J15[24]     NOR3C        Y        Out     0.624     18.121      -
    HADDR_TEMP_c24                          Net          -        -       0.806     -           3
    usb_slave_0.HADDR_TEMP_RNIMR0D5[26]     NOR3C        B        In      -         18.928      -
    usb_slave_0.HADDR_TEMP_RNIMR0D5[26]     NOR3C        Y        Out     0.624     19.552      -
    HADDR_TEMP_c26                          Net          -        -       0.806     -           3
    usb_slave_0.HADDR_TEMP_RNI3UEO5[28]     NOR3C        B        In      -         20.358      -
    usb_slave_0.HADDR_TEMP_RNI3UEO5[28]     NOR3C        Y        Out     0.624     20.982      -
    HADDR_TEMP_c28                          Net          -        -       0.386     -           2
    usb_slave_0.HADDR_TEMP_RNIB56U5[29]     NOR2B        A        In      -         21.368      -
    usb_slave_0.HADDR_TEMP_RNIB56U5[29]     NOR2B        Y        Out     0.488     21.856      -
    HADDR_TEMP_c29                          Net          -        -       0.386     -           2
    usb_slave_0.HADDR_TEMP_RNO[31]          AX1C         B        In      -         22.242      -
    usb_slave_0.HADDR_TEMP_RNO[31]          AX1C         Y        Out     0.970     23.212      -
    HADDR_TEMP_n31                          Net          -        -       0.322     -           1
    usb_slave_0.HADDR_TEMP[31]              DFN1E1C0     D        In      -         23.533      -
    ======================================================================================================
    Total path delay (propagation time + setup) of 24.072 is 11.312(47.0%) logic and 12.760(53.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                     Starting                                                                  Arrival
    Instance                         Reference     Type          Pin              Net                          Time        Slack
                                     Clock
    ------------------------------------------------------------------------------------------------------------------------------
    usb_mss_0.FIO_INBUF_0            System        INBUF_MSS     Y                IO_0_Y_0                     0.000       982.743
    usb_mss_0.MSS_CCC_0.I_MSSCCC     System        MSS_CCC       LOCK             usb_mss_0_FAB_LOCK           0.000       994.506
    usb_mss_0.MSS_ADLIB_INST         System        MSS_AHB       EMCDBOE          MSS_EMI_0_DB_15_E            0.000       997.827
    usb_mss_0.MSS_ADLIB_INST         System        MSS_AHB       FABHREADYOUT     FABHREADYOUT                 0.000       998.339
    usb_mss_0.MSS_ADLIB_INST         System        MSS_AHB       EMCCLK           MSS_EMI_0_CLK_D              0.000       999.614
    usb_mss_0.MSS_ADLIB_INST         System        MSS_AHB       SPI0MODE         MSS_SPI_0_SS_E               0.000       999.614
    usb_mss_0.MSS_ADLIB_INST         System        MSS_AHB       SPI1MODE         MSS_SPI_1_SS_E               0.000       999.614
    usb_mss_0.MSS_CCC_0.I_MSSCCC     System        MSS_CCC       GLAMSS           MSS_ADLIB_INST_FCLK          0.000       999.678
    usb_mss_0.MSS_CCC_0.I_MSSCCC     System        MSS_CCC       LOCKMSS          MSS_ADLIB_INST_PLLLOCK       0.000       999.678
    usb_mss_0.MSS_CCC_0.I_MSSCCC     System        MSS_CCC       MACCLK           MSS_ADLIB_INST_MACCLKCCC     0.000       999.678
    ==============================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                       Starting                                                 Required
    Instance                                           Reference     Type       Pin     Net                     Time         Slack
                                                       Clock
    --------------------------------------------------------------------------------------------------------------------------------
    usb_slave_0.FIFO_INST.DFN1C0_FULL                  System        DFN1C0     D       FULLINT                 999.461      982.743
    usb_slave_0.FIFO_INST.DFN1C0_WGRY_8_inst           System        DFN1C0     D       XOR2_52_Y               999.461      985.734
    usb_slave_0.FIFO_INST.DFN1C0_WGRY_9_inst           System        DFN1C0     D       XOR2_15_Y               999.461      985.734
    usb_slave_0.FIFO_INST.DFN1C0_WGRY_6_inst           System        DFN1C0     D       XOR2_41_Y               999.461      986.154
    usb_slave_0.FIFO_INST.DFN1C0_WGRY_10_inst          System        DFN1C0     D       XOR2_44_Y               999.461      986.182
    usb_slave_0.FIFO_INST.DFN1C0_WGRY_7_inst           System        DFN1C0     D       XOR2_50_Y               999.461      986.602
    usb_slave_0.FIFO_INST.DFN1C0_MEM_WADDR_9_inst      System        DFN1C0     D       WBINNXTSHIFT_9_net      999.461      986.992
    usb_slave_0.FIFO_INST.DFN1C0_MEM_WADDR_10_inst     System        DFN1C0     D       WBINNXTSHIFT_10_net     999.461      986.992
    usb_slave_0.FIFO_INST.DFN1C0_WGRY_5_inst           System        DFN1C0     D       XOR2_29_Y               999.461      987.073
    usb_slave_0.FIFO_INST.DFN1C0_WGRY_4_inst           System        DFN1C0     D       XOR2_53_Y               999.461      987.138
    ================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      1000.000
        - Setup time:                            0.539
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         999.461

        - Propagation time:                      16.718
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 982.743

        Number of logic level(s):                13
        Starting point:                          usb_mss_0.FIO_INBUF_0 / Y
        Ending point:                            usb_slave_0.FIFO_INST.DFN1C0_FULL / D
        The start point is clocked by            System [falling]
        The end   point is clocked by            usbee_top_level|USB_CLK [falling] on pin CLK

    Instance / Net                                                   Pin      Pin               Arrival     No. of
    Name                                               Type          Name     Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------------------------------
    usb_mss_0.FIO_INBUF_0                              INBUF_MSS     Y        Out     0.000     0.000       -
    IO_0_Y_0                                           Net           -        -       1.708     -           10
    usb_slave_0.FIFO_INST.WEBUBBLE                     INV           A        In      -         1.708       -
    usb_slave_0.FIFO_INST.WEBUBBLE                     INV           Y        Out     0.363     2.072       -
    WEP                                                Net           -        -       0.322     -           1
    usb_slave_0.FIFO_INST.AND2_MEMORYWE                AND2          B        In      -         2.393       -
    usb_slave_0.FIFO_INST.AND2_MEMORYWE                AND2          Y        Out     0.627     3.021       -
    MEMORYWE                                           Net           -        -       0.806     -           3
    usb_slave_0.FIFO_INST.AND2_32                      AND2          B        In      -         3.827       -
    usb_slave_0.FIFO_INST.AND2_32                      AND2          Y        Out     0.627     4.454       -
    AND2_32_Y                                          Net           -        -       0.386     -           2
    usb_slave_0.FIFO_INST.AO1_1                        AO1           B        In      -         4.840       -
    usb_slave_0.FIFO_INST.AO1_1                        AO1           Y        Out     0.598     5.438       -
    AO1_1_Y                                            Net           -        -       0.806     -           3
    usb_slave_0.FIFO_INST.AO1_44                       AO1           B        In      -         6.244       -
    usb_slave_0.FIFO_INST.AO1_44                       AO1           Y        Out     0.598     6.842       -
    AO1_44_Y                                           Net           -        -       1.184     -           4
    usb_slave_0.FIFO_INST.AO1_36                       AO1           B        In      -         8.026       -
    usb_slave_0.FIFO_INST.AO1_36                       AO1           Y        Out     0.598     8.624       -
    AO1_36_Y                                           Net           -        -       0.386     -           2
    usb_slave_0.FIFO_INST.AO1_18                       AO1           B        In      -         9.009       -
    usb_slave_0.FIFO_INST.AO1_18                       AO1           Y        Out     0.598     9.607       -
    AO1_18_Y                                           Net           -        -       0.322     -           1
    usb_slave_0.FIFO_INST.XOR2_WBINNXTSHIFT_7_inst     XOR2          B        In      -         9.929       -
    usb_slave_0.FIFO_INST.XOR2_WBINNXTSHIFT_7_inst     XOR2          Y        Out     0.937     10.865      -
    WBINNXTSHIFT_7_net                                 Net           -        -       1.184     -           4
    usb_slave_0.FIFO_INST.XNOR2_9                      XNOR2         B        In      -         12.049      -
    usb_slave_0.FIFO_INST.XNOR2_9                      XNOR2         Y        Out     0.937     12.986      -
    XNOR2_9_Y                                          Net           -        -       0.322     -           1
    usb_slave_0.FIFO_INST.AND3_3                       AND3          B        In      -         13.307      -
    usb_slave_0.FIFO_INST.AND3_3                       AND3          Y        Out     0.624     13.931      -
    AND3_3_Y                                           Net           -        -       0.322     -           1
    usb_slave_0.FIFO_INST.AND3_1                       AND3          A        In      -         14.253      -
    usb_slave_0.FIFO_INST.AND3_1                       AND3          Y        Out     0.525     14.777      -
    AND3_1_Y                                           Net           -        -       0.322     -           1
    usb_slave_0.FIFO_INST.AND2_22                      AND2          A        In      -         15.099      -
    usb_slave_0.FIFO_INST.AND2_22                      AND2          Y        Out     0.488     15.587      -
    AND2_22_Y                                          Net           -        -       0.322     -           1
    usb_slave_0.FIFO_INST.AND2_FULLINT                 AND2          A        In      -         15.909      -
    usb_slave_0.FIFO_INST.AND2_FULLINT                 AND2          Y        Out     0.488     16.397      -
    FULLINT                                            Net           -        -       0.322     -           1
    usb_slave_0.FIFO_INST.DFN1C0_FULL                  DFN1C0        D        In      -         16.718      -
    ==================================================================================================================
    Total path delay (propagation time + setup) of 17.257 is 8.547(49.5%) logic and 8.711(50.5%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    --------------------------------------------------------------------------------
    Target Part: A3PE600_FBGA256_Std
    Report for cell usbee_top_level.def_arch
      Core Cell usage:
                  cell count     area count*area
                  AND2    45      1.0       45.0
                 AND2A     1      1.0        1.0
                  AND3     8      1.0        8.0
                   AO1    60      1.0       60.0
                  AO1A     2      1.0        2.0
                  AO1B    33      1.0       33.0
                  AO1C     5      1.0        5.0
                  AO1D     3      1.0        3.0
                  AOI1     6      1.0        6.0
                 AOI1B    37      1.0       37.0
                  AX1B     1      1.0        1.0
                  AX1C    16      1.0       16.0
                  AX1E     2      1.0        2.0
                  BUFF    12      1.0       12.0
                CLKINT     2      0.0        0.0
                   GND    27      0.0        0.0
                   INV     7      1.0        7.0
               MSS_AHB     1      0.0        0.0
               MSS_CCC     1      0.0        0.0
                   MX2    98      1.0       98.0
                  MX2A     1      1.0        1.0
                  MX2B     1      1.0        1.0
                  MX2C    10      1.0       10.0
                 NAND2     2      1.0        2.0
                  NOR2    16      1.0       16.0
                 NOR2A    18      1.0       18.0
                 NOR2B    18      1.0       18.0
                  NOR3     7      1.0        7.0
                 NOR3A    13      1.0       13.0
                 NOR3B     5      1.0        5.0
                 NOR3C    29      1.0       29.0
                   OA1     1      1.0        1.0
                  OA1A     1      1.0        1.0
                  OA1B     3      1.0        3.0
                  OAI1     3      1.0        3.0
                   OR2    11      1.0       11.0
                  OR2A     4      1.0        4.0
                  OR2B    49      1.0       49.0
                   OR3     6      1.0        6.0
                  OR3A     2      1.0        2.0
                  OR3B     3      1.0        3.0
                  OR3C     8      1.0        8.0
                   VCC    27      0.0        0.0
                  XA1B    10      1.0       10.0
                 XNOR2    33      1.0       33.0
                 XNOR3    40      1.0       40.0
                  XOR2   122      1.0      122.0
                  XOR3    10      1.0       10.0
                 ZOR3I     1      1.0        1.0

              DFI1E1P0     1      1.0        1.0
                  DFN1    89      1.0       89.0
                DFN1C0   107      1.0      107.0
                DFN1C1    16      1.0       16.0
                DFN1E0    50      1.0       50.0
              DFN1E0C0     2      1.0        2.0
                DFN1E1    32      1.0       32.0
              DFN1E1C0   101      1.0      101.0
              DFN1E1C1     1      1.0        1.0
              DFN1E1P0     3      1.0        3.0
                DFN1P0     2      1.0        2.0
                DFN1P1     1      1.0        1.0
                RAM4K9     2      0.0        0.0
             RAM512X18     2      0.0        0.0
                       -----          ----------
                 TOTAL  1230              1168.0

      IO Cell usage:
                  cell count
       BIBUF_LVCMOS33U     8
             BIBUF_MSS    21
       BIBUF_OPEND_MSS     4
                CLKBUF     1
             INBUF_MSS    10
            MSS_XTLOSC     1
                OUTBUF     1
            OUTBUF_MSS    54
           TRIBUFF_MSS     2
                 UJTAG     1
                       -----
                 TOTAL   103

    Core Cells         : 1168 of 13824 (8%)
    IO Cells           : 103

      RAM/ROM Usage Summary
    Block Rams : 4 of 24 (16%)

    Mapper successful!
    Process took 0h:00m:15s realtime, 0h:00m:05s cputime
    # Sun Jul 18 21:44:34 2010

    ###########################################################]
    $ Running Identify Instrumentor. See log file:
    @N: : identify.log |
    #Sun Jul 18 22:23:48 2010

`