`

    Synplicity Identify Instrumentor, version C-2009.06A-SP2, Build 016R, built Aug 13 2009
    Copyright (C) 1994-2009, Synopsys Inc.  All Rights Reserved

    @N: :  | dded instrumentation 'synthesis_1' to the project
    @N: :  | dded file 'D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\component\Actel\SmartFusionMSS\MSS\2.2.101\mss_comps.v' to project
    @N: :  | dded file 'D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\component\work\mss_top\MSS_CCC_0\mss_top_tmp_MSS_CCC_0_MSS_CCC.v' to project
    @N: :  | dded file 'D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\component\work\mss_top\mss_top.v' to project
    @N: :  | dded file 'D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\component\Actel\DirectCore\CORESPI\3.0.156\rtl\vlog\core\spi_master.v' to project
    @N: :  | dded file 'D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\component\Actel\DirectCore\CORESPI\3.0.156\rtl\vlog\core\spi_slave.v' to project
    @N: :  | dded file 'D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\component\Actel\DirectCore\CORESPI\3.0.156\rtl\vlog\core\corespi_sfr.v' to project
    @N: :  | dded file 'D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\component\Actel\DirectCore\CORESPI\3.0.156\rtl\vlog\core\corespi.v' to project
    @N: :  | dded file 'D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3_muxptob3.v' to project
    @N: :  | dded file 'D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v' to project
    @N: :  | dded file 'D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\component\work\top_level\top_level.v' to project
    @N: : fusion.v | "C:\Actel\Libero_v9.0\Synopsys\synplify_D200912A\lib\proasic\fusion.v"
    @N: : mss_comps.v | "D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\component\Actel\SmartFusionMSS\MSS\2.2.101\mss_comps.v"
    @N: : mss_top_tmp_MSS_CCC_0_MSS_CCC.v | "D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\component\work\mss_top\MSS_CCC_0\mss_top_tmp_MSS_CCC_0_MSS_CCC.v"
    @N: : mss_top.v | "D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\component\work\mss_top\mss_top.v"
    @N: : spi_master.v | "D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\component\Actel\DirectCore\CORESPI\3.0.156\rtl\vlog\core\spi_master.v"
    @N: : spi_slave.v | "D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\component\Actel\DirectCore\CORESPI\3.0.156\rtl\vlog\core\spi_slave.v"
    @N: : corespi_sfr.v | "D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\component\Actel\DirectCore\CORESPI\3.0.156\rtl\vlog\core\corespi_sfr.v"
    @N: : corespi.v | "D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\component\Actel\DirectCore\CORESPI\3.0.156\rtl\vlog\core\corespi.v"
    @N: : coreapb3_muxptob3.v | "D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3_muxptob3.v"
    @N: : coreapb3.v | "D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core\coreapb3.v"
    @N: : top_level.v | "D:\LABS\FTDI_SPI_WS\HW\Core_SPI_verilog\component\work\top_level\top_level.v"
    @N: :  | erilog syntax check successful!
    @N: :  | electing top level module top_level
    @N: : coreapb3_muxptob3.v(30) | Synthesizing module COREAPB3_MUXPTOB3
    @N: : coreapb3.v(30) | Synthesizing module CoreAPB3
    @N: : fusion.v(2043) | Synthesizing module VCC
    @N: : mss_comps.v(67) | Synthesizing module BIBUF_MSS
    @N: : mss_comps.v(23) | Synthesizing module INBUF_MSS
    @N: : mss_comps.v(37) | Synthesizing module OUTBUF_MSS
    @N: : mss_comps.v(85) | Synthesizing module BIBUF_OPEND_MSS
    @N: : mss_comps.v(51) | Synthesizing module TRIBUFF_MSS
    @N: : fusion.v(1224) | Synthesizing module GND
    @N: : mss_comps.v(151) | Synthesizing module MSS_CCC
    @N: : mss_comps.v(1) | Synthesizing module MSS_XTLOSC
    @N: : mss_top_tmp_MSS_CCC_0_MSS_CCC.v(5) | Synthesizing module mss_top_tmp_MSS_CCC_0_MSS_CCC
    @N: : mss_comps.v(680) | Synthesizing module MSS_APB
    @N: : mss_comps.v(145) | Synthesizing module MSSINT
    @N: : mss_top.v(5) | Synthesizing module mss_top
    @N: : corespi_sfr.v(19) | Synthesizing module CORESPI_SFR
    @N: : spi_slave.v(18) | Synthesizing module spi_slave
    @N: : corespi.v(13) | Synthesizing module CORESPI
    @N: : top_level.v(5) | Synthesizing module top_level
    @N: :  | esign compiled with: 0 warnings
    @N: :  | oading design instrumentation version 6.2
    @N: :  | reated Tue Aug 17 14:54:01 2010
    @N: :  | ser		 =  cherukupallyu
    @N: :  | latform		 =  windows
    @N: :  | achine Name	 =  wxpl-cherukupallyu
    @N: :  | achine Type	 =  intel
    @N: :  | S		 =  windows
    @N: :  | S version	 =  4.1.1
    @N: :  | _hdl version	 =
    @N: :  | _vhdl version	 =
    @N: :  | _ver version	 =  comp400rc, Build 082R R on Aug 13 2009 18:10:31 by sbg_build@BLDWIN2000F
    @N: :  | urrent design is `top_level'
    @N: :  | oading instrumentation 'synthesis_1'
    @N: :  | nstrumenting design `top_level' in directory D:/LABS/FTDI_SPI_WS/HW/Core_SPI_verilog/synthesis/synthesis_1
    @N: :  | enerating IICE model of TOP
    @N: :  | enerating IICE for the following settings:
    @N: :  | Design settings:
    @N: :  | Device family          Fusion
    @N: :  | JTAG port              builtin
    @N: :  | Skew-resistant logic   off
    @N: :  | Export Trigger         no
    @N: :  | Language               verilog
    @N: :  | Sample Buffer:
    @N: :  | Type                   behavioral
    @N: :  | Depth                  128
    @N: :  | Width                  14 bits
    @N: :  | Qualified sampling     off
    @N: :  | Always armed sampling  off
    @N: :  | Trigger controller:
    @N: :  | Type                   Simple Triggering
    @N: :  |
    @N: :  | urrent area estimate: 	IICE=IICE Logic: 100 Tiles, Buffer: 1792 bits
    Total current area estimates:Logic: 510 Tiles, Buffer: 1792 bits

`