Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Thu Dec 29 14:51:51 2011


Design: usbee_top_level
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               USB_CLK
Period (ns):                6.129
Frequency (MHz):            163.159
Required Period (ns):       1000.000
Required Frequency (MHz):   1.000
External Setup (ns):        5.283
External Hold (ns):         -0.766
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                15.552
Frequency (MHz):            64.300
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.661
External Hold (ns):         1.288
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               usb_mss_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             4.727
Max Delay (ns):             12.512

END SUMMARY
-----------------------------------------------------

Clock Domain USB_CLK

SET Register to Register

Path 1
  From:                        usb_slave_0/FIFO_INST/FIFOBLOCK_0_inst:WCLK
  To:                          usb_slave_0/FIFO_INST/FIFOBLOCK_0_inst:WEN
  Delay (ns):                  4.974
  Slack (ns):                  993.871
  Arrival (ns):                7.008
  Required (ns):               1000.879
  Setup (ns):                  1.155
  Minimum Period (ns):         6.129

Path 2
  From:                        usb_slave_0/FIFO_INST/FIFOBLOCK_1_inst:WCLK
  To:                          usb_slave_0/FIFO_INST/FIFOBLOCK_0_inst:WEN
  Delay (ns):                  4.893
  Slack (ns):                  993.947
  Arrival (ns):                6.932
  Required (ns):               1000.879
  Setup (ns):                  1.155
  Minimum Period (ns):         6.053

Path 3
  From:                        usb_slave_0/FIFO_INST/FIFOBLOCK_0_inst:WCLK
  To:                          usb_slave_0/FIFO_INST/FIFOBLOCK_1_inst:WEN
  Delay (ns):                  4.865
  Slack (ns):                  993.985
  Arrival (ns):                6.899
  Required (ns):               1000.884
  Setup (ns):                  1.155
  Minimum Period (ns):         6.015

Path 4
  From:                        usb_slave_0/FIFO_INST/FIFOBLOCK_1_inst:WCLK
  To:                          usb_slave_0/FIFO_INST/FIFOBLOCK_1_inst:WEN
  Delay (ns):                  4.784
  Slack (ns):                  994.061
  Arrival (ns):                6.823
  Required (ns):               1000.884
  Setup (ns):                  1.155
  Minimum Period (ns):         5.939

Path 5
  From:                        usb_slave_0/input_states[0]:CLK
  To:                          usb_slave_0/input_32_bit_data[21]:D
  Delay (ns):                  3.867
  Slack (ns):                  995.611
  Arrival (ns):                5.712
  Required (ns):               1001.323
  Setup (ns):                  0.522
  Minimum Period (ns):         4.389


Expanded Path 1
  From: usb_slave_0/FIFO_INST/FIFOBLOCK_0_inst:WCLK
  To: usb_slave_0/FIFO_INST/FIFOBLOCK_0_inst:WEN
  data required time                             1000.879
  data arrival time                          -   7.008
  slack                                          993.871
  ________________________________________________________
  Data arrival time calculation
  0.000                        USB_CLK
               +     0.000          Clock source
  0.000                        USB_CLK (r)
               +     0.000          net: USB_CLK
  0.000                        USB_CLK_pad/U0/U0:PAD (r)
               +     0.935          cell: ADLIB:IOPAD_IN
  0.935                        USB_CLK_pad/U0/U0:Y (r)
               +     0.000          net: USB_CLK_pad/U0/NET1
  0.935                        USB_CLK_pad/U0/U1:A (r)
               +     0.285          cell: ADLIB:CLKSRC
  1.220                        USB_CLK_pad/U0/U1:Y (r)
               +     0.814          net: USB_CLK_c
  2.034                        usb_slave_0/FIFO_INST/FIFOBLOCK_0_inst:WCLK (r)
               +     1.988          cell: ADLIB:FIFO4K18
  4.022                        usb_slave_0/FIFO_INST/FIFOBLOCK_0_inst:FULL (r)
               +     1.230          net: usb_slave_0/FIFO_INST/FULLX_I_0_net
  5.252                        usb_slave_0/FIFO_INST/WRITE_AND:A (r)
               +     0.422          cell: ADLIB:OR3
  5.674                        usb_slave_0/FIFO_INST/WRITE_AND:Y (r)
               +     1.334          net: usb_slave_0/FIFO_INST/WRITE_ENABLE_I
  7.008                        usb_slave_0/FIFO_INST/FIFOBLOCK_0_inst:WEN (r)
                                    
  7.008                        data arrival time
  ________________________________________________________
  Data required time calculation
  1000.000                     USB_CLK
               +     0.000          Clock source
  1000.000                     USB_CLK (r)
               +     0.000          net: USB_CLK
  1000.000                     USB_CLK_pad/U0/U0:PAD (r)
               +     0.935          cell: ADLIB:IOPAD_IN
  1000.935                     USB_CLK_pad/U0/U0:Y (r)
               +     0.000          net: USB_CLK_pad/U0/NET1
  1000.935                     USB_CLK_pad/U0/U1:A (r)
               +     0.285          cell: ADLIB:CLKSRC
  1001.220                     USB_CLK_pad/U0/U1:Y (r)
               +     0.814          net: USB_CLK_c
  1002.034                     usb_slave_0/FIFO_INST/FIFOBLOCK_0_inst:WCLK (r)
               -     1.155          Library setup time: ADLIB:FIFO4K18
  1000.879                     usb_slave_0/FIFO_INST/FIFOBLOCK_0_inst:WEN
                                    
  1000.879                     data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        USB_DATA_PAD[2]
  To:                          usb_slave_0/input_32_bit_data[10]:D
  Delay (ns):                  6.638
  Slack (ns):
  Arrival (ns):                6.638
  Required (ns):
  Setup (ns):                  0.490
  External Setup (ns):         5.283

Path 2
  From:                        USB_DATA_PAD[2]
  To:                          usb_slave_0/input_32_bit_data[18]:D
  Delay (ns):                  5.797
  Slack (ns):
  Arrival (ns):                5.797
  Required (ns):
  Setup (ns):                  0.490
  External Setup (ns):         4.442

Path 3
  From:                        USB_DATA_PAD[2]
  To:                          usb_slave_0/input_32_bit_data[26]:D
  Delay (ns):                  5.788
  Slack (ns):
  Arrival (ns):                5.788
  Required (ns):
  Setup (ns):                  0.490
  External Setup (ns):         4.433

Path 4
  From:                        USB_DATA_PAD[5]
  To:                          usb_slave_0/input_32_bit_data[29]:D
  Delay (ns):                  5.741
  Slack (ns):
  Arrival (ns):                5.741
  Required (ns):
  Setup (ns):                  0.490
  External Setup (ns):         4.386

Path 5
  From:                        USB_DATA_PAD[4]
  To:                          usb_slave_0/input_32_bit_data[4]:D
  Delay (ns):                  5.629
  Slack (ns):
  Arrival (ns):                5.629
  Required (ns):
  Setup (ns):                  0.490
  External Setup (ns):         4.326


Expanded Path 1
  From: USB_DATA_PAD[2]
  To: usb_slave_0/input_32_bit_data[10]:D
  data required time                             N/C
  data arrival time                          -   6.638
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        USB_DATA_PAD[2] (r)
               +     0.000          net: USB_DATA_PAD[2]
  0.000                        usb_slave_0/GEN.2.DATA_PINS/U0/U0:PAD (r)
               +     0.967          cell: ADLIB:IOPAD_BI
  0.967                        usb_slave_0/GEN.2.DATA_PINS/U0/U0:Y (r)
               +     0.000          net: usb_slave_0/GEN_2_DATA_PINS/U0/NET3
  0.967                        usb_slave_0/GEN.2.DATA_PINS/U0/U1:YIN (r)
               +     0.039          cell: ADLIB:IOBI_IB_OB_EB
  1.006                        usb_slave_0/GEN.2.DATA_PINS/U0/U1:Y (r)
               +     4.695          net: usb_slave_0/USB_DATA_IN[2]
  5.701                        usb_slave_0/input_32_bit_data_RNO[10]:B (r)
               +     0.617          cell: ADLIB:MX2
  6.318                        usb_slave_0/input_32_bit_data_RNO[10]:Y (r)
               +     0.320          net: usb_slave_0/input_32_bit_data_RNO[10]
  6.638                        usb_slave_0/input_32_bit_data[10]:D (r)
                                    
  6.638                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          USB_CLK
               +     0.000          Clock source
  N/C                          USB_CLK (r)
               +     0.000          net: USB_CLK
  N/C                          USB_CLK_pad/U0/U0:PAD (r)
               +     0.935          cell: ADLIB:IOPAD_IN
  N/C                          USB_CLK_pad/U0/U0:Y (r)
               +     0.000          net: USB_CLK_pad/U0/NET1
  N/C                          USB_CLK_pad/U0/U1:A (r)
               +     0.285          cell: ADLIB:CLKSRC
  N/C                          USB_CLK_pad/U0/U1:Y (r)
               +     0.625          net: USB_CLK_c
  N/C                          usb_slave_0/input_32_bit_data[10]:CLK (r)
               -     0.490          Library setup time: ADLIB:DFN1C1
  N/C                          usb_slave_0/input_32_bit_data[10]:D


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

Path 1
  From:                        IO_0_PADIN
  To:                          usb_slave_0/input_32_bit_data[15]:CLR
  Delay (ns):                  8.783
  Slack (ns):
  Arrival (ns):                8.783
  Required (ns):
  Recovery (ns):               0.271
  External Recovery (ns):      7.244

Path 2
  From:                        IO_0_PADIN
  To:                          usb_slave_0/input_32_bit_data[19]:CLR
  Delay (ns):                  8.783
  Slack (ns):
  Arrival (ns):                8.783
  Required (ns):
  Recovery (ns):               0.271
  External Recovery (ns):      7.244

Path 3
  From:                        IO_0_PADIN
  To:                          usb_slave_0/input_32_bit_data[20]:CLR
  Delay (ns):                  8.783
  Slack (ns):
  Arrival (ns):                8.783
  Required (ns):
  Recovery (ns):               0.271
  External Recovery (ns):      7.209

Path 4
  From:                        IO_0_PADIN
  To:                          usb_slave_0/input_32_bit_data[10]:CLR
  Delay (ns):                  8.783
  Slack (ns):
  Arrival (ns):                8.783
  Required (ns):
  Recovery (ns):               0.271
  External Recovery (ns):      7.209

Path 5
  From:                        IO_0_PADIN
  To:                          usb_slave_0/input_32_bit_data[16]:CLR
  Delay (ns):                  8.783
  Slack (ns):
  Arrival (ns):                8.783
  Required (ns):
  Recovery (ns):               0.271
  External Recovery (ns):      7.209


Expanded Path 1
  From: IO_0_PADIN
  To: usb_slave_0/input_32_bit_data[15]:CLR
  data required time                             N/C
  data arrival time                          -   8.783
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        IO_0_PADIN (f)
               +     0.000          net: IO_0_PADIN
  0.000                        usb_mss_0/FIO_INBUF_0/U0/U0:PAD (f)
               +     0.634          cell: ADLIB:IOPAD_IN
  0.634                        usb_mss_0/FIO_INBUF_0/U0/U0:Y (f)
               +     0.000          net: usb_mss_0/FIO_INBUF_0/U0/Y_INT
  0.634                        usb_mss_0/FIO_INBUF_0/U0/U1:PIN1INT (f)
               +     0.088          cell: ADLIB:MSS_IF
  0.722                        usb_mss_0/FIO_INBUF_0/U0/U1:PIN1 (f)
               +     3.190          net: IO_0_Y
  3.912                        usb_mss_0/FIO_INBUF_0_RNI5UVF:A (f)
               +     0.462          cell: ADLIB:BUFF
  4.374                        usb_mss_0/FIO_INBUF_0_RNI5UVF:Y (f)
               +     4.409          net: IO_0_Y_0
  8.783                        usb_slave_0/input_32_bit_data[15]:CLR (f)
                                    
  8.783                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          USB_CLK
               +     0.000          Clock source
  N/C                          USB_CLK (r)
               +     0.000          net: USB_CLK
  N/C                          USB_CLK_pad/U0/U0:PAD (r)
               +     0.935          cell: ADLIB:IOPAD_IN
  N/C                          USB_CLK_pad/U0/U0:Y (r)
               +     0.000          net: USB_CLK_pad/U0/NET1
  N/C                          USB_CLK_pad/U0/U1:A (r)
               +     0.285          cell: ADLIB:CLKSRC
  N/C                          USB_CLK_pad/U0/U1:Y (r)
               +     0.590          net: USB_CLK_c
  N/C                          usb_slave_0/input_32_bit_data[15]:CLK (r)
               -     0.271          Library recovery time: ADLIB:DFN1C1
  N/C                          usb_slave_0/input_32_bit_data[15]:CLR


END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        usb_slave_0/HADDR_TEMP[5]/U1:CLK
  To:                          usb_slave_0/HADDR_TEMP[17]/U1:D
  Delay (ns):                  15.023
  Slack (ns):
  Arrival (ns):                15.687
  Required (ns):
  Setup (ns):                  0.522
  Minimum Period (ns):         15.552

Path 2
  From:                        usb_slave_0/HADDR_TEMP[0]:CLK
  To:                          usb_slave_0/HADDR_TEMP[17]/U1:D
  Delay (ns):                  14.034
  Slack (ns):
  Arrival (ns):                14.691
  Required (ns):
  Setup (ns):                  0.522
  Minimum Period (ns):         14.556

Path 3
  From:                        usb_slave_0/HADDR_TEMP[5]/U1:CLK
  To:                          usb_slave_0/HADDR_TEMP[16]/U1:D
  Delay (ns):                  13.705
  Slack (ns):
  Arrival (ns):                14.369
  Required (ns):
  Setup (ns):                  0.490
  Minimum Period (ns):         14.202

Path 4
  From:                        usb_slave_0/HADDR_TEMP[6]/U1:CLK
  To:                          usb_slave_0/HADDR_TEMP[17]/U1:D
  Delay (ns):                  13.642
  Slack (ns):
  Arrival (ns):                14.317
  Required (ns):
  Setup (ns):                  0.490
  Minimum Period (ns):         14.150

Path 5
  From:                        usb_slave_0/HADDR_TEMP[5]/U1:CLK
  To:                          usb_slave_0/HADDR_TEMP[15]/U1:D
  Delay (ns):                  13.596
  Slack (ns):
  Arrival (ns):                14.260
  Required (ns):
  Setup (ns):                  0.522
  Minimum Period (ns):         14.125


Expanded Path 1
  From: usb_slave_0/HADDR_TEMP[5]/U1:CLK
  To: usb_slave_0/HADDR_TEMP[17]/U1:D
  data required time                             N/C
  data arrival time                          -   15.687
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        usb_mss_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: usb_mss_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  0.000                        usb_mss_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        usb_mss_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.664          net: FAB_CLK
  0.664                        usb_slave_0/HADDR_TEMP[5]/U1:CLK (r)
               +     0.671          cell: ADLIB:DFN1P0
  1.335                        usb_slave_0/HADDR_TEMP[5]/U1:Q (f)
               +     2.462          net: _usb_slave_0_HADDR_[7]_
  3.797                        usb_slave_0/HADDR_TEMP_RNI5J6F[6]:B (f)
               +     0.574          cell: ADLIB:NOR2B
  4.371                        usb_slave_0/HADDR_TEMP_RNI5J6F[6]:Y (f)
               +     0.368          net: usb_slave_0/HADDR_TEMP_c6_0
  4.739                        usb_slave_0/HADDR_TEMP_RNI66DU[3]:C (f)
               +     0.620          cell: ADLIB:NOR3C
  5.359                        usb_slave_0/HADDR_TEMP_RNI66DU[3]:Y (f)
               +     1.734          net: usb_slave_0/HADDR_TEMP_c11_m6_0_a2_4_2
  7.093                        usb_slave_0/HADDR_TEMP_RNICK3L3[12]:B (f)
               +     0.552          cell: ADLIB:NOR3B
  7.645                        usb_slave_0/HADDR_TEMP_RNICK3L3[12]:Y (f)
               +     3.298          net: usb_slave_0/HADDR_TEMP_c12
  10.943                       usb_slave_0/HADDR_TEMP_RNIFMGG4[14]:B (f)
               +     0.552          cell: ADLIB:NOR3C
  11.495                       usb_slave_0/HADDR_TEMP_RNIFMGG4[14]:Y (f)
               +     0.308          net: usb_slave_0/HADDR_TEMP_c14
  11.803                       usb_slave_0/HADDR_TEMP_RNIID7U4[15]:A (f)
               +     0.468          cell: ADLIB:NOR2B
  12.271                       usb_slave_0/HADDR_TEMP_RNIID7U4[15]:Y (f)
               +     0.368          net: usb_slave_0/HADDR_TEMP_c15
  12.639                       usb_slave_0/HADDR_TEMP_RNO[17]:B (f)
               +     0.910          cell: ADLIB:AX1C
  13.549                       usb_slave_0/HADDR_TEMP_RNO[17]:Y (f)
               +     1.322          net: usb_slave_0/HADDR_TEMP_n17
  14.871                       usb_slave_0/HADDR_TEMP[17]/U0:B (f)
               +     0.520          cell: ADLIB:MX2
  15.391                       usb_slave_0/HADDR_TEMP[17]/U0:Y (f)
               +     0.296          net: usb_slave_0/HADDR_TEMP[17]/Y
  15.687                       usb_slave_0/HADDR_TEMP[17]/U1:D (f)
                                    
  15.687                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          usb_mss_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: usb_mss_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  N/C                          usb_mss_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          usb_mss_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.657          net: FAB_CLK
  N/C                          usb_slave_0/HADDR_TEMP[17]/U1:CLK (r)
               -     0.522          Library setup time: ADLIB:DFN1P0
  N/C                          usb_slave_0/HADDR_TEMP[17]/U1:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin usb_mss_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          usb_mss_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.937
  Slack (ns):
  Arrival (ns):                0.937
  Required (ns):
  Setup (ns):                  -2.139
  External Setup (ns):         -1.661


Expanded Path 1
  From: MSS_RESET_N
  To: usb_mss_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.937
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        usb_mss_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.937          cell: ADLIB:IOPAD_IN
  0.937                        usb_mss_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: usb_mss_0/MSS_RESET_0_MSS_RESET_N_Y
  0.937                        usb_mss_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.937                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          usb_mss_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.459          net: usb_mss_0/GLA0
  N/C                          usb_mss_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -2.139          Library setup time: ADLIB:MSS_AHB_IP
  N/C                          usb_mss_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain usb_mss_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

Path 1
  From:                        IO_0_PADIN
  To:                          USB_DATA_PAD[4]
  Delay (ns):                  12.512
  Slack (ns):
  Arrival (ns):                12.512
  Required (ns):

Path 2
  From:                        IO_0_PADIN
  To:                          USB_DATA_PAD[3]
  Delay (ns):                  12.327
  Slack (ns):
  Arrival (ns):                12.327
  Required (ns):

Path 3
  From:                        IO_0_PADIN
  To:                          USB_DATA_PAD[7]
  Delay (ns):                  12.129
  Slack (ns):
  Arrival (ns):                12.129
  Required (ns):

Path 4
  From:                        IO_0_PADIN
  To:                          USB_DATA_PAD[1]
  Delay (ns):                  11.976
  Slack (ns):
  Arrival (ns):                11.976
  Required (ns):

Path 5
  From:                        IO_0_PADIN
  To:                          USB_DATA_PAD[2]
  Delay (ns):                  11.976
  Slack (ns):
  Arrival (ns):                11.976
  Required (ns):


Expanded Path 1
  From: IO_0_PADIN
  To: USB_DATA_PAD[4]
  data required time                             N/C
  data arrival time                          -   12.512
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        IO_0_PADIN (r)
               +     0.000          net: IO_0_PADIN
  0.000                        usb_mss_0/FIO_INBUF_0/U0/U0:PAD (r)
               +     0.937          cell: ADLIB:IOPAD_IN
  0.937                        usb_mss_0/FIO_INBUF_0/U0/U0:Y (r)
               +     0.000          net: usb_mss_0/FIO_INBUF_0/U0/Y_INT
  0.937                        usb_mss_0/FIO_INBUF_0/U0/U1:PIN1INT (r)
               +     0.089          cell: ADLIB:MSS_IF
  1.026                        usb_mss_0/FIO_INBUF_0/U0/U1:PIN1 (r)
               +     3.313          net: IO_0_Y
  4.339                        usb_mss_0/FIO_INBUF_0_RNI5UVF:A (r)
               +     0.331          cell: ADLIB:BUFF
  4.670                        usb_mss_0/FIO_INBUF_0_RNI5UVF:Y (r)
               +     4.021          net: IO_0_Y_0
  8.691                        usb_slave_0/GEN.4.DATA_PINS/U0/U1:E (r)
               +     0.389          cell: ADLIB:IOBI_IB_OB_EB
  9.080                        usb_slave_0/GEN.4.DATA_PINS/U0/U1:EOUT (r)
               +     0.000          net: usb_slave_0/GEN_4_DATA_PINS/U0/NET2
  9.080                        usb_slave_0/GEN.4.DATA_PINS/U0/U0:E (r)
               +     3.432          cell: ADLIB:IOPAD_BI
  12.512                       usb_slave_0/GEN.4.DATA_PINS/U0/U0:PAD (f)
               +     0.000          net: USB_DATA_PAD[4]
  12.512                       USB_DATA_PAD[4] (f)
                                    
  12.512                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          IO_0_PADIN (r)
                                    
  N/C                          USB_DATA_PAD[4] (f)
                                    
  N/C                          data required time


END SET Input to Output

----------------------------------------------------

Path set User Sets

