#  
# This is an automatically generated script file for loading the instrumented 
# design into Identify (used mostly for Identify testing purposes) 
# 
compile add -vhdl -work work  "//idm/CAE/pavan m/USB/USBeee/Using_Fabric_Master/HW_USBee/synthesis/synthesis_1/instr_sources/component/Actel/SmartFusionMSS/MSS/2.0.100/mss_comps.vhd"
compile add -vhdl -work work  "//idm/CAE/pavan m/USB/USBeee/Using_Fabric_Master/HW_USBee/synthesis/synthesis_1/instr_sources/component/work/usb_mss/MSS_CCC_0/usb_mss_tmp_MSS_CCC_0_MSS_CCC.vhd"
compile add -vhdl -work work  "//idm/CAE/pavan m/USB/USBeee/Using_Fabric_Master/HW_USBee/synthesis/synthesis_1/instr_sources/component/work/usb_mss/usb_mss.vhd"
compile add -vhdl -work work  "//idm/CAE/pavan m/USB/USBeee/Using_Fabric_Master/HW_USBee/synthesis/synthesis_1/instr_sources/smartgen/Fifo_1024/Fifo_1024.vhd"
compile add -vhdl -work work  "//idm/CAE/pavan m/USB/USBeee/Using_Fabric_Master/HW_USBee/synthesis/synthesis_1/instr_sources/hdl/usb_slave.vhd"
compile add -vhdl -work work  "//idm/CAE/pavan m/USB/USBeee/Using_Fabric_Master/HW_USBee/synthesis/synthesis_1/instr_sources/component/work/usbee_top_level/usbee_top_level.vhd"
compile add "//idm/CAE/pavan m/USB/USBeee/Using_Fabric_Master/HW_USBee/synthesis/synthesis_1/instr_sources/syn_dics.vhd"
compile toplevel work.usbee_top_level
instrumentation new synthesis_1
instrumentation load synthesis_1
device family ProASIC3E 
