-- Version: 9.0 SPC 9.0.1.10

library ieee;
use ieee.std_logic_1164.all;
library smartfusion;
use smartfusion.all;

entity Fifo_1024 is 
    port( DATA : in std_logic_vector(7 downto 0); Q : out 
        std_logic_vector(7 downto 0);WEN, REN, WCLOCK, RCLOCK : 
        in std_logic;  FULL, EMPTY : out std_logic;  RESET : in 
        std_logic;  AFULL : out std_logic; uplink_15_a : OUT std_logic_vector(0 TO 7)) ;
end Fifo_1024;


architecture DEF_ARCH of  Fifo_1024 is

    component XNOR3
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component INV
        port(A : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component DFN1C0
        port(D, CLK, CLR : in std_logic := 'U'; Q : out std_logic
        ) ;
    end component;

    component NOR3
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component AND2
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component AND3
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component XOR2
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component XNOR2
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component AO1
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component XOR3
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component DFN1E1C0
        port(D, CLK, CLR, E : in std_logic := 'U'; Q : out 
        std_logic) ;
    end component;

    component OR2
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component MX2
        port(A, B, S : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component BUFF
        port(A : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component AO1C
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component RAM4K9
    generic (MEMORYFILE:string := "");

        port(ADDRA11, ADDRA10, ADDRA9, ADDRA8, ADDRA7, ADDRA6, 
        ADDRA5, ADDRA4, ADDRA3, ADDRA2, ADDRA1, ADDRA0, ADDRB11, 
        ADDRB10, ADDRB9, ADDRB8, ADDRB7, ADDRB6, ADDRB5, ADDRB4, 
        ADDRB3, ADDRB2, ADDRB1, ADDRB0, DINA8, DINA7, DINA6, 
        DINA5, DINA4, DINA3, DINA2, DINA1, DINA0, DINB8, DINB7, 
        DINB6, DINB5, DINB4, DINB3, DINB2, DINB1, DINB0, WIDTHA0, 
        WIDTHA1, WIDTHB0, WIDTHB1, PIPEA, PIPEB, WMODEA, WMODEB, 
        BLKA, BLKB, WENA, WENB, CLKA, CLKB, RESET : in std_logic := 
        'U'; DOUTA8, DOUTA7, DOUTA6, DOUTA5, DOUTA4, DOUTA3, 
        DOUTA2, DOUTA1, DOUTA0, DOUTB8, DOUTB7, DOUTB6, DOUTB5, 
        DOUTB4, DOUTB3, DOUTB2, DOUTB1, DOUTB0 : out std_logic) ;
    end component;

    component AND2A
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component NOR3A
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component OR2A
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component NAND3A
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component OA1C
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component OR3
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component NAND2
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component OA1A
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component AOI1
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component DFN1P0
        port(D, CLK, PRE : in std_logic := 'U'; Q : out std_logic
        ) ;
    end component;

    component NOR2A
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component DFN1
        port(D, CLK : in std_logic := 'U'; Q : out std_logic) ;
    end component;

    component VCC
        port( Y : out std_logic);
    end component;

    component GND
        port( Y : out std_logic);
    end component;

    signal FULL_1_net, EMPTY_1_net, WCLOCKP, WEP, REP, 
        MEM_RADDR_0_net, RBINNXTSHIFT_0_net, WBINSYNCSHIFT_0_net, 
        MEM_WADDR_0_net, WBINNXTSHIFT_0_net, RBINSYNCSHIFT_0_net, 
        MEM_RADDR_1_net, RBINNXTSHIFT_1_net, WBINSYNCSHIFT_1_net, 
        MEM_WADDR_1_net, WBINNXTSHIFT_1_net, RBINSYNCSHIFT_1_net, 
        MEM_RADDR_2_net, RBINNXTSHIFT_2_net, WBINSYNCSHIFT_2_net, 
        MEM_WADDR_2_net, WBINNXTSHIFT_2_net, RBINSYNCSHIFT_2_net, 
        MEM_RADDR_3_net, RBINNXTSHIFT_3_net, WBINSYNCSHIFT_3_net, 
        MEM_WADDR_3_net, WBINNXTSHIFT_3_net, RBINSYNCSHIFT_3_net, 
        MEM_RADDR_4_net, RBINNXTSHIFT_4_net, WBINSYNCSHIFT_4_net, 
        MEM_WADDR_4_net, WBINNXTSHIFT_4_net, RBINSYNCSHIFT_4_net, 
        MEM_RADDR_5_net, RBINNXTSHIFT_5_net, WBINSYNCSHIFT_5_net, 
        MEM_WADDR_5_net, WBINNXTSHIFT_5_net, RBINSYNCSHIFT_5_net, 
        MEM_RADDR_6_net, RBINNXTSHIFT_6_net, WBINSYNCSHIFT_6_net, 
        MEM_WADDR_6_net, WBINNXTSHIFT_6_net, RBINSYNCSHIFT_6_net, 
        MEM_RADDR_7_net, RBINNXTSHIFT_7_net, WBINSYNCSHIFT_7_net, 
        MEM_WADDR_7_net, WBINNXTSHIFT_7_net, RBINSYNCSHIFT_7_net, 
        MEM_RADDR_8_net, RBINNXTSHIFT_8_net, WBINSYNCSHIFT_8_net, 
        MEM_WADDR_8_net, WBINNXTSHIFT_8_net, RBINSYNCSHIFT_8_net, 
        MEM_RADDR_9_net, RBINNXTSHIFT_9_net, WBINSYNCSHIFT_9_net, 
        MEM_WADDR_9_net, WBINNXTSHIFT_9_net, RBINSYNCSHIFT_9_net, 
        MEM_RADDR_10_net, RBINNXTSHIFT_10_net, READDOMAIN_WMSB, 
        MEM_WADDR_10_net, WBINNXTSHIFT_10_net, 
        RBINSYNCSHIFT_10_net, FULLINT, MEMORYWE, MEMWENEG, 
        WDIFF_0_net, WDIFF_1_net, WDIFF_2_net, WDIFF_3_net, 
        WDIFF_4_net, WDIFF_5_net, WDIFF_6_net, WDIFF_7_net, 
        WDIFF_8_net, WDIFF_9_net, WDIFF_10_net, AFVALCONST_0_net, 
        AFVALCONST_1_net, WGRY_0_net, WGRY_1_net, WGRY_2_net, 
        WGRY_3_net, WGRY_4_net, WGRY_5_net, WGRY_6_net, 
        WGRY_7_net, WGRY_8_net, WGRY_9_net, WGRY_10_net, 
        RGRYSYNC_0_net, RGRYSYNC_1_net, RGRYSYNC_2_net, 
        RGRYSYNC_3_net, RGRYSYNC_4_net, RGRYSYNC_5_net, 
        RGRYSYNC_6_net, RGRYSYNC_7_net, RGRYSYNC_8_net, 
        RGRYSYNC_9_net, RGRYSYNC_10_net, EMPTYINT, MEMORYRE, 
        MEMRENEG, DVLDI, DVLDX, RGRY_0_net, RGRY_1_net, 
        RGRY_2_net, RGRY_3_net, RGRY_4_net, RGRY_5_net, 
        RGRY_6_net, RGRY_7_net, RGRY_8_net, RGRY_9_net, 
        RGRY_10_net, WGRYSYNC_0_net, WGRYSYNC_1_net, 
        WGRYSYNC_2_net, WGRYSYNC_3_net, WGRYSYNC_4_net, 
        WGRYSYNC_5_net, WGRYSYNC_6_net, WGRYSYNC_7_net, 
        WGRYSYNC_8_net, WGRYSYNC_9_net, WGRYSYNC_10_net, 
        QXI_0_net, QXI_1_net, QXI_2_net, QXI_3_net, QXI_4_net, 
        QXI_5_net, QXI_6_net, QXI_7_net, DFN1C0_10_Q, DFN1C0_8_Q, 
        DFN1C0_9_Q, DFN1C0_20_Q, DFN1C0_4_Q, DFN1C0_18_Q, 
        DFN1C0_14_Q, DFN1C0_7_Q, DFN1C0_17_Q, DFN1C0_16_Q, 
        DFN1C0_2_Q, XNOR3_0_Y, XNOR3_4_Y, XNOR3_26_Y, XNOR3_6_Y, 
        XNOR3_21_Y, XNOR3_28_Y, XOR3_2_Y, XNOR3_2_Y, XNOR3_30_Y, 
        XNOR3_23_Y, XNOR3_3_Y, XNOR3_14_Y, XOR3_3_Y, XNOR3_1_Y, 
        XNOR3_27_Y, XOR3_6_Y, XNOR3_15_Y, XNOR3_29_Y, XOR3_7_Y, 
        XNOR3_7_Y, XOR2_12_Y, XOR2_22_Y, XOR2_47_Y, XOR2_49_Y, 
        XOR2_72_Y, XOR2_78_Y, XOR2_63_Y, XOR2_18_Y, XOR2_62_Y, 
        XOR2_34_Y, XOR2_75_Y, AND2_42_Y, AND2_17_Y, AND2_55_Y, 
        AND2_4_Y, AND2_15_Y, AND2_1_Y, AND2_38_Y, AND2_28_Y, 
        AND2_40_Y, AND2_31_Y, XOR2_65_Y, XOR2_4_Y, XOR2_7_Y, 
        XOR2_2_Y, XOR2_8_Y, XOR2_24_Y, XOR2_59_Y, XOR2_3_Y, 
        XOR2_14_Y, XOR2_73_Y, XOR2_57_Y, AND2_9_Y, AO1_39_Y, 
        AND2_23_Y, AO1_12_Y, AND2_20_Y, AO1_45_Y, AND2_65_Y, 
        AO1_41_Y, AND2_21_Y, AND2_39_Y, AO1_10_Y, AND2_58_Y, 
        AND2_51_Y, AND2_71_Y, AND2_3_Y, AND2_68_Y, AND2_0_Y, 
        AND2_77_Y, AND2_45_Y, AO1_17_Y, AND2_79_Y, AND2_74_Y, 
        AO1_20_Y, AO1_43_Y, AO1_21_Y, AO1_6_Y, AO1_0_Y, AO1_22_Y, 
        AO1_42_Y, AO1_31_Y, AO1_25_Y, XOR2_80_Y, XOR2_39_Y, 
        XOR2_37_Y, XOR2_58_Y, XOR2_81_Y, XOR2_21_Y, XOR2_76_Y, 
        XOR2_71_Y, XOR2_82_Y, XOR2_6_Y, NAND2_1_Y, XOR2_33_Y, 
        XOR2_28_Y, XOR2_17_Y, XOR2_61_Y, XOR2_53_Y, XOR2_29_Y, 
        XOR2_41_Y, XOR2_50_Y, XOR2_52_Y, XOR2_15_Y, XOR2_44_Y, 
        AND2_54_Y, AND2_10_Y, AND2_6_Y, AND2_59_Y, AND2_11_Y, 
        AND2_63_Y, AND2_14_Y, AND2_69_Y, AND2_60_Y, AND2_2_Y, 
        XOR2_38_Y, XOR2_31_Y, XOR2_16_Y, XOR2_74_Y, XOR2_70_Y, 
        XOR2_66_Y, XOR2_0_Y, XOR2_55_Y, XOR2_19_Y, XOR2_46_Y, 
        XOR2_68_Y, AND2_18_Y, AO1_28_Y, AND2_12_Y, AO1_7_Y, 
        AND2_67_Y, AO1_8_Y, AND2_66_Y, AO1_23_Y, AND2_70_Y, 
        AND2_53_Y, AO1_32_Y, AND2_7_Y, AND2_13_Y, AND2_34_Y, 
        AND2_30_Y, AND2_52_Y, AND2_48_Y, AND2_25_Y, AND2_24_Y, 
        AO1_26_Y, AND2_27_Y, AND2_32_Y, AO1_1_Y, AO1_19_Y, 
        AO1_44_Y, AO1_13_Y, AO1_36_Y, AO1_18_Y, AO1_30_Y, 
        AO1_33_Y, AO1_9_Y, XOR2_26_Y, XOR2_56_Y, XOR2_11_Y, 
        XOR2_77_Y, XOR2_83_Y, XOR2_43_Y, XOR2_67_Y, XOR2_25_Y, 
        XOR2_1_Y, XOR2_69_Y, XNOR3_16_Y, XNOR3_22_Y, XNOR3_5_Y, 
        XNOR3_24_Y, XNOR3_9_Y, XNOR3_10_Y, XOR3_0_Y, XNOR3_18_Y, 
        XNOR3_12_Y, XNOR3_13_Y, XNOR3_19_Y, XNOR3_25_Y, XOR3_1_Y, 
        XNOR3_17_Y, XNOR3_8_Y, XOR3_4_Y, XNOR3_31_Y, XNOR3_11_Y, 
        XOR3_5_Y, XNOR3_20_Y, DFN1C0_21_Q, DFN1C0_0_Q, DFN1C0_5_Q, 
        DFN1C0_13_Q, DFN1C0_3_Q, DFN1C0_11_Q, DFN1C0_15_Q, 
        DFN1C0_12_Q, DFN1C0_19_Q, DFN1C0_1_Q, DFN1C0_6_Q, MX2_4_Y, 
        MX2_7_Y, MX2_3_Y, MX2_6_Y, MX2_0_Y, MX2_1_Y, MX2_5_Y, 
        MX2_2_Y, DFN1_1_Q, DFN1_0_Q, BUFF_0_Y, INV_4_Y, BUFF_1_Y, 
        INV_11_Y, OR2_1_Y, OR2_2_Y, OR2_3_Y, OR2_4_Y, 
        RAM4K9_0_DOUTB0, RAM4K9_0_DOUTB1, RAM4K9_0_DOUTB2, 
        RAM4K9_0_DOUTB3, RAM4K9_0_DOUTB4, RAM4K9_0_DOUTB5, 
        RAM4K9_0_DOUTB6, RAM4K9_0_DOUTB7, RAM4K9_1_DOUTB0, 
        RAM4K9_1_DOUTB1, RAM4K9_1_DOUTB2, RAM4K9_1_DOUTB3, 
        RAM4K9_1_DOUTB4, RAM4K9_1_DOUTB5, RAM4K9_1_DOUTB6, 
        RAM4K9_1_DOUTB7, RAM4K9_0_DOUTA0, RAM4K9_0_DOUTA1, 
        RAM4K9_0_DOUTA2, RAM4K9_0_DOUTA3, RAM4K9_0_DOUTA4, 
        RAM4K9_0_DOUTA5, RAM4K9_0_DOUTA6, RAM4K9_0_DOUTA7, 
        RAM4K9_1_DOUTA0, RAM4K9_1_DOUTA1, RAM4K9_1_DOUTA2, 
        RAM4K9_1_DOUTA3, RAM4K9_1_DOUTA4, RAM4K9_1_DOUTA5, 
        RAM4K9_1_DOUTA6, RAM4K9_1_DOUTA7, AND2_19_Y, XNOR2_25_Y, 
        XNOR2_13_Y, XNOR2_8_Y, XNOR2_15_Y, XNOR2_16_Y, XNOR2_27_Y, 
        XNOR2_12_Y, XNOR2_21_Y, XNOR2_23_Y, XNOR2_19_Y, 
        XNOR2_11_Y, AND3_8_Y, AND3_9_Y, AND3_10_Y, AND3_6_Y, 
        NOR2A_0_Y, INV_2_Y, INV_12_Y, INV_5_Y, INV_1_Y, INV_0_Y, 
        INV_8_Y, INV_9_Y, INV_3_Y, INV_7_Y, INV_10_Y, INV_6_Y, 
        AND2_56_Y, AND2_50_Y, AND2_8_Y, AND2_80_Y, AND2_33_Y, 
        AND2_76_Y, AND2_78_Y, AND2_29_Y, AND2_16_Y, AND2_75_Y, 
        AND2_36_Y, AND2_57_Y, XOR2_9_Y, XOR2_10_Y, XOR2_5_Y, 
        XOR2_51_Y, XOR2_20_Y, XOR2_40_Y, XOR2_35_Y, XOR2_84_Y, 
        XOR2_13_Y, XOR2_79_Y, AND2_72_Y, AO1_5_Y, AND2_46_Y, 
        AO1_3_Y, AND2_41_Y, AO1_15_Y, AND2_73_Y, AO1_37_Y, 
        AND2_43_Y, AND2_61_Y, AO1_40_Y, AND2_49_Y, AND2_35_Y, 
        AND2_47_Y, AO1_14_Y, AND2_26_Y, AND2_62_Y, AND2_44_Y, 
        AND2_37_Y, AND2_64_Y, OR3_0_Y, AO1_16_Y, AO1_35_Y, 
        AO1_27_Y, AO1_29_Y, AO1_34_Y, AO1_38_Y, AO1_2_Y, AO1_4_Y, 
        XOR2_36_Y, XOR2_23_Y, XOR2_27_Y, XOR2_60_Y, XOR2_42_Y, 
        XOR2_48_Y, XOR2_30_Y, XOR2_32_Y, XOR2_64_Y, XOR2_54_Y, 
        AND2A_1_Y, AND2_22_Y, XOR2_45_Y, XNOR2_1_Y, XNOR2_20_Y, 
        XNOR2_24_Y, XNOR2_22_Y, XNOR2_0_Y, XNOR2_7_Y, XNOR2_17_Y, 
        XNOR2_9_Y, XNOR2_2_Y, XNOR2_4_Y, AND3_4_Y, AND3_1_Y, 
        AND3_3_Y, AND3_2_Y, NAND2_0_Y, AOI1_0_Y, OR2_0_Y, 
        AND3_7_Y, AO1_11_Y, AO1_24_Y, AND3_5_Y, NAND3A_2_Y, 
        NAND3A_3_Y, OR2A_4_Y, AO1C_0_Y, NOR3A_1_Y, OR2A_3_Y, 
        NAND3A_1_Y, OR2A_2_Y, AO1C_1_Y, NOR3A_0_Y, OR2A_5_Y, 
        NAND3A_0_Y, XNOR2_30_Y, XNOR2_28_Y, XNOR2_10_Y, AND2_5_Y, 
        NOR3_0_Y, NAND3A_4_Y, OR2A_0_Y, AO1C_2_Y, NOR3A_2_Y, 
        OR2A_1_Y, NAND3A_5_Y, OA1A_0_Y, AND2A_0_Y, OA1C_0_Y, 
        XNOR2_3_Y, XNOR2_29_Y, XNOR2_14_Y, XNOR2_5_Y, XNOR2_18_Y, 
        XNOR2_26_Y, XNOR2_6_Y, AND3_0_Y, VCC_1_net, GND_1_net : std_logic ;
    COMPONENT ldic5_0 PORT ( data : IN std_logic_vector(natural RANGE 7 DOWNTO 0); uplink_15 : OUT std_logic_vector(0 TO 7)); END COMPONENT; begin   

    VCC_1_net <= AFVALCONST_0_net;
    GND_1_net <= AFVALCONST_1_net;
    FULL <= FULL_1_net;
    
    EMPTY <= EMPTY_1_net;
    
    VCC_2_net : VCC port map(Y => AFVALCONST_0_net);
    GND_2_net : GND port map(Y => AFVALCONST_1_net);
    XNOR3_14 : XNOR3
      port map(A => RGRYSYNC_4_net, B => RGRYSYNC_3_net, C => 
        RGRYSYNC_2_net, Y => XNOR3_14_Y);
    INV_0 : INV
      port map(A => RBINSYNCSHIFT_5_net, Y => INV_0_Y);
    XNOR3_5 : XNOR3
      port map(A => WGRYSYNC_4_net, B => WGRYSYNC_3_net, C => 
        XNOR3_22_Y, Y => XNOR3_5_Y);
    DFN1C0_RGRYSYNC_4_inst : DFN1C0
      port map(D => DFN1C0_3_Q, CLK => WCLOCKP, CLR => RESET, 
        Q => RGRYSYNC_4_net);
    NOR3_0 : NOR3
      port map(A => OA1A_0_Y, B => AND2A_0_Y, C => OA1C_0_Y, Y => 
        NOR3_0_Y);
    AND2_2 : AND2
      port map(A => MEM_WADDR_10_net, B => GND_1_net, Y => 
        AND2_2_Y);
    AND3_6 : AND3
      port map(A => XNOR2_16_Y, B => XNOR2_27_Y, C => XNOR2_12_Y, 
        Y => AND3_6_Y);
    AND2_20 : AND2
      port map(A => XOR2_8_Y, B => XOR2_24_Y, Y => AND2_20_Y);
    XOR2_82 : XOR2
      port map(A => MEM_RADDR_9_net, B => GND_1_net, Y => 
        XOR2_82_Y);
    XNOR2_13 : XNOR2
      port map(A => RBINNXTSHIFT_0_net, B => WBINSYNCSHIFT_0_net, 
        Y => XNOR2_13_Y);
    AO1_11 : AO1
      port map(A => AND2_5_Y, B => NAND3A_4_Y, C => NOR3_0_Y, 
        Y => AO1_11_Y);
    AND2_11 : AND2
      port map(A => MEM_WADDR_5_net, B => GND_1_net, Y => 
        AND2_11_Y);
    XOR2_WBINNXTSHIFT_2_inst : XOR2
      port map(A => XOR2_56_Y, B => AO1_1_Y, Y => 
        WBINNXTSHIFT_2_net);
    XNOR3_25 : XNOR3
      port map(A => WGRYSYNC_4_net, B => WGRYSYNC_3_net, C => 
        WGRYSYNC_2_net, Y => XNOR3_25_Y);
    AND2_22 : AND2
      port map(A => AND3_1_Y, B => XNOR2_4_Y, Y => AND2_22_Y);
    XOR3_WBINSYNCSHIFT_8_inst : XOR3
      port map(A => WGRYSYNC_10_net, B => WGRYSYNC_9_net, C => 
        WGRYSYNC_8_net, Y => WBINSYNCSHIFT_8_net);
    DFN1C0_RGRY_9_inst : DFN1C0
      port map(D => XOR2_34_Y, CLK => RCLOCK, CLR => RESET, Q => 
        RGRY_9_net);
    DFN1C0_FULL : DFN1C0
      port map(D => FULLINT, CLK => WCLOCKP, CLR => RESET, Q => 
        FULL_1_net);
    XNOR2_9 : XNOR2
      port map(A => RBINSYNCSHIFT_7_net, B => WBINNXTSHIFT_7_net, 
        Y => XNOR2_9_Y);
    AND2_71 : AND2
      port map(A => AND2_39_Y, B => AND2_20_Y, Y => AND2_71_Y);
    DFN1C0_17 : DFN1C0
      port map(D => WGRY_8_net, CLK => RCLOCK, CLR => RESET, Q => 
        DFN1C0_17_Q);
    XOR2_19 : XOR2
      port map(A => MEM_WADDR_8_net, B => GND_1_net, Y => 
        XOR2_19_Y);
    AND2_44 : AND2
      port map(A => AND2_61_Y, B => XOR2_20_Y, Y => AND2_44_Y);
    AO1_31 : AO1
      port map(A => XOR2_14_Y, B => AO1_42_Y, C => AND2_28_Y, 
        Y => AO1_31_Y);
    XOR2_23 : XOR2
      port map(A => WBINNXTSHIFT_2_net, B => INV_12_Y, Y => 
        XOR2_23_Y);
    XOR2_1 : XOR2
      port map(A => MEM_WADDR_9_net, B => GND_1_net, Y => 
        XOR2_1_Y);
    DFN1E1C0_Q_1_inst : DFN1E1C0
      port map(D => QXI_1_net, CLK => RCLOCK, CLR => RESET, E => 
        DVLDI, Q => Q(1));
    XNOR3_13 : XNOR3
      port map(A => WGRYSYNC_10_net, B => WGRYSYNC_9_net, C => 
        WGRYSYNC_8_net, Y => XNOR3_13_Y);
    DFN1C0_RGRYSYNC_3_inst : DFN1C0
      port map(D => DFN1C0_13_Q, CLK => WCLOCKP, CLR => RESET, 
        Q => RGRYSYNC_3_net);
    DFN1E1C0_Q_4_inst : DFN1E1C0
      port map(D => QXI_4_net, CLK => RCLOCK, CLR => RESET, E => 
        DVLDI, Q => Q(4));
    OR2_2 : OR2
      port map(A => BUFF_1_Y, B => MEMRENEG, Y => OR2_2_Y);
    INV_1 : INV
      port map(A => RBINSYNCSHIFT_4_net, Y => INV_1_Y);
    DFN1E1C0_Q_7_inst : DFN1E1C0
      port map(D => QXI_7_net, CLK => RCLOCK, CLR => RESET, E => 
        DVLDI, Q => Q(7));
    XOR2_47 : XOR2
      port map(A => RBINNXTSHIFT_2_net, B => RBINNXTSHIFT_3_net, 
        Y => XOR2_47_Y);
    XOR2_38 : XOR2
      port map(A => MEM_WADDR_0_net, B => MEMORYWE, Y => 
        XOR2_38_Y);
    MX2_QXI_6_inst : MX2
      port map(A => RAM4K9_0_DOUTB6, B => RAM4K9_1_DOUTB6, S => 
        DFN1_0_Q, Y => QXI_6_net);
    BUFF_READDOMAIN_WMSB : BUFF
      port map(A => WGRYSYNC_10_net, Y => READDOMAIN_WMSB);
    XOR2_RBINNXTSHIFT_0_inst : XOR2
      port map(A => MEM_RADDR_0_net, B => MEMORYRE, Y => 
        RBINNXTSHIFT_0_net);
    AO1C_1 : AO1C
      port map(A => AFVALCONST_1_net, B => WDIFF_4_net, C => 
        AFVALCONST_1_net, Y => AO1C_1_Y);
    AO1_7 : AO1
      port map(A => XOR2_66_Y, B => AND2_59_Y, C => AND2_11_Y, 
        Y => AO1_7_Y);
    DFN1C0_9 : DFN1C0
      port map(D => WGRY_2_net, CLK => RCLOCK, CLR => RESET, Q => 
        DFN1C0_9_Q);
    DFN1C0_WGRY_6_inst : DFN1C0
      port map(D => XOR2_41_Y, CLK => WCLOCKP, CLR => RESET, Q => 
        WGRY_6_net);
    AND2_18 : AND2
      port map(A => XOR2_38_Y, B => XOR2_31_Y, Y => AND2_18_Y);
    AND2_15 : AND2
      port map(A => MEM_RADDR_5_net, B => GND_1_net, Y => 
        AND2_15_Y);
    INV_7 : INV
      port map(A => RBINSYNCSHIFT_9_net, Y => INV_7_Y);
    AO1_25 : AO1
      port map(A => AND2_21_Y, B => AO1_42_Y, C => AO1_41_Y, Y => 
        AO1_25_Y);
    AND2_78 : AND2
      port map(A => WBINNXTSHIFT_5_net, B => INV_0_Y, Y => 
        AND2_78_Y);
    AND2_75 : AND2
      port map(A => WBINNXTSHIFT_8_net, B => INV_3_Y, Y => 
        AND2_75_Y);
    XOR2_45 : XOR2
      port map(A => RBINSYNCSHIFT_10_net, B => 
        WBINNXTSHIFT_10_net, Y => XOR2_45_Y);
    DFN1C0_RGRYSYNC_7_inst : DFN1C0
      port map(D => DFN1C0_12_Q, CLK => WCLOCKP, CLR => RESET, 
        Q => RGRYSYNC_7_net);
    XOR2_RBINNXTSHIFT_9_inst : XOR2
      port map(A => XOR2_82_Y, B => AO1_31_Y, Y => 
        RBINNXTSHIFT_9_net);
    DFN1C0_11 : DFN1C0
      port map(D => RGRY_5_net, CLK => WCLOCKP, CLR => RESET, 
        Q => DFN1C0_11_Q);
    DFN1C0_0 : DFN1C0
      port map(D => RGRY_1_net, CLK => WCLOCKP, CLR => RESET, 
        Q => DFN1C0_0_Q);
    AND2_1 : AND2
      port map(A => MEM_RADDR_6_net, B => GND_1_net, Y => 
        AND2_1_Y);
    DFN1C0_MEM_WADDR_0_inst : DFN1C0
      port map(D => WBINNXTSHIFT_0_net, CLK => WCLOCKP, CLR => 
        RESET, Q => MEM_WADDR_0_net);
    DFN1C0_MEM_WADDR_3_inst : DFN1C0
      port map(D => WBINNXTSHIFT_3_net, CLK => WCLOCKP, CLR => 
        RESET, Q => MEM_WADDR_3_net);
    XNOR2_21 : XNOR2
      port map(A => RBINNXTSHIFT_6_net, B => WBINSYNCSHIFT_6_net, 
        Y => XNOR2_21_Y);
    AND2_49 : AND2
      port map(A => AND2_41_Y, B => AND2_73_Y, Y => AND2_49_Y);
    DFN1C0_MEM_RADDR_1_inst : DFN1C0
      port map(D => RBINNXTSHIFT_1_net, CLK => RCLOCK, CLR => 
        RESET, Q => MEM_RADDR_1_net);
    AO1_8 : AO1
      port map(A => XOR2_55_Y, B => AND2_63_Y, C => AND2_14_Y, 
        Y => AO1_8_Y);
    DFN1C0_20 : DFN1C0
      port map(D => WGRY_3_net, CLK => RCLOCK, CLR => RESET, Q => 
        DFN1C0_20_Q);
    AND2_10 : AND2
      port map(A => MEM_WADDR_2_net, B => GND_1_net, Y => 
        AND2_10_Y);
    RAM4K9_0 : RAM4K9
      port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net, 
        ADDRA9 => GND_1_net, ADDRA8 => MEM_WADDR_8_net, ADDRA7 => 
        MEM_WADDR_7_net, ADDRA6 => MEM_WADDR_6_net, ADDRA5 => 
        MEM_WADDR_5_net, ADDRA4 => MEM_WADDR_4_net, ADDRA3 => 
        MEM_WADDR_3_net, ADDRA2 => MEM_WADDR_2_net, ADDRA1 => 
        MEM_WADDR_1_net, ADDRA0 => MEM_WADDR_0_net, ADDRB11 => 
        GND_1_net, ADDRB10 => GND_1_net, ADDRB9 => GND_1_net, 
        ADDRB8 => MEM_RADDR_8_net, ADDRB7 => MEM_RADDR_7_net, 
        ADDRB6 => MEM_RADDR_6_net, ADDRB5 => MEM_RADDR_5_net, 
        ADDRB4 => MEM_RADDR_4_net, ADDRB3 => MEM_RADDR_3_net, 
        ADDRB2 => MEM_RADDR_2_net, ADDRB1 => MEM_RADDR_1_net, 
        ADDRB0 => MEM_RADDR_0_net, DINA8 => GND_1_net, DINA7 => 
        DATA(7), DINA6 => DATA(6), DINA5 => DATA(5), DINA4 => 
        DATA(4), DINA3 => DATA(3), DINA2 => DATA(2), DINA1 => 
        DATA(1), DINA0 => DATA(0), DINB8 => GND_1_net, DINB7 => 
        GND_1_net, DINB6 => GND_1_net, DINB5 => GND_1_net, 
        DINB4 => GND_1_net, DINB3 => GND_1_net, DINB2 => 
        GND_1_net, DINB1 => GND_1_net, DINB0 => GND_1_net, 
        WIDTHA0 => VCC_1_net, WIDTHA1 => VCC_1_net, WIDTHB0 => 
        VCC_1_net, WIDTHB1 => VCC_1_net, PIPEA => GND_1_net, 
        PIPEB => GND_1_net, WMODEA => GND_1_net, WMODEB => 
        GND_1_net, BLKA => OR2_1_Y, BLKB => OR2_2_Y, WENA => 
        GND_1_net, WENB => VCC_1_net, CLKA => WCLOCKP, CLKB => 
        RCLOCK, RESET => RESET, DOUTA8 => OPEN , DOUTA7 => 
        RAM4K9_0_DOUTA7, DOUTA6 => RAM4K9_0_DOUTA6, DOUTA5 => 
        RAM4K9_0_DOUTA5, DOUTA4 => RAM4K9_0_DOUTA4, DOUTA3 => 
        RAM4K9_0_DOUTA3, DOUTA2 => RAM4K9_0_DOUTA2, DOUTA1 => 
        RAM4K9_0_DOUTA1, DOUTA0 => RAM4K9_0_DOUTA0, DOUTB8 => 
        OPEN , DOUTB7 => RAM4K9_0_DOUTB7, DOUTB6 => 
        RAM4K9_0_DOUTB6, DOUTB5 => RAM4K9_0_DOUTB5, DOUTB4 => 
        RAM4K9_0_DOUTB4, DOUTB3 => RAM4K9_0_DOUTB3, DOUTB2 => 
        RAM4K9_0_DOUTB2, DOUTB1 => RAM4K9_0_DOUTB1, DOUTB0 => 
        RAM4K9_0_DOUTB0);
    DFN1C0_RGRYSYNC_6_inst : DFN1C0
      port map(D => DFN1C0_15_Q, CLK => WCLOCKP, CLR => RESET, 
        Q => RGRYSYNC_6_net);
    AND2_7 : AND2
      port map(A => AND2_67_Y, B => AND2_66_Y, Y => AND2_7_Y);
    XOR2_20 : XOR2
      port map(A => WBINNXTSHIFT_5_net, B => INV_0_Y, Y => 
        XOR2_20_Y);
    XOR2_63 : XOR2
      port map(A => RBINNXTSHIFT_6_net, B => RBINNXTSHIFT_7_net, 
        Y => XOR2_63_Y);
    AND2_70 : AND2
      port map(A => XOR2_19_Y, B => XOR2_46_Y, Y => AND2_70_Y);
    AND2A_1 : AND2A
      port map(A => EMPTY_1_net, B => REP, Y => AND2A_1_Y);
    AND2_12 : AND2
      port map(A => XOR2_16_Y, B => XOR2_74_Y, Y => AND2_12_Y);
    DFN1C0_WGRY_5_inst : DFN1C0
      port map(D => XOR2_29_Y, CLK => WCLOCKP, CLR => RESET, Q => 
        WGRY_5_net);
    AO1_42 : AO1
      port map(A => AND2_58_Y, B => AO1_21_Y, C => AO1_10_Y, Y => 
        AO1_42_Y);
    XOR2_52 : XOR2
      port map(A => WBINNXTSHIFT_8_net, B => WBINNXTSHIFT_9_net, 
        Y => XOR2_52_Y);
    AND2_72 : AND2
      port map(A => XOR2_9_Y, B => XOR2_10_Y, Y => AND2_72_Y);
    AND2_61 : AND2
      port map(A => AND2_72_Y, B => AND2_46_Y, Y => AND2_61_Y);
    DFN1C0_MEM_WADDR_4_inst : DFN1C0
      port map(D => WBINNXTSHIFT_4_net, CLK => WCLOCKP, CLR => 
        RESET, Q => MEM_WADDR_4_net);
    MX2_5 : MX2
      port map(A => RAM4K9_0_DOUTA6, B => RAM4K9_1_DOUTA6, S => 
        DFN1_1_Q, Y => MX2_5_Y);
    XOR2_WBINNXTSHIFT_0_inst : XOR2
      port map(A => MEM_WADDR_0_net, B => MEMORYWE, Y => 
        WBINNXTSHIFT_0_net);
    AO1_15 : AO1
      port map(A => XOR2_84_Y, B => AND2_16_Y, C => AND2_75_Y, 
        Y => AO1_15_Y);
    DFN1C0_WGRY_7_inst : DFN1C0
      port map(D => XOR2_50_Y, CLK => WCLOCKP, CLR => RESET, Q => 
        WGRY_7_net);
    XNOR3_WBINSYNCSHIFT_2_inst : XNOR3
      port map(A => XNOR3_13_Y, B => XNOR3_18_Y, C => XNOR3_12_Y, 
        Y => WBINSYNCSHIFT_2_net);
    AND2_EMPTYINT : AND2
      port map(A => AND2_19_Y, B => XNOR2_25_Y, Y => EMPTYINT);
    XNOR2_RBINSYNCSHIFT_5_inst : XNOR2
      port map(A => XOR3_2_Y, B => XNOR3_28_Y, Y => 
        RBINSYNCSHIFT_5_net);
    XOR2_24 : XOR2
      port map(A => MEM_RADDR_5_net, B => GND_1_net, Y => 
        XOR2_24_Y);
    AND2_57 : AND2
      port map(A => WBINNXTSHIFT_10_net, B => INV_10_Y, Y => 
        AND2_57_Y);
    XNOR3_20 : XNOR3
      port map(A => WGRYSYNC_1_net, B => WGRYSYNC_0_net, C => 
        XOR3_5_Y, Y => XNOR3_20_Y);
    MX2_QXI_0_inst : MX2
      port map(A => RAM4K9_0_DOUTB0, B => RAM4K9_1_DOUTB0, S => 
        DFN1_0_Q, Y => QXI_0_net);
    XOR2_21 : XOR2
      port map(A => MEM_RADDR_6_net, B => GND_1_net, Y => 
        XOR2_21_Y);
    NOR3A_2 : NOR3A
      port map(A => OR2A_0_Y, B => AO1C_2_Y, C => WDIFF_6_net, 
        Y => NOR3A_2_Y);
    AO1_35 : AO1
      port map(A => XOR2_5_Y, B => AO1_16_Y, C => AND2_33_Y, Y => 
        AO1_35_Y);
    XOR2_WBINNXTSHIFT_9_inst : XOR2
      port map(A => XOR2_1_Y, B => AO1_33_Y, Y => 
        WBINNXTSHIFT_9_net);
    MX2_QXI_5_inst : MX2
      port map(A => RAM4K9_0_DOUTB5, B => RAM4K9_1_DOUTB5, S => 
        DFN1_0_Q, Y => QXI_5_net);
    XOR2_WDIFF_5_inst : XOR2
      port map(A => XOR2_42_Y, B => AO1_27_Y, Y => WDIFF_5_net);
    INV_11 : INV
      port map(A => MEM_RADDR_9_net, Y => INV_11_Y);
    AND2_46 : AND2
      port map(A => XOR2_5_Y, B => XOR2_51_Y, Y => AND2_46_Y);
    XNOR2_28 : XNOR2
      port map(A => WDIFF_4_net, B => AFVALCONST_1_net, Y => 
        XNOR2_28_Y);
    XOR2_RBINNXTSHIFT_8_inst : XOR2
      port map(A => XOR2_71_Y, B => AO1_42_Y, Y => 
        RBINNXTSHIFT_8_net);
    XNOR2_RBINSYNCSHIFT_1_inst : XNOR2
      port map(A => XNOR3_14_Y, B => XNOR3_1_Y, Y => 
        RBINSYNCSHIFT_1_net);
    XNOR3_9 : XNOR3
      port map(A => WGRYSYNC_10_net, B => WGRYSYNC_9_net, C => 
        WGRYSYNC_8_net, Y => XNOR3_9_Y);
    XNOR3_8 : XNOR3
      port map(A => WGRYSYNC_7_net, B => WGRYSYNC_6_net, C => 
        WGRYSYNC_5_net, Y => XNOR3_8_Y);
    XOR2_16 : XOR2
      port map(A => MEM_WADDR_2_net, B => GND_1_net, Y => 
        XOR2_16_Y);
    DFN1C0_4 : DFN1C0
      port map(D => WGRY_4_net, CLK => RCLOCK, CLR => RESET, Q => 
        DFN1C0_4_Q);
    OR2_4 : OR2
      port map(A => INV_11_Y, B => MEMRENEG, Y => OR2_4_Y);
    XOR2_60 : XOR2
      port map(A => WBINNXTSHIFT_4_net, B => INV_1_Y, Y => 
        XOR2_60_Y);
    DFN1C0_14 : DFN1C0
      port map(D => WGRY_6_net, CLK => RCLOCK, CLR => RESET, Q => 
        DFN1C0_14_Q);
    AND2_68 : AND2
      port map(A => AND2_9_Y, B => XOR2_7_Y, Y => AND2_68_Y);
    AND2_65 : AND2
      port map(A => XOR2_59_Y, B => XOR2_3_Y, Y => AND2_65_Y);
    AND2_43 : AND2
      port map(A => XOR2_13_Y, B => XOR2_79_Y, Y => AND2_43_Y);
    AO1_24 : AO1
      port map(A => AND3_5_Y, B => NAND3A_3_Y, C => NAND3A_2_Y, 
        Y => AO1_24_Y);
    AND3_3 : AND3
      port map(A => XNOR2_17_Y, B => XNOR2_9_Y, C => XNOR2_2_Y, 
        Y => AND3_3_Y);
    INV_5 : INV
      port map(A => RBINSYNCSHIFT_3_net, Y => INV_5_Y);
    OR2_0 : OR2
      port map(A => AOI1_0_Y, B => FULL_1_net, Y => OR2_0_Y);
    MEMWEBUBBLE : INV
      port map(A => MEMORYWE, Y => MEMWENEG);
    AND2_6 : AND2
      port map(A => MEM_WADDR_3_net, B => GND_1_net, Y => 
        AND2_6_Y);
    XOR2_64 : XOR2
      port map(A => WBINNXTSHIFT_9_net, B => INV_7_Y, Y => 
        XOR2_64_Y);
    AND3_0 : AND3
      port map(A => XNOR2_14_Y, B => XNOR2_5_Y, C => XNOR2_18_Y, 
        Y => AND3_0_Y);
    DFN1C0_MEM_RADDR_2_inst : DFN1C0
      port map(D => RBINNXTSHIFT_2_net, CLK => RCLOCK, CLR => 
        RESET, Q => MEM_RADDR_2_net);
    AND2_60 : AND2
      port map(A => MEM_WADDR_9_net, B => GND_1_net, Y => 
        AND2_60_Y);
    XOR2_61 : XOR2
      port map(A => WBINNXTSHIFT_3_net, B => WBINNXTSHIFT_4_net, 
        Y => XOR2_61_Y);
    OR2A_4 : OR2A
      port map(A => WDIFF_2_net, B => AFVALCONST_1_net, Y => 
        OR2A_4_Y);
    XOR2_57 : XOR2
      port map(A => MEM_RADDR_10_net, B => GND_1_net, Y => 
        XOR2_57_Y);
    DFN1C0_RGRY_2_inst : DFN1C0
      port map(D => XOR2_47_Y, CLK => RCLOCK, CLR => RESET, Q => 
        RGRY_2_net);
    AND2_62 : AND2
      port map(A => AND2_72_Y, B => XOR2_5_Y, Y => AND2_62_Y);
    XOR2_33 : XOR2
      port map(A => WBINNXTSHIFT_0_net, B => WBINNXTSHIFT_1_net, 
        Y => XOR2_33_Y);
    INV_3 : INV
      port map(A => RBINSYNCSHIFT_8_net, Y => INV_3_Y);
    XNOR2_2 : XNOR2
      port map(A => RBINSYNCSHIFT_8_net, B => WBINNXTSHIFT_8_net, 
        Y => XNOR2_2_Y);
    XOR2_WBINNXTSHIFT_8_inst : XOR2
      port map(A => XOR2_25_Y, B => AO1_30_Y, Y => 
        WBINNXTSHIFT_8_net);
    XNOR2_19 : XNOR2
      port map(A => RBINNXTSHIFT_8_net, B => WBINSYNCSHIFT_8_net, 
        Y => XNOR2_19_Y);
    XOR2_49 : XOR2
      port map(A => RBINNXTSHIFT_3_net, B => RBINNXTSHIFT_4_net, 
        Y => XOR2_49_Y);
    AO1_14 : AO1
      port map(A => AND2_43_Y, B => AO1_2_Y, C => AO1_37_Y, Y => 
        AO1_14_Y);
    XOR2_RBINSYNCSHIFT_9_inst : XOR2
      port map(A => RGRYSYNC_10_net, B => RGRYSYNC_9_net, Y => 
        RBINSYNCSHIFT_9_net);
    XOR2_4 : XOR2
      port map(A => MEM_RADDR_1_net, B => GND_1_net, Y => 
        XOR2_4_Y);
    XOR2_WDIFF_0_inst : XOR2
      port map(A => WBINNXTSHIFT_0_net, B => RBINSYNCSHIFT_0_net, 
        Y => WDIFF_0_net);
    AND3_1 : AND3
      port map(A => AND3_3_Y, B => AND3_4_Y, C => AND3_2_Y, Y => 
        AND3_1_Y);
    XNOR2_WBINSYNCSHIFT_3_inst : XNOR2
      port map(A => XNOR3_16_Y, B => XNOR3_5_Y, Y => 
        WBINSYNCSHIFT_3_net);
    AND3_10 : AND3
      port map(A => XNOR2_21_Y, B => XNOR2_23_Y, C => XNOR2_19_Y, 
        Y => AND3_10_Y);
    XOR2_55 : XOR2
      port map(A => MEM_WADDR_7_net, B => GND_1_net, Y => 
        XOR2_55_Y);
    AND2_24 : AND2
      port map(A => AND2_13_Y, B => XOR2_19_Y, Y => AND2_24_Y);
    XOR2_72 : XOR2
      port map(A => RBINNXTSHIFT_4_net, B => RBINNXTSHIFT_5_net, 
        Y => XOR2_72_Y);
    AO1_40 : AO1
      port map(A => AND2_73_Y, B => AO1_3_Y, C => AO1_15_Y, Y => 
        AO1_40_Y);
    XNOR2_0 : XNOR2
      port map(A => RBINSYNCSHIFT_4_net, B => WBINNXTSHIFT_4_net, 
        Y => XNOR2_0_Y);
    OR2A_3 : OR2A
      port map(A => AFVALCONST_1_net, B => WDIFF_2_net, Y => 
        OR2A_3_Y);
    AND2_31 : AND2
      port map(A => MEM_RADDR_10_net, B => GND_1_net, Y => 
        AND2_31_Y);
    DFN1C0_MEM_WADDR_10_inst : DFN1C0
      port map(D => WBINNXTSHIFT_10_net, CLK => WCLOCKP, CLR => 
        RESET, Q => MEM_WADDR_10_net);
    DFN1C0_15 : DFN1C0
      port map(D => RGRY_6_net, CLK => WCLOCKP, CLR => RESET, 
        Q => DFN1C0_15_Q);
    AO1_34 : AO1
      port map(A => AND2_41_Y, B => AO1_27_Y, C => AO1_3_Y, Y => 
        AO1_34_Y);
    DFN1C0_12 : DFN1C0
      port map(D => RGRY_7_net, CLK => WCLOCKP, CLR => RESET, 
        Q => DFN1C0_12_Q);
    XNOR3_19 : XNOR3
      port map(A => WGRYSYNC_7_net, B => WGRYSYNC_6_net, C => 
        WGRYSYNC_5_net, Y => XNOR3_19_Y);
    XOR2_18 : XOR2
      port map(A => RBINNXTSHIFT_7_net, B => RBINNXTSHIFT_8_net, 
        Y => XOR2_18_Y);
    XNOR2_25 : XNOR2
      port map(A => RBINNXTSHIFT_10_net, B => READDOMAIN_WMSB, 
        Y => XNOR2_25_Y);
    XOR2_RBINNXTSHIFT_4_inst : XOR2
      port map(A => XOR2_58_Y, B => AO1_21_Y, Y => 
        RBINNXTSHIFT_4_net);
    DFN1C0_WGRYSYNC_9_inst : DFN1C0
      port map(D => DFN1C0_16_Q, CLK => RCLOCK, CLR => RESET, 
        Q => WGRYSYNC_9_net);
    XNOR3_22 : XNOR3
      port map(A => WGRYSYNC_10_net, B => WGRYSYNC_9_net, C => 
        WGRYSYNC_8_net, Y => XNOR3_22_Y);
    DFN1C0_MEM_WADDR_8_inst : DFN1C0
      port map(D => WBINNXTSHIFT_8_net, CLK => WCLOCKP, CLR => 
        RESET, Q => MEM_WADDR_8_net);
    DFN1C0_RGRY_1_inst : DFN1C0
      port map(D => XOR2_22_Y, CLK => RCLOCK, CLR => RESET, Q => 
        RGRY_1_net);
    DFN1C0_RGRYSYNC_5_inst : DFN1C0
      port map(D => DFN1C0_11_Q, CLK => WCLOCKP, CLR => RESET, 
        Q => RGRYSYNC_5_net);
    DFN1C0_WGRY_3_inst : DFN1C0
      port map(D => XOR2_61_Y, CLK => WCLOCKP, CLR => RESET, Q => 
        WGRY_3_net);
    DFN1E1C0_Q_6_inst : DFN1E1C0
      port map(D => QXI_6_net, CLK => RCLOCK, CLR => RESET, E => 
        DVLDI, Q => Q(6));
    XOR2_8 : XOR2
      port map(A => MEM_RADDR_4_net, B => GND_1_net, Y => 
        XOR2_8_Y);
    NAND3A_0 : NAND3A
      port map(A => WDIFF_4_net, B => AFVALCONST_1_net, C => 
        OR2A_2_Y, Y => NAND3A_0_Y);
    AO1_43 : AO1
      port map(A => XOR2_7_Y, B => AO1_20_Y, C => AND2_17_Y, Y => 
        AO1_43_Y);
    XOR2_RBINNXTSHIFT_6_inst : XOR2
      port map(A => XOR2_21_Y, B => AO1_0_Y, Y => 
        RBINNXTSHIFT_6_net);
    XOR2_30 : XOR2
      port map(A => WBINNXTSHIFT_7_net, B => INV_9_Y, Y => 
        XOR2_30_Y);
    OR2A_2 : OR2A
      port map(A => WDIFF_5_net, B => AFVALCONST_1_net, Y => 
        OR2A_2_Y);
    AND2_38 : AND2
      port map(A => MEM_RADDR_7_net, B => GND_1_net, Y => 
        AND2_38_Y);
    AND2_35 : AND2
      port map(A => AND2_61_Y, B => AND2_49_Y, Y => AND2_35_Y);
    MEMREBUBBLE : INV
      port map(A => MEMORYRE, Y => MEMRENEG);
    DFN1C0_MEM_WADDR_7_inst : DFN1C0
      port map(D => WBINNXTSHIFT_7_net, CLK => WCLOCKP, CLR => 
        RESET, Q => MEM_WADDR_7_net);
    AND2_29 : AND2
      port map(A => WBINNXTSHIFT_6_net, B => INV_8_Y, Y => 
        AND2_29_Y);
    DFN1C0_MEM_RADDR_4_inst : DFN1C0
      port map(D => RBINNXTSHIFT_4_net, CLK => RCLOCK, CLR => 
        RESET, Q => MEM_RADDR_4_net);
    XNOR3_7 : XNOR3
      port map(A => RGRYSYNC_1_net, B => RGRYSYNC_0_net, C => 
        XOR3_7_Y, Y => XNOR3_7_Y);
    XOR2_34 : XOR2
      port map(A => RBINNXTSHIFT_9_net, B => RBINNXTSHIFT_10_net, 
        Y => XOR2_34_Y);
    XOR2_31 : XOR2
      port map(A => MEM_WADDR_1_net, B => GND_1_net, Y => 
        XOR2_31_Y);
    WEBUBBLE : INV
      port map(A => WEN, Y => WEP);
    AND2_3 : AND2
      port map(A => AND2_51_Y, B => AND2_21_Y, Y => AND2_3_Y);
    AND2_30 : AND2
      port map(A => AND2_13_Y, B => AND2_70_Y, Y => AND2_30_Y);
    XNOR3_26 : XNOR3
      port map(A => RGRYSYNC_4_net, B => RGRYSYNC_3_net, C => 
        XNOR3_4_Y, Y => XNOR3_26_Y);
    XOR2_WBINNXTSHIFT_4_inst : XOR2
      port map(A => XOR2_77_Y, B => AO1_44_Y, Y => 
        WBINNXTSHIFT_4_net);
    XNOR2_6 : XNOR2
      port map(A => AFVALCONST_1_net, B => WDIFF_10_net, Y => 
        XNOR2_6_Y);
    AND2_14 : AND2
      port map(A => MEM_WADDR_7_net, B => GND_1_net, Y => 
        AND2_14_Y);
    OA1C_0 : OA1C
      port map(A => AFVALCONST_1_net, B => WDIFF_9_net, C => 
        AFVALCONST_1_net, Y => OA1C_0_Y);
    INV_4 : INV
      port map(A => MEM_WADDR_9_net, Y => INV_4_Y);
    AND2_74 : AND2
      port map(A => MEM_RADDR_0_net, B => MEMORYRE, Y => 
        AND2_74_Y);
    XOR2_77 : XOR2
      port map(A => MEM_WADDR_4_net, B => GND_1_net, Y => 
        XOR2_77_Y);
    BUFF_RBINSYNCSHIFT_10_inst : BUFF
      port map(A => RGRYSYNC_10_net, Y => RBINSYNCSHIFT_10_net);
    AND2_32 : AND2
      port map(A => MEM_WADDR_0_net, B => MEMORYWE, Y => 
        AND2_32_Y);
    OR2A_1 : OR2A
      port map(A => AFVALCONST_1_net, B => WDIFF_8_net, Y => 
        OR2A_1_Y);
    DFN1C0_MEM_RADDR_5_inst : DFN1C0
      port map(D => RBINNXTSHIFT_5_net, CLK => RCLOCK, CLR => 
        RESET, Q => MEM_RADDR_5_net);
    XOR2_WBINNXTSHIFT_6_inst : XOR2
      port map(A => XOR2_43_Y, B => AO1_36_Y, Y => 
        WBINNXTSHIFT_6_net);
    AND3_8 : AND3
      port map(A => XNOR2_13_Y, B => XNOR2_8_Y, C => XNOR2_15_Y, 
        Y => AND3_8_Y);
    NAND3A_2 : NAND3A
      port map(A => NOR3A_0_Y, B => OR2A_5_Y, C => NAND3A_0_Y, 
        Y => NAND3A_2_Y);
    XOR3_4 : XOR3
      port map(A => WGRYSYNC_10_net, B => WGRYSYNC_9_net, C => 
        WGRYSYNC_8_net, Y => XOR3_4_Y);
    XOR2_46 : XOR2
      port map(A => MEM_WADDR_9_net, B => GND_1_net, Y => 
        XOR2_46_Y);
    XNOR2_11 : XNOR2
      port map(A => RBINNXTSHIFT_9_net, B => WBINSYNCSHIFT_9_net, 
        Y => XNOR2_11_Y);
    AO1_2 : AO1
      port map(A => AND2_49_Y, B => AO1_27_Y, C => AO1_40_Y, Y => 
        AO1_2_Y);
    DFN1C0_MEM_RADDR_8_inst : DFN1C0
      port map(D => RBINNXTSHIFT_8_net, CLK => RCLOCK, CLR => 
        RESET, Q => MEM_RADDR_8_net);
    DFN1C0_WGRY_0_inst : DFN1C0
      port map(D => XOR2_33_Y, CLK => WCLOCKP, CLR => RESET, Q => 
        WGRY_0_net);
    XOR2_75 : XOR2
      port map(A => RBINNXTSHIFT_10_net, B => GND_1_net, Y => 
        XOR2_75_Y);
    AND2_26 : AND2
      port map(A => AND2_35_Y, B => AND2_43_Y, Y => AND2_26_Y);
    XOR2_9 : XOR2
      port map(A => WBINNXTSHIFT_1_net, B => INV_2_Y, Y => 
        XOR2_9_Y);
    AND3_5 : AND3
      port map(A => XNOR2_30_Y, B => XNOR2_28_Y, C => XNOR2_10_Y, 
        Y => AND3_5_Y);
    XOR2_WDIFF_2_inst : XOR2
      port map(A => XOR2_23_Y, B => OR3_0_Y, Y => WDIFF_2_net);
    XNOR2_WBINSYNCSHIFT_5_inst : XNOR2
      port map(A => XOR3_0_Y, B => XNOR3_10_Y, Y => 
        WBINSYNCSHIFT_5_net);
    INV_12 : INV
      port map(A => RBINSYNCSHIFT_2_net, Y => INV_12_Y);
    XOR2_59 : XOR2
      port map(A => MEM_RADDR_6_net, B => GND_1_net, Y => 
        XOR2_59_Y);
    AND2_23 : AND2
      port map(A => XOR2_7_Y, B => XOR2_2_Y, Y => AND2_23_Y);
    DFN1C0_MEM_WADDR_9_inst : DFN1C0
      port map(D => WBINNXTSHIFT_9_net, CLK => WCLOCKP, CLR => 
        RESET, Q => MEM_WADDR_9_net);
    DFN1C0_WGRYSYNC_1_inst : DFN1C0
      port map(D => DFN1C0_8_Q, CLK => RCLOCK, CLR => RESET, Q => 
        WGRYSYNC_1_net);
    XNOR2_4 : XNOR2
      port map(A => RBINSYNCSHIFT_9_net, B => WBINNXTSHIFT_9_net, 
        Y => XNOR2_4_Y);
    DFN1C0_RGRY_8_inst : DFN1C0
      port map(D => XOR2_62_Y, CLK => RCLOCK, CLR => RESET, Q => 
        RGRY_8_net);
    XOR2_5 : XOR2
      port map(A => WBINNXTSHIFT_3_net, B => INV_5_Y, Y => 
        XOR2_5_Y);
    XNOR2_20 : XNOR2
      port map(A => RBINSYNCSHIFT_1_net, B => WBINNXTSHIFT_1_net, 
        Y => XNOR2_20_Y);
    MX2_0 : MX2
      port map(A => RAM4K9_0_DOUTA4, B => RAM4K9_1_DOUTA4, S => 
        DFN1_1_Q, Y => MX2_0_Y);
    DFN1C0_16 : DFN1C0
      port map(D => WGRY_9_net, CLK => RCLOCK, CLR => RESET, Q => 
        DFN1C0_16_Q);
    XNOR3_11 : XNOR3
      port map(A => WGRYSYNC_4_net, B => WGRYSYNC_3_net, C => 
        WGRYSYNC_2_net, Y => XNOR3_11_Y);
    AO1_28 : AO1
      port map(A => XOR2_74_Y, B => AND2_10_Y, C => AND2_6_Y, 
        Y => AO1_28_Y);
    AND2_19 : AND2
      port map(A => AND3_9_Y, B => XNOR2_11_Y, Y => AND2_19_Y);
    DFN1C0_6 : DFN1C0
      port map(D => RGRY_10_net, CLK => WCLOCKP, CLR => RESET, 
        Q => DFN1C0_6_Q);
    MX2_QXI_1_inst : MX2
      port map(A => RAM4K9_0_DOUTB1, B => RAM4K9_1_DOUTB1, S => 
        DFN1_0_Q, Y => QXI_1_net);
    MX2_QXI_3_inst : MX2
      port map(A => RAM4K9_0_DOUTB3, B => RAM4K9_1_DOUTB3, S => 
        DFN1_0_Q, Y => QXI_3_net);
    AND2_79 : AND2
      port map(A => AND2_3_Y, B => XOR2_57_Y, Y => AND2_79_Y);
    XNOR2_WBINSYNCSHIFT_7_inst : XNOR2
      port map(A => WGRYSYNC_7_net, B => XNOR3_9_Y, Y => 
        WBINSYNCSHIFT_7_net);
    DFN1C0_MEM_RADDR_6_inst : DFN1C0
      port map(D => RBINNXTSHIFT_6_net, CLK => RCLOCK, CLR => 
        RESET, Q => MEM_RADDR_6_net);
    DFN1E1C0_Q_0_inst : DFN1E1C0
      port map(D => QXI_0_net, CLK => RCLOCK, CLR => RESET, E => 
        DVLDI, Q => Q(0));
    XNOR3_27 : XNOR3
      port map(A => RGRYSYNC_7_net, B => RGRYSYNC_6_net, C => 
        RGRYSYNC_5_net, Y => XNOR3_27_Y);
    XOR2_22 : XOR2
      port map(A => RBINNXTSHIFT_1_net, B => RBINNXTSHIFT_2_net, 
        Y => XOR2_22_Y);
    AO1_1 : AO1
      port map(A => XOR2_31_Y, B => AND2_32_Y, C => AND2_54_Y, 
        Y => AO1_1_Y);
    DFN1C0_10 : DFN1C0
      port map(D => WGRY_0_net, CLK => RCLOCK, CLR => RESET, Q => 
        DFN1C0_10_Q);
    XOR2_13 : XOR2
      port map(A => WBINNXTSHIFT_9_net, B => INV_7_Y, Y => 
        XOR2_13_Y);
    DFN1C0_WGRYSYNC_2_inst : DFN1C0
      port map(D => DFN1C0_9_Q, CLK => RCLOCK, CLR => RESET, Q => 
        WGRYSYNC_2_net);
    XNOR3_31 : XNOR3
      port map(A => WGRYSYNC_7_net, B => WGRYSYNC_6_net, C => 
        WGRYSYNC_5_net, Y => XNOR3_31_Y);
    INV_6 : INV
      port map(A => NOR2A_0_Y, Y => INV_6_Y);
    DFN1C0_WGRYSYNC_0_inst : DFN1C0
      port map(D => DFN1C0_10_Q, CLK => RCLOCK, CLR => RESET, 
        Q => WGRYSYNC_0_net);
    XNOR2_18 : XNOR2
      port map(A => AFVALCONST_1_net, B => WDIFF_8_net, Y => 
        XNOR2_18_Y);
    AND2_51 : AND2
      port map(A => AND2_39_Y, B => AND2_58_Y, Y => AND2_51_Y);
    REBUBBLE : INV
      port map(A => REN, Y => REP);
    AO1_3 : AO1
      port map(A => XOR2_40_Y, B => AND2_78_Y, C => AND2_29_Y, 
        Y => AO1_3_Y);
    AND2_64 : AND2
      port map(A => AND2_35_Y, B => XOR2_13_Y, Y => AND2_64_Y);
    AND2_47 : AND2
      port map(A => AND2_61_Y, B => AND2_41_Y, Y => AND2_47_Y);
    AO1_18 : AO1
      port map(A => XOR2_0_Y, B => AO1_36_Y, C => AND2_63_Y, Y => 
        AO1_18_Y);
    XOR2_48 : XOR2
      port map(A => WBINNXTSHIFT_6_net, B => INV_8_Y, Y => 
        XOR2_48_Y);
    XOR2_RBINNXTSHIFT_3_inst : XOR2
      port map(A => XOR2_37_Y, B => AO1_43_Y, Y => 
        RBINNXTSHIFT_3_net);
    DFN1C0_3 : DFN1C0
      port map(D => RGRY_4_net, CLK => WCLOCKP, CLR => RESET, 
        Q => DFN1C0_3_Q);
    AO1C_0 : AO1C
      port map(A => AFVALCONST_1_net, B => WDIFF_1_net, C => 
        AFVALCONST_0_net, Y => AO1C_0_Y);
    DFN1C0_MEM_RADDR_7_inst : DFN1C0
      port map(D => RBINNXTSHIFT_7_net, CLK => RCLOCK, CLR => 
        RESET, Q => MEM_RADDR_7_net);
    XNOR3_18 : XNOR3
      port map(A => WGRYSYNC_7_net, B => WGRYSYNC_6_net, C => 
        WGRYSYNC_5_net, Y => XNOR3_18_Y);
    AND2_16 : AND2
      port map(A => WBINNXTSHIFT_7_net, B => INV_9_Y, Y => 
        AND2_16_Y);
    XNOR3_24 : XNOR3
      port map(A => WGRYSYNC_10_net, B => WGRYSYNC_9_net, C => 
        WGRYSYNC_8_net, Y => XNOR3_24_Y);
    XOR2_WDIFF_3_inst : XOR2
      port map(A => XOR2_27_Y, B => AO1_16_Y, Y => WDIFF_3_net);
    AND2_76 : AND2
      port map(A => WBINNXTSHIFT_4_net, B => INV_1_Y, Y => 
        AND2_76_Y);
    OR2A_5 : OR2A
      port map(A => AFVALCONST_1_net, B => WDIFF_5_net, Y => 
        OR2A_5_Y);
    AO1_38 : AO1
      port map(A => XOR2_35_Y, B => AO1_34_Y, C => AND2_16_Y, 
        Y => AO1_38_Y);
    DFN1C0_WGRY_9_inst : DFN1C0
      port map(D => XOR2_15_Y, CLK => WCLOCKP, CLR => RESET, Q => 
        WGRY_9_net);
    XOR2_62 : XOR2
      port map(A => RBINNXTSHIFT_8_net, B => RBINNXTSHIFT_9_net, 
        Y => XOR2_62_Y);
    AND2_13 : AND2
      port map(A => AND2_53_Y, B => AND2_7_Y, Y => AND2_13_Y);
    DFN1C0_18 : DFN1C0
      port map(D => WGRY_5_net, CLK => RCLOCK, CLR => RESET, Q => 
        DFN1C0_18_Q);
    AND2_73 : AND2
      port map(A => XOR2_35_Y, B => XOR2_84_Y, Y => AND2_73_Y);
    XOR2_10 : XOR2
      port map(A => WBINNXTSHIFT_2_net, B => INV_12_Y, Y => 
        XOR2_10_Y);
    XNOR2_1 : XNOR2
      port map(A => RBINSYNCSHIFT_0_net, B => WBINNXTSHIFT_0_net, 
        Y => XNOR2_1_Y);
    AND2_58 : AND2
      port map(A => AND2_20_Y, B => AND2_65_Y, Y => AND2_58_Y);
    AND2_55 : AND2
      port map(A => MEM_RADDR_3_net, B => GND_1_net, Y => 
        AND2_55_Y);
    INV_8 : INV
      port map(A => RBINSYNCSHIFT_6_net, Y => INV_8_Y);
    MX2_2 : MX2
      port map(A => RAM4K9_0_DOUTA7, B => RAM4K9_1_DOUTA7, S => 
        DFN1_1_Q, Y => MX2_2_Y);
    XNOR3_6 : XNOR3
      port map(A => RGRYSYNC_10_net, B => RGRYSYNC_9_net, C => 
        RGRYSYNC_8_net, Y => XNOR3_6_Y);
    DFN1C0_RGRY_4_inst : DFN1C0
      port map(D => XOR2_72_Y, CLK => RCLOCK, CLR => RESET, Q => 
        RGRY_4_net);
    DFN1C0_2 : DFN1C0
      port map(D => WGRY_10_net, CLK => RCLOCK, CLR => RESET, 
        Q => DFN1C0_2_Q);
    AND2_69 : AND2
      port map(A => MEM_WADDR_8_net, B => GND_1_net, Y => 
        AND2_69_Y);
    DFN1C0_MEM_WADDR_2_inst : DFN1C0
      port map(D => WBINNXTSHIFT_2_net, CLK => WCLOCKP, CLR => 
        RESET, Q => MEM_WADDR_2_net);
    XOR2_79 : XOR2
      port map(A => WBINNXTSHIFT_10_net, B => INV_10_Y, Y => 
        XOR2_79_Y);
    XOR2_27 : XOR2
      port map(A => WBINNXTSHIFT_3_net, B => INV_5_Y, Y => 
        XOR2_27_Y);
    XOR3_3 : XOR3
      port map(A => RGRYSYNC_10_net, B => RGRYSYNC_9_net, C => 
        RGRYSYNC_8_net, Y => XOR3_3_Y);
    AND2_MEMORYRE : AND2
      port map(A => NAND2_1_Y, B => REP, Y => MEMORYRE);
    XOR2_WBINNXTSHIFT_3_inst : XOR2
      port map(A => XOR2_11_Y, B => AO1_19_Y, Y => 
        WBINNXTSHIFT_3_net);
    XOR2_7 : XOR2
      port map(A => MEM_RADDR_2_net, B => GND_1_net, Y => 
        XOR2_7_Y);
    AND2_5 : AND2
      port map(A => XNOR2_3_Y, B => XNOR2_29_Y, Y => AND2_5_Y);
    XOR2_56 : XOR2
      port map(A => MEM_WADDR_2_net, B => GND_1_net, Y => 
        XOR2_56_Y);
    XOR2_14 : XOR2
      port map(A => MEM_RADDR_8_net, B => GND_1_net, Y => 
        XOR2_14_Y);
    XNOR3_23 : XNOR3
      port map(A => RGRYSYNC_10_net, B => RGRYSYNC_9_net, C => 
        RGRYSYNC_8_net, Y => XNOR3_23_Y);
    AND2_50 : AND2
      port map(A => WBINNXTSHIFT_1_net, B => INV_6_Y, Y => 
        AND2_50_Y);
    XNOR3_1 : XNOR3
      port map(A => RGRYSYNC_1_net, B => XOR3_3_Y, C => XNOR3_3_Y, 
        Y => XNOR3_1_Y);
    DFN1C0_7 : DFN1C0
      port map(D => WGRY_7_net, CLK => RCLOCK, CLR => RESET, Q => 
        DFN1C0_7_Q);
    XNOR2_3 : XNOR2
      port map(A => WDIFF_9_net, B => AFVALCONST_1_net, Y => 
        XNOR2_3_Y);
    XOR2_11 : XOR2
      port map(A => MEM_WADDR_3_net, B => GND_1_net, Y => 
        XOR2_11_Y);
    XNOR2_22 : XNOR2
      port map(A => RBINSYNCSHIFT_3_net, B => WBINNXTSHIFT_3_net, 
        Y => XNOR2_22_Y);
    NAND3A_3 : NAND3A
      port map(A => NOR3A_1_Y, B => OR2A_3_Y, C => NAND3A_1_Y, 
        Y => NAND3A_3_Y);
    AND2_52 : AND2
      port map(A => AND2_18_Y, B => XOR2_16_Y, Y => AND2_52_Y);
    XOR3_6 : XOR3
      port map(A => RGRYSYNC_10_net, B => RGRYSYNC_9_net, C => 
        RGRYSYNC_8_net, Y => XOR3_6_Y);
    XOR2_25 : XOR2
      port map(A => MEM_WADDR_8_net, B => GND_1_net, Y => 
        XOR2_25_Y);
    XNOR2_15 : XNOR2
      port map(A => RBINNXTSHIFT_2_net, B => WBINSYNCSHIFT_2_net, 
        Y => XNOR2_15_Y);
    AO1_22 : AO1
      port map(A => XOR2_59_Y, B => AO1_0_Y, C => AND2_1_Y, Y => 
        AO1_22_Y);
    BUFF_0 : BUFF
      port map(A => MEM_WADDR_9_net, Y => BUFF_0_Y);
    XNOR3_3 : XNOR3
      port map(A => RGRYSYNC_7_net, B => RGRYSYNC_6_net, C => 
        RGRYSYNC_5_net, Y => XNOR3_3_Y);
    XNOR2_RBINSYNCSHIFT_7_inst : XNOR2
      port map(A => RGRYSYNC_7_net, B => XNOR3_21_Y, Y => 
        RBINSYNCSHIFT_7_net);
    DFN1C0_RGRYSYNC_10_inst : DFN1C0
      port map(D => DFN1C0_6_Q, CLK => WCLOCKP, CLR => RESET, 
        Q => RGRYSYNC_10_net);
    MX2_QXI_7_inst : MX2
      port map(A => RAM4K9_0_DOUTB7, B => RAM4K9_1_DOUTB7, S => 
        DFN1_0_Q, Y => QXI_7_net);
    DFN1C0_RGRYSYNC_9_inst : DFN1C0
      port map(D => DFN1C0_1_Q, CLK => WCLOCKP, CLR => RESET, 
        Q => RGRYSYNC_9_net);
    AND2_34 : AND2
      port map(A => AND2_53_Y, B => AND2_67_Y, Y => AND2_34_Y);
    AND2_66 : AND2
      port map(A => XOR2_0_Y, B => XOR2_55_Y, Y => AND2_66_Y);
    AO1_41 : AO1
      port map(A => XOR2_73_Y, B => AND2_28_Y, C => AND2_40_Y, 
        Y => AO1_41_Y);
    AO1_6 : AO1
      port map(A => XOR2_8_Y, B => AO1_21_Y, C => AND2_4_Y, Y => 
        AO1_6_Y);
    XNOR3_15 : XNOR3
      port map(A => RGRYSYNC_7_net, B => RGRYSYNC_6_net, C => 
        RGRYSYNC_5_net, Y => XNOR3_15_Y);
    DFN1C0_MEM_RADDR_3_inst : DFN1C0
      port map(D => RBINNXTSHIFT_3_net, CLK => RCLOCK, CLR => 
        RESET, Q => MEM_RADDR_3_net);
    XOR2_67 : XOR2
      port map(A => MEM_WADDR_7_net, B => GND_1_net, Y => 
        XOR2_67_Y);
    AND2_63 : AND2
      port map(A => MEM_WADDR_6_net, B => GND_1_net, Y => 
        AND2_63_Y);
    AND3_2 : AND3
      port map(A => XNOR2_22_Y, B => XNOR2_0_Y, C => XNOR2_7_Y, 
        Y => AND3_2_Y);
    XNOR2_26 : XNOR2
      port map(A => AFVALCONST_1_net, B => WDIFF_9_net, Y => 
        XNOR2_26_Y);
    AO1_12 : AO1
      port map(A => XOR2_24_Y, B => AND2_4_Y, C => AND2_15_Y, 
        Y => AO1_12_Y);
    NOR3A_1 : NOR3A
      port map(A => OR2A_4_Y, B => AO1C_0_Y, C => WDIFF_0_net, 
        Y => NOR3A_1_Y);
    XOR2_32 : XOR2
      port map(A => WBINNXTSHIFT_8_net, B => INV_3_Y, Y => 
        XOR2_32_Y);
    OR3_0 : OR3
      port map(A => AND2_56_Y, B => AND2_50_Y, C => AND2_8_Y, 
        Y => OR3_0_Y);
    MX2_6 : MX2
      port map(A => RAM4K9_0_DOUTA3, B => RAM4K9_1_DOUTA3, S => 
        DFN1_1_Q, Y => MX2_6_Y);
    AND2_9 : AND2
      port map(A => XOR2_65_Y, B => XOR2_4_Y, Y => AND2_9_Y);
    DFN1E1C0_Q_5_inst : DFN1E1C0
      port map(D => QXI_5_net, CLK => RCLOCK, CLR => RESET, E => 
        DVLDI, Q => Q(5));
    XOR2_65 : XOR2
      port map(A => MEM_RADDR_0_net, B => MEMORYRE, Y => 
        XOR2_65_Y);
    NOR3A_0 : NOR3A
      port map(A => OR2A_2_Y, B => AO1C_1_Y, C => WDIFF_3_net, 
        Y => NOR3A_0_Y);
    DFN1C0_AFULL : DFN1C0
      port map(D => OR2_0_Y, CLK => WCLOCKP, CLR => RESET, Q => 
        AFULL);
    XOR2_58 : XOR2
      port map(A => MEM_RADDR_4_net, B => GND_1_net, Y => 
        XOR2_58_Y);
    XOR2_43 : XOR2
      port map(A => MEM_WADDR_6_net, B => GND_1_net, Y => 
        XOR2_43_Y);
    AO1_32 : AO1
      port map(A => AND2_66_Y, B => AO1_7_Y, C => AO1_8_Y, Y => 
        AO1_32_Y);
    INV_2 : INV
      port map(A => RBINSYNCSHIFT_1_net, Y => INV_2_Y);
    XNOR2_RBINSYNCSHIFT_3_inst : XNOR2
      port map(A => XNOR3_0_Y, B => XNOR3_26_Y, Y => 
        RBINSYNCSHIFT_3_net);
    WCLKBUBBLE : INV
      port map(A => WCLOCK, Y => WCLOCKP);
    MX2_7 : MX2
      port map(A => RAM4K9_0_DOUTA1, B => RAM4K9_1_DOUTA1, S => 
        DFN1_1_Q, Y => MX2_7_Y);
    AO1_9 : AO1
      port map(A => AND2_70_Y, B => AO1_30_Y, C => AO1_23_Y, Y => 
        AO1_9_Y);
    DFN1C0_DVLDX : DFN1C0
      port map(D => DVLDI, CLK => RCLOCK, CLR => RESET, Q => 
        DVLDX);
    AND2_39 : AND2
      port map(A => AND2_9_Y, B => AND2_23_Y, Y => AND2_39_Y);
    NAND2_0 : NAND2
      port map(A => FULL_1_net, B => VCC_1_net, Y => NAND2_0_Y);
    NAND3A_1 : NAND3A
      port map(A => WDIFF_1_net, B => AFVALCONST_1_net, C => 
        OR2A_4_Y, Y => NAND3A_1_Y);
    XOR2_WBINSYNCSHIFT_9_inst : XOR2
      port map(A => WGRYSYNC_10_net, B => WGRYSYNC_9_net, Y => 
        WBINSYNCSHIFT_9_net);
    XNOR3_0 : XNOR3
      port map(A => RGRYSYNC_7_net, B => RGRYSYNC_6_net, C => 
        RGRYSYNC_5_net, Y => XNOR3_0_Y);
    DFN1C0_WGRYSYNC_10_inst : DFN1C0
      port map(D => DFN1C0_2_Q, CLK => RCLOCK, CLR => RESET, Q => 
        WGRYSYNC_10_net);
    DFN1C0_RGRY_6_inst : DFN1C0
      port map(D => XOR2_63_Y, CLK => RCLOCK, CLR => RESET, Q => 
        RGRY_6_net);
    XOR2_76 : XOR2
      port map(A => MEM_RADDR_7_net, B => GND_1_net, Y => 
        XOR2_76_Y);
    AND2_27 : AND2
      port map(A => AND2_30_Y, B => XOR2_68_Y, Y => AND2_27_Y);
    DFN1C0_DVLDI : DFN1C0
      port map(D => AND2A_1_Y, CLK => RCLOCK, CLR => RESET, Q => 
        DVLDI);
    OR2_1 : OR2
      port map(A => BUFF_0_Y, B => MEMWENEG, Y => OR2_1_Y);
    MX2_3 : MX2
      port map(A => RAM4K9_0_DOUTA2, B => RAM4K9_1_DOUTA2, S => 
        DFN1_1_Q, Y => MX2_3_Y);
    XNOR2_10 : XNOR2
      port map(A => WDIFF_5_net, B => AFVALCONST_1_net, Y => 
        XNOR2_10_Y);
    XOR2_83 : XOR2
      port map(A => MEM_WADDR_5_net, B => GND_1_net, Y => 
        XOR2_83_Y);
    AND2_MEMORYWE : AND2
      port map(A => NAND2_0_Y, B => WEP, Y => MEMORYWE);
    XNOR2_27 : XNOR2
      port map(A => RBINNXTSHIFT_4_net, B => WBINSYNCSHIFT_4_net, 
        Y => XNOR2_27_Y);
    AO1_20 : AO1
      port map(A => XOR2_4_Y, B => AND2_74_Y, C => AND2_42_Y, 
        Y => AO1_20_Y);
    DFN1C0_WGRY_2_inst : DFN1C0
      port map(D => XOR2_17_Y, CLK => WCLOCKP, CLR => RESET, Q => 
        WGRY_2_net);
    AO1_0 : AO1
      port map(A => AND2_20_Y, B => AO1_21_Y, C => AO1_12_Y, Y => 
        AO1_0_Y);
    XOR2_29 : XOR2
      port map(A => WBINNXTSHIFT_5_net, B => WBINNXTSHIFT_6_net, 
        Y => XOR2_29_Y);
    DFN1C0_WGRYSYNC_8_inst : DFN1C0
      port map(D => DFN1C0_17_Q, CLK => RCLOCK, CLR => RESET, 
        Q => WGRYSYNC_8_net);
    AO1_45 : AO1
      port map(A => XOR2_3_Y, B => AND2_1_Y, C => AND2_38_Y, Y => 
        AO1_45_Y);
    XOR2_40 : XOR2
      port map(A => WBINNXTSHIFT_6_net, B => INV_8_Y, Y => 
        XOR2_40_Y);
    DFN1C0_RGRYSYNC_1_inst : DFN1C0
      port map(D => DFN1C0_0_Q, CLK => WCLOCKP, CLR => RESET, 
        Q => RGRYSYNC_1_net);
    XOR3_0 : XOR3
      port map(A => WGRYSYNC_10_net, B => WGRYSYNC_9_net, C => 
        WGRYSYNC_8_net, Y => XOR3_0_Y);
    XOR2_WDIFF_10_inst : XOR2
      port map(A => XOR2_54_Y, B => AO1_4_Y, Y => WDIFF_10_net);
    XOR2_2 : XOR2
      port map(A => MEM_RADDR_3_net, B => GND_1_net, Y => 
        XOR2_2_Y);
    DFN1C0_8 : DFN1C0
      port map(D => WGRY_1_net, CLK => RCLOCK, CLR => RESET, Q => 
        DFN1C0_8_Q);
    DFN1C0_RGRY_5_inst : DFN1C0
      port map(D => XOR2_78_Y, CLK => RCLOCK, CLR => RESET, Q => 
        RGRY_5_net);
    XNOR3_10 : XNOR3
      port map(A => WGRYSYNC_7_net, B => WGRYSYNC_6_net, C => 
        WGRYSYNC_5_net, Y => XNOR3_10_Y);
    XNOR2_30 : XNOR2
      port map(A => WDIFF_3_net, B => AFVALCONST_1_net, Y => 
        XNOR2_30_Y);
    XOR2_37 : XOR2
      port map(A => MEM_RADDR_3_net, B => GND_1_net, Y => 
        XOR2_37_Y);
    AND2A_0 : AND2A
      port map(A => AFVALCONST_1_net, B => WDIFF_10_net, Y => 
        AND2A_0_Y);
    AND2_36 : AND2
      port map(A => WBINNXTSHIFT_9_net, B => INV_7_Y, Y => 
        AND2_36_Y);
    XNOR2_WDIFF_1_inst : XNOR2
      port map(A => XOR2_36_Y, B => NOR2A_0_Y, Y => WDIFF_1_net);
    AO1_26 : AO1
      port map(A => XOR2_68_Y, B => AO1_9_Y, C => AND2_2_Y, Y => 
        AO1_26_Y);
    DFN1C0_WGRY_10_inst : DFN1C0
      port map(D => XOR2_44_Y, CLK => WCLOCKP, CLR => RESET, Q => 
        WGRY_10_net);
    DFN1C0_RGRY_7_inst : DFN1C0
      port map(D => XOR2_18_Y, CLK => RCLOCK, CLR => RESET, Q => 
        RGRY_7_net);
    XNOR3_WBINSYNCSHIFT_0_inst : XNOR3
      port map(A => XNOR3_31_Y, B => XNOR3_11_Y, C => XNOR3_20_Y, 
        Y => WBINSYNCSHIFT_0_net);
    OA1A_0 : OA1A
      port map(A => AFVALCONST_1_net, B => WDIFF_9_net, C => 
        WDIFF_10_net, Y => OA1A_0_Y);
    AND3_9 : AND3
      port map(A => AND3_10_Y, B => AND3_8_Y, C => AND3_6_Y, Y => 
        AND3_9_Y);
    XOR3_5 : XOR3
      port map(A => WGRYSYNC_10_net, B => WGRYSYNC_9_net, C => 
        WGRYSYNC_8_net, Y => XOR3_5_Y);
    XOR2_RBINNXTSHIFT_5_inst : XOR2
      port map(A => XOR2_81_Y, B => AO1_6_Y, Y => 
        RBINNXTSHIFT_5_net);
    AO1_23 : AO1
      port map(A => XOR2_46_Y, B => AND2_69_Y, C => AND2_60_Y, 
        Y => AO1_23_Y);
    AOI1_0 : AOI1
      port map(A => AND3_7_Y, B => AO1_24_Y, C => AO1_11_Y, Y => 
        AOI1_0_Y);
    OR2_3 : OR2
      port map(A => INV_4_Y, B => MEMWENEG, Y => OR2_3_Y);
    AND2_33 : AND2
      port map(A => WBINNXTSHIFT_3_net, B => INV_5_Y, Y => 
        AND2_33_Y);
    XOR2_44 : XOR2
      port map(A => WBINNXTSHIFT_10_net, B => GND_1_net, Y => 
        XOR2_44_Y);
    DFN1C0_RGRYSYNC_2_inst : DFN1C0
      port map(D => DFN1C0_5_Q, CLK => WCLOCKP, CLR => RESET, 
        Q => RGRYSYNC_2_net);
    AO1_10 : AO1
      port map(A => AND2_65_Y, B => AO1_12_Y, C => AO1_45_Y, Y => 
        AO1_10_Y);
    XNOR3_30 : XNOR3
      port map(A => RGRYSYNC_4_net, B => RGRYSYNC_3_net, C => 
        RGRYSYNC_2_net, Y => XNOR3_30_Y);
    XOR2_41 : XOR2
      port map(A => WBINNXTSHIFT_6_net, B => WBINNXTSHIFT_7_net, 
        Y => XOR2_41_Y);
    XOR2_35 : XOR2
      port map(A => WBINNXTSHIFT_7_net, B => INV_9_Y, Y => 
        XOR2_35_Y);
    DFN1C0_RGRYSYNC_0_inst : DFN1C0
      port map(D => DFN1C0_21_Q, CLK => WCLOCKP, CLR => RESET, 
        Q => RGRYSYNC_0_net);
    XNOR2_24 : XNOR2
      port map(A => RBINSYNCSHIFT_2_net, B => WBINNXTSHIFT_2_net, 
        Y => XNOR2_24_Y);
    XOR2_RBINNXTSHIFT_10_inst : XOR2
      port map(A => XOR2_6_Y, B => AO1_25_Y, Y => 
        RBINNXTSHIFT_10_net);
    MX2_QXI_2_inst : MX2
      port map(A => RAM4K9_0_DOUTB2, B => RAM4K9_1_DOUTB2, S => 
        DFN1_0_Q, Y => QXI_2_net);
    XOR2_80 : XOR2
      port map(A => MEM_RADDR_1_net, B => GND_1_net, Y => 
        XOR2_80_Y);
    DFN1C0_WGRY_1_inst : DFN1C0
      port map(D => XOR2_28_Y, CLK => WCLOCKP, CLR => RESET, Q => 
        WGRY_1_net);
    DFN1P0_EMPTY : DFN1P0
      port map(D => EMPTYINT, CLK => RCLOCK, PRE => RESET, Q => 
        EMPTY_1_net);
    DFN1E1C0_Q_3_inst : DFN1E1C0
      port map(D => QXI_3_net, CLK => RCLOCK, CLR => RESET, E => 
        DVLDI, Q => Q(3));
    DFN1C0_WGRYSYNC_4_inst : DFN1C0
      port map(D => DFN1C0_4_Q, CLK => RCLOCK, CLR => RESET, Q => 
        WGRYSYNC_4_net);
    XNOR3_29 : XNOR3
      port map(A => RGRYSYNC_4_net, B => RGRYSYNC_3_net, C => 
        RGRYSYNC_2_net, Y => XNOR3_29_Y);
    XNOR3_RBINSYNCSHIFT_4_inst : XNOR3
      port map(A => RGRYSYNC_4_net, B => XOR3_6_Y, C => 
        XNOR3_27_Y, Y => RBINSYNCSHIFT_4_net);
    XOR2_78 : XOR2
      port map(A => RBINNXTSHIFT_5_net, B => RBINNXTSHIFT_6_net, 
        Y => XOR2_78_Y);
    AO1_30 : AO1
      port map(A => AND2_7_Y, B => AO1_44_Y, C => AO1_32_Y, Y => 
        AO1_30_Y);
    XOR2_RBINNXTSHIFT_7_inst : XOR2
      port map(A => XOR2_76_Y, B => AO1_22_Y, Y => 
        RBINNXTSHIFT_7_net);
    AND2_41 : AND2
      port map(A => XOR2_20_Y, B => XOR2_40_Y, Y => AND2_41_Y);
    AND2_0 : AND2
      port map(A => AND2_39_Y, B => XOR2_8_Y, Y => AND2_0_Y);
    XOR2_69 : XOR2
      port map(A => MEM_WADDR_10_net, B => GND_1_net, Y => 
        XOR2_69_Y);
    AO1_16 : AO1
      port map(A => XOR2_10_Y, B => OR3_0_Y, C => AND2_80_Y, Y => 
        AO1_16_Y);
    AND2_17 : AND2
      port map(A => MEM_RADDR_2_net, B => GND_1_net, Y => 
        AND2_17_Y);
    XNOR2_WBINSYNCSHIFT_1_inst : XNOR2
      port map(A => XNOR3_25_Y, B => XNOR3_17_Y, Y => 
        WBINSYNCSHIFT_1_net);
    NOR2A_0 : NOR2A
      port map(A => RBINSYNCSHIFT_0_net, B => WBINNXTSHIFT_0_net, 
        Y => NOR2A_0_Y);
    AO1_29 : AO1
      port map(A => XOR2_20_Y, B => AO1_27_Y, C => AND2_78_Y, 
        Y => AO1_29_Y);
    XOR2_6 : XOR2
      port map(A => MEM_RADDR_10_net, B => GND_1_net, Y => 
        XOR2_6_Y);
    AND2_77 : AND2
      port map(A => AND2_71_Y, B => XOR2_59_Y, Y => AND2_77_Y);
    AND2_54 : AND2
      port map(A => MEM_WADDR_1_net, B => GND_1_net, Y => 
        AND2_54_Y);
    AO1_13 : AO1
      port map(A => XOR2_70_Y, B => AO1_44_Y, C => AND2_59_Y, 
        Y => AO1_13_Y);
    XOR2_84 : XOR2
      port map(A => WBINNXTSHIFT_8_net, B => INV_3_Y, Y => 
        XOR2_84_Y);
    XNOR3_RBINSYNCSHIFT_2_inst : XNOR3
      port map(A => XNOR3_23_Y, B => XNOR3_2_Y, C => XNOR3_30_Y, 
        Y => RBINSYNCSHIFT_2_net);
    DFN1C0_MEM_WADDR_6_inst : DFN1C0
      port map(D => WBINNXTSHIFT_6_net, CLK => WCLOCKP, CLR => 
        RESET, Q => MEM_WADDR_6_net);
    XOR2_WBINNXTSHIFT_5_inst : XOR2
      port map(A => XOR2_83_Y, B => AO1_13_Y, Y => 
        WBINNXTSHIFT_5_net);
    XOR2_81 : XOR2
      port map(A => MEM_RADDR_5_net, B => GND_1_net, Y => 
        XOR2_81_Y);
    XOR2_WDIFF_7_inst : XOR2
      port map(A => XOR2_30_Y, B => AO1_34_Y, Y => WDIFF_7_net);
    AO1_36 : AO1
      port map(A => AND2_67_Y, B => AO1_44_Y, C => AO1_7_Y, Y => 
        AO1_36_Y);
    XOR2_53 : XOR2
      port map(A => WBINNXTSHIFT_4_net, B => WBINNXTSHIFT_5_net, 
        Y => XOR2_53_Y);
    XNOR2_23 : XNOR2
      port map(A => RBINNXTSHIFT_7_net, B => WBINSYNCSHIFT_7_net, 
        Y => XNOR2_23_Y);
    DFN1C0_19 : DFN1C0
      port map(D => RGRY_8_net, CLK => WCLOCKP, CLR => RESET, 
        Q => DFN1C0_19_Q);
    AO1_33 : AO1
      port map(A => XOR2_19_Y, B => AO1_30_Y, C => AND2_69_Y, 
        Y => AO1_33_Y);
    XOR2_WBINNXTSHIFT_10_inst : XOR2
      port map(A => XOR2_69_Y, B => AO1_9_Y, Y => 
        WBINNXTSHIFT_10_net);
    AO1_44 : AO1
      port map(A => AND2_12_Y, B => AO1_1_Y, C => AO1_28_Y, Y => 
        AO1_44_Y);
    DFN1C0_WGRYSYNC_3_inst : DFN1C0
      port map(D => DFN1C0_20_Q, CLK => RCLOCK, CLR => RESET, 
        Q => WGRYSYNC_3_net);
    OR2A_0 : OR2A
      port map(A => WDIFF_8_net, B => AFVALCONST_1_net, Y => 
        OR2A_0_Y);
    DFN1_0 : DFN1
      port map(D => MEM_RADDR_9_net, CLK => RCLOCK, Q => DFN1_0_Q);
    XNOR2_12 : XNOR2
      port map(A => RBINNXTSHIFT_5_net, B => WBINSYNCSHIFT_5_net, 
        Y => XNOR2_12_Y);
    XNOR2_7 : XNOR2
      port map(A => RBINSYNCSHIFT_5_net, B => WBINNXTSHIFT_5_net, 
        Y => XNOR2_7_Y);
    XOR2_12 : XOR2
      port map(A => RBINNXTSHIFT_0_net, B => RBINNXTSHIFT_1_net, 
        Y => XOR2_12_Y);
    AND2_48 : AND2
      port map(A => AND2_53_Y, B => XOR2_70_Y, Y => AND2_48_Y);
    AND2_45 : AND2
      port map(A => AND2_51_Y, B => XOR2_14_Y, Y => AND2_45_Y);
    DFN1C0_5 : DFN1C0
      port map(D => RGRY_2_net, CLK => WCLOCKP, CLR => RESET, 
        Q => DFN1C0_5_Q);
    DFN1C0_21 : DFN1C0
      port map(D => RGRY_0_net, CLK => WCLOCKP, CLR => RESET, 
        Q => DFN1C0_21_Q);
    AO1_19 : AO1
      port map(A => XOR2_16_Y, B => AO1_1_Y, C => AND2_10_Y, Y => 
        AO1_19_Y);
    XOR2_WBINNXTSHIFT_7_inst : XOR2
      port map(A => XOR2_67_Y, B => AO1_18_Y, Y => 
        WBINNXTSHIFT_7_net);
    DFN1_1 : DFN1
      port map(D => MEM_WADDR_9_net, CLK => WCLOCKP, Q => 
        DFN1_1_Q);
    XOR2_26 : XOR2
      port map(A => MEM_WADDR_1_net, B => GND_1_net, Y => 
        XOR2_26_Y);
    DFN1C0_1 : DFN1C0
      port map(D => RGRY_9_net, CLK => WCLOCKP, CLR => RESET, 
        Q => DFN1C0_1_Q);
    AND2_59 : AND2
      port map(A => MEM_WADDR_4_net, B => GND_1_net, Y => 
        AND2_59_Y);
    DFN1C0_RGRY_10_inst : DFN1C0
      port map(D => XOR2_75_Y, CLK => RCLOCK, CLR => RESET, Q => 
        RGRY_10_net);
    DFN1C0_WGRYSYNC_7_inst : DFN1C0
      port map(D => DFN1C0_7_Q, CLK => RCLOCK, CLR => RESET, Q => 
        WGRYSYNC_7_net);
    AND2_4 : AND2
      port map(A => MEM_RADDR_4_net, B => GND_1_net, Y => 
        AND2_4_Y);
    AND2_FULLINT : AND2
      port map(A => AND2_22_Y, B => XOR2_45_Y, Y => FULLINT);
    AO1_39 : AO1
      port map(A => XOR2_2_Y, B => AND2_17_Y, C => AND2_55_Y, 
        Y => AO1_39_Y);
    AND2_40 : AND2
      port map(A => MEM_RADDR_9_net, B => GND_1_net, Y => 
        AND2_40_Y);
    XOR2_WDIFF_6_inst : XOR2
      port map(A => XOR2_48_Y, B => AO1_29_Y, Y => WDIFF_6_net);
    XNOR3_12 : XNOR3
      port map(A => WGRYSYNC_4_net, B => WGRYSYNC_3_net, C => 
        WGRYSYNC_2_net, Y => XNOR3_12_Y);
    XOR2_50 : XOR2
      port map(A => WBINNXTSHIFT_7_net, B => WBINNXTSHIFT_8_net, 
        Y => XOR2_50_Y);
    DFN1C0_WGRYSYNC_6_inst : DFN1C0
      port map(D => DFN1C0_14_Q, CLK => RCLOCK, CLR => RESET, 
        Q => WGRYSYNC_6_net);
    AND2_42 : AND2
      port map(A => MEM_RADDR_1_net, B => GND_1_net, Y => 
        AND2_42_Y);
    DFN1E1C0_Q_2_inst : DFN1E1C0
      port map(D => QXI_2_net, CLK => RCLOCK, CLR => RESET, E => 
        DVLDI, Q => Q(2));
    DFN1C0_WGRY_8_inst : DFN1C0
      port map(D => XOR2_52_Y, CLK => WCLOCKP, CLR => RESET, Q => 
        WGRY_8_net);
    MX2_4 : MX2
      port map(A => RAM4K9_0_DOUTA0, B => RAM4K9_1_DOUTA0, S => 
        DFN1_1_Q, Y => MX2_4_Y);
    XNOR2_5 : XNOR2
      port map(A => AFVALCONST_1_net, B => WDIFF_7_net, Y => 
        XNOR2_5_Y);
    AO1_5 : AO1
      port map(A => XOR2_51_Y, B => AND2_33_Y, C => AND2_76_Y, 
        Y => AO1_5_Y);
    AND2_67 : AND2
      port map(A => XOR2_70_Y, B => XOR2_66_Y, Y => AND2_67_Y);
    XNOR2_16 : XNOR2
      port map(A => RBINNXTSHIFT_3_net, B => WBINSYNCSHIFT_3_net, 
        Y => XNOR2_16_Y);
    XOR2_WDIFF_4_inst : XOR2
      port map(A => XOR2_60_Y, B => AO1_35_Y, Y => WDIFF_4_net);
    DFN1C0_RGRY_3_inst : DFN1C0
      port map(D => XOR2_49_Y, CLK => RCLOCK, CLR => RESET, Q => 
        RGRY_3_net);
    XOR3_2 : XOR3
      port map(A => RGRYSYNC_10_net, B => RGRYSYNC_9_net, C => 
        RGRYSYNC_8_net, Y => XOR3_2_Y);
    XOR2_39 : XOR2
      port map(A => MEM_RADDR_2_net, B => GND_1_net, Y => 
        XOR2_39_Y);
    AND2_8 : AND2
      port map(A => INV_2_Y, B => INV_6_Y, Y => AND2_8_Y);
    AND2_80 : AND2
      port map(A => WBINNXTSHIFT_2_net, B => INV_12_Y, Y => 
        AND2_80_Y);
    XOR2_WDIFF_8_inst : XOR2
      port map(A => XOR2_32_Y, B => AO1_38_Y, Y => WDIFF_8_net);
    XOR2_3 : XOR2
      port map(A => MEM_RADDR_7_net, B => GND_1_net, Y => 
        XOR2_3_Y);
    XOR2_54 : XOR2
      port map(A => WBINNXTSHIFT_10_net, B => INV_10_Y, Y => 
        XOR2_54_Y);
    XNOR3_21 : XNOR3
      port map(A => RGRYSYNC_10_net, B => RGRYSYNC_9_net, C => 
        RGRYSYNC_8_net, Y => XNOR3_21_Y);
    MX2_QXI_4_inst : MX2
      port map(A => RAM4K9_0_DOUTB4, B => RAM4K9_1_DOUTB4, S => 
        DFN1_0_Q, Y => QXI_4_net);
    XOR3_1 : XOR3
      port map(A => WGRYSYNC_10_net, B => WGRYSYNC_9_net, C => 
        WGRYSYNC_8_net, Y => XOR3_1_Y);
    RAM4K9_1 : RAM4K9
      port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net, 
        ADDRA9 => GND_1_net, ADDRA8 => MEM_WADDR_8_net, ADDRA7 => 
        MEM_WADDR_7_net, ADDRA6 => MEM_WADDR_6_net, ADDRA5 => 
        MEM_WADDR_5_net, ADDRA4 => MEM_WADDR_4_net, ADDRA3 => 
        MEM_WADDR_3_net, ADDRA2 => MEM_WADDR_2_net, ADDRA1 => 
        MEM_WADDR_1_net, ADDRA0 => MEM_WADDR_0_net, ADDRB11 => 
        GND_1_net, ADDRB10 => GND_1_net, ADDRB9 => GND_1_net, 
        ADDRB8 => MEM_RADDR_8_net, ADDRB7 => MEM_RADDR_7_net, 
        ADDRB6 => MEM_RADDR_6_net, ADDRB5 => MEM_RADDR_5_net, 
        ADDRB4 => MEM_RADDR_4_net, ADDRB3 => MEM_RADDR_3_net, 
        ADDRB2 => MEM_RADDR_2_net, ADDRB1 => MEM_RADDR_1_net, 
        ADDRB0 => MEM_RADDR_0_net, DINA8 => GND_1_net, DINA7 => 
        DATA(7), DINA6 => DATA(6), DINA5 => DATA(5), DINA4 => 
        DATA(4), DINA3 => DATA(3), DINA2 => DATA(2), DINA1 => 
        DATA(1), DINA0 => DATA(0), DINB8 => GND_1_net, DINB7 => 
        GND_1_net, DINB6 => GND_1_net, DINB5 => GND_1_net, 
        DINB4 => GND_1_net, DINB3 => GND_1_net, DINB2 => 
        GND_1_net, DINB1 => GND_1_net, DINB0 => GND_1_net, 
        WIDTHA0 => VCC_1_net, WIDTHA1 => VCC_1_net, WIDTHB0 => 
        VCC_1_net, WIDTHB1 => VCC_1_net, PIPEA => GND_1_net, 
        PIPEB => GND_1_net, WMODEA => GND_1_net, WMODEB => 
        GND_1_net, BLKA => OR2_3_Y, BLKB => OR2_4_Y, WENA => 
        GND_1_net, WENB => VCC_1_net, CLKA => WCLOCKP, CLKB => 
        RCLOCK, RESET => RESET, DOUTA8 => OPEN , DOUTA7 => 
        RAM4K9_1_DOUTA7, DOUTA6 => RAM4K9_1_DOUTA6, DOUTA5 => 
        RAM4K9_1_DOUTA5, DOUTA4 => RAM4K9_1_DOUTA4, DOUTA3 => 
        RAM4K9_1_DOUTA3, DOUTA2 => RAM4K9_1_DOUTA2, DOUTA1 => 
        RAM4K9_1_DOUTA1, DOUTA0 => RAM4K9_1_DOUTA0, DOUTB8 => 
        OPEN , DOUTB7 => RAM4K9_1_DOUTB7, DOUTB6 => 
        RAM4K9_1_DOUTB6, DOUTB5 => RAM4K9_1_DOUTB5, DOUTB4 => 
        RAM4K9_1_DOUTB4, DOUTB3 => RAM4K9_1_DOUTB3, DOUTB2 => 
        RAM4K9_1_DOUTB2, DOUTB1 => RAM4K9_1_DOUTB1, DOUTB0 => 
        RAM4K9_1_DOUTB0);
    XOR2_51 : XOR2
      port map(A => WBINNXTSHIFT_4_net, B => INV_1_Y, Y => 
        XOR2_51_Y);
    AO1_27 : AO1
      port map(A => AND2_46_Y, B => AO1_16_Y, C => AO1_5_Y, Y => 
        AO1_27_Y);
    XOR2_66 : XOR2
      port map(A => MEM_WADDR_5_net, B => GND_1_net, Y => 
        XOR2_66_Y);
    AND2_56 : AND2
      port map(A => WBINNXTSHIFT_1_net, B => INV_2_Y, Y => 
        AND2_56_Y);
    XNOR3_RBINSYNCSHIFT_0_inst : XNOR3
      port map(A => XNOR3_15_Y, B => XNOR3_29_Y, C => XNOR3_7_Y, 
        Y => RBINSYNCSHIFT_0_net);
    INV_10 : INV
      port map(A => RBINSYNCSHIFT_10_net, Y => INV_10_Y);
    XNOR3_16 : XNOR3
      port map(A => WGRYSYNC_7_net, B => WGRYSYNC_6_net, C => 
        WGRYSYNC_5_net, Y => XNOR3_16_Y);
    DFN1C0_MEM_WADDR_1_inst : DFN1C0
      port map(D => WBINNXTSHIFT_1_net, CLK => WCLOCKP, CLR => 
        RESET, Q => MEM_WADDR_1_net);
    XOR2_RBINNXTSHIFT_1_inst : XOR2
      port map(A => XOR2_80_Y, B => AND2_74_Y, Y => 
        RBINNXTSHIFT_1_net);
    XOR2_17 : XOR2
      port map(A => WBINNXTSHIFT_2_net, B => WBINNXTSHIFT_3_net, 
        Y => XOR2_17_Y);
    XOR2_73 : XOR2
      port map(A => MEM_RADDR_9_net, B => GND_1_net, Y => 
        XOR2_73_Y);
    AND2_53 : AND2
      port map(A => AND2_18_Y, B => AND2_12_Y, Y => AND2_53_Y);
    DFN1C0_13 : DFN1C0
      port map(D => RGRY_3_net, CLK => WCLOCKP, CLR => RESET, 
        Q => DFN1C0_13_Q);
    AND3_7 : AND3
      port map(A => AND3_0_Y, B => XNOR2_26_Y, C => XNOR2_6_Y, 
        Y => AND3_7_Y);
    XOR2_28 : XOR2
      port map(A => WBINNXTSHIFT_1_net, B => WBINNXTSHIFT_2_net, 
        Y => XOR2_28_Y);
    INV_9 : INV
      port map(A => RBINSYNCSHIFT_7_net, Y => INV_9_Y);
    DFN1C0_MEM_WADDR_5_inst : DFN1C0
      port map(D => WBINNXTSHIFT_5_net, CLK => WCLOCKP, CLR => 
        RESET, Q => MEM_WADDR_5_net);
    XOR2_15 : XOR2
      port map(A => WBINNXTSHIFT_9_net, B => WBINNXTSHIFT_10_net, 
        Y => XOR2_15_Y);
    XOR2_WDIFF_9_inst : XOR2
      port map(A => XOR2_64_Y, B => AO1_2_Y, Y => WDIFF_9_net);
    DFN1C0_MEM_RADDR_0_inst : DFN1C0
      port map(D => RBINNXTSHIFT_0_net, CLK => RCLOCK, CLR => 
        RESET, Q => MEM_RADDR_0_net);
    AO1_17 : AO1
      port map(A => XOR2_57_Y, B => AO1_25_Y, C => AND2_31_Y, 
        Y => AO1_17_Y);
    XNOR2_17 : XNOR2
      port map(A => RBINSYNCSHIFT_6_net, B => WBINNXTSHIFT_6_net, 
        Y => XNOR2_17_Y);
    XNOR3_WBINSYNCSHIFT_4_inst : XNOR3
      port map(A => WGRYSYNC_4_net, B => XOR3_4_Y, C => XNOR3_8_Y, 
        Y => WBINSYNCSHIFT_4_net);
    DFN1C0_MEM_RADDR_10_inst : DFN1C0
      port map(D => RBINNXTSHIFT_10_net, CLK => RCLOCK, CLR => 
        RESET, Q => MEM_RADDR_10_net);
    NAND3A_4 : NAND3A
      port map(A => NOR3A_2_Y, B => OR2A_1_Y, C => NAND3A_5_Y, 
        Y => NAND3A_4_Y);
    AND3_4 : AND3
      port map(A => XNOR2_1_Y, B => XNOR2_20_Y, C => XNOR2_24_Y, 
        Y => AND3_4_Y);
    XNOR3_28 : XNOR3
      port map(A => RGRYSYNC_7_net, B => RGRYSYNC_6_net, C => 
        RGRYSYNC_5_net, Y => XNOR3_28_Y);
    DFN1C0_RGRY_0_inst : DFN1C0
      port map(D => XOR2_12_Y, CLK => RCLOCK, CLR => RESET, Q => 
        RGRY_0_net);
    XOR3_RBINSYNCSHIFT_8_inst : XOR3
      port map(A => RGRYSYNC_10_net, B => RGRYSYNC_9_net, C => 
        RGRYSYNC_8_net, Y => RBINSYNCSHIFT_8_net);
    XOR2_WBINNXTSHIFT_1_inst : XOR2
      port map(A => XOR2_26_Y, B => AND2_32_Y, Y => 
        WBINNXTSHIFT_1_net);
    AND2_21 : AND2
      port map(A => XOR2_14_Y, B => XOR2_73_Y, Y => AND2_21_Y);
    AO1_37 : AO1
      port map(A => XOR2_79_Y, B => AND2_36_Y, C => AND2_57_Y, 
        Y => AO1_37_Y);
    XOR3_7 : XOR3
      port map(A => RGRYSYNC_10_net, B => RGRYSYNC_9_net, C => 
        RGRYSYNC_8_net, Y => XOR3_7_Y);
    DFN1C0_WGRY_4_inst : DFN1C0
      port map(D => XOR2_53_Y, CLK => WCLOCKP, CLR => RESET, Q => 
        WGRY_4_net);
    XNOR3_17 : XNOR3
      port map(A => WGRYSYNC_1_net, B => XOR3_1_Y, C => 
        XNOR3_19_Y, Y => XNOR3_17_Y);
    XOR2_0 : XOR2
      port map(A => MEM_WADDR_6_net, B => GND_1_net, Y => 
        XOR2_0_Y);
    XOR2_70 : XOR2
      port map(A => MEM_WADDR_4_net, B => GND_1_net, Y => 
        XOR2_70_Y);
    NAND2_1 : NAND2
      port map(A => EMPTY_1_net, B => VCC_1_net, Y => NAND2_1_Y);
    NAND3A_5 : NAND3A
      port map(A => WDIFF_7_net, B => AFVALCONST_1_net, C => 
        OR2A_0_Y, Y => NAND3A_5_Y);
    XNOR3_WBINSYNCSHIFT_6_inst : XNOR3
      port map(A => WGRYSYNC_7_net, B => WGRYSYNC_6_net, C => 
        XNOR3_24_Y, Y => WBINSYNCSHIFT_6_net);
    DFN1C0_RGRYSYNC_8_inst : DFN1C0
      port map(D => DFN1C0_19_Q, CLK => WCLOCKP, CLR => RESET, 
        Q => RGRYSYNC_8_net);
    AO1_4 : AO1
      port map(A => XOR2_13_Y, B => AO1_2_Y, C => AND2_36_Y, Y => 
        AO1_4_Y);
    XOR2_68 : XOR2
      port map(A => MEM_WADDR_10_net, B => GND_1_net, Y => 
        XOR2_68_Y);
    AND2_37 : AND2
      port map(A => AND2_47_Y, B => XOR2_35_Y, Y => AND2_37_Y);
    XNOR3_4 : XNOR3
      port map(A => RGRYSYNC_10_net, B => RGRYSYNC_9_net, C => 
        RGRYSYNC_8_net, Y => XNOR3_4_Y);
    XOR2_RBINNXTSHIFT_2_inst : XOR2
      port map(A => XOR2_39_Y, B => AO1_20_Y, Y => 
        RBINNXTSHIFT_2_net);
    XNOR2_14 : XNOR2
      port map(A => AFVALCONST_1_net, B => WDIFF_6_net, Y => 
        XNOR2_14_Y);
    XOR2_42 : XOR2
      port map(A => WBINNXTSHIFT_5_net, B => INV_0_Y, Y => 
        XOR2_42_Y);
    XNOR2_29 : XNOR2
      port map(A => WDIFF_10_net, B => AFVALCONST_1_net, Y => 
        XNOR2_29_Y);
    AO1_21 : AO1
      port map(A => AND2_23_Y, B => AO1_20_Y, C => AO1_39_Y, Y => 
        AO1_21_Y);
    DFN1C0_MEM_RADDR_9_inst : DFN1C0
      port map(D => RBINNXTSHIFT_9_net, CLK => RCLOCK, CLR => 
        RESET, Q => MEM_RADDR_9_net);
    XOR2_36 : XOR2
      port map(A => WBINNXTSHIFT_1_net, B => INV_2_Y, Y => 
        XOR2_36_Y);
    BUFF_1 : BUFF
      port map(A => MEM_RADDR_9_net, Y => BUFF_1_Y);
    XOR2_74 : XOR2
      port map(A => MEM_WADDR_3_net, B => GND_1_net, Y => 
        XOR2_74_Y);
    XNOR2_8 : XNOR2
      port map(A => RBINNXTSHIFT_1_net, B => WBINSYNCSHIFT_1_net, 
        Y => XNOR2_8_Y);
    XNOR3_2 : XNOR3
      port map(A => RGRYSYNC_7_net, B => RGRYSYNC_6_net, C => 
        RGRYSYNC_5_net, Y => XNOR3_2_Y);
    XNOR3_RBINSYNCSHIFT_6_inst : XNOR3
      port map(A => RGRYSYNC_7_net, B => RGRYSYNC_6_net, C => 
        XNOR3_6_Y, Y => RBINSYNCSHIFT_6_net);
    MX2_1 : MX2
      port map(A => RAM4K9_0_DOUTA5, B => RAM4K9_1_DOUTA5, S => 
        DFN1_1_Q, Y => MX2_1_Y);
    XOR2_71 : XOR2
      port map(A => MEM_RADDR_8_net, B => GND_1_net, Y => 
        XOR2_71_Y);
    AND2_28 : AND2
      port map(A => MEM_RADDR_8_net, B => GND_1_net, Y => 
        AND2_28_Y);
    AND2_25 : AND2
      port map(A => AND2_34_Y, B => XOR2_0_Y, Y => AND2_25_Y);
    DFN1C0_WGRYSYNC_5_inst : DFN1C0
      port map(D => DFN1C0_18_Q, CLK => RCLOCK, CLR => RESET, 
        Q => WGRYSYNC_5_net);
    AO1C_2 : AO1C
      port map(A => AFVALCONST_1_net, B => WDIFF_7_net, C => 
        AFVALCONST_1_net, Y => AO1C_2_Y);
ldic5_inst_0 : ldic5_0 PORT MAP ( data => data, uplink_15 => uplink_15_a); end DEF_ARCH;
