Timing Report Min Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Thu Dec 29 14:51:52 2011


Design: usbee_top_level
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               USB_CLK
Period (ns):                6.129
Frequency (MHz):            163.159
Required Period (ns):       1000.000
Required Frequency (MHz):   1.000
External Setup (ns):        5.283
External Hold (ns):         -0.766
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                15.552
Frequency (MHz):            64.300
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.661
External Hold (ns):         1.288
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               usb_mss_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             4.727
Max Delay (ns):             12.512

END SUMMARY
-----------------------------------------------------

Clock Domain USB_CLK

SET Register to Register

Path 1
  From:                        usb_slave_0/input_32_bit_data[19]:CLK
  To:                          usb_slave_0/FIFO_INST/FIFOBLOCK_1_inst:WD1
  Delay (ns):                  0.774
  Slack (ns):                  0.581
  Arrival (ns):                1.589
  Required (ns):               1.008
  Hold (ns):                   0.000

Path 2
  From:                        usb_slave_0/input_32_bit_data[4]:CLK
  To:                          usb_slave_0/FIFO_INST/FIFOBLOCK_0_inst:WD4
  Delay (ns):                  0.786
  Slack (ns):                  0.587
  Arrival (ns):                1.592
  Required (ns):               1.005
  Hold (ns):                   0.000

Path 3
  From:                        usb_slave_0/input_32_bit_data[3]:CLK
  To:                          usb_slave_0/FIFO_INST/FIFOBLOCK_0_inst:WD3
  Delay (ns):                  0.803
  Slack (ns):                  0.594
  Arrival (ns):                1.599
  Required (ns):               1.005
  Hold (ns):                   0.000

Path 4
  From:                        usb_slave_0/input_32_bit_data[12]:CLK
  To:                          usb_slave_0/FIFO_INST/FIFOBLOCK_0_inst:WD12
  Delay (ns):                  0.811
  Slack (ns):                  0.615
  Arrival (ns):                1.620
  Required (ns):               1.005
  Hold (ns):                   0.000

Path 5
  From:                        usb_slave_0/input_32_bit_data[7]:CLK
  To:                          usb_slave_0/FIFO_INST/FIFOBLOCK_0_inst:WD7
  Delay (ns):                  0.813
  Slack (ns):                  0.617
  Arrival (ns):                1.622
  Required (ns):               1.005
  Hold (ns):                   0.000


Expanded Path 1
  From: usb_slave_0/input_32_bit_data[19]:CLK
  To: usb_slave_0/FIFO_INST/FIFOBLOCK_1_inst:WD1
  data arrival time                              1.589
  data required time                         -   1.008
  slack                                          0.581
  ________________________________________________________
  Data arrival time calculation
  0.000                        USB_CLK
               +     0.000          Clock source
  0.000                        USB_CLK (r)
               +     0.000          net: USB_CLK
  0.000                        USB_CLK_pad/U0/U0:PAD (r)
               +     0.391          cell: ADLIB:IOPAD_IN
  0.391                        USB_CLK_pad/U0/U0:Y (r)
               +     0.000          net: USB_CLK_pad/U0/NET1
  0.391                        USB_CLK_pad/U0/U1:A (r)
               +     0.134          cell: ADLIB:CLKSRC
  0.525                        USB_CLK_pad/U0/U1:Y (r)
               +     0.290          net: USB_CLK_c
  0.815                        usb_slave_0/input_32_bit_data[19]:CLK (r)
               +     0.249          cell: ADLIB:DFN1C1
  1.064                        usb_slave_0/input_32_bit_data[19]:Q (r)
               +     0.525          net: usb_slave_0/input_32_bit_data[19]
  1.589                        usb_slave_0/FIFO_INST/FIFOBLOCK_1_inst:WD1 (r)
                                    
  1.589                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        USB_CLK
               +     0.000          Clock source
  0.000                        USB_CLK (r)
               +     0.000          net: USB_CLK
  0.000                        USB_CLK_pad/U0/U0:PAD (r)
               +     0.391          cell: ADLIB:IOPAD_IN
  0.391                        USB_CLK_pad/U0/U0:Y (r)
               +     0.000          net: USB_CLK_pad/U0/NET1
  0.391                        USB_CLK_pad/U0/U1:A (r)
               +     0.134          cell: ADLIB:CLKSRC
  0.525                        USB_CLK_pad/U0/U1:Y (r)
               +     0.483          net: USB_CLK_c
  1.008                        usb_slave_0/FIFO_INST/FIFOBLOCK_1_inst:WCLK (r)
               +     0.000          Library hold time: ADLIB:FIFO4K18
  1.008                        usb_slave_0/FIFO_INST/FIFOBLOCK_1_inst:WD1
                                    
  1.008                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        USB_DATA_PAD[6]
  To:                          usb_slave_0/input_32_bit_data[22]:D
  Delay (ns):                  1.766
  Slack (ns):
  Arrival (ns):                1.766
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -0.766

Path 2
  From:                        USB_DATA_PAD[6]
  To:                          usb_slave_0/input_32_bit_data[6]:D
  Delay (ns):                  1.994
  Slack (ns):
  Arrival (ns):                1.994
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -1.025

Path 3
  From:                        USB_DATA_PAD[6]
  To:                          usb_slave_0/input_32_bit_data[14]:D
  Delay (ns):                  2.001
  Slack (ns):
  Arrival (ns):                2.001
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -1.032

Path 4
  From:                        USB_DATA_PAD[5]
  To:                          usb_slave_0/input_32_bit_data[13]:D
  Delay (ns):                  2.098
  Slack (ns):
  Arrival (ns):                2.098
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -1.126

Path 5
  From:                        USB_DATA_PAD[0]
  To:                          usb_slave_0/input_32_bit_data[0]:D
  Delay (ns):                  2.177
  Slack (ns):
  Arrival (ns):                2.177
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -1.205


Expanded Path 1
  From: USB_DATA_PAD[6]
  To: usb_slave_0/input_32_bit_data[22]:D
  data arrival time                              1.766
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        USB_DATA_PAD[6] (f)
               +     0.000          net: USB_DATA_PAD[6]
  0.000                        usb_slave_0/GEN.6.DATA_PINS/U0/U0:PAD (f)
               +     0.277          cell: ADLIB:IOPAD_BI
  0.277                        usb_slave_0/GEN.6.DATA_PINS/U0/U0:Y (f)
               +     0.000          net: usb_slave_0/GEN_6_DATA_PINS/U0/NET3
  0.277                        usb_slave_0/GEN.6.DATA_PINS/U0/U1:YIN (f)
               +     0.017          cell: ADLIB:IOBI_IB_OB_EB
  0.294                        usb_slave_0/GEN.6.DATA_PINS/U0/U1:Y (f)
               +     1.055          net: usb_slave_0/USB_DATA_IN[6]
  1.349                        usb_slave_0/input_32_bit_data_RNO[22]:A (f)
               +     0.269          cell: ADLIB:MX2
  1.618                        usb_slave_0/input_32_bit_data_RNO[22]:Y (f)
               +     0.148          net: usb_slave_0/N_49
  1.766                        usb_slave_0/input_32_bit_data[22]:D (f)
                                    
  1.766                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          USB_CLK
               +     0.000          Clock source
  N/C                          USB_CLK (r)
               +     0.000          net: USB_CLK
  N/C                          USB_CLK_pad/U0/U0:PAD (r)
               +     0.470          cell: ADLIB:IOPAD_IN
  N/C                          USB_CLK_pad/U0/U0:Y (r)
               +     0.000          net: USB_CLK_pad/U0/NET1
  N/C                          USB_CLK_pad/U0/U1:A (r)
               +     0.161          cell: ADLIB:CLKSRC
  N/C                          USB_CLK_pad/U0/U1:Y (r)
               +     0.369          net: USB_CLK_c
  N/C                          usb_slave_0/input_32_bit_data[22]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C1
  N/C                          usb_slave_0/input_32_bit_data[22]:D


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

Path 1
  From:                        IO_0_PADIN
  To:                          usb_slave_0/input_32_bit_data[22]:CLR
  Delay (ns):                  2.431
  Slack (ns):
  Arrival (ns):                2.431
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       -1.431

Path 2
  From:                        IO_0_PADIN
  To:                          usb_slave_0/wr_en/U1:PRE
  Delay (ns):                  2.447
  Slack (ns):
  Arrival (ns):                2.447
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       -1.490

Path 3
  From:                        IO_0_PADIN
  To:                          usb_slave_0/input_32_bit_data[25]:CLR
  Delay (ns):                  2.529
  Slack (ns):
  Arrival (ns):                2.529
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       -1.529

Path 4
  From:                        IO_0_PADIN
  To:                          usb_slave_0/input_states[0]:CLR
  Delay (ns):                  2.529
  Slack (ns):
  Arrival (ns):                2.529
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       -1.529

Path 5
  From:                        IO_0_PADIN
  To:                          usb_slave_0/input_states[1]:CLR
  Delay (ns):                  2.529
  Slack (ns):
  Arrival (ns):                2.529
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       -1.529


Expanded Path 1
  From: IO_0_PADIN
  To: usb_slave_0/input_32_bit_data[22]:CLR
  data arrival time                              2.431
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        IO_0_PADIN (f)
               +     0.000          net: IO_0_PADIN
  0.000                        usb_mss_0/FIO_INBUF_0/U0/U0:PAD (f)
               +     0.277          cell: ADLIB:IOPAD_IN
  0.277                        usb_mss_0/FIO_INBUF_0/U0/U0:Y (f)
               +     0.000          net: usb_mss_0/FIO_INBUF_0/U0/Y_INT
  0.277                        usb_mss_0/FIO_INBUF_0/U0/U1:PIN1INT (f)
               +     0.042          cell: ADLIB:MSS_IF
  0.319                        usb_mss_0/FIO_INBUF_0/U0/U1:PIN1 (f)
               +     2.112          net: IO_0_Y
  2.431                        usb_slave_0/input_32_bit_data[22]:CLR (f)
                                    
  2.431                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          USB_CLK
               +     0.000          Clock source
  N/C                          USB_CLK (r)
               +     0.000          net: USB_CLK
  N/C                          USB_CLK_pad/U0/U0:PAD (r)
               +     0.470          cell: ADLIB:IOPAD_IN
  N/C                          USB_CLK_pad/U0/U0:Y (r)
               +     0.000          net: USB_CLK_pad/U0/NET1
  N/C                          USB_CLK_pad/U0/U1:A (r)
               +     0.161          cell: ADLIB:CLKSRC
  N/C                          USB_CLK_pad/U0/U1:Y (r)
               +     0.369          net: USB_CLK_c
  N/C                          usb_slave_0/input_32_bit_data[22]:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1C1
  N/C                          usb_slave_0/input_32_bit_data[22]:CLR


END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        usb_slave_0/INTRPT_COUNT[7]:CLK
  To:                          usb_slave_0/INTRPT_COUNT[7]:D
  Delay (ns):                  0.748
  Slack (ns):
  Arrival (ns):                1.078
  Required (ns):
  Hold (ns):                   0.000

Path 2
  From:                        usb_slave_0/INTRPT_COUNT[1]:CLK
  To:                          usb_slave_0/INTRPT_COUNT[1]:D
  Delay (ns):                  0.781
  Slack (ns):
  Arrival (ns):                1.106
  Required (ns):
  Hold (ns):                   0.000

Path 3
  From:                        usb_slave_0/FABINT/U1:CLK
  To:                          usb_slave_0/FABINT/U1:D
  Delay (ns):                  0.798
  Slack (ns):
  Arrival (ns):                1.120
  Required (ns):
  Hold (ns):                   0.000

Path 4
  From:                        usb_slave_0/HADDR_TEMP[29]/U1:CLK
  To:                          usb_slave_0/HADDR_TEMP[29]/U1:D
  Delay (ns):                  0.823
  Slack (ns):
  Arrival (ns):                1.145
  Required (ns):
  Hold (ns):                   0.000

Path 5
  From:                        usb_slave_0/HADDR_TEMP[17]/U1:CLK
  To:                          usb_slave_0/HADDR_TEMP[17]/U1:D
  Delay (ns):                  0.828
  Slack (ns):
  Arrival (ns):                1.150
  Required (ns):
  Hold (ns):                   0.000


Expanded Path 1
  From: usb_slave_0/INTRPT_COUNT[7]:CLK
  To: usb_slave_0/INTRPT_COUNT[7]:D
  data arrival time                              1.078
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        usb_mss_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: usb_mss_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  0.000                        usb_mss_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        usb_mss_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.330          net: FAB_CLK
  0.330                        usb_slave_0/INTRPT_COUNT[7]:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  0.579                        usb_slave_0/INTRPT_COUNT[7]:Q (r)
               +     0.205          net: usb_slave_0/INTRPT_COUNT[7]
  0.784                        usb_slave_0/INTRPT_COUNT_RNO[7]:A (r)
               +     0.148          cell: ADLIB:XA1
  0.932                        usb_slave_0/INTRPT_COUNT_RNO[7]:Y (r)
               +     0.146          net: usb_slave_0/N_24
  1.078                        usb_slave_0/INTRPT_COUNT[7]:D (r)
                                    
  1.078                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          usb_mss_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: usb_mss_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  N/C                          usb_mss_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          usb_mss_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.346          net: FAB_CLK
  N/C                          usb_slave_0/INTRPT_COUNT[7]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          usb_slave_0/INTRPT_COUNT[7]:D


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin usb_mss_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          usb_mss_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.277
  Slack (ns):
  Arrival (ns):                0.277
  Required (ns):
  Hold (ns):                   1.294
  External Hold (ns):          1.288


Expanded Path 1
  From: MSS_RESET_N
  To: usb_mss_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.277
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        usb_mss_0/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.277          cell: ADLIB:IOPAD_IN
  0.277                        usb_mss_0/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: usb_mss_0/MSS_RESET_0_MSS_RESET_N_Y
  0.277                        usb_mss_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.277                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          usb_mss_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.271          net: usb_mss_0/GLA0
  N/C                          usb_mss_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.294          Library hold time: ADLIB:MSS_AHB_IP
  N/C                          usb_mss_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain usb_mss_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

Path 1
  From:                        IO_0_PADIN
  To:                          USB_DATA_PAD[5]
  Delay (ns):                  4.727
  Slack (ns):
  Arrival (ns):                4.727
  Required (ns):

Path 2
  From:                        IO_0_PADIN
  To:                          USB_DATA_PAD[0]
  Delay (ns):                  4.829
  Slack (ns):
  Arrival (ns):                4.829
  Required (ns):

Path 3
  From:                        IO_0_PADIN
  To:                          USB_DATA_PAD[6]
  Delay (ns):                  4.945
  Slack (ns):
  Arrival (ns):                4.945
  Required (ns):

Path 4
  From:                        IO_0_PADIN
  To:                          USB_DATA_PAD[1]
  Delay (ns):                  5.229
  Slack (ns):
  Arrival (ns):                5.229
  Required (ns):

Path 5
  From:                        IO_0_PADIN
  To:                          USB_DATA_PAD[2]
  Delay (ns):                  5.229
  Slack (ns):
  Arrival (ns):                5.229
  Required (ns):


Expanded Path 1
  From: IO_0_PADIN
  To: USB_DATA_PAD[5]
  data arrival time                              4.727
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        IO_0_PADIN (r)
               +     0.000          net: IO_0_PADIN
  0.000                        usb_mss_0/FIO_INBUF_0/U0/U0:PAD (r)
               +     0.392          cell: ADLIB:IOPAD_IN
  0.392                        usb_mss_0/FIO_INBUF_0/U0/U0:Y (r)
               +     0.000          net: usb_mss_0/FIO_INBUF_0/U0/Y_INT
  0.392                        usb_mss_0/FIO_INBUF_0/U0/U1:PIN1INT (r)
               +     0.042          cell: ADLIB:MSS_IF
  0.434                        usb_mss_0/FIO_INBUF_0/U0/U1:PIN1 (r)
               +     1.626          net: IO_0_Y
  2.060                        usb_mss_0/FIO_INBUF_0_RNI5UVF:A (r)
               +     0.156          cell: ADLIB:BUFF
  2.216                        usb_mss_0/FIO_INBUF_0_RNI5UVF:Y (r)
               +     1.209          net: IO_0_Y_0
  3.425                        usb_slave_0/GEN.5.DATA_PINS/U0/U1:E (r)
               +     0.183          cell: ADLIB:IOBI_IB_OB_EB
  3.608                        usb_slave_0/GEN.5.DATA_PINS/U0/U1:EOUT (r)
               +     0.000          net: usb_slave_0/GEN_5_DATA_PINS/U0/NET2
  3.608                        usb_slave_0/GEN.5.DATA_PINS/U0/U0:E (r)
               +     1.119          cell: ADLIB:IOPAD_BI
  4.727                        usb_slave_0/GEN.5.DATA_PINS/U0/U0:PAD (r)
               +     0.000          net: USB_DATA_PAD[5]
  4.727                        USB_DATA_PAD[5] (r)
                                    
  4.727                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          IO_0_PADIN (r)
                                    
  N/C                          USB_DATA_PAD[5] (r)
                                    
  N/C                          data required time


END SET Input to Output

----------------------------------------------------

Path set User Sets

