Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Thu Dec 08 10:37:18 2011


Design: DSP_Coprocessor
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                8.030
Frequency (MHz):            124.533
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                14.723
Frequency (MHz):            67.921
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        -4.928
External Hold (ns):         4.007
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               DSP_Coprocessor_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[14]
  Delay (ns):                  9.858
  Slack (ns):                  16.970
  Arrival (ns):                13.785
  Required (ns):               30.755
  Setup (ns):                  -1.828
  Minimum Period (ns):         8.030

Path 2
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[15]
  Delay (ns):                  9.823
  Slack (ns):                  17.006
  Arrival (ns):                13.750
  Required (ns):               30.756
  Setup (ns):                  -1.829
  Minimum Period (ns):         7.994

Path 3
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[8]
  Delay (ns):                  9.409
  Slack (ns):                  17.409
  Arrival (ns):                13.336
  Required (ns):               30.745
  Setup (ns):                  -1.818
  Minimum Period (ns):         7.591

Path 4
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[6]
  Delay (ns):                  9.334
  Slack (ns):                  17.491
  Arrival (ns):                13.261
  Required (ns):               30.752
  Setup (ns):                  -1.825
  Minimum Period (ns):         7.509

Path 5
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[3]
  Delay (ns):                  9.326
  Slack (ns):                  17.498
  Arrival (ns):                13.253
  Required (ns):               30.751
  Setup (ns):                  -1.824
  Minimum Period (ns):         7.502


Expanded Path 1
  From: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[14]
  data required time                             30.755
  data arrival time                          -   13.785
  slack                                          16.970
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.927          Clock generation
  3.927
               +     2.343          cell: ADLIB:MSS_APB_IP
  6.270                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPADDR[9] (r)
               +     0.099          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPADDR[9]INT_NET
  6.369                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_33:PIN1INT (r)
               +     0.074          cell: ADLIB:MSS_IF
  6.443                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_33:PIN1 (r)
               +     1.389          net: CoreAPB3_0_APBmslave0_PADDR_[9]
  7.832                        CoreAPB3_0/CAPB3O11_1_0[0]:B (r)
               +     0.486          cell: ADLIB:OR3A
  8.318                        CoreAPB3_0/CAPB3O11_1_0[0]:Y (r)
               +     0.237          net: CoreAPB3_0/CAPB3O11_1_0[0]
  8.555                        CoreAPB3_0/CAPB3O11[0]:A (r)
               +     0.353          cell: ADLIB:NOR2
  8.908                        CoreAPB3_0/CAPB3O11[0]:Y (f)
               +     1.539          net: CoreAPB3_0_APBmslave0_PSELx
  10.447                       CoreAPB3_0/CAPB3llOI/PRDATA_14:B (f)
               +     0.476          cell: ADLIB:NOR2B
  10.923                       CoreAPB3_0/CAPB3llOI/PRDATA_14:Y (f)
               +     2.294          net: PRDATA_14
  13.217                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_41:PIN4 (f)
               +     0.158          cell: ADLIB:MSS_IF
  13.375                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_41:PIN4INT (f)
               +     0.410          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPRDATA[14]INT_NET
  13.785                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[14] (f)
                                    
  13.785                       data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_fabric_interface_clock
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.927          Clock generation
  28.927
               -    -1.828          Library setup time: ADLIB:MSS_APB_IP
  30.755                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[14]
                                    
  30.755                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_fabric_interface_clock

Path 1
  From:                        Aapb_int_fft_0/PREADY0:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  4.084
  Slack (ns):                  19.981
  Arrival (ns):                9.926
  Required (ns):               29.907
  Setup (ns):                  -0.980

Path 2
  From:                        Aapb_int_fft_0/PREADY1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  4.066
  Slack (ns):                  19.999
  Arrival (ns):                9.908
  Required (ns):               29.907
  Setup (ns):                  -0.980

Path 3
  From:                        Aapb_int_fft_0/EMPTY_OUT_REG/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  4.018
  Slack (ns):                  20.018
  Arrival (ns):                9.889
  Required (ns):               29.907
  Setup (ns):                  -0.980

Path 4
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  3.749
  Slack (ns):                  20.259
  Arrival (ns):                9.648
  Required (ns):               29.907
  Setup (ns):                  -0.980

Path 5
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_7_inst/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[7]
  Delay (ns):                  4.456
  Slack (ns):                  20.465
  Arrival (ns):                10.287
  Required (ns):               30.752
  Setup (ns):                  -1.825


Expanded Path 1
  From: Aapb_int_fft_0/PREADY0:CLK
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  data required time                             29.907
  data arrival time                          -   9.926
  slack                                          19.981
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.593          net: FAB_CLK
  5.842                        Aapb_int_fft_0/PREADY0:CLK (r)
               +     0.440          cell: ADLIB:DFN1P0
  6.282                        Aapb_int_fft_0/PREADY0:Q (r)
               +     0.292          net: Aapb_int_fft_0/PREADY0
  6.574                        Aapb_int_fft_0/PREADY1_RNIA7U4:B (r)
               +     0.543          cell: ADLIB:NOR3B
  7.117                        Aapb_int_fft_0/PREADY1_RNIA7U4:Y (r)
               +     0.255          net: Aapb_int_fft_0/un1_PREADY
  7.372                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_RNIBGQ7:A (r)
               +     0.431          cell: ADLIB:MX2C
  7.803                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_RNIBGQ7:Y (f)
               +     0.255          net: CoreAPB3_0_APBmslave0_PREADY
  8.058                        CoreAPB3_0/CAPB3llOI/PREADY:B (f)
               +     0.479          cell: ADLIB:OR2B
  8.537                        CoreAPB3_0/CAPB3llOI/PREADY:Y (r)
               +     0.979          net: DSP_Coprocessor_MSS_0_MSS_MASTER_APB_PREADY
  9.516                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_36:PIN5 (r)
               +     0.066          cell: ADLIB:MSS_IF
  9.582                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_36:PIN5INT (r)
               +     0.344          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPREADYINT_NET
  9.926                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY (r)
                                    
  9.926                        data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_fabric_interface_clock
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.927          Clock generation
  28.927
               -    -0.980          Library setup time: ADLIB:MSS_APB_IP
  29.907                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
                                    
  29.907                       data required time


END SET mss_ccc_gla1 to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_pclk1

Path 1
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[2]
  Delay (ns):                  2.653
  Slack (ns):                  21.493
  Arrival (ns):                8.506
  Required (ns):               29.999
  Setup (ns):                  -1.072

Path 2
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1P0_EMPTY:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[3]
  Delay (ns):                  2.436
  Slack (ns):                  21.808
  Arrival (ns):                8.239
  Required (ns):               30.047
  Setup (ns):                  -1.120

Path 3
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[0]
  Delay (ns):                  2.179
  Slack (ns):                  21.907
  Arrival (ns):                8.078
  Required (ns):               29.985
  Setup (ns):                  -1.058

Path 4
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[1]
  Delay (ns):                  1.594
  Slack (ns):                  22.534
  Arrival (ns):                7.445
  Required (ns):               29.979
  Setup (ns):                  -1.052


Expanded Path 1
  From: Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:CLK
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[2]
  data required time                             29.999
  data arrival time                          -   8.506
  slack                                          21.493
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.604          net: FAB_CLK
  5.853                        Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:CLK (r)
               +     0.559          cell: ADLIB:DFN1P0
  6.412                        Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:Q (f)
               +     1.936          net: Aapb_int_fft_0_AEMPTY_OUT
  8.348                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_22:PIN5 (f)
               +     0.158          cell: ADLIB:MSS_IF
  8.506                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_22:PIN5INT (f)
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/GPI[2]INT_NET
  8.506                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[2] (f)
                                    
  8.506                        data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_pclk1
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     3.927          Clock generation
  28.927
               -    -1.072          Library setup time: ADLIB:MSS_APB_IP
  29.999                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[2]
                                    
  29.999                       data required time


END SET mss_ccc_gla1 to mss_pclk1

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        Aapb_int_fft_0/PENABLE_reg:CLK
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D
  Delay (ns):                  14.337
  Slack (ns):                  10.277
  Arrival (ns):                20.141
  Required (ns):               30.418
  Setup (ns):                  0.435
  Minimum Period (ns):         14.723

Path 2
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1C0_FULL:CLK
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1C0_AFULL:D
  Delay (ns):                  12.609
  Slack (ns):                  11.985
  Arrival (ns):                18.457
  Required (ns):               30.442
  Setup (ns):                  0.409
  Minimum Period (ns):         13.015

Path 3
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1P0_EMPTY:CLK
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D
  Delay (ns):                  12.593
  Slack (ns):                  12.022
  Arrival (ns):                18.396
  Required (ns):               30.418
  Setup (ns):                  0.435
  Minimum Period (ns):         12.978

Path 4
  From:                        Aapb_int_fft_0/ifoY_valid:CLK
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1C0_AFULL:D
  Delay (ns):                  12.431
  Slack (ns):                  12.154
  Arrival (ns):                18.288
  Required (ns):               30.442
  Setup (ns):                  0.409
  Minimum Period (ns):         12.846

Path 5
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1C0_MEM_WADDR_0_inst:CLK
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1C0_AFULL:D
  Delay (ns):                  11.592
  Slack (ns):                  13.002
  Arrival (ns):                17.440
  Required (ns):               30.442
  Setup (ns):                  0.409
  Minimum Period (ns):         11.998


Expanded Path 1
  From: Aapb_int_fft_0/PENABLE_reg:CLK
  To: Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D
  data required time                             30.418
  data arrival time                          -   20.141
  slack                                          10.277
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.555          net: FAB_CLK
  5.804                        Aapb_int_fft_0/PENABLE_reg:CLK (r)
               +     0.559          cell: ADLIB:DFN1P0
  6.363                        Aapb_int_fft_0/PENABLE_reg:Q (f)
               +     0.264          net: Aapb_int_fft_0/PENABLE_reg_i
  6.627                        Aapb_int_fft_0/PENABLE_reg_RNICCCC:B (f)
               +     0.486          cell: ADLIB:NOR3C
  7.113                        Aapb_int_fft_0/PENABLE_reg_RNICCCC:Y (f)
               +     0.256          net: Aapb_int_fft_0/un1_fifo_rd_en_m2_e_3
  7.369                        Aapb_int_fft_0/PENABLE_reg_RNI4HTI:B (f)
               +     0.460          cell: ADLIB:NOR3B
  7.829                        Aapb_int_fft_0/PENABLE_reg_RNI4HTI:Y (f)
               +     0.842          net: Aapb_int_fft_0/REP
  8.671                        Aapb_int_fft_0/fifo64X16_inst/AND2_MEMORYRE:B (f)
               +     0.476          cell: ADLIB:AND2A
  9.147                        Aapb_int_fft_0/fifo64X16_inst/AND2_MEMORYRE:Y (f)
               +     0.360          net: Aapb_int_fft_0/fifo64X16_inst/MEMORYRE
  9.507                        Aapb_int_fft_0/fifo64X16_inst/AND2_55:B (f)
               +     0.479          cell: ADLIB:AND2
  9.986                        Aapb_int_fft_0/fifo64X16_inst/AND2_55:Y (f)
               +     0.801          net: Aapb_int_fft_0/fifo64X16_inst/AND2_55_Y
  10.787                       Aapb_int_fft_0/fifo64X16_inst/AO1_15:B (f)
               +     0.479          cell: ADLIB:NOR2B
  11.266                       Aapb_int_fft_0/fifo64X16_inst/AO1_15:Y (f)
               +     0.364          net: Aapb_int_fft_0/fifo64X16_inst/AO1_15_Y
  11.630                       Aapb_int_fft_0/fifo64X16_inst/AO1_29:C (f)
               +     0.517          cell: ADLIB:NOR3C
  12.147                       Aapb_int_fft_0/fifo64X16_inst/AO1_29:Y (f)
               +     0.340          net: Aapb_int_fft_0/fifo64X16_inst/AO1_29_Y
  12.487                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RBINNXTSHIFT_4_inst:B (f)
               +     0.711          cell: ADLIB:XOR2
  13.198                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RBINNXTSHIFT_4_inst:Y (r)
               +     0.533          net: Aapb_int_fft_0/fifo64X16_inst/RBINNXTSHIFT_4_net
  13.731                       Aapb_int_fft_0/fifo64X16_inst/INV_13:A (r)
               +     0.276          cell: ADLIB:INV
  14.007                       Aapb_int_fft_0/fifo64X16_inst/INV_13:Y (f)
               +     0.292          net: Aapb_int_fft_0/fifo64X16_inst/INV_13_Y
  14.299                       Aapb_int_fft_0/fifo64X16_inst/XOR2_38:B (f)
               +     0.711          cell: ADLIB:XOR2
  15.010                       Aapb_int_fft_0/fifo64X16_inst/XOR2_38:Y (r)
               +     0.295          net: Aapb_int_fft_0/fifo64X16_inst/XOR2_38_Y
  15.305                       Aapb_int_fft_0/fifo64X16_inst/AO1_7:A (r)
               +     0.394          cell: ADLIB:AO1
  15.699                       Aapb_int_fft_0/fifo64X16_inst/AO1_7:Y (r)
               +     0.551          net: Aapb_int_fft_0/fifo64X16_inst/AO1_7_Y
  16.250                       Aapb_int_fft_0/fifo64X16_inst/AO1_10:C (r)
               +     0.497          cell: ADLIB:AO1
  16.747                       Aapb_int_fft_0/fifo64X16_inst/AO1_10:Y (r)
               +     0.308          net: Aapb_int_fft_0/fifo64X16_inst/AO1_10_Y
  17.055                       Aapb_int_fft_0/fifo64X16_inst/AO1_1:B (r)
               +     0.430          cell: ADLIB:AO1
  17.485                       Aapb_int_fft_0/fifo64X16_inst/AO1_1:Y (r)
               +     0.255          net: Aapb_int_fft_0/fifo64X16_inst/AO1_1_Y
  17.740                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RDIFF_6_inst:C (r)
               +     0.747          cell: ADLIB:XNOR3
  18.487                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RDIFF_6_inst:Y (f)
               +     0.294          net: Aapb_int_fft_0/fifo64X16_inst/RDIFF_6_net
  18.781                       Aapb_int_fft_0/fifo64X16_inst/AND3_0:A (f)
               +     0.398          cell: ADLIB:AND3C
  19.179                       Aapb_int_fft_0/fifo64X16_inst/AND3_0:Y (r)
               +     0.255          net: Aapb_int_fft_0/fifo64X16_inst/AND3_0_Y
  19.434                       Aapb_int_fft_0/fifo64X16_inst/AOI1_0:A (r)
               +     0.460          cell: ADLIB:AOI1
  19.894                       Aapb_int_fft_0/fifo64X16_inst/AOI1_0:Y (f)
               +     0.247          net: Aapb_int_fft_0/fifo64X16_inst/AOI1_0_Y
  20.141                       Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D (f)
                                    
  20.141                       data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_ccc_gla1
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  30.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.604          net: FAB_CLK
  30.853                       Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:CLK (r)
               -     0.435          Library setup time: ADLIB:DFN1P0
  30.418                       Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D
                                    
  30.418                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/wA[0]:CLR
  Delay (ns):                  5.809
  Slack (ns):                  18.943
  Arrival (ns):                11.621
  Required (ns):               30.564
  Recovery (ns):               0.225
  Minimum Period (ns):         6.057
  Skew (ns):                   0.023

Path 2
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/wA[2]:CLR
  Delay (ns):                  5.850
  Slack (ns):                  18.956
  Arrival (ns):                11.662
  Required (ns):               30.618
  Recovery (ns):               0.225
  Minimum Period (ns):         6.044
  Skew (ns):                   -0.031

Path 3
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/Q[0]:CLR
  Delay (ns):                  5.850
  Slack (ns):                  18.956
  Arrival (ns):                11.662
  Required (ns):               30.618
  Recovery (ns):               0.225
  Minimum Period (ns):         6.044
  Skew (ns):                   -0.031

Path 4
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/Q[4]:CLR
  Delay (ns):                  5.850
  Slack (ns):                  18.956
  Arrival (ns):                11.662
  Required (ns):               30.618
  Recovery (ns):               0.225
  Minimum Period (ns):         6.044
  Skew (ns):                   -0.031

Path 5
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/Q[5]:CLR
  Delay (ns):                  5.850
  Slack (ns):                  18.956
  Arrival (ns):                11.662
  Required (ns):               30.618
  Recovery (ns):               0.225
  Minimum Period (ns):         6.044
  Skew (ns):                   -0.031


Expanded Path 1
  From: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK
  To: Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/wA[0]:CLR
  data required time                             30.564
  data arrival time                          -   11.621
  slack                                          18.943
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.563          net: FAB_CLK
  5.812                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK (r)
               +     0.559          cell: ADLIB:DFN1P0
  6.371                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:Q (f)
               +     1.596          net: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/initRst
  7.967                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835:B (f)
               +     0.370          cell: ADLIB:NOR2A
  8.337                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835:Y (r)
               +     2.068          net: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835
  10.405                       Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835_0/U_CLKSRC:A (r)
               +     0.691          cell: ADLIB:CLKSRC
  11.096                       Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835_0/U_CLKSRC:Y (r)
               +     0.525          net: Aapb_int_fft_0/fftTop_inst/smTop_0/nGrst
  11.621                       Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/wA[0]:CLR (r)
                                    
  11.621                       data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_ccc_gla1
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  30.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.540          net: FAB_CLK
  30.789                       Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/wA[0]:CLK (r)
               -     0.225          Library recovery time: ADLIB:DFN1C0
  30.564                       Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/wA[0]:CLR
                                    
  30.564                       data required time


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_gla1

Path 1
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D
  Delay (ns):                  17.709
  Slack (ns):                  8.782
  Arrival (ns):                21.636
  Required (ns):               30.418
  Setup (ns):                  0.435

Path 2
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1P0_EMPTY:D
  Delay (ns):                  14.731
  Slack (ns):                  11.736
  Arrival (ns):                18.658
  Required (ns):               30.394
  Setup (ns):                  0.409

Path 3
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1C0_MEM_RADDR_6_inst:D
  Delay (ns):                  11.097
  Slack (ns):                  15.370
  Arrival (ns):                15.024
  Required (ns):               30.394
  Setup (ns):                  0.409

Path 4
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1C0_MEM_RADDR_5_inst:D
  Delay (ns):                  11.046
  Slack (ns):                  15.421
  Arrival (ns):                14.973
  Required (ns):               30.394
  Setup (ns):                  0.409

Path 5
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1C0_MEM_RADDR_4_inst:D
  Delay (ns):                  11.044
  Slack (ns):                  15.477
  Arrival (ns):                14.971
  Required (ns):               30.448
  Setup (ns):                  0.409


Expanded Path 1
  From: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To: Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D
  data required time                             30.418
  data arrival time                          -   21.636
  slack                                          8.782
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.927          Clock generation
  3.927
               +     2.266          cell: ADLIB:MSS_APB_IP
  6.193                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPENABLE (f)
               +     0.130          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPENABLEINT_NET
  6.323                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_42:PIN2INT (f)
               +     0.079          cell: ADLIB:MSS_IF
  6.402                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_42:PIN2 (f)
               +     0.966          net: CoreAPB3_0_APBmslave0_PENABLE
  7.368                        Aapb_int_fft_0/un1_fifo_rd_en_m2_e_2:A (f)
               +     0.476          cell: ADLIB:NOR2A
  7.844                        Aapb_int_fft_0/un1_fifo_rd_en_m2_e_2:Y (f)
               +     0.963          net: Aapb_int_fft_0/un1_fifo_rd_en_m2_e_2
  8.807                        Aapb_int_fft_0/PENABLE_reg_RNI4HTI:A (f)
               +     0.517          cell: ADLIB:NOR3B
  9.324                        Aapb_int_fft_0/PENABLE_reg_RNI4HTI:Y (f)
               +     0.842          net: Aapb_int_fft_0/REP
  10.166                       Aapb_int_fft_0/fifo64X16_inst/AND2_MEMORYRE:B (f)
               +     0.476          cell: ADLIB:AND2A
  10.642                       Aapb_int_fft_0/fifo64X16_inst/AND2_MEMORYRE:Y (f)
               +     0.360          net: Aapb_int_fft_0/fifo64X16_inst/MEMORYRE
  11.002                       Aapb_int_fft_0/fifo64X16_inst/AND2_55:B (f)
               +     0.479          cell: ADLIB:AND2
  11.481                       Aapb_int_fft_0/fifo64X16_inst/AND2_55:Y (f)
               +     0.801          net: Aapb_int_fft_0/fifo64X16_inst/AND2_55_Y
  12.282                       Aapb_int_fft_0/fifo64X16_inst/AO1_15:B (f)
               +     0.479          cell: ADLIB:NOR2B
  12.761                       Aapb_int_fft_0/fifo64X16_inst/AO1_15:Y (f)
               +     0.364          net: Aapb_int_fft_0/fifo64X16_inst/AO1_15_Y
  13.125                       Aapb_int_fft_0/fifo64X16_inst/AO1_29:C (f)
               +     0.517          cell: ADLIB:NOR3C
  13.642                       Aapb_int_fft_0/fifo64X16_inst/AO1_29:Y (f)
               +     0.340          net: Aapb_int_fft_0/fifo64X16_inst/AO1_29_Y
  13.982                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RBINNXTSHIFT_4_inst:B (f)
               +     0.711          cell: ADLIB:XOR2
  14.693                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RBINNXTSHIFT_4_inst:Y (r)
               +     0.533          net: Aapb_int_fft_0/fifo64X16_inst/RBINNXTSHIFT_4_net
  15.226                       Aapb_int_fft_0/fifo64X16_inst/INV_13:A (r)
               +     0.276          cell: ADLIB:INV
  15.502                       Aapb_int_fft_0/fifo64X16_inst/INV_13:Y (f)
               +     0.292          net: Aapb_int_fft_0/fifo64X16_inst/INV_13_Y
  15.794                       Aapb_int_fft_0/fifo64X16_inst/XOR2_38:B (f)
               +     0.711          cell: ADLIB:XOR2
  16.505                       Aapb_int_fft_0/fifo64X16_inst/XOR2_38:Y (r)
               +     0.295          net: Aapb_int_fft_0/fifo64X16_inst/XOR2_38_Y
  16.800                       Aapb_int_fft_0/fifo64X16_inst/AO1_7:A (r)
               +     0.394          cell: ADLIB:AO1
  17.194                       Aapb_int_fft_0/fifo64X16_inst/AO1_7:Y (r)
               +     0.551          net: Aapb_int_fft_0/fifo64X16_inst/AO1_7_Y
  17.745                       Aapb_int_fft_0/fifo64X16_inst/AO1_10:C (r)
               +     0.497          cell: ADLIB:AO1
  18.242                       Aapb_int_fft_0/fifo64X16_inst/AO1_10:Y (r)
               +     0.308          net: Aapb_int_fft_0/fifo64X16_inst/AO1_10_Y
  18.550                       Aapb_int_fft_0/fifo64X16_inst/AO1_1:B (r)
               +     0.430          cell: ADLIB:AO1
  18.980                       Aapb_int_fft_0/fifo64X16_inst/AO1_1:Y (r)
               +     0.255          net: Aapb_int_fft_0/fifo64X16_inst/AO1_1_Y
  19.235                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RDIFF_6_inst:C (r)
               +     0.747          cell: ADLIB:XNOR3
  19.982                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RDIFF_6_inst:Y (f)
               +     0.294          net: Aapb_int_fft_0/fifo64X16_inst/RDIFF_6_net
  20.276                       Aapb_int_fft_0/fifo64X16_inst/AND3_0:A (f)
               +     0.398          cell: ADLIB:AND3C
  20.674                       Aapb_int_fft_0/fifo64X16_inst/AND3_0:Y (r)
               +     0.255          net: Aapb_int_fft_0/fifo64X16_inst/AND3_0_Y
  20.929                       Aapb_int_fft_0/fifo64X16_inst/AOI1_0:A (r)
               +     0.460          cell: ADLIB:AOI1
  21.389                       Aapb_int_fft_0/fifo64X16_inst/AOI1_0:Y (f)
               +     0.247          net: Aapb_int_fft_0/fifo64X16_inst/AOI1_0_Y
  21.636                       Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D (f)
                                    
  21.636                       data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_ccc_gla1
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  30.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.604          net: FAB_CLK
  30.853                       Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:CLK (r)
               -     0.435          Library setup time: ADLIB:DFN1P0
  30.418                       Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D
                                    
  30.418                       data required time


END SET mss_fabric_interface_clock to mss_ccc_gla1

----------------------------------------------------

SET mss_ccc_gla0 to mss_ccc_gla1

Path 1
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/wA[0]:CLR
  Delay (ns):                  9.293
  Slack (ns):                  17.344
  Arrival (ns):                13.220
  Required (ns):               30.564
  Setup (ns):

Path 2
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/wA[2]:CLR
  Delay (ns):                  9.334
  Slack (ns):                  17.357
  Arrival (ns):                13.261
  Required (ns):               30.618
  Setup (ns):

Path 3
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/Q[0]:CLR
  Delay (ns):                  9.334
  Slack (ns):                  17.357
  Arrival (ns):                13.261
  Required (ns):               30.618
  Setup (ns):

Path 4
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/Q[4]:CLR
  Delay (ns):                  9.334
  Slack (ns):                  17.357
  Arrival (ns):                13.261
  Required (ns):               30.618
  Setup (ns):

Path 5
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/Q[5]:CLR
  Delay (ns):                  9.334
  Slack (ns):                  17.357
  Arrival (ns):                13.261
  Required (ns):               30.618
  Setup (ns):


Expanded Path 1
  From: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To: Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/wA[0]:CLR
  data required time                             30.564
  data arrival time                          -   13.220
  slack                                          17.344
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  3.545
               +     0.382          net: DSP_Coprocessor_MSS_0/GLA0
  3.927                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     2.776          cell: ADLIB:MSS_APB_IP
  6.703                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:M2FRESETn (r)
               +     0.101          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/M2FRESETnINT_NET
  6.804                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_46:PIN2INT (r)
               +     0.079          cell: ADLIB:MSS_IF
  6.883                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_46:PIN2 (r)
               +     2.661          net: DSP_Coprocessor_MSS_0_M2F_RESET_N
  9.544                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835:A (r)
               +     0.392          cell: ADLIB:NOR2A
  9.936                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835:Y (r)
               +     2.068          net: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835
  12.004                       Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835_0/U_CLKSRC:A (r)
               +     0.691          cell: ADLIB:CLKSRC
  12.695                       Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835_0/U_CLKSRC:Y (r)
               +     0.525          net: Aapb_int_fft_0/fftTop_inst/smTop_0/nGrst
  13.220                       Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/wA[0]:CLR (r)
                                    
  13.220                       data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_ccc_gla1
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  30.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.540          net: FAB_CLK
  30.789                       Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/wA[0]:CLK (r)
               -     0.225          Library recovery time: ADLIB:DFN1C0
  30.564                       Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/wA[0]:CLR
                                    
  30.564                       data required time


END SET mss_ccc_gla0 to mss_ccc_gla1

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.781
  Slack (ns):
  Arrival (ns):                0.781
  Required (ns):
  Setup (ns):                  -1.782
  External Setup (ns):         -4.928


Expanded Path 1
  From: MSS_RESET_N
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.781
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        DSP_Coprocessor_MSS_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.781          cell: ADLIB:IOPAD_IN
  0.781                        DSP_Coprocessor_MSS_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_RESET_0_MSS_RESET_N_Y
  0.781                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.781                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  N/C
               +     0.382          net: DSP_Coprocessor_MSS_0/GLA0
  N/C                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -1.782          Library setup time: ADLIB:MSS_APB_IP
  N/C                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain DSP_Coprocessor_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

