Timing Report Min Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Thu Dec 08 10:34:56 2011


Design: DSP_Coprocessor
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                7.315
Frequency (MHz):            136.705
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                14.506
Frequency (MHz):            68.937
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        -4.928
External Hold (ns):         4.007
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               DSP_Coprocessor_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  3.491
  Slack (ns):                  2.360
  Arrival (ns):                6.440
  Required (ns):               4.080
  Hold (ns):                   1.131

Path 2
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[6]
  Delay (ns):                  4.348
  Slack (ns):                  3.040
  Arrival (ns):                7.297
  Required (ns):               4.257
  Hold (ns):                   1.308

Path 3
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[13]
  Delay (ns):                  4.375
  Slack (ns):                  3.064
  Arrival (ns):                7.324
  Required (ns):               4.260
  Hold (ns):                   1.311

Path 4
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[15]
  Delay (ns):                  4.403
  Slack (ns):                  3.093
  Arrival (ns):                7.352
  Required (ns):               4.259
  Hold (ns):                   1.310

Path 5
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[7]
  Delay (ns):                  4.511
  Slack (ns):                  3.182
  Arrival (ns):                7.460
  Required (ns):               4.278
  Hold (ns):                   1.329


Expanded Path 1
  From: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  data arrival time                              6.440
  data required time                         -   4.080
  slack                                          2.360
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.949          Clock generation
  2.949
               +     1.278          cell: ADLIB:MSS_APB_IP
  4.227                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPWRITE (r)
               +     0.061          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPWRITEINT_NET
  4.288                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_42:PIN3INT (r)
               +     0.040          cell: ADLIB:MSS_IF
  4.328                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_42:PIN3 (r)
               +     0.612          net: CoreAPB3_0_APBmslave0_PWRITE
  4.940                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int_RNIN76C:S (r)
               +     0.156          cell: ADLIB:MX2C
  5.096                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int_RNIN76C:Y (r)
               +     0.152          net: CoreAPB3_0_APBmslave0_PREADY
  5.248                        CoreAPB3_0/CAPB3O1II/PREADY:B (r)
               +     0.256          cell: ADLIB:OR2B
  5.504                        CoreAPB3_0/CAPB3O1II/PREADY:Y (f)
               +     0.654          net: DSP_Coprocessor_MSS_0_MSS_MASTER_APB_PREADY
  6.158                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_36:PIN5 (f)
               +     0.045          cell: ADLIB:MSS_IF
  6.203                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_36:PIN5INT (f)
               +     0.237          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPREADYINT_NET
  6.440                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY (f)
                                    
  6.440                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.949          Clock generation
  2.949
               +     1.131          Library hold time: ADLIB:MSS_APB_IP
  4.080                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
                                    
  4.080                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_fabric_interface_clock

Path 1
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_6_inst/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[6]
  Delay (ns):                  1.491
  Slack (ns):                  1.593
  Arrival (ns):                5.872
  Required (ns):               4.279
  Hold (ns):                   1.330

Path 2
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_15_inst/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[15]
  Delay (ns):                  1.507
  Slack (ns):                  1.607
  Arrival (ns):                5.888
  Required (ns):               4.281
  Hold (ns):                   1.332

Path 3
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_5_inst/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[5]
  Delay (ns):                  1.596
  Slack (ns):                  1.694
  Arrival (ns):                5.973
  Required (ns):               4.279
  Hold (ns):                   1.330

Path 4
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_9_inst/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[9]
  Delay (ns):                  1.601
  Slack (ns):                  1.702
  Arrival (ns):                5.983
  Required (ns):               4.281
  Hold (ns):                   1.332

Path 5
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_4_inst/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[4]
  Delay (ns):                  1.628
  Slack (ns):                  1.726
  Arrival (ns):                6.005
  Required (ns):               4.279
  Hold (ns):                   1.330


Expanded Path 1
  From: Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_6_inst/U1:CLK
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[6]
  data arrival time                              5.872
  data required time                         -   4.279
  slack                                          1.593
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.346          net: FAB_CLK
  4.381                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_6_inst/U1:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  4.629                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_6_inst/U1:Q (r)
               +     0.189          net: _CoreAPB3_0_APBmslave0_PRDATA_[6]_
  4.818                        CoreAPB3_0/CAPB3O1II/PRDATA_6:B (r)
               +     0.221          cell: ADLIB:NOR2B
  5.039                        CoreAPB3_0/CAPB3O1II/PRDATA_6:Y (r)
               +     0.536          net: _DSP_Coprocessor_MSS_0_MSS_MASTER_APB_PRDATA_[6]_
  5.575                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_38:PIN6 (r)
               +     0.089          cell: ADLIB:MSS_IF
  5.664                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_38:PIN6INT (r)
               +     0.208          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPRDATA[6]INT_NET
  5.872                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[6] (r)
                                    
  5.872                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.949          Clock generation
  2.949
               +     1.330          Library hold time: ADLIB:MSS_APB_IP
  4.279                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[6]
                                    
  4.279                        data required time


END SET mss_ccc_gla1 to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_pclk1

Path 1
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[0]
  Delay (ns):                  1.017
  Slack (ns):                  1.638
  Arrival (ns):                5.396
  Required (ns):               3.758
  Hold (ns):                   0.809

Path 2
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1P0_EMPTY:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[3]
  Delay (ns):                  1.168
  Slack (ns):                  1.729
  Arrival (ns):                5.541
  Required (ns):               3.812
  Hold (ns):                   0.863

Path 3
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn_int:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[1]
  Delay (ns):                  1.049
  Slack (ns):                  1.729
  Arrival (ns):                5.474
  Required (ns):               3.745
  Hold (ns):                   0.796

Path 4
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[2]
  Delay (ns):                  1.382
  Slack (ns):                  1.989
  Arrival (ns):                5.755
  Required (ns):               3.766
  Hold (ns):                   0.817


Expanded Path 1
  From: Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int:CLK
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[0]
  data arrival time                              5.396
  data required time                         -   3.758
  slack                                          1.638
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.344          net: FAB_CLK
  4.379                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  4.627                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int:Q (r)
               +     0.732          net: Aapb_int_fft_0_FFT_IP_RDY
  5.359                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_20:PIN5 (r)
               +     0.037          cell: ADLIB:MSS_IF
  5.396                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_20:PIN5INT (r)
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/GPI[0]INT_NET
  5.396                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[0] (r)
                                    
  5.396                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_pclk1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     2.949          Clock generation
  2.949
               +     0.809          Library hold time: ADLIB:MSS_APB_IP
  3.758                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[0]
                                    
  3.758                        data required time


END SET mss_ccc_gla1 to mss_pclk1

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        Aapb_int_fft_0/fftTop_inst/twidLUT_1/rA_r[6]:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/twidLUT_1/twidLUT_0/wrapRam_0/actram_R0C0:RADDR6
  Delay (ns):                  0.464
  Slack (ns):                  0.295
  Arrival (ns):                4.836
  Required (ns):               4.541
  Hold (ns):                   0.000

Path 2
  From:                        Aapb_int_fft_0/fftTop_inst/twidLUT_1/rA_r[1]:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/twidLUT_1/twidLUT_0/wrapRam_0/actram_R0C0:RADDR1
  Delay (ns):                  0.464
  Slack (ns):                  0.295
  Arrival (ns):                4.836
  Required (ns):               4.541
  Hold (ns):                   0.000

Path 3
  From:                        Aapb_int_fft_0/fftTop_inst/bfly_0/pipe5[1]:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/bfly_0/pipe6[1]:D
  Delay (ns):                  0.393
  Slack (ns):                  0.318
  Arrival (ns):                4.772
  Required (ns):               4.454
  Hold (ns):                   0.000

Path 4
  From:                        Aapb_int_fft_0/fftTop_inst/outBuff_0/inQ_r[8]:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/outBuff_0/outBuf_1/wrapRam_0/actram_R0C0:WD8
  Delay (ns):                  0.473
  Slack (ns):                  0.339
  Arrival (ns):                4.865
  Required (ns):               4.526
  Hold (ns):                   0.000

Path 5
  From:                        Aapb_int_fft_0/fftTop_inst/bfly_0/PiT4_r[6]:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/bfly_0/PiT5_r[6]:D
  Delay (ns):                  0.393
  Slack (ns):                  0.348
  Arrival (ns):                4.785
  Required (ns):               4.437
  Hold (ns):                   0.000


Expanded Path 1
  From: Aapb_int_fft_0/fftTop_inst/twidLUT_1/rA_r[6]:CLK
  To: Aapb_int_fft_0/fftTop_inst/twidLUT_1/twidLUT_0/wrapRam_0/actram_R0C0:RADDR6
  data arrival time                              4.836
  data required time                         -   4.541
  slack                                          0.295
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.337          net: FAB_CLK
  4.372                        Aapb_int_fft_0/fftTop_inst/twidLUT_1/rA_r[6]:CLK (r)
               +     0.248          cell: ADLIB:DFN1
  4.620                        Aapb_int_fft_0/fftTop_inst/twidLUT_1/rA_r[6]:Q (r)
               +     0.216          net: Aapb_int_fft_0/fftTop_inst/twidLUT_1/rA_r[6]
  4.836                        Aapb_int_fft_0/fftTop_inst/twidLUT_1/twidLUT_0/wrapRam_0/actram_R0C0:RADDR6 (r)
                                    
  4.836                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.506          net: FAB_CLK
  4.541                        Aapb_int_fft_0/fftTop_inst/twidLUT_1/twidLUT_0/wrapRam_0/actram_R0C0:RCLK (r)
               +     0.000          Library hold time: ADLIB:RAM512X18
  4.541                        Aapb_int_fft_0/fftTop_inst/twidLUT_1/twidLUT_0/wrapRam_0/actram_R0C0:RADDR6
                                    
  4.541                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/stage_timer/Q_out[1]:CLR
  Delay (ns):                  3.087
  Slack (ns):                  3.031
  Arrival (ns):                7.445
  Required (ns):               4.414
  Removal (ns):                0.000
  Skew (ns):                   -0.056

Path 2
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ldCount/Q_out[1]:CLR
  Delay (ns):                  3.086
  Slack (ns):                  3.033
  Arrival (ns):                7.444
  Required (ns):               4.411
  Removal (ns):                0.000
  Skew (ns):                   -0.053

Path 3
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ldCount/Q_out[2]:CLR
  Delay (ns):                  3.086
  Slack (ns):                  3.033
  Arrival (ns):                7.444
  Required (ns):               4.411
  Removal (ns):                0.000
  Skew (ns):                   -0.053

Path 4
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/stage_timer/tc_out:CLR
  Delay (ns):                  3.084
  Slack (ns):                  3.036
  Arrival (ns):                7.442
  Required (ns):               4.406
  Removal (ns):                0.000
  Skew (ns):                   -0.048

Path 5
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rA_0/tc_out:CLR
  Delay (ns):                  3.085
  Slack (ns):                  3.041
  Arrival (ns):                7.443
  Required (ns):               4.402
  Removal (ns):                0.000
  Skew (ns):                   -0.044


Expanded Path 1
  From: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To: Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/stage_timer/Q_out[1]:CLR
  data arrival time                              7.445
  data required time                         -   4.414
  slack                                          3.031
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.323          net: FAB_CLK
  4.358                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK (r)
               +     0.319          cell: ADLIB:DFN1P0
  4.677                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:Q (f)
               +     0.567          net: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/initRst
  5.244                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8:B (f)
               +     0.209          cell: ADLIB:NOR2A
  5.453                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8:Y (r)
               +     1.292          net: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8
  6.745                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8_0/U_CLKSRC:A (r)
               +     0.390          cell: ADLIB:CLKSRC
  7.135                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8_0/U_CLKSRC:Y (r)
               +     0.310          net: Aapb_int_fft_0/fftTop_inst/smTop_0/nGrst
  7.445                        Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/stage_timer/Q_out[1]:CLR (r)
                                    
  7.445                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.379          net: FAB_CLK
  4.414                        Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/stage_timer/Q_out[1]:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1E0C0
  4.414                        Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/stage_timer/Q_out[1]:CLR
                                    
  4.414                        data required time


END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_gla1

Path 1
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/PENABLE_reg:D
  Delay (ns):                  1.904
  Slack (ns):                  0.475
  Arrival (ns):                4.853
  Required (ns):               4.378
  Hold (ns):                   0.000

Path 2
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fftTop_inst/inBuf_0/piBuf/memQ/wrapRam_0/actram_R0C0:WD7
  Delay (ns):                  2.810
  Slack (ns):                  1.221
  Arrival (ns):                5.759
  Required (ns):               4.538
  Hold (ns):                   0.000

Path 3
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fftTop_inst/inBuf_0/piBuf/memP/wrapRam_0/actram_R0C0:WD14
  Delay (ns):                  2.839
  Slack (ns):                  1.250
  Arrival (ns):                5.788
  Required (ns):               4.538
  Hold (ns):                   0.000

Path 4
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fftTop_inst/inBuf_0/piBuf/memQ/wrapRam_0/actram_R0C0:WD13
  Delay (ns):                  2.848
  Slack (ns):                  1.259
  Arrival (ns):                5.797
  Required (ns):               4.538
  Hold (ns):                   0.000

Path 5
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fftTop_inst/inBuf_0/piBuf/memQ/wrapRam_0/actram_R0C0:WD1
  Delay (ns):                  2.941
  Slack (ns):                  1.352
  Arrival (ns):                5.890
  Required (ns):               4.538
  Hold (ns):                   0.000


Expanded Path 1
  From: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To: Aapb_int_fft_0/PENABLE_reg:D
  data arrival time                              4.853
  data required time                         -   4.378
  slack                                          0.475
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.949          Clock generation
  2.949
               +     1.283          cell: ADLIB:MSS_APB_IP
  4.232                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPENABLE (r)
               +     0.058          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPENABLEINT_NET
  4.290                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_42:PIN2INT (r)
               +     0.044          cell: ADLIB:MSS_IF
  4.334                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_42:PIN2 (r)
               +     0.519          net: CoreAPB3_0_APBmslave0_PENABLE
  4.853                        Aapb_int_fft_0/PENABLE_reg:D (r)
                                    
  4.853                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.343          net: FAB_CLK
  4.378                        Aapb_int_fft_0/PENABLE_reg:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  4.378                        Aapb_int_fft_0/PENABLE_reg:D
                                    
  4.378                        data required time


END SET mss_fabric_interface_clock to mss_ccc_gla1

----------------------------------------------------

SET mss_ccc_gla0 to mss_ccc_gla1

Path 1
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_5_inst/U1:CLR
  Delay (ns):                  2.219
  Slack (ns):                  0.773
  Arrival (ns):                5.168
  Required (ns):               4.395
  Hold (ns):

Path 2
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/data_out_reg[1]:CLR
  Delay (ns):                  2.253
  Slack (ns):                  0.796
  Arrival (ns):                5.202
  Required (ns):               4.406
  Hold (ns):

Path 3
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/PSEL_reg:CLR
  Delay (ns):                  2.258
  Slack (ns):                  0.801
  Arrival (ns):                5.207
  Required (ns):               4.406
  Hold (ns):

Path 4
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_8_inst/U1:CLR
  Delay (ns):                  2.262
  Slack (ns):                  0.809
  Arrival (ns):                5.211
  Required (ns):               4.402
  Hold (ns):

Path 5
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/data_out_reg[5]:CLR
  Delay (ns):                  2.288
  Slack (ns):                  0.831
  Arrival (ns):                5.237
  Required (ns):               4.406
  Hold (ns):


Expanded Path 1
  From: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To: Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_5_inst/U1:CLR
  data arrival time                              5.168
  data required time                         -   4.395
  slack                                          0.773
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  2.724
               +     0.225          net: DSP_Coprocessor_MSS_0/GLA0
  2.949                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.564          cell: ADLIB:MSS_APB_IP
  4.513                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:M2FRESETn (r)
               +     0.059          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/M2FRESETnINT_NET
  4.572                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_46:PIN2INT (r)
               +     0.044          cell: ADLIB:MSS_IF
  4.616                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_46:PIN2 (r)
               +     0.552          net: DSP_Coprocessor_MSS_0_M2F_RESET_N
  5.168                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_5_inst/U1:CLR (r)
                                    
  5.168                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.360          net: FAB_CLK
  4.395                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_5_inst/U1:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1C0
  4.395                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_5_inst/U1:CLR
                                    
  4.395                        data required time


END SET mss_ccc_gla0 to mss_ccc_gla1

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.276
  Slack (ns):
  Arrival (ns):                0.276
  Required (ns):
  Hold (ns):                   1.289
  External Hold (ns):          4.007


Expanded Path 1
  From: MSS_RESET_N
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.276
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        DSP_Coprocessor_MSS_0/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.276          cell: ADLIB:IOPAD_IN
  0.276                        DSP_Coprocessor_MSS_0/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_RESET_0_MSS_RESET_N_Y
  0.276                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.276                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  N/C
               +     0.270          net: DSP_Coprocessor_MSS_0/GLA0
  N/C                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.289          Library hold time: ADLIB:MSS_APB_IP
  N/C                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain DSP_Coprocessor_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

