Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Thu Dec 08 10:34:56 2011


Design: DSP_Coprocessor
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                7.315
Frequency (MHz):            136.705
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                14.506
Frequency (MHz):            68.937
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        -4.928
External Hold (ns):         4.007
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               DSP_Coprocessor_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[2]
  Delay (ns):                  9.131
  Slack (ns):                  17.685
  Arrival (ns):                13.058
  Required (ns):               30.743
  Setup (ns):                  -1.816
  Minimum Period (ns):         7.315

Path 2
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[1]
  Delay (ns):                  8.779
  Slack (ns):                  18.035
  Arrival (ns):                12.706
  Required (ns):               30.741
  Setup (ns):                  -1.814
  Minimum Period (ns):         6.965

Path 3
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  7.939
  Slack (ns):                  18.131
  Arrival (ns):                11.866
  Required (ns):               29.997
  Setup (ns):                  -1.070
  Minimum Period (ns):         6.869

Path 4
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[8]
  Delay (ns):                  8.673
  Slack (ns):                  18.156
  Arrival (ns):                12.600
  Required (ns):               30.756
  Setup (ns):                  -1.829
  Minimum Period (ns):         6.844

Path 5
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[10]
  Delay (ns):                  8.621
  Slack (ns):                  18.207
  Arrival (ns):                12.548
  Required (ns):               30.755
  Setup (ns):                  -1.828
  Minimum Period (ns):         6.793


Expanded Path 1
  From: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[2]
  data required time                             30.743
  data arrival time                          -   13.058
  slack                                          17.685
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.927          Clock generation
  3.927
               +     2.352          cell: ADLIB:MSS_APB_IP
  6.279                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPADDR[9] (f)
               +     0.130          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPADDR[9]INT_NET
  6.409                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_33:PIN1INT (f)
               +     0.073          cell: ADLIB:MSS_IF
  6.482                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_33:PIN1 (f)
               +     1.021          net: _CoreAPB3_0_APBmslave0_PADDR_[9]_
  7.503                        CoreAPB3_0/CAPB3iool_1_0[0]:B (f)
               +     0.542          cell: ADLIB:OR3A
  8.045                        CoreAPB3_0/CAPB3iool_1_0[0]:Y (f)
               +     0.245          net: CoreAPB3_0/CAPB3iool_1_0[0]
  8.290                        CoreAPB3_0/CAPB3iool[0]:A (f)
               +     0.407          cell: ADLIB:NOR2
  8.697                        CoreAPB3_0/CAPB3iool[0]:Y (r)
               +     2.248          net: CoreAPB3_0_APBmslave0_PSELx
  10.945                       CoreAPB3_0/CAPB3O1II/PRDATA_2:A (r)
               +     0.370          cell: ADLIB:NOR2B
  11.315                       CoreAPB3_0/CAPB3O1II/PRDATA_2:Y (r)
               +     1.209          net: _DSP_Coprocessor_MSS_0_MSS_MASTER_APB_PRDATA_[2]_
  12.524                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_37:PIN4 (r)
               +     0.180          cell: ADLIB:MSS_IF
  12.704                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_37:PIN4INT (r)
               +     0.354          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPRDATA[2]INT_NET
  13.058                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[2] (r)
                                    
  13.058                       data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_fabric_interface_clock
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.927          Clock generation
  28.927
               -    -1.816          Library setup time: ADLIB:MSS_APB_IP
  30.743                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[2]
                                    
  30.743                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_fabric_interface_clock

Path 1
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  4.663
  Slack (ns):                  19.407
  Arrival (ns):                10.500
  Required (ns):               29.907
  Setup (ns):                  -0.980

Path 2
  From:                        Aapb_int_fft_0/PREADY0:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  4.270
  Slack (ns):                  19.795
  Arrival (ns):                10.112
  Required (ns):               29.907
  Setup (ns):                  -0.980

Path 3
  From:                        Aapb_int_fft_0/PREADY1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  4.252
  Slack (ns):                  19.813
  Arrival (ns):                10.094
  Required (ns):               29.907
  Setup (ns):                  -0.980

Path 4
  From:                        Aapb_int_fft_0/EMPTY_OUT_REG/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  4.215
  Slack (ns):                  19.874
  Arrival (ns):                10.033
  Required (ns):               29.907
  Setup (ns):                  -0.980

Path 5
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_8_inst/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[8]
  Delay (ns):                  3.979
  Slack (ns):                  20.935
  Arrival (ns):                9.821
  Required (ns):               30.756
  Setup (ns):                  -1.829


Expanded Path 1
  From: Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int:CLK
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  data required time                             29.907
  data arrival time                          -   10.500
  slack                                          19.407
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.588          net: FAB_CLK
  5.837                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int:CLK (r)
               +     0.440          cell: ADLIB:DFN1C0
  6.277                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int:Q (r)
               +     1.482          net: Aapb_int_fft_0_FFT_IP_RDY
  7.759                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int_RNIN76C:B (r)
               +     0.444          cell: ADLIB:MX2C
  8.203                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int_RNIN76C:Y (f)
               +     0.267          net: CoreAPB3_0_APBmslave0_PREADY
  8.470                        CoreAPB3_0/CAPB3O1II/PREADY:B (f)
               +     0.479          cell: ADLIB:OR2B
  8.949                        CoreAPB3_0/CAPB3O1II/PREADY:Y (r)
               +     1.141          net: DSP_Coprocessor_MSS_0_MSS_MASTER_APB_PREADY
  10.090                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_36:PIN5 (r)
               +     0.066          cell: ADLIB:MSS_IF
  10.156                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_36:PIN5INT (r)
               +     0.344          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPREADYINT_NET
  10.500                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY (r)
                                    
  10.500                       data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_fabric_interface_clock
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.927          Clock generation
  28.927
               -    -0.980          Library setup time: ADLIB:MSS_APB_IP
  29.907                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
                                    
  29.907                       data required time


END SET mss_ccc_gla1 to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_pclk1

Path 1
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[2]
  Delay (ns):                  2.566
  Slack (ns):                  21.606
  Arrival (ns):                8.393
  Required (ns):               29.999
  Setup (ns):                  -1.072

Path 2
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1P0_EMPTY:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[3]
  Delay (ns):                  2.164
  Slack (ns):                  22.056
  Arrival (ns):                7.991
  Required (ns):               30.047
  Setup (ns):                  -1.120

Path 3
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn_int:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[1]
  Delay (ns):                  1.979
  Slack (ns):                  22.085
  Arrival (ns):                7.894
  Required (ns):               29.979
  Setup (ns):                  -1.052

Path 4
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[0]
  Delay (ns):                  1.843
  Slack (ns):                  22.305
  Arrival (ns):                7.680
  Required (ns):               29.985
  Setup (ns):                  -1.058


Expanded Path 1
  From: Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:CLK
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[2]
  data required time                             29.999
  data arrival time                          -   8.393
  slack                                          21.606
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.578          net: FAB_CLK
  5.827                        Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:CLK (r)
               +     0.559          cell: ADLIB:DFN1P0
  6.386                        Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:Q (f)
               +     1.849          net: Aapb_int_fft_0_AEMPTY_OUT
  8.235                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_22:PIN5 (f)
               +     0.158          cell: ADLIB:MSS_IF
  8.393                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_22:PIN5INT (f)
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/GPI[2]INT_NET
  8.393                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[2] (f)
                                    
  8.393                        data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_pclk1
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     3.927          Clock generation
  28.927
               -    -1.072          Library setup time: ADLIB:MSS_APB_IP
  29.999                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[2]
                                    
  29.999                       data required time


END SET mss_ccc_gla1 to mss_pclk1

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        Aapb_int_fft_0/PENABLE_reg:CLK
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D
  Delay (ns):                  14.090
  Slack (ns):                  10.494
  Arrival (ns):                19.898
  Required (ns):               30.392
  Setup (ns):                  0.435
  Minimum Period (ns):         14.506

Path 2
  From:                        Aapb_int_fft_0/ifoY_valid:CLK
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1C0_AFULL:D
  Delay (ns):                  13.057
  Slack (ns):                  11.559
  Arrival (ns):                18.880
  Required (ns):               30.439
  Setup (ns):                  0.409
  Minimum Period (ns):         13.441

Path 3
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1P0_EMPTY:CLK
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D
  Delay (ns):                  12.759
  Slack (ns):                  11.806
  Arrival (ns):                18.586
  Required (ns):               30.392
  Setup (ns):                  0.435
  Minimum Period (ns):         13.194

Path 4
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1C0_FULL:CLK
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1C0_AFULL:D
  Delay (ns):                  12.803
  Slack (ns):                  11.813
  Arrival (ns):                18.626
  Required (ns):               30.439
  Setup (ns):                  0.409
  Minimum Period (ns):         13.187

Path 5
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1C0_MEM_WADDR_0_inst:CLK
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1C0_AFULL:D
  Delay (ns):                  12.169
  Slack (ns):                  12.450
  Arrival (ns):                17.989
  Required (ns):               30.439
  Setup (ns):                  0.409
  Minimum Period (ns):         12.550


Expanded Path 1
  From: Aapb_int_fft_0/PENABLE_reg:CLK
  To: Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D
  data required time                             30.392
  data arrival time                          -   19.898
  slack                                          10.494
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.559          net: FAB_CLK
  5.808                        Aapb_int_fft_0/PENABLE_reg:CLK (r)
               +     0.440          cell: ADLIB:DFN1C0
  6.248                        Aapb_int_fft_0/PENABLE_reg:Q (r)
               +     0.255          net: Aapb_int_fft_0/PENABLE_reg
  6.503                        Aapb_int_fft_0/PENABLE_reg_RNICCCC:C (r)
               +     0.273          cell: ADLIB:NOR3B
  6.776                        Aapb_int_fft_0/PENABLE_reg_RNICCCC:Y (f)
               +     0.247          net: Aapb_int_fft_0/un3_fifo_rd_en_m2_e_3
  7.023                        Aapb_int_fft_0/PENABLE_reg_RNI4HTI:B (f)
               +     0.460          cell: ADLIB:NOR3B
  7.483                        Aapb_int_fft_0/PENABLE_reg_RNI4HTI:Y (f)
               +     0.898          net: Aapb_int_fft_0/REP
  8.381                        Aapb_int_fft_0/fifo64X16_inst/AND2_MEMORYRE:B (f)
               +     0.476          cell: ADLIB:AND2A
  8.857                        Aapb_int_fft_0/fifo64X16_inst/AND2_MEMORYRE:Y (f)
               +     0.360          net: Aapb_int_fft_0/fifo64X16_inst/MEMORYRE
  9.217                        Aapb_int_fft_0/fifo64X16_inst/AND2_55:B (f)
               +     0.479          cell: ADLIB:AND2
  9.696                        Aapb_int_fft_0/fifo64X16_inst/AND2_55:Y (f)
               +     0.793          net: Aapb_int_fft_0/fifo64X16_inst/AND2_55_Y
  10.489                       Aapb_int_fft_0/fifo64X16_inst/AO1_15:B (f)
               +     0.479          cell: ADLIB:NOR2B
  10.968                       Aapb_int_fft_0/fifo64X16_inst/AO1_15:Y (f)
               +     0.364          net: Aapb_int_fft_0/fifo64X16_inst/AO1_15_Y
  11.332                       Aapb_int_fft_0/fifo64X16_inst/AO1_29:C (f)
               +     0.517          cell: ADLIB:NOR3C
  11.849                       Aapb_int_fft_0/fifo64X16_inst/AO1_29:Y (f)
               +     0.756          net: Aapb_int_fft_0/fifo64X16_inst/AO1_29_Y
  12.605                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RBINNXTSHIFT_4_inst:B (f)
               +     0.711          cell: ADLIB:XOR2
  13.316                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RBINNXTSHIFT_4_inst:Y (r)
               +     0.351          net: Aapb_int_fft_0/fifo64X16_inst/RBINNXTSHIFT_4_net
  13.667                       Aapb_int_fft_0/fifo64X16_inst/INV_13:A (r)
               +     0.276          cell: ADLIB:INV
  13.943                       Aapb_int_fft_0/fifo64X16_inst/INV_13:Y (f)
               +     0.292          net: Aapb_int_fft_0/fifo64X16_inst/INV_13_Y
  14.235                       Aapb_int_fft_0/fifo64X16_inst/XOR2_38:B (f)
               +     0.711          cell: ADLIB:XOR2
  14.946                       Aapb_int_fft_0/fifo64X16_inst/XOR2_38:Y (r)
               +     0.306          net: Aapb_int_fft_0/fifo64X16_inst/XOR2_38_Y
  15.252                       Aapb_int_fft_0/fifo64X16_inst/AND2_32:B (r)
               +     0.392          cell: ADLIB:AND2
  15.644                       Aapb_int_fft_0/fifo64X16_inst/AND2_32:Y (r)
               +     0.496          net: Aapb_int_fft_0/fifo64X16_inst/AND2_32_Y
  16.140                       Aapb_int_fft_0/fifo64X16_inst/AO1_10:A (r)
               +     0.364          cell: ADLIB:AO1
  16.504                       Aapb_int_fft_0/fifo64X16_inst/AO1_10:Y (r)
               +     0.308          net: Aapb_int_fft_0/fifo64X16_inst/AO1_10_Y
  16.812                       Aapb_int_fft_0/fifo64X16_inst/AO1_1:B (r)
               +     0.430          cell: ADLIB:AO1
  17.242                       Aapb_int_fft_0/fifo64X16_inst/AO1_1:Y (r)
               +     0.255          net: Aapb_int_fft_0/fifo64X16_inst/AO1_1_Y
  17.497                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RDIFF_6_inst:C (r)
               +     0.747          cell: ADLIB:XNOR3
  18.244                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RDIFF_6_inst:Y (f)
               +     0.294          net: Aapb_int_fft_0/fifo64X16_inst/RDIFF_6_net
  18.538                       Aapb_int_fft_0/fifo64X16_inst/AND3_0:A (f)
               +     0.398          cell: ADLIB:AND3C
  18.936                       Aapb_int_fft_0/fifo64X16_inst/AND3_0:Y (r)
               +     0.255          net: Aapb_int_fft_0/fifo64X16_inst/AND3_0_Y
  19.191                       Aapb_int_fft_0/fifo64X16_inst/AOI1_0:A (r)
               +     0.460          cell: ADLIB:AOI1
  19.651                       Aapb_int_fft_0/fifo64X16_inst/AOI1_0:Y (f)
               +     0.247          net: Aapb_int_fft_0/fifo64X16_inst/AOI1_0_Y
  19.898                       Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D (f)
                                    
  19.898                       data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_ccc_gla1
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  30.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.578          net: FAB_CLK
  30.827                       Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:CLK (r)
               -     0.435          Library setup time: ADLIB:DFN1P0
  30.392                       Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D
                                    
  30.392                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/tc_out:CLR
  Delay (ns):                  5.331
  Slack (ns):                  19.460
  Arrival (ns):                11.132
  Required (ns):               30.592
  Recovery (ns):               0.225
  Minimum Period (ns):         5.540
  Skew (ns):                   -0.016

Path 2
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/Q_out[4]:CLR
  Delay (ns):                  5.326
  Slack (ns):                  19.485
  Arrival (ns):                11.127
  Required (ns):               30.612
  Recovery (ns):               0.225
  Minimum Period (ns):         5.515
  Skew (ns):                   -0.036

Path 3
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int:CLR
  Delay (ns):                  5.326
  Slack (ns):                  19.485
  Arrival (ns):                11.127
  Required (ns):               30.612
  Recovery (ns):               0.225
  Minimum Period (ns):         5.515
  Skew (ns):                   -0.036

Path 4
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/Q_out[3]:CLR
  Delay (ns):                  5.326
  Slack (ns):                  19.485
  Arrival (ns):                11.127
  Required (ns):               30.612
  Recovery (ns):               0.225
  Minimum Period (ns):         5.515
  Skew (ns):                   -0.036

Path 5
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/Q_out[0]:CLR
  Delay (ns):                  5.326
  Slack (ns):                  19.485
  Arrival (ns):                11.127
  Required (ns):               30.612
  Recovery (ns):               0.225
  Minimum Period (ns):         5.515
  Skew (ns):                   -0.036


Expanded Path 1
  From: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To: Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/tc_out:CLR
  data required time                             30.592
  data arrival time                          -   11.132
  slack                                          19.460
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.552          net: FAB_CLK
  5.801                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK (r)
               +     0.559          cell: ADLIB:DFN1P0
  6.360                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:Q (f)
               +     0.952          net: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/initRst
  7.312                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8:B (f)
               +     0.370          cell: ADLIB:NOR2A
  7.682                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8:Y (r)
               +     2.200          net: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8
  9.882                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8_0/U_CLKSRC:A (r)
               +     0.691          cell: ADLIB:CLKSRC
  10.573                       Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8_0/U_CLKSRC:Y (r)
               +     0.559          net: Aapb_int_fft_0/fftTop_inst/smTop_0/nGrst
  11.132                       Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/tc_out:CLR (r)
                                    
  11.132                       data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_ccc_gla1
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  30.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.568          net: FAB_CLK
  30.817                       Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/tc_out:CLK (r)
               -     0.225          Library recovery time: ADLIB:DFN1C0
  30.592                       Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/tc_out:CLR
                                    
  30.592                       data required time


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_gla1

Path 1
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D
  Delay (ns):                  18.183
  Slack (ns):                  8.282
  Arrival (ns):                22.110
  Required (ns):               30.392
  Setup (ns):                  0.435

Path 2
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1P0_EMPTY:D
  Delay (ns):                  14.388
  Slack (ns):                  12.103
  Arrival (ns):                18.315
  Required (ns):               30.418
  Setup (ns):                  0.409

Path 3
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1C0_MEM_RADDR_6_inst:D
  Delay (ns):                  12.899
  Slack (ns):                  13.585
  Arrival (ns):                16.826
  Required (ns):               30.411
  Setup (ns):                  0.409

Path 4
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1C0_MEM_RADDR_4_inst:D
  Delay (ns):                  11.957
  Slack (ns):                  14.534
  Arrival (ns):                15.884
  Required (ns):               30.418
  Setup (ns):                  0.409

Path 5
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1C0_MEM_RADDR_5_inst:D
  Delay (ns):                  11.473
  Slack (ns):                  15.027
  Arrival (ns):                15.400
  Required (ns):               30.427
  Setup (ns):                  0.409


Expanded Path 1
  From: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To: Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D
  data required time                             30.392
  data arrival time                          -   22.110
  slack                                          8.282
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.927          Clock generation
  3.927
               +     2.367          cell: ADLIB:MSS_APB_IP
  6.294                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPADDR[10] (r)
               +     0.101          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPADDR[10]INT_NET
  6.395                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_33:PIN2INT (r)
               +     0.079          cell: ADLIB:MSS_IF
  6.474                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_33:PIN2 (r)
               +     0.821          net: _CoreAPB3_0_APBmslave0_PADDR_[10]_
  7.295                        Aapb_int_fft_0/un3_fifo_rd_en_m2_e_1:B (r)
               +     0.390          cell: ADLIB:NOR2
  7.685                        Aapb_int_fft_0/un3_fifo_rd_en_m2_e_1:Y (f)
               +     0.843          net: Aapb_int_fft_0/un3_fifo_rd_en_m2_e_1
  8.528                        Aapb_int_fft_0/PENABLE_reg_RNICCCC:B (f)
               +     0.460          cell: ADLIB:NOR3B
  8.988                        Aapb_int_fft_0/PENABLE_reg_RNICCCC:Y (f)
               +     0.247          net: Aapb_int_fft_0/un3_fifo_rd_en_m2_e_3
  9.235                        Aapb_int_fft_0/PENABLE_reg_RNI4HTI:B (f)
               +     0.460          cell: ADLIB:NOR3B
  9.695                        Aapb_int_fft_0/PENABLE_reg_RNI4HTI:Y (f)
               +     0.898          net: Aapb_int_fft_0/REP
  10.593                       Aapb_int_fft_0/fifo64X16_inst/AND2_MEMORYRE:B (f)
               +     0.476          cell: ADLIB:AND2A
  11.069                       Aapb_int_fft_0/fifo64X16_inst/AND2_MEMORYRE:Y (f)
               +     0.360          net: Aapb_int_fft_0/fifo64X16_inst/MEMORYRE
  11.429                       Aapb_int_fft_0/fifo64X16_inst/AND2_55:B (f)
               +     0.479          cell: ADLIB:AND2
  11.908                       Aapb_int_fft_0/fifo64X16_inst/AND2_55:Y (f)
               +     0.793          net: Aapb_int_fft_0/fifo64X16_inst/AND2_55_Y
  12.701                       Aapb_int_fft_0/fifo64X16_inst/AO1_15:B (f)
               +     0.479          cell: ADLIB:NOR2B
  13.180                       Aapb_int_fft_0/fifo64X16_inst/AO1_15:Y (f)
               +     0.364          net: Aapb_int_fft_0/fifo64X16_inst/AO1_15_Y
  13.544                       Aapb_int_fft_0/fifo64X16_inst/AO1_29:C (f)
               +     0.517          cell: ADLIB:NOR3C
  14.061                       Aapb_int_fft_0/fifo64X16_inst/AO1_29:Y (f)
               +     0.756          net: Aapb_int_fft_0/fifo64X16_inst/AO1_29_Y
  14.817                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RBINNXTSHIFT_4_inst:B (f)
               +     0.711          cell: ADLIB:XOR2
  15.528                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RBINNXTSHIFT_4_inst:Y (r)
               +     0.351          net: Aapb_int_fft_0/fifo64X16_inst/RBINNXTSHIFT_4_net
  15.879                       Aapb_int_fft_0/fifo64X16_inst/INV_13:A (r)
               +     0.276          cell: ADLIB:INV
  16.155                       Aapb_int_fft_0/fifo64X16_inst/INV_13:Y (f)
               +     0.292          net: Aapb_int_fft_0/fifo64X16_inst/INV_13_Y
  16.447                       Aapb_int_fft_0/fifo64X16_inst/XOR2_38:B (f)
               +     0.711          cell: ADLIB:XOR2
  17.158                       Aapb_int_fft_0/fifo64X16_inst/XOR2_38:Y (r)
               +     0.306          net: Aapb_int_fft_0/fifo64X16_inst/XOR2_38_Y
  17.464                       Aapb_int_fft_0/fifo64X16_inst/AND2_32:B (r)
               +     0.392          cell: ADLIB:AND2
  17.856                       Aapb_int_fft_0/fifo64X16_inst/AND2_32:Y (r)
               +     0.496          net: Aapb_int_fft_0/fifo64X16_inst/AND2_32_Y
  18.352                       Aapb_int_fft_0/fifo64X16_inst/AO1_10:A (r)
               +     0.364          cell: ADLIB:AO1
  18.716                       Aapb_int_fft_0/fifo64X16_inst/AO1_10:Y (r)
               +     0.308          net: Aapb_int_fft_0/fifo64X16_inst/AO1_10_Y
  19.024                       Aapb_int_fft_0/fifo64X16_inst/AO1_1:B (r)
               +     0.430          cell: ADLIB:AO1
  19.454                       Aapb_int_fft_0/fifo64X16_inst/AO1_1:Y (r)
               +     0.255          net: Aapb_int_fft_0/fifo64X16_inst/AO1_1_Y
  19.709                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RDIFF_6_inst:C (r)
               +     0.747          cell: ADLIB:XNOR3
  20.456                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RDIFF_6_inst:Y (f)
               +     0.294          net: Aapb_int_fft_0/fifo64X16_inst/RDIFF_6_net
  20.750                       Aapb_int_fft_0/fifo64X16_inst/AND3_0:A (f)
               +     0.398          cell: ADLIB:AND3C
  21.148                       Aapb_int_fft_0/fifo64X16_inst/AND3_0:Y (r)
               +     0.255          net: Aapb_int_fft_0/fifo64X16_inst/AND3_0_Y
  21.403                       Aapb_int_fft_0/fifo64X16_inst/AOI1_0:A (r)
               +     0.460          cell: ADLIB:AOI1
  21.863                       Aapb_int_fft_0/fifo64X16_inst/AOI1_0:Y (f)
               +     0.247          net: Aapb_int_fft_0/fifo64X16_inst/AOI1_0_Y
  22.110                       Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D (f)
                                    
  22.110                       data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_ccc_gla1
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  30.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.578          net: FAB_CLK
  30.827                       Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:CLK (r)
               -     0.435          Library setup time: ADLIB:DFN1P0
  30.392                       Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D
                                    
  30.392                       data required time


END SET mss_fabric_interface_clock to mss_ccc_gla1

----------------------------------------------------

SET mss_ccc_gla0 to mss_ccc_gla1

Path 1
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/tc_out:CLR
  Delay (ns):                  9.225
  Slack (ns):                  17.440
  Arrival (ns):                13.152
  Required (ns):               30.592
  Setup (ns):

Path 2
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/Q_out[4]:CLR
  Delay (ns):                  9.220
  Slack (ns):                  17.465
  Arrival (ns):                13.147
  Required (ns):               30.612
  Setup (ns):

Path 3
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int:CLR
  Delay (ns):                  9.220
  Slack (ns):                  17.465
  Arrival (ns):                13.147
  Required (ns):               30.612
  Setup (ns):

Path 4
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/Q_out[3]:CLR
  Delay (ns):                  9.220
  Slack (ns):                  17.465
  Arrival (ns):                13.147
  Required (ns):               30.612
  Setup (ns):

Path 5
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/Q_out[0]:CLR
  Delay (ns):                  9.220
  Slack (ns):                  17.465
  Arrival (ns):                13.147
  Required (ns):               30.612
  Setup (ns):


Expanded Path 1
  From: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To: Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/tc_out:CLR
  data required time                             30.592
  data arrival time                          -   13.152
  slack                                          17.440
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  3.545
               +     0.382          net: DSP_Coprocessor_MSS_0/GLA0
  3.927                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     2.776          cell: ADLIB:MSS_APB_IP
  6.703                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:M2FRESETn (r)
               +     0.101          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/M2FRESETnINT_NET
  6.804                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_46:PIN2INT (r)
               +     0.079          cell: ADLIB:MSS_IF
  6.883                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_46:PIN2 (r)
               +     2.427          net: DSP_Coprocessor_MSS_0_M2F_RESET_N
  9.310                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8:A (r)
               +     0.392          cell: ADLIB:NOR2A
  9.702                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8:Y (r)
               +     2.200          net: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8
  11.902                       Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8_0/U_CLKSRC:A (r)
               +     0.691          cell: ADLIB:CLKSRC
  12.593                       Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8_0/U_CLKSRC:Y (r)
               +     0.559          net: Aapb_int_fft_0/fftTop_inst/smTop_0/nGrst
  13.152                       Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/tc_out:CLR (r)
                                    
  13.152                       data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_ccc_gla1
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  30.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.568          net: FAB_CLK
  30.817                       Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/tc_out:CLK (r)
               -     0.225          Library recovery time: ADLIB:DFN1C0
  30.592                       Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/tc_out:CLR
                                    
  30.592                       data required time


END SET mss_ccc_gla0 to mss_ccc_gla1

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.781
  Slack (ns):
  Arrival (ns):                0.781
  Required (ns):
  Setup (ns):                  -1.782
  External Setup (ns):         -4.928


Expanded Path 1
  From: MSS_RESET_N
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.781
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        DSP_Coprocessor_MSS_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.781          cell: ADLIB:IOPAD_IN
  0.781                        DSP_Coprocessor_MSS_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_RESET_0_MSS_RESET_N_Y
  0.781                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.781                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  N/C
               +     0.382          net: DSP_Coprocessor_MSS_0/GLA0
  N/C                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -1.782          Library setup time: ADLIB:MSS_APB_IP
  N/C                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain DSP_Coprocessor_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

