Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Thu Dec 08 10:31:19 2011


Design: DSP_Coprocessor
Family: SmartFusion
Die: A2F200M3F
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                8.122
Frequency (MHz):            123.122
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                18.189
Frequency (MHz):            54.978
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        -5.434
External Hold (ns):         4.176
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               DSP_Coprocessor_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[15]
  Delay (ns):                  10.355
  Slack (ns):                  16.878
  Arrival (ns):                14.530
  Required (ns):               31.408
  Setup (ns):                  -2.233
  Minimum Period (ns):         8.122

Path 2
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  8.706
  Slack (ns):                  16.942
  Arrival (ns):                12.881
  Required (ns):               29.823
  Setup (ns):                  -0.648
  Minimum Period (ns):         8.058

Path 3
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[14]
  Delay (ns):                  10.008
  Slack (ns):                  17.219
  Arrival (ns):                14.183
  Required (ns):               31.402
  Setup (ns):                  -2.227
  Minimum Period (ns):         7.781

Path 4
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[7]
  Delay (ns):                  9.805
  Slack (ns):                  17.422
  Arrival (ns):                13.980
  Required (ns):               31.402
  Setup (ns):                  -2.227
  Minimum Period (ns):         7.578

Path 5
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[8]
  Delay (ns):                  9.695
  Slack (ns):                  17.535
  Arrival (ns):                13.870
  Required (ns):               31.405
  Setup (ns):                  -2.230
  Minimum Period (ns):         7.465


Expanded Path 1
  From: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[15]
  data required time                             31.408
  data arrival time                          -   14.530
  slack                                          16.878
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.175          Clock generation
  4.175
               +     3.667          cell: ADLIB:MSS_APB_IP
  7.842                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPADDR[8] (f)
               +     0.158          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPADDR[8]INT_NET
  8.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_32:PIN3INT (f)
               +     0.086          cell: ADLIB:MSS_IF
  8.086                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_32:PIN3 (f)
               +     0.324          net: CoreAPB3_0_APBmslave0_PADDR_[8]
  8.410                        CoreAPB3_0/CAPB3O11_1[0]:B (f)
               +     0.588          cell: ADLIB:OR2
  8.998                        CoreAPB3_0/CAPB3O11_1[0]:Y (f)
               +     0.891          net: CoreAPB3_0_CAPB3O11_1[0]
  9.889                        CoreAPB3_0/CAPB3O11[0]:B (f)
               +     0.592          cell: ADLIB:NOR2
  10.481                       CoreAPB3_0/CAPB3O11[0]:Y (r)
               +     2.100          net: CoreAPB3_0_APBmslave0_PSELx
  12.581                       CoreAPB3_0/CAPB3llOI/PRDATA_15:B (r)
               +     0.470          cell: ADLIB:NOR2B
  13.051                       CoreAPB3_0/CAPB3llOI/PRDATA_15:Y (r)
               +     0.848          net: PRDATA_15
  13.899                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_41:PIN6 (r)
               +     0.190          cell: ADLIB:MSS_IF
  14.089                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_41:PIN6INT (r)
               +     0.441          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPRDATA[15]INT_NET
  14.530                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[15] (r)
                                    
  14.530                       data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_fabric_interface_clock
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.175          Clock generation
  29.175
               -    -2.233          Library setup time: ADLIB:MSS_APB_IP
  31.408                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[15]
                                    
  31.408                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_fabric_interface_clock

Path 1
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  5.152
  Slack (ns):                  18.750
  Arrival (ns):                11.073
  Required (ns):               29.823
  Setup (ns):                  -0.648

Path 2
  From:                        Aapb_int_fft_0/PREADY0:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  4.641
  Slack (ns):                  19.308
  Arrival (ns):                10.515
  Required (ns):               29.823
  Setup (ns):                  -0.648

Path 3
  From:                        Aapb_int_fft_0/PREADY1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  4.614
  Slack (ns):                  19.335
  Arrival (ns):                10.488
  Required (ns):               29.823
  Setup (ns):                  -0.648

Path 4
  From:                        Aapb_int_fft_0/EMPTY_OUT_REG/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  4.582
  Slack (ns):                  19.430
  Arrival (ns):                10.456
  Required (ns):               29.886
  Setup (ns):                  -0.711

Path 5
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_8_inst/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[8]
  Delay (ns):                  5.065
  Slack (ns):                  20.415
  Arrival (ns):                10.990
  Required (ns):               31.405
  Setup (ns):                  -2.230


Expanded Path 1
  From: Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn:CLK
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  data required time                             29.823
  data arrival time                          -   11.073
  slack                                          18.750
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.672          net: FAB_CLK
  5.921                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn:CLK (r)
               +     0.671          cell: ADLIB:DFN1C0
  6.592                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn:Q (f)
               +     1.767          net: Aapb_int_fft_0_FFT_IP_RDY
  8.359                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_RNIBGQ7:B (f)
               +     0.520          cell: ADLIB:MX2C
  8.879                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_RNIBGQ7:Y (r)
               +     0.296          net: CoreAPB3_0_APBmslave0_PREADY
  9.175                        CoreAPB3_0/CAPB3llOI/PREADY:B (r)
               +     0.538          cell: ADLIB:OR2B
  9.713                        CoreAPB3_0/CAPB3llOI/PREADY:Y (f)
               +     0.843          net: DSP_Coprocessor_MSS_0_MSS_MASTER_APB_PREADY
  10.556                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_36:PIN5 (f)
               +     0.095          cell: ADLIB:MSS_IF
  10.651                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_36:PIN5INT (f)
               +     0.422          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPREADYINT_NET
  11.073                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY (f)
                                    
  11.073                       data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_fabric_interface_clock
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.175          Clock generation
  29.175
               -    -0.648          Library setup time: ADLIB:MSS_APB_IP
  29.823                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
                                    
  29.823                       data required time


END SET mss_ccc_gla1 to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_pclk1

Path 1
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[2]
  Delay (ns):                  4.017
  Slack (ns):                  19.471
  Arrival (ns):                9.892
  Required (ns):               29.363
  Setup (ns):                  -0.188

Path 2
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1P0_EMPTY:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[3]
  Delay (ns):                  3.477
  Slack (ns):                  20.078
  Arrival (ns):                9.380
  Required (ns):               29.458
  Setup (ns):                  -0.283

Path 3
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[0]
  Delay (ns):                  2.268
  Slack (ns):                  21.047
  Arrival (ns):                8.189
  Required (ns):               29.236
  Setup (ns):                  -0.061

Path 4
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[1]
  Delay (ns):                  0.883
  Slack (ns):                  22.493
  Arrival (ns):                6.750
  Required (ns):               29.243
  Setup (ns):                  -0.068


Expanded Path 1
  From: Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:CLK
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[2]
  data required time                             29.363
  data arrival time                          -   9.892
  slack                                          19.471
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.626          net: FAB_CLK
  5.875                        Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:CLK (r)
               +     0.528          cell: ADLIB:DFN1P0
  6.403                        Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:Q (r)
               +     3.273          net: Aapb_int_fft_0_AEMPTY_OUT
  9.676                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_22:PIN5 (r)
               +     0.216          cell: ADLIB:MSS_IF
  9.892                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_22:PIN5INT (r)
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/GPI[2]INT_NET
  9.892                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[2] (r)
                                    
  9.892                        data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_pclk1
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     4.175          Clock generation
  29.175
               -    -0.188          Library setup time: ADLIB:MSS_APB_IP
  29.363                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[2]
                                    
  29.363                       data required time


END SET mss_ccc_gla1 to mss_pclk1

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        Aapb_int_fft_0/PENABLE_reg:CLK
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D
  Delay (ns):                  17.695
  Slack (ns):                  6.811
  Arrival (ns):                23.542
  Required (ns):               30.353
  Setup (ns):                  0.522
  Minimum Period (ns):         18.189

Path 2
  From:                        Aapb_int_fft_0/ifoY_valid:CLK
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1C0_AFULL:D
  Delay (ns):                  17.212
  Slack (ns):                  7.308
  Arrival (ns):                23.055
  Required (ns):               30.363
  Setup (ns):                  0.490
  Minimum Period (ns):         17.692

Path 3
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1C0_FULL:CLK
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1C0_AFULL:D
  Delay (ns):                  16.847
  Slack (ns):                  7.665
  Arrival (ns):                22.698
  Required (ns):               30.363
  Setup (ns):                  0.490
  Minimum Period (ns):         17.335

Path 4
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1C0_MEM_WADDR_0_inst:CLK
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1C0_AFULL:D
  Delay (ns):                  15.594
  Slack (ns):                  8.918
  Arrival (ns):                21.445
  Required (ns):               30.363
  Setup (ns):                  0.490
  Minimum Period (ns):         16.082

Path 5
  From:                        Aapb_int_fft_0/PENABLE_reg:CLK
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1P0_EMPTY:D
  Delay (ns):                  15.487
  Slack (ns):                  9.079
  Arrival (ns):                21.334
  Required (ns):               30.413
  Setup (ns):                  0.490
  Minimum Period (ns):         15.921


Expanded Path 1
  From: Aapb_int_fft_0/PENABLE_reg:CLK
  To: Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D
  data required time                             30.353
  data arrival time                          -   23.542
  slack                                          6.811
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.598          net: FAB_CLK
  5.847                        Aapb_int_fft_0/PENABLE_reg:CLK (r)
               +     0.671          cell: ADLIB:DFN1P0
  6.518                        Aapb_int_fft_0/PENABLE_reg:Q (f)
               +     0.306          net: Aapb_int_fft_0/PENABLE_reg_i
  6.824                        Aapb_int_fft_0/PENABLE_reg_RNICCCC:B (f)
               +     0.584          cell: ADLIB:NOR3C
  7.408                        Aapb_int_fft_0/PENABLE_reg_RNICCCC:Y (f)
               +     0.296          net: Aapb_int_fft_0/un1_fifo_rd_en_m2_e_3
  7.704                        Aapb_int_fft_0/PENABLE_reg_RNI4HTI:B (f)
               +     0.552          cell: ADLIB:NOR3B
  8.256                        Aapb_int_fft_0/PENABLE_reg_RNI4HTI:Y (f)
               +     2.193          net: Aapb_int_fft_0/REP
  10.449                       Aapb_int_fft_0/fifo64X16_inst/AND2_MEMORYRE:B (f)
               +     0.571          cell: ADLIB:AND2A
  11.020                       Aapb_int_fft_0/fifo64X16_inst/AND2_MEMORYRE:Y (f)
               +     0.370          net: Aapb_int_fft_0/fifo64X16_inst/MEMORYRE
  11.390                       Aapb_int_fft_0/fifo64X16_inst/AND2_55:B (f)
               +     0.574          cell: ADLIB:AND2
  11.964                       Aapb_int_fft_0/fifo64X16_inst/AND2_55:Y (f)
               +     0.953          net: Aapb_int_fft_0/fifo64X16_inst/AND2_55_Y
  12.917                       Aapb_int_fft_0/fifo64X16_inst/AO1_15:B (f)
               +     0.574          cell: ADLIB:NOR2B
  13.491                       Aapb_int_fft_0/fifo64X16_inst/AO1_15:Y (f)
               +     0.440          net: Aapb_int_fft_0/fifo64X16_inst/AO1_15_Y
  13.931                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RBINNXTSHIFT_3_inst:B (f)
               +     0.910          cell: ADLIB:AX1C
  14.841                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RBINNXTSHIFT_3_inst:Y (f)
               +     0.824          net: Aapb_int_fft_0/fifo64X16_inst/RBINNXTSHIFT_3_net
  15.665                       Aapb_int_fft_0/fifo64X16_inst/INV_3:A (f)
               +     0.462          cell: ADLIB:INV
  16.127                       Aapb_int_fft_0/fifo64X16_inst/INV_3:Y (r)
               +     0.384          net: Aapb_int_fft_0/fifo64X16_inst/INV_3_Y
  16.511                       Aapb_int_fft_0/fifo64X16_inst/AND2_57:B (r)
               +     0.470          cell: ADLIB:AND2
  16.981                       Aapb_int_fft_0/fifo64X16_inst/AND2_57:Y (r)
               +     0.910          net: Aapb_int_fft_0/fifo64X16_inst/AND2_57_Y
  17.891                       Aapb_int_fft_0/fifo64X16_inst/AO1_7:B (r)
               +     0.606          cell: ADLIB:AO1
  18.497                       Aapb_int_fft_0/fifo64X16_inst/AO1_7:Y (r)
               +     0.320          net: Aapb_int_fft_0/fifo64X16_inst/AO1_7_Y
  18.817                       Aapb_int_fft_0/fifo64X16_inst/AO1_10:C (r)
               +     0.596          cell: ADLIB:AO1
  19.413                       Aapb_int_fft_0/fifo64X16_inst/AO1_10:Y (r)
               +     0.369          net: Aapb_int_fft_0/fifo64X16_inst/AO1_10_Y
  19.782                       Aapb_int_fft_0/fifo64X16_inst/AO1_1:B (r)
               +     0.516          cell: ADLIB:AO1
  20.298                       Aapb_int_fft_0/fifo64X16_inst/AO1_1:Y (r)
               +     0.306          net: Aapb_int_fft_0/fifo64X16_inst/AO1_1_Y
  20.604                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RDIFF_6_inst:C (r)
               +     0.897          cell: ADLIB:XNOR3
  21.501                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RDIFF_6_inst:Y (f)
               +     0.381          net: Aapb_int_fft_0/fifo64X16_inst/RDIFF_6_net
  21.882                       Aapb_int_fft_0/fifo64X16_inst/AND3_0:A (f)
               +     0.478          cell: ADLIB:AND3C
  22.360                       Aapb_int_fft_0/fifo64X16_inst/AND3_0:Y (r)
               +     0.334          net: Aapb_int_fft_0/fifo64X16_inst/AND3_0_Y
  22.694                       Aapb_int_fft_0/fifo64X16_inst/AOI1_0:A (r)
               +     0.552          cell: ADLIB:AOI1
  23.246                       Aapb_int_fft_0/fifo64X16_inst/AOI1_0:Y (f)
               +     0.296          net: Aapb_int_fft_0/fifo64X16_inst/AOI1_0_Y
  23.542                       Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D (f)
                                    
  23.542                       data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_ccc_gla1
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  30.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.626          net: FAB_CLK
  30.875                       Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:CLK (r)
               -     0.522          Library setup time: ADLIB:DFN1P0
  30.353                       Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D
                                    
  30.353                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn:CLR
  Delay (ns):                  5.060
  Slack (ns):                  19.658
  Arrival (ns):                10.938
  Required (ns):               30.596
  Recovery (ns):               0.271
  Minimum Period (ns):         5.342
  Skew (ns):                   0.011

Path 2
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/pipe22:CLR
  Delay (ns):                  4.922
  Slack (ns):                  19.772
  Arrival (ns):                10.800
  Required (ns):               30.572
  Recovery (ns):               0.271
  Minimum Period (ns):         5.228
  Skew (ns):                   0.035

Path 3
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/pipe21:CLR
  Delay (ns):                  4.922
  Slack (ns):                  19.772
  Arrival (ns):                10.800
  Required (ns):               30.572
  Recovery (ns):               0.271
  Minimum Period (ns):         5.228
  Skew (ns):                   0.035

Path 4
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/rdValid:PRE
  Delay (ns):                  4.922
  Slack (ns):                  19.780
  Arrival (ns):                10.800
  Required (ns):               30.580
  Recovery (ns):               0.271
  Minimum Period (ns):         5.220
  Skew (ns):                   0.027

Path 5
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/wA[0]:CLR
  Delay (ns):                  4.929
  Slack (ns):                  19.782
  Arrival (ns):                10.807
  Required (ns):               30.589
  Recovery (ns):               0.271
  Minimum Period (ns):         5.218
  Skew (ns):                   0.018


Expanded Path 1
  From: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK
  To: Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn:CLR
  data required time                             30.596
  data arrival time                          -   10.938
  slack                                          19.658
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.629          net: FAB_CLK
  5.878                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK (r)
               +     0.671          cell: ADLIB:DFN1P0
  6.549                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:Q (f)
               +     0.417          net: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/initRst
  6.966                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835:B (f)
               +     0.445          cell: ADLIB:NOR2A
  7.411                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835:Y (r)
               +     1.971          net: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835
  9.382                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835_0/U_CLKSRC:A (r)
               +     0.829          cell: ADLIB:CLKSRC
  10.211                       Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835_0/U_CLKSRC:Y (r)
               +     0.727          net: Aapb_int_fft_0/fftTop_inst/smTop_0/nGrst
  10.938                       Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn:CLR (r)
                                    
  10.938                       data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_ccc_gla1
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  30.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.618          net: FAB_CLK
  30.867                       Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn:CLK (r)
               -     0.271          Library recovery time: ADLIB:DFN1C0
  30.596                       Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn:CLR
                                    
  30.596                       data required time


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_gla1

Path 1
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D
  Delay (ns):                  22.708
  Slack (ns):                  3.470
  Arrival (ns):                26.883
  Required (ns):               30.353
  Setup (ns):                  0.522

Path 2
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1P0_EMPTY:D
  Delay (ns):                  20.500
  Slack (ns):                  5.738
  Arrival (ns):                24.675
  Required (ns):               30.413
  Setup (ns):                  0.490

Path 3
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1C0_MEM_RADDR_6_inst:D
  Delay (ns):                  17.164
  Slack (ns):                  9.022
  Arrival (ns):                21.339
  Required (ns):               30.361
  Setup (ns):                  0.490

Path 4
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1C0_MEM_RADDR_5_inst:D
  Delay (ns):                  16.189
  Slack (ns):                  9.984
  Arrival (ns):                20.364
  Required (ns):               30.348
  Setup (ns):                  0.490

Path 5
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1C0_MEM_RADDR_4_inst:D
  Delay (ns):                  15.841
  Slack (ns):                  10.397
  Arrival (ns):                20.016
  Required (ns):               30.413
  Setup (ns):                  0.490


Expanded Path 1
  From: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To: Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D
  data required time                             30.353
  data arrival time                          -   26.883
  slack                                          3.470
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.175          Clock generation
  4.175
               +     3.806          cell: ADLIB:MSS_APB_IP
  7.981                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPADDR[10] (r)
               +     0.122          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPADDR[10]INT_NET
  8.103                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_33:PIN2INT (r)
               +     0.095          cell: ADLIB:MSS_IF
  8.198                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_33:PIN2 (r)
               +     0.428          net: CoreAPB3_0_APBmslave0_PADDR_[10]
  8.626                        Aapb_int_fft_0/un1_fifo_rd_en_m2_e_1:B (r)
               +     0.468          cell: ADLIB:NOR2
  9.094                        Aapb_int_fft_0/un1_fifo_rd_en_m2_e_1:Y (f)
               +     1.071          net: Aapb_int_fft_0/un1_fifo_rd_en_m2_e_1
  10.165                       Aapb_int_fft_0/PENABLE_reg_RNICCCC:C (f)
               +     0.584          cell: ADLIB:NOR3C
  10.749                       Aapb_int_fft_0/PENABLE_reg_RNICCCC:Y (f)
               +     0.296          net: Aapb_int_fft_0/un1_fifo_rd_en_m2_e_3
  11.045                       Aapb_int_fft_0/PENABLE_reg_RNI4HTI:B (f)
               +     0.552          cell: ADLIB:NOR3B
  11.597                       Aapb_int_fft_0/PENABLE_reg_RNI4HTI:Y (f)
               +     2.193          net: Aapb_int_fft_0/REP
  13.790                       Aapb_int_fft_0/fifo64X16_inst/AND2_MEMORYRE:B (f)
               +     0.571          cell: ADLIB:AND2A
  14.361                       Aapb_int_fft_0/fifo64X16_inst/AND2_MEMORYRE:Y (f)
               +     0.370          net: Aapb_int_fft_0/fifo64X16_inst/MEMORYRE
  14.731                       Aapb_int_fft_0/fifo64X16_inst/AND2_55:B (f)
               +     0.574          cell: ADLIB:AND2
  15.305                       Aapb_int_fft_0/fifo64X16_inst/AND2_55:Y (f)
               +     0.953          net: Aapb_int_fft_0/fifo64X16_inst/AND2_55_Y
  16.258                       Aapb_int_fft_0/fifo64X16_inst/AO1_15:B (f)
               +     0.574          cell: ADLIB:NOR2B
  16.832                       Aapb_int_fft_0/fifo64X16_inst/AO1_15:Y (f)
               +     0.440          net: Aapb_int_fft_0/fifo64X16_inst/AO1_15_Y
  17.272                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RBINNXTSHIFT_3_inst:B (f)
               +     0.910          cell: ADLIB:AX1C
  18.182                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RBINNXTSHIFT_3_inst:Y (f)
               +     0.824          net: Aapb_int_fft_0/fifo64X16_inst/RBINNXTSHIFT_3_net
  19.006                       Aapb_int_fft_0/fifo64X16_inst/INV_3:A (f)
               +     0.462          cell: ADLIB:INV
  19.468                       Aapb_int_fft_0/fifo64X16_inst/INV_3:Y (r)
               +     0.384          net: Aapb_int_fft_0/fifo64X16_inst/INV_3_Y
  19.852                       Aapb_int_fft_0/fifo64X16_inst/AND2_57:B (r)
               +     0.470          cell: ADLIB:AND2
  20.322                       Aapb_int_fft_0/fifo64X16_inst/AND2_57:Y (r)
               +     0.910          net: Aapb_int_fft_0/fifo64X16_inst/AND2_57_Y
  21.232                       Aapb_int_fft_0/fifo64X16_inst/AO1_7:B (r)
               +     0.606          cell: ADLIB:AO1
  21.838                       Aapb_int_fft_0/fifo64X16_inst/AO1_7:Y (r)
               +     0.320          net: Aapb_int_fft_0/fifo64X16_inst/AO1_7_Y
  22.158                       Aapb_int_fft_0/fifo64X16_inst/AO1_10:C (r)
               +     0.596          cell: ADLIB:AO1
  22.754                       Aapb_int_fft_0/fifo64X16_inst/AO1_10:Y (r)
               +     0.369          net: Aapb_int_fft_0/fifo64X16_inst/AO1_10_Y
  23.123                       Aapb_int_fft_0/fifo64X16_inst/AO1_1:B (r)
               +     0.516          cell: ADLIB:AO1
  23.639                       Aapb_int_fft_0/fifo64X16_inst/AO1_1:Y (r)
               +     0.306          net: Aapb_int_fft_0/fifo64X16_inst/AO1_1_Y
  23.945                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RDIFF_6_inst:C (r)
               +     0.897          cell: ADLIB:XNOR3
  24.842                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RDIFF_6_inst:Y (f)
               +     0.381          net: Aapb_int_fft_0/fifo64X16_inst/RDIFF_6_net
  25.223                       Aapb_int_fft_0/fifo64X16_inst/AND3_0:A (f)
               +     0.478          cell: ADLIB:AND3C
  25.701                       Aapb_int_fft_0/fifo64X16_inst/AND3_0:Y (r)
               +     0.334          net: Aapb_int_fft_0/fifo64X16_inst/AND3_0_Y
  26.035                       Aapb_int_fft_0/fifo64X16_inst/AOI1_0:A (r)
               +     0.552          cell: ADLIB:AOI1
  26.587                       Aapb_int_fft_0/fifo64X16_inst/AOI1_0:Y (f)
               +     0.296          net: Aapb_int_fft_0/fifo64X16_inst/AOI1_0_Y
  26.883                       Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D (f)
                                    
  26.883                       data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_ccc_gla1
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  30.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.626          net: FAB_CLK
  30.875                       Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:CLK (r)
               -     0.522          Library setup time: ADLIB:DFN1P0
  30.353                       Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D
                                    
  30.353                       data required time


END SET mss_fabric_interface_clock to mss_ccc_gla1

----------------------------------------------------

SET mss_ccc_gla0 to mss_ccc_gla1

Path 1
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn:CLR
  Delay (ns):                  11.064
  Slack (ns):                  15.357
  Arrival (ns):                15.239
  Required (ns):               30.596
  Setup (ns):

Path 2
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/pipe22:CLR
  Delay (ns):                  10.926
  Slack (ns):                  15.471
  Arrival (ns):                15.101
  Required (ns):               30.572
  Setup (ns):

Path 3
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/pipe21:CLR
  Delay (ns):                  10.926
  Slack (ns):                  15.471
  Arrival (ns):                15.101
  Required (ns):               30.572
  Setup (ns):

Path 4
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/rdValid:PRE
  Delay (ns):                  10.926
  Slack (ns):                  15.479
  Arrival (ns):                15.101
  Required (ns):               30.580
  Setup (ns):

Path 5
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/wA[0]:CLR
  Delay (ns):                  10.933
  Slack (ns):                  15.481
  Arrival (ns):                15.108
  Required (ns):               30.589
  Setup (ns):


Expanded Path 1
  From: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To: Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn:CLR
  data required time                             30.596
  data arrival time                          -   15.239
  slack                                          15.357
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  3.545
               +     0.630          net: DSP_Coprocessor_MSS_0/GLA0
  4.175                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     3.632          cell: ADLIB:MSS_APB_IP
  7.807                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:M2FRESETn (r)
               +     0.122          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/M2FRESETnINT_NET
  7.929                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_46:PIN2INT (r)
               +     0.095          cell: ADLIB:MSS_IF
  8.024                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_46:PIN2 (r)
               +     3.218          net: DSP_Coprocessor_MSS_0_M2F_RESET_N
  11.242                       Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835:A (r)
               +     0.470          cell: ADLIB:NOR2A
  11.712                       Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835:Y (r)
               +     1.971          net: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835
  13.683                       Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835_0/U_CLKSRC:A (r)
               +     0.829          cell: ADLIB:CLKSRC
  14.512                       Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835_0/U_CLKSRC:Y (r)
               +     0.727          net: Aapb_int_fft_0/fftTop_inst/smTop_0/nGrst
  15.239                       Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn:CLR (r)
                                    
  15.239                       data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_ccc_gla1
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  30.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.618          net: FAB_CLK
  30.867                       Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn:CLK (r)
               -     0.271          Library recovery time: ADLIB:DFN1C0
  30.596                       Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn:CLR
                                    
  30.596                       data required time


END SET mss_ccc_gla0 to mss_ccc_gla1

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.937
  Slack (ns):
  Arrival (ns):                0.937
  Required (ns):
  Setup (ns):                  -2.196
  External Setup (ns):         -5.434


Expanded Path 1
  From: MSS_RESET_N
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.937
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        DSP_Coprocessor_MSS_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.937          cell: ADLIB:IOPAD_IN
  0.937                        DSP_Coprocessor_MSS_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_RESET_0_MSS_RESET_N_Y
  0.937                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.937                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  N/C
               +     0.630          net: DSP_Coprocessor_MSS_0/GLA0
  N/C                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -2.196          Library setup time: ADLIB:MSS_APB_IP
  N/C                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain DSP_Coprocessor_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

