#Build: Synplify Pro E-2010.09A-1, Build 006R, Oct 6 2010 #install: \\idm\tools\releases\production\Libero\Libero_91\PC_Libero_9_1_0_18_winxp_32\Synopsys\synplify_E201009A-1 #OS: Windows XP 5.1 #Hostname: VXP-ARNIS #Implementation: synthesis #Wed Apr 27 17:03:54 2011 $ Start of Compile #Wed Apr 27 17:03:54 2011 Synopsys VHDL Compiler, version comp520rcp1, Build 028R, built Sep 23 2010 @N: : | Running in 32-bit mode Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved @N:CD720 : std.vhd(123) | Setting time resolution to ns @N: : DSP_Coprocessor.vhd(10) | Top entity is set to DSP_Coprocessor. VHDL syntax check successful! Compiler output is up to date. No re-compile necessary @N:CD231 : std_logic_textio.vhd(79) | Using onehot encoding for type mvl9plus ('U'="1000000000") @N:CD630 : DSP_Coprocessor.vhd(10) | Synthesizing work.dsp_coprocessor.def_arch @N:CD630 : Aapb_int_fft.vhd(27) | Synthesizing work.aapb_int_fft.behav @N:CD630 : fifo64x16.vhd(8) | Synthesizing work.fifo64x16.def_arch @N:CD630 : smartfusion.vhd(2988) | Synthesizing smartfusion.ram512x18.syn_black_box Post processing for smartfusion.ram512x18.syn_black_box @N:CD630 : smartfusion.vhd(163) | Synthesizing smartfusion.ao1c.syn_black_box Post processing for smartfusion.ao1c.syn_black_box @N:CD630 : smartfusion.vhd(13) | Synthesizing smartfusion.and2.syn_black_box Post processing for smartfusion.and2.syn_black_box @N:CD630 : smartfusion.vhd(2802) | Synthesizing smartfusion.xnor2.syn_black_box Post processing for smartfusion.xnor2.syn_black_box @N:CD630 : smartfusion.vhd(2837) | Synthesizing smartfusion.xor2.syn_black_box Post processing for smartfusion.xor2.syn_black_box @N:CD630 : smartfusion.vhd(136) | Synthesizing smartfusion.ao1.syn_black_box Post processing for smartfusion.ao1.syn_black_box @N:CD630 : smartfusion.vhd(2043) | Synthesizing smartfusion.nand2.syn_black_box Post processing for smartfusion.nand2.syn_black_box @N:CD630 : smartfusion.vhd(1385) | Synthesizing smartfusion.dfn1c0.syn_black_box Post processing for smartfusion.dfn1c0.syn_black_box @N:CD630 : smartfusion.vhd(37) | Synthesizing smartfusion.and3.syn_black_box Post processing for smartfusion.and3.syn_black_box @N:CD630 : smartfusion.vhd(1469) | Synthesizing smartfusion.dfn1e1c0.syn_black_box Post processing for smartfusion.dfn1e1c0.syn_black_box @N:CD630 : smartfusion.vhd(172) | Synthesizing smartfusion.ao1d.syn_black_box Post processing for smartfusion.ao1d.syn_black_box @N:CD630 : smartfusion.vhd(1945) | Synthesizing smartfusion.inv.syn_black_box Post processing for smartfusion.inv.syn_black_box @N:CD630 : smartfusion.vhd(2217) | Synthesizing smartfusion.or2a.syn_black_box Post processing for smartfusion.or2a.syn_black_box @N:CD630 : smartfusion.vhd(2112) | Synthesizing smartfusion.nor2a.syn_black_box Post processing for smartfusion.nor2a.syn_black_box @N:CD630 : smartfusion.vhd(1513) | Synthesizing smartfusion.dfn1p0.syn_black_box Post processing for smartfusion.dfn1p0.syn_black_box @N:CD630 : smartfusion.vhd(190) | Synthesizing smartfusion.aoi1.syn_black_box Post processing for smartfusion.aoi1.syn_black_box @N:CD630 : smartfusion.vhd(21) | Synthesizing smartfusion.and2a.syn_black_box Post processing for smartfusion.and2a.syn_black_box @N:CD630 : smartfusion.vhd(2077) | Synthesizing smartfusion.nand3a.syn_black_box Post processing for smartfusion.nand3a.syn_black_box @N:CD630 : smartfusion.vhd(2137) | Synthesizing smartfusion.nor3a.syn_black_box Post processing for smartfusion.nor3a.syn_black_box @N:CD630 : smartfusion.vhd(2233) | Synthesizing smartfusion.or3.syn_black_box Post processing for smartfusion.or3.syn_black_box @N:CD630 : smartfusion.vhd(2209) | Synthesizing smartfusion.or2.syn_black_box Post processing for smartfusion.or2.syn_black_box @N:CD630 : smartfusion.vhd(1784) | Synthesizing smartfusion.gnd.syn_black_box Post processing for smartfusion.gnd.syn_black_box @N:CD630 : smartfusion.vhd(2742) | Synthesizing smartfusion.vcc.syn_black_box Post processing for smartfusion.vcc.syn_black_box Post processing for work.fifo64x16.def_arch @W:CL168 : fifo64x16.vhd(1100) | Pruning instance AND2_25 - not in use ... @W:CL168 : fifo64x16.vhd(1083) | Pruning instance XOR2_42 - not in use ... @W:CL168 : fifo64x16.vhd(1067) | Pruning instance DFN1C0_WGRY_4_inst - not in use ... @W:CL168 : fifo64x16.vhd(1058) | Pruning instance DFN1C0_RGRY_0_inst - not in use ... @W:CL168 : fifo64x16.vhd(1024) | Pruning instance XOR2_28 - not in use ... @W:CL168 : fifo64x16.vhd(1019) | Pruning instance AND2_53 - not in use ... @W:CL168 : fifo64x16.vhd(1002) | Pruning instance XOR2_51 - not in use ... @W:CL168 : fifo64x16.vhd(999) | Pruning instance AO1_27 - not in use ... @W:CL168 : fifo64x16.vhd(996) | Pruning instance XOR2_54 - not in use ... @W:CL168 : fifo64x16.vhd(984) | Pruning instance DFN1C0_RGRY_3_inst - not in use ... @W:CL168 : fifo64x16.vhd(960) | Pruning instance AND2_40 - not in use ... @W:CL168 : fifo64x16.vhd(942) | Pruning instance AND2_45 - not in use ... @W:CL168 : fifo64x16.vhd(940) | Pruning instance AND2_48 - not in use ... @W:CL168 : fifo64x16.vhd(923) | Pruning instance XOR2_53 - not in use ... @W:CL168 : fifo64x16.vhd(909) | Pruning instance AND2_54 - not in use ... @W:CL168 : fifo64x16.vhd(898) | Pruning instance AND2_17 - not in use ... @W:CL168 : fifo64x16.vhd(892) | Pruning instance AND2_0 - not in use ... @W:CL168 : fifo64x16.vhd(890) | Pruning instance AND2_41 - not in use ... @W:CL168 : fifo64x16.vhd(878) | Pruning instance DFN1C0_WGRY_1_inst - not in use ... @W:CL168 : fifo64x16.vhd(872) | Pruning instance XOR2_41 - not in use ... @W:CL168 : fifo64x16.vhd(866) | Pruning instance XOR2_44 - not in use ... @W:CL168 : fifo64x16.vhd(857) | Pruning instance AO1_23 - not in use ... @W:CL168 : fifo64x16.vhd(843) | Pruning instance XOR2_37 - not in use ... @W:CL168 : fifo64x16.vhd(841) | Pruning instance AND2_36 - not in use ... @W:CL168 : fifo64x16.vhd(836) | Pruning instance DFN1C0_RGRY_5_inst - not in use ... @W:CL168 : fifo64x16.vhd(828) | Pruning instance XOR2_29 - not in use ... @W:CL168 : fifo64x16.vhd(822) | Pruning instance DFN1C0_WGRY_2_inst - not in use ... @W:CL168 : fifo64x16.vhd(817) | Pruning instance AO1_20 - not in use ... @W:CL168 : fifo64x16.vhd(797) | Pruning instance DFN1C0_RGRY_6_inst - not in use ... @W:CL168 : fifo64x16.vhd(790) | Pruning instance DFN1C0_DVLDX - not in use ... @W:CL168 : fifo64x16.vhd(765) | Pruning instance AND2_9 - not in use ... @W:CL168 : fifo64x16.vhd(756) | Pruning instance XOR2_32 - not in use ... @W:CL168 : fifo64x16.vhd(736) | Pruning instance AND2_34 - not in use ... @W:CL168 : fifo64x16.vhd(730) | Pruning instance AO1_22 - not in use ... @W:CL168 : fifo64x16.vhd(711) | Pruning instance AND2_50 - not in use ... @W:CL168 : fifo64x16.vhd(703) | Pruning instance AND2_5 - not in use ... @W:CL168 : fifo64x16.vhd(686) | Pruning instance DFN1C0_RGRY_4_inst - not in use ... @W:CL168 : fifo64x16.vhd(673) | Pruning instance XOR2_10 - not in use ... @W:CL168 : fifo64x16.vhd(671) | Pruning instance AND2_13 - not in use ... @W:CL168 : fifo64x16.vhd(661) | Pruning instance AND2_16 - not in use ... @W:CL168 : fifo64x16.vhd(647) | Pruning instance AND2_47 - not in use ... @W:CL168 : fifo64x16.vhd(640) | Pruning instance AND2_51 - not in use ... @W:CL168 : fifo64x16.vhd(632) | Pruning instance XOR2_13 - not in use ... @W:CL168 : fifo64x16.vhd(626) | Pruning instance XOR2_22 - not in use ... @W:CL168 : fifo64x16.vhd(613) | Pruning instance XOR2_5 - not in use ... @W:CL168 : fifo64x16.vhd(605) | Pruning instance AND2_23 - not in use ... @W:CL168 : fifo64x16.vhd(602) | Pruning instance XOR2_59 - not in use ... @W:CL168 : fifo64x16.vhd(586) | Pruning instance DFN1C0_WGRY_0_inst - not in use ... @W:CL168 : fifo64x16.vhd(583) | Pruning instance AO1_2 - not in use ... @W:CL168 : fifo64x16.vhd(499) | Pruning instance AND2_38 - not in use ... @W:CL168 : fifo64x16.vhd(473) | Pruning instance DFN1C0_WGRY_3_inst - not in use ... @W:CL168 : fifo64x16.vhd(470) | Pruning instance DFN1C0_RGRY_1_inst - not in use ... @W:CL168 : fifo64x16.vhd(461) | Pruning instance XOR2_18 - not in use ... @W:CL168 : fifo64x16.vhd(448) | Pruning instance AND2_24 - not in use ... @W:CL168 : fifo64x16.vhd(445) | Pruning instance XOR2_55 - not in use ... @W:CL168 : fifo64x16.vhd(433) | Pruning instance AO1_14 - not in use ... @W:CL168 : fifo64x16.vhd(423) | Pruning instance XOR2_33 - not in use ... @W:CL168 : fifo64x16.vhd(420) | Pruning instance DFN1C0_RGRY_2_inst - not in use ... @W:CL168 : fifo64x16.vhd(397) | Pruning instance AND2_6 - not in use ... @W:CL168 : fifo64x16.vhd(374) | Pruning instance AND2_46 - not in use ... @W:CL168 : fifo64x16.vhd(350) | Pruning instance AND2_61 - not in use ... @W:CL168 : fifo64x16.vhd(341) | Pruning instance DFN1C0_WGRY_5_inst - not in use ... @W:CL168 : fifo64x16.vhd(327) | Pruning instance XOR2_63 - not in use ... @W:CL168 : fifo64x16.vhd(307) | Pruning instance AND2_49 - not in use ... @W:CL168 : fifo64x16.vhd(302) | Pruning instance AND2_1 - not in use ... @W:CL168 : fifo64x16.vhd(299) | Pruning instance XOR2_45 - not in use ... @W:CL168 : fifo64x16.vhd(287) | Pruning instance AND2_15 - not in use ... @W:CL168 : fifo64x16.vhd(285) | Pruning instance AND2_18 - not in use ... @W:CL168 : fifo64x16.vhd(282) | Pruning instance DFN1C0_WGRY_6_inst - not in use ... @W:CL168 : fifo64x16.vhd(267) | Pruning instance XOR2_47 - not in use ... @W:CL168 : fifo64x16.vhd(250) | Pruning instance XOR2_1 - not in use ... @N:CD630 : fftTop.vhd(33) | Synthesizing work.ffttop.translated @N:CD630 : fftDp.vhd(592) | Synthesizing work.autoscale.translated @N:CD630 : primitives.vhd(100) | Synthesizing work.edgedetect.translated Post processing for work.edgedetect.translated @W:CL169 : primitives.vhd(127) | Pruning Register in_pipe Post processing for work.autoscale.translated @N:CD630 : fftDp.vhd(450) | Synthesizing work.outbuff.translated @N:CD630 : fftDp.vhd(561) | Synthesizing work.wrapram.rtl @N:CD630 : actram.vhd(8) | Synthesizing work.actram.def_arch @W:CD280 : actram.vhd(32) | Unbound component VCC mapped to black box @W:CD280 : actram.vhd(36) | Unbound component GND mapped to black box @W:CD280 : actram.vhd(19) | Unbound component RAM512X18 mapped to black box @N:CD630 : actram.vhd(19) | Synthesizing work.ram512x18.syn_black_box Post processing for work.ram512x18.syn_black_box @N:CD630 : actram.vhd(36) | Synthesizing work.gnd.syn_black_box Post processing for work.gnd.syn_black_box @N:CD630 : actram.vhd(32) | Synthesizing work.vcc.syn_black_box Post processing for work.vcc.syn_black_box Post processing for work.actram.def_arch Post processing for work.wrapram.rtl Post processing for work.outbuff.translated @N:CD630 : fftDp.vhd(21) | Synthesizing work.switch.translated Post processing for work.switch.translated @N:CD630 : fftDp.vhd(517) | Synthesizing work.twidlut.translated Post processing for work.twidlut.translated @N:CD630 : twiddle.vhd(22) | Synthesizing work.twiddle.translated Post processing for work.twiddle.translated @N:CD630 : fftDp.vhd(183) | Synthesizing work.bfly2.translated @N:CD630 : fftDp.vhd(118) | Synthesizing work.agen.rtl @N:CD630 : fftDp.vhd(72) | Synthesizing work.kitrndup.rtl Post processing for work.kitrndup.rtl @W:CL265 : fftDp.vhd(94) | Pruning bit 0 of int_outp(8 downto 0) - not in use ... @N:CD630 : actar.vhd(8) | Synthesizing work.actar.def_arch @W:CD280 : actar.vhd(17) | Unbound component DFN1 mapped to black box @W:CD280 : actar.vhd(21) | Unbound component MAJ3 mapped to black box @W:CD280 : actar.vhd(25) | Unbound component AND2 mapped to black box @W:CD280 : actar.vhd(29) | Unbound component NOR2 mapped to black box @W:CD280 : actar.vhd(33) | Unbound component AO1 mapped to black box @W:CD280 : actar.vhd(37) | Unbound component XOR2 mapped to black box @W:CD280 : actar.vhd(41) | Unbound component BUFF mapped to black box @W:CD280 : actar.vhd(45) | Unbound component MX2 mapped to black box @W:CD280 : actar.vhd(49) | Unbound component AOI1 mapped to black box @W:CD280 : actar.vhd(53) | Unbound component OR3 mapped to black box @W:CD280 : actar.vhd(57) | Unbound component AND2A mapped to black box @W:CD280 : actar.vhd(61) | Unbound component AND3 mapped to black box @W:CD280 : actar.vhd(65) | Unbound component XNOR2 mapped to black box @W:CD280 : actar.vhd(69) | Unbound component XOR3 mapped to black box @N:CD630 : actar.vhd(17) | Synthesizing work.dfn1.syn_black_box Post processing for work.dfn1.syn_black_box @N:CD630 : actar.vhd(45) | Synthesizing work.mx2.syn_black_box Post processing for work.mx2.syn_black_box @N:CD630 : actar.vhd(25) | Synthesizing work.and2.syn_black_box Post processing for work.and2.syn_black_box @N:CD630 : actar.vhd(69) | Synthesizing work.xor3.syn_black_box Post processing for work.xor3.syn_black_box @N:CD630 : actar.vhd(65) | Synthesizing work.xnor2.syn_black_box Post processing for work.xnor2.syn_black_box @N:CD630 : actar.vhd(41) | Synthesizing work.buff.syn_black_box Post processing for work.buff.syn_black_box @N:CD630 : actar.vhd(37) | Synthesizing work.xor2.syn_black_box Post processing for work.xor2.syn_black_box @N:CD630 : actar.vhd(33) | Synthesizing work.ao1.syn_black_box Post processing for work.ao1.syn_black_box @N:CD630 : actar.vhd(21) | Synthesizing work.maj3.syn_black_box Post processing for work.maj3.syn_black_box @N:CD630 : actar.vhd(29) | Synthesizing work.nor2.syn_black_box Post processing for work.nor2.syn_black_box @N:CD630 : actar.vhd(49) | Synthesizing work.aoi1.syn_black_box Post processing for work.aoi1.syn_black_box @N:CD630 : actar.vhd(57) | Synthesizing work.and2a.syn_black_box Post processing for work.and2a.syn_black_box @N:CD630 : actar.vhd(53) | Synthesizing work.or3.syn_black_box Post processing for work.or3.syn_black_box @N:CD630 : actar.vhd(61) | Synthesizing work.and3.syn_black_box Post processing for work.and3.syn_black_box Post processing for work.actar.def_arch @W:CL168 : actar.vhd(1079) | Pruning instance XOR2_0 - not in use ... @W:CL168 : actar.vhd(997) | Pruning instance AND2_67 - not in use ... @W:CL168 : actar.vhd(984) | Pruning instance AND2_42 - not in use ... @W:CL168 : actar.vhd(958) | Pruning instance AO1_19 - not in use ... @W:CL168 : actar.vhd(954) | Pruning instance AND2_48 - not in use ... @W:CL168 : actar.vhd(911) | Pruning instance AND2_17 - not in use ... @W:CL168 : actar.vhd(904) | Pruning instance AND2_0 - not in use ... @W:CL168 : actar.vhd(896) | Pruning instance AO1_30 - not in use ... @W:CL168 : actar.vhd(844) | Pruning instance AND2_36 - not in use ... @W:CL168 : actar.vhd(741) | Pruning instance XOR2_32 - not in use ... @W:CL168 : actar.vhd(688) | Pruning instance AND2_52 - not in use ... @W:CL168 : actar.vhd(640) | Pruning instance AND2_58 - not in use ... @W:CL168 : actar.vhd(624) | Pruning instance AND2_16 - not in use ... @W:CL168 : actar.vhd(510) | Pruning instance AND2_74 - not in use ... @W:CL168 : actar.vhd(482) | Pruning instance AND2_29 - not in use ... @W:CL168 : actar.vhd(367) | Pruning instance AND2_43 - not in use ... @W:CL168 : actar.vhd(343) | Pruning instance AND2_46 - not in use ... @W:CL168 : actar.vhd(333) | Pruning instance AND2_57 - not in use ... @W:CL168 : actar.vhd(281) | Pruning instance AND2_1 - not in use ... @W:CL168 : actar.vhd(270) | Pruning instance AND2_75 - not in use ... @W:CL168 : actar.vhd(268) | Pruning instance AND2_78 - not in use ... @W:CL168 : actar.vhd(261) | Pruning instance AND2_84 - not in use ... @W:CL168 : actar.vhd(207) | Pruning instance AO1_31 - not in use ... @W:CL168 : actar.vhd(185) | Pruning instance AND2_11 - not in use ... Post processing for work.agen.rtl Post processing for work.bfly2.translated @N:CD630 : fftDp.vhd(383) | Synthesizing work.pipobuffer.translated @N:CD630 : fftDp.vhd(308) | Synthesizing work.inbuffer.translated Post processing for work.inbuffer.translated Post processing for work.pipobuffer.translated @N:CD630 : fftSm.vhd(503) | Synthesizing work.sm_top.translated @N:CD630 : fftSm.vhd(410) | Synthesizing work.outbufa.translated @N:CD630 : primitives.vhd(23) | Synthesizing work.counter.translated Post processing for work.counter.translated Post processing for work.outbufa.translated @N:CD630 : fftSm.vhd(282) | Synthesizing work.inbuf_ffta.translated Post processing for work.inbuf_ffta.translated @N:CD630 : fftSm.vhd(356) | Synthesizing work.twid_wamod.translated @N:CD630 : primitives.vhd(69) | Synthesizing work.bcounter.translated Post processing for work.bcounter.translated Post processing for work.twid_wamod.translated @A: : fftSm.vhd(393) | Feedback mux created for signal rstAfterInit_int. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @A: : fftSm.vhd(393) | Feedback mux created for signal preRstAfterInit. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @N:CD630 : fftSm.vhd(22) | Synthesizing work.twid_ra.translated Post processing for work.twid_ra.translated @N:CD630 : fftSm.vhd(193) | Synthesizing work.inbuf_lda.translated Post processing for work.inbuf_lda.translated @N:CD630 : fftSm.vhd(148) | Synthesizing work.wrffttimer.translated @N:CD630 : primitives.vhd(23) | Synthesizing work.counter.translated Post processing for work.counter.translated @N:CD630 : primitives.vhd(23) | Synthesizing work.counter.translated Post processing for work.counter.translated Post processing for work.wrffttimer.translated @N:CD630 : fftSm.vhd(67) | Synthesizing work.rdffttimer.translated @N:CD630 : primitives.vhd(23) | Synthesizing work.counter.translated Post processing for work.counter.translated Post processing for work.rdffttimer.translated Post processing for work.sm_top.translated Post processing for work.ffttop.translated Post processing for work.aapb_int_fft.behav @W:CL240 : Aapb_int_fft.vhd(42) | PSLVERR is not assigned a value (floating) - a simulation mismatch is possible @N:CD630 : DSP_Coprocessor_MSS.vhd(8) | Synthesizing work.dsp_coprocessor_mss.def_arch @N:CD630 : mss_comps.vhd(168) | Synthesizing work.mssint.def_arch Post processing for work.mssint.def_arch @N:CD630 : mss_comps.vhd(4) | Synthesizing work.inbuf_mss.def_arch Post processing for work.inbuf_mss.def_arch @N:CD630 : DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd(8) | Synthesizing work.dsp_coprocessor_mss_tmp_mss_ccc_0_mss_ccc.def_arch @N:CD630 : smartfusion.vhd(3703) | Synthesizing smartfusion.rcosc.syn_black_box Post processing for smartfusion.rcosc.syn_black_box @N:CD630 : mss_comps.vhd(472) | Synthesizing work.mss_ccc.def_arch Post processing for work.mss_ccc.def_arch Post processing for work.dsp_coprocessor_mss_tmp_mss_ccc_0_mss_ccc.def_arch @W:CL240 : DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd(38) | LPXIN_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible @W:CL240 : DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd(37) | MAINXIN_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible @W:CL240 : DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd(36) | RCOSC_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible @N:CD630 : mss_comps.vhd(24) | Synthesizing work.outbuf_mss.def_arch Post processing for work.outbuf_mss.def_arch @N:CD630 : mss_tshell.vhd(4) | Synthesizing work.mss_apb.def_arch Post processing for work.mss_apb.def_arch Post processing for work.dsp_coprocessor_mss.def_arch @N:CD630 : coreapb3.vhd(14) | Synthesizing coreapb3_lib.coreapb3.capb3i0l @W:CD604 : coreapb3.vhd(439) | OTHERS clause is not synthesized @N:CD630 : coreapb3_muxptob3.vhd(14) | Synthesizing coreapb3_lib.capb3o.capb3ll @W:CD604 : coreapb3_muxptob3.vhd(152) | OTHERS clause is not synthesized @W:CD604 : coreapb3_muxptob3.vhd(195) | OTHERS clause is not synthesized @W:CD604 : coreapb3_muxptob3.vhd(238) | OTHERS clause is not synthesized Post processing for coreapb3_lib.capb3o.capb3ll Post processing for coreapb3_lib.coreapb3.capb3i0l Post processing for work.dsp_coprocessor.def_arch @W:CL246 : coreapb3.vhd(35) | Input port bits 23 to 12 of paddr(23 downto 0) are unused @W:CL159 : coreapb3.vhd(33) | Input presetn is unused @W:CL159 : coreapb3.vhd(34) | Input pclk is unused @W:CL159 : coreapb3.vhd(65) | Input PRDATAS1 is unused @W:CL159 : coreapb3.vhd(66) | Input PRDATAS2 is unused @W:CL159 : coreapb3.vhd(67) | Input PRDATAS3 is unused @W:CL159 : coreapb3.vhd(68) | Input PRDATAS4 is unused @W:CL159 : coreapb3.vhd(69) | Input PRDATAS5 is unused @W:CL159 : coreapb3.vhd(70) | Input PRDATAS6 is unused @W:CL159 : coreapb3.vhd(71) | Input PRDATAS7 is unused @W:CL159 : coreapb3.vhd(72) | Input PRDATAS8 is unused @W:CL159 : coreapb3.vhd(73) | Input PRDATAS9 is unused @W:CL159 : coreapb3.vhd(74) | Input PRDATAS10 is unused @W:CL159 : coreapb3.vhd(75) | Input PRDATAS11 is unused @W:CL159 : coreapb3.vhd(76) | Input PRDATAS12 is unused @W:CL159 : coreapb3.vhd(77) | Input PRDATAS13 is unused @W:CL159 : coreapb3.vhd(78) | Input PRDATAS14 is unused @W:CL159 : coreapb3.vhd(79) | Input PRDATAS15 is unused @W:CL159 : coreapb3.vhd(81) | Input preadys1 is unused @W:CL159 : coreapb3.vhd(82) | Input preadys2 is unused @W:CL159 : coreapb3.vhd(83) | Input preADYS3 is unused @W:CL159 : coreapb3.vhd(84) | Input preadys4 is unused @W:CL159 : coreapb3.vhd(85) | Input PREADYs5 is unused @W:CL159 : coreapb3.vhd(86) | Input preadyS6 is unused @W:CL159 : coreapb3.vhd(87) | Input PREadys7 is unused @W:CL159 : coreapb3.vhd(88) | Input pREADYS8 is unused @W:CL159 : coreapb3.vhd(89) | Input preADYS9 is unused @W:CL159 : coreapb3.vhd(90) | Input preadys10 is unused @W:CL159 : coreapb3.vhd(91) | Input preaDYS11 is unused @W:CL159 : coreapb3.vhd(92) | Input PREADYS12 is unused @W:CL159 : coreapb3.vhd(93) | Input PREadys13 is unused @W:CL159 : coreapb3.vhd(94) | Input preADYS14 is unused @W:CL159 : coreapb3.vhd(95) | Input PREAdys15 is unused @W:CL159 : coreapb3.vhd(97) | Input PSLVERrs1 is unused @W:CL159 : coreapb3.vhd(98) | Input pslverrs2 is unused @W:CL159 : coreapb3.vhd(99) | Input pslverrS3 is unused @W:CL159 : coreapb3.vhd(100) | Input pSLVERRS4 is unused @W:CL159 : coreapb3.vhd(101) | Input PSLVERRS5 is unused @W:CL159 : coreapb3.vhd(102) | Input PSLVERRS6 is unused @W:CL159 : coreapb3.vhd(103) | Input pslvERRS7 is unused @W:CL159 : coreapb3.vhd(104) | Input pslverrs8 is unused @W:CL159 : coreapb3.vhd(105) | Input PSLVERRS9 is unused @W:CL159 : coreapb3.vhd(106) | Input PSLVERRS10 is unused @W:CL159 : coreapb3.vhd(107) | Input pslverRS11 is unused @W:CL159 : coreapb3.vhd(108) | Input PSLverrs12 is unused @W:CL159 : coreapb3.vhd(109) | Input PSLVERRS13 is unused @W:CL159 : coreapb3.vhd(110) | Input pslverrs14 is unused @W:CL159 : coreapb3.vhd(111) | Input pSLVERRS15 is unused @W:CL159 : DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd(10) | Input CLKA is unused @W:CL159 : DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd(11) | Input CLKA_PAD is unused @W:CL159 : DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd(12) | Input CLKA_PADP is unused @W:CL159 : DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd(13) | Input CLKA_PADN is unused @W:CL159 : DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd(14) | Input CLKB is unused @W:CL159 : DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd(15) | Input CLKB_PAD is unused @W:CL159 : DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd(16) | Input CLKB_PADP is unused @W:CL159 : DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd(17) | Input CLKB_PADN is unused @W:CL159 : DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd(18) | Input CLKC is unused @W:CL159 : DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd(19) | Input CLKC_PAD is unused @W:CL159 : DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd(20) | Input CLKC_PADP is unused @W:CL159 : DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd(21) | Input CLKC_PADN is unused @W:CL159 : DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd(22) | Input MAINXIN is unused @W:CL159 : DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd(23) | Input LPXIN is unused @W:CL159 : DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd(24) | Input MAC_CLK is unused @W:CL159 : fftSm.vhd(413) | Input clkEn is unused @W:CL159 : fftDp.vhd(318) | Input rEn is unused @W:CL260 : fftDp.vhd(276) | Pruning Register bit 8 of outQ_xhdl2(15 downto 0) @W:CL260 : fftDp.vhd(276) | Pruning Register bit 0 of outQ_xhdl2(15 downto 0) @W:CL159 : fftDp.vhd(454) | Input clkEn is unused @W:CL159 : primitives.vhd(105) | Input clkEn is unused @W:CL159 : fftDp.vhd(597) | Input ifo_loadOn is unused @W:CL246 : Aapb_int_fft.vhd(38) | Input port bits 31 to 16 of pwdata(31 downto 0) are unused @W:CL157 : Aapb_int_fft.vhd(112) | Output PRDATA has undriven bits - a simulation mismatch is possible @W:CL159 : Aapb_int_fft.vhd(35) | Input PADDR is unused @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Apr 27 17:03:55 2011 ###########################################################] Synopsys Actel Technology Mapper, Version mapact, Build 023R, Built Sep 29 2010 09:29:00 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved Product Version E-2010.09A-1 @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled @W:MO111 : aapb_int_fft.vhd(112) | tristate driver PRDATA_16 on net PRDATA_16 has its enable tied to GND (module Aapb_int_fft) @W:MO111 : aapb_int_fft.vhd(112) | tristate driver PRDATA_15 on net PRDATA_15 has its enable tied to GND (module Aapb_int_fft) @W:MO111 : aapb_int_fft.vhd(112) | tristate driver PRDATA_14 on net PRDATA_14 has its enable tied to GND (module Aapb_int_fft) @W:MO111 : aapb_int_fft.vhd(112) | tristate driver PRDATA_13 on net PRDATA_13 has its enable tied to GND (module Aapb_int_fft) @W:MO111 : aapb_int_fft.vhd(112) | tristate driver PRDATA_12 on net PRDATA_12 has its enable tied to GND (module Aapb_int_fft) @W:MO111 : aapb_int_fft.vhd(112) | tristate driver PRDATA_11 on net PRDATA_11 has its enable tied to GND (module Aapb_int_fft) @W:MO111 : aapb_int_fft.vhd(112) | tristate driver PRDATA_10 on net PRDATA_10 has its enable tied to GND (module Aapb_int_fft) @W:MO111 : aapb_int_fft.vhd(112) | tristate driver PRDATA_9 on net PRDATA_9 has its enable tied to GND (module Aapb_int_fft) @W:MO111 : aapb_int_fft.vhd(112) | tristate driver PRDATA_8 on net PRDATA_8 has its enable tied to GND (module Aapb_int_fft) @W:MO111 : aapb_int_fft.vhd(112) | tristate driver PRDATA_7 on net PRDATA_7 has its enable tied to GND (module Aapb_int_fft) @W:MO111 : aapb_int_fft.vhd(112) | tristate driver PRDATA_6 on net PRDATA_6 has its enable tied to GND (module Aapb_int_fft) @W:MO111 : aapb_int_fft.vhd(112) | tristate driver PRDATA_5 on net PRDATA_5 has its enable tied to GND (module Aapb_int_fft) @W:MO111 : aapb_int_fft.vhd(112) | tristate driver PRDATA_4 on net PRDATA_4 has its enable tied to GND (module Aapb_int_fft) @W:MO111 : aapb_int_fft.vhd(112) | tristate driver PRDATA_3 on net PRDATA_3 has its enable tied to GND (module Aapb_int_fft) @W:MO111 : aapb_int_fft.vhd(112) | tristate driver PRDATA_2 on net PRDATA_2 has its enable tied to GND (module Aapb_int_fft) @W:MO111 : aapb_int_fft.vhd(112) | tristate driver PRDATA_1 on net PRDATA_1 has its enable tied to GND (module Aapb_int_fft) @W:MO111 : | tristate driver \\CoreAPB3_0_APBmslave0_PRDATA_\[31\]\\_t on net \\CoreAPB3_0_APBmslave0_PRDATA_\[31\]\\ has its enable tied to GND (module DSP_Coprocessor) @W:MO111 : | tristate driver \\CoreAPB3_0_APBmslave0_PRDATA_\[30\]\\_t on net \\CoreAPB3_0_APBmslave0_PRDATA_\[30\]\\ has its enable tied to GND (module DSP_Coprocessor) @W:MO111 : | tristate driver \\CoreAPB3_0_APBmslave0_PRDATA_\[29\]\\_t on net \\CoreAPB3_0_APBmslave0_PRDATA_\[29\]\\ has its enable tied to GND (module DSP_Coprocessor) @W:MO111 : | tristate driver \\CoreAPB3_0_APBmslave0_PRDATA_\[28\]\\_t on net \\CoreAPB3_0_APBmslave0_PRDATA_\[28\]\\ has its enable tied to GND (module DSP_Coprocessor) @W:MO111 : | tristate driver \\CoreAPB3_0_APBmslave0_PRDATA_\[27\]\\_t on net \\CoreAPB3_0_APBmslave0_PRDATA_\[27\]\\ has its enable tied to GND (module DSP_Coprocessor) @W:MO111 : | tristate driver \\CoreAPB3_0_APBmslave0_PRDATA_\[26\]\\_t on net \\CoreAPB3_0_APBmslave0_PRDATA_\[26\]\\ has its enable tied to GND (module DSP_Coprocessor) @W:MO111 : | tristate driver \\CoreAPB3_0_APBmslave0_PRDATA_\[25\]\\_t on net \\CoreAPB3_0_APBmslave0_PRDATA_\[25\]\\ has its enable tied to GND (module DSP_Coprocessor) @W:MO111 : | tristate driver \\CoreAPB3_0_APBmslave0_PRDATA_\[24\]\\_t on net \\CoreAPB3_0_APBmslave0_PRDATA_\[24\]\\ has its enable tied to GND (module DSP_Coprocessor) @W:MO111 : | tristate driver \\CoreAPB3_0_APBmslave0_PRDATA_\[23\]\\_t on net \\CoreAPB3_0_APBmslave0_PRDATA_\[23\]\\ has its enable tied to GND (module DSP_Coprocessor) @W:MO111 : | tristate driver \\CoreAPB3_0_APBmslave0_PRDATA_\[22\]\\_t on net \\CoreAPB3_0_APBmslave0_PRDATA_\[22\]\\ has its enable tied to GND (module DSP_Coprocessor) @W:MO111 : | tristate driver \\CoreAPB3_0_APBmslave0_PRDATA_\[21\]\\_t on net \\CoreAPB3_0_APBmslave0_PRDATA_\[21\]\\ has its enable tied to GND (module DSP_Coprocessor) @W:MO111 : | tristate driver \\CoreAPB3_0_APBmslave0_PRDATA_\[20\]\\_t on net \\CoreAPB3_0_APBmslave0_PRDATA_\[20\]\\ has its enable tied to GND (module DSP_Coprocessor) @W:MO111 : | tristate driver \\CoreAPB3_0_APBmslave0_PRDATA_\[19\]\\_t on net \\CoreAPB3_0_APBmslave0_PRDATA_\[19\]\\ has its enable tied to GND (module DSP_Coprocessor) @W:MO111 : | tristate driver \\CoreAPB3_0_APBmslave0_PRDATA_\[18\]\\_t on net \\CoreAPB3_0_APBmslave0_PRDATA_\[18\]\\ has its enable tied to GND (module DSP_Coprocessor) @W:MO111 : | tristate driver \\CoreAPB3_0_APBmslave0_PRDATA_\[17\]\\_t on net \\CoreAPB3_0_APBmslave0_PRDATA_\[17\]\\ has its enable tied to GND (module DSP_Coprocessor) @W:MO111 : | tristate driver \\CoreAPB3_0_APBmslave0_PRDATA_\[16\]\\_t on net \\CoreAPB3_0_APBmslave0_PRDATA_\[16\]\\ has its enable tied to GND (module DSP_Coprocessor) @N:BN116 : actar.vhd(351) | Removing sequential instance actar_0.DFN1_30 of view:smartfusion.DFN1(prim) because there are no references to its outputs @N:BN116 : actar.vhd(272) | Removing sequential instance actar_0.DFN1_Mult_0_inst of view:smartfusion.DFN1(prim) because there are no references to its outputs Available hyper_sources - for debug and ip models None Found @W: : dsp_coprocessor_mss_tmp_mss_ccc_0_mss_ccc.vhd(118) | Net DSP_Coprocessor_MSS_0.MSS_ADLIB_INST_FCLK appears to be a clock source which was not identfied. Assuming default frequency. @W: : dsp_coprocessor_mss_tmp_mss_ccc_0_mss_ccc.vhd(118) | Net Aapb_int_fft_0/PCLK appears to be a clock source which was not identfied. Assuming default frequency. Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 58MB peak: 60MB) @N:MO106 : twiddle.vhd(37) | Found ROM, 'lut_0.t_int1[14:0]', 128 words by 15 bits @N: : primitives.vhd(42) | Found counter in view:work.counter_8_139(translated) inst Q_out[7:0] @N: : primitives.vhd(42) | Found counter in view:work.counter_3_7(translated) inst Q_out[2:0] @N: : primitives.vhd(42) | Found counter in view:work.counter_7_127(translated) inst Q_out[6:0] @N: : primitives.vhd(42) | Found counter in view:work.counter_8_255_ldCount(translated) inst Q_out[7:0] @N:MF176 : | Default generator successful @N: : primitives.vhd(82) | Found counter in view:work.bcounter(translated) inst Q_out[9:0] @N:MF176 : | Default generator successful @N: : primitives.vhd(42) | Found counter in view:work.counter_8_255_outBuf_rA_0(translated) inst Q_out[7:0] @N:MF184 : fftdp.vhd(272) | Found 8 by 8 bit subtractor, 'Hi_w_0_0[7:0]' @N:MF176 : | Default generator successful @N:MF184 : fftdp.vhd(277) | Found 8 by 8 bit subtractor, 'outQ_xhdl2_1_0[7:0]' @N:MF184 : fftdp.vhd(278) | Found 8 by 8 bit subtractor, 'outQ_xhdl2_2_0_0[7:0]' @N:MF176 : | Default generator successful @N:MF176 : | Default generator successful @N:MF176 : | Default generator successful @N:MF238 : fftdp.vhd(104) | Found 9 bit incrementor, 'un5_int_outp[8:0]' Finished factoring (Time elapsed 0h:00m:03s; Memory used current: 60MB peak: 61MB) @N:BN116 : fftdp.vhd(54) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.postBflySw_0.validOut_xhdl3 of view:PrimLib.dff(prim) because there are no references to its outputs @N:BN116 : fftdp.vhd(54) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.postBflySw_0.pipe1 of view:PrimLib.dff(prim) because there are no references to its outputs @N:BN116 : fftsm.vhd(338) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.smTop_0.inBuf_wA_0.fftDone_int of view:PrimLib.dff(prim) because there are no references to its outputs @N:BN116 : fftsm.vhd(338) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.smTop_0.inBuf_wA_0.swCross_int of view:PrimLib.dff(prim) because there are no references to its outputs @W:BN132 : primitives.vhd(127) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.smTop_0.outBufA_0.fedge_0.in_t1, because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.outBuff_0.wEn_r @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTr.t_r[0], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTr.t_r[0] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTr.t_r[1], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTr.t_r[1] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTr.t_r[2], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTr.t_r[2] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTr.t_r[3], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTr.t_r[3] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTr.t_r[4], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTr.t_r[4] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTr.t_r[5], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTr.t_r[5] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTr.t_r[6], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTr.t_r[6] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTr.t_r[7], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTr.t_r[7] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTi.t_r[0], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTi.t_r[0] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTi.t_r[1], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTi.t_r[1] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTi.t_r[2], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTi.t_r[2] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTi.t_r[3], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTi.t_r[3] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTi.t_r[4], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTi.t_r[4] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTi.t_r[5], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTi.t_r[5] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTi.t_r[6], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTi.t_r[6] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTi.t_r[7], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTi.t_r[7] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTr.a_r[0], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTi.a_r[0] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTr.a_r[1], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTi.a_r[1] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTr.a_r[2], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTi.a_r[2] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTr.a_r[3], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTi.a_r[3] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTr.a_r[4], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTi.a_r[4] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTr.a_r[5], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTi.a_r[5] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTr.a_r[6], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTi.a_r[6] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTr.a_r[7], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QrTi.a_r[7] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTr.a_r[0], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTi.a_r[0] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTr.a_r[1], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTi.a_r[1] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTr.a_r[2], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTi.a_r[2] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTr.a_r[3], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTi.a_r[3] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTr.a_r[4], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTi.a_r[4] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTr.a_r[5], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTi.a_r[5] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTr.a_r[6], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTi.a_r[6] @W:BN132 : fftdp.vhd(168) | Removing sequential instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTr.a_r[7], because it is equivalent to instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTi.a_r[7] Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:03s; Memory used current: 62MB peak: 62MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:03s; Memory used current: 62MB peak: 63MB) Starting Early Timing Optimization (Time elapsed 0h:00m:03s; Memory used current: 63MB peak: 63MB) Finished Early Timing Optimization (Time elapsed 0h:00m:03s; Memory used current: 63MB peak: 63MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:04s; Memory used current: 62MB peak: 63MB) Finished preparing to map (Time elapsed 0h:00m:04s; Memory used current: 67MB peak: 68MB) High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes ------------------------------------------------------------------------------------------------------ DSP_Coprocessor_MSS_0.MSS_ADLIB_INST / M2FRESETn 75 : 36 asynchronous set/reset Aapb_int_fft_0.fftTop_inst.smTop_0.smPong_xhdl14 / Q 115 Aapb_int_fft_0.fftTop_inst.smTop_0.twid_wA_0.slowTimer.Q_out[3] / Q 47 Aapb_int_fft_0.fftTop_inst.smTop_0.twid_wA_0.slowTimer.Q_out[4] / Q 45 Aapb_int_fft_0.fftTop_inst.smTop_0.twid_wA_0.slowTimer.Q_out[5] / Q 47 Aapb_int_fft_0.fftTop_inst.smTop_0.twid_wA_0.slowTimer.Q_out[6] / Q 60 Aapb_int_fft_0.fftTop_inst.smTop_0.twid_wA_0.slowTimer.Q_out[7] / Q 41 Aapb_int_fft_0.fftTop_inst.smTop_0.twid_wA_0.slowTimer.Q_out[8] / Q 25 Aapb_int_fft_0.fftTop_inst.smTop_0.inBuf_rA_0.swCross_int / Q 33 Aapb_int_fft_0.fftTop_inst.autoScale_0.upScale_xhdl1 / Q 30 Aapb_int_fft_0.fftTop_inst.bfly_0.swCrossOut_xhdl4 / Q 32 Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTr.t_r[0] / Q 28 Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTi.t_r[0] / Q 28 Aapb_int_fft_0.fftTop_inst.smTop_0.nGrst / Y 52 : 52 asynchronous set/reset ====================================================================================================== @N:FP130 : | Promoting Net Aapb_int_fft_0.un1_fftTop_inst on CLKINT I_113 @N:FP130 : | Promoting Net Aapb_int_fft_0.fftTop_inst.twid_wA_w[3] on CLKINT I_114 @N:FP130 : | Promoting Net Aapb_int_fft_0.fftTop_inst.smTop_0.nGrst on CLKINT I_115 Replicating Sequential Instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTi.t_r[0], fanout 28 segments 2 Replicating Sequential Instance Aapb_int_fft_0.fftTop_inst.bfly_0.am3QiTr.t_r[0], fanout 28 segments 2 Replicating Sequential Instance Aapb_int_fft_0.fftTop_inst.bfly_0.swCrossOut_xhdl4, fanout 32 segments 2 Replicating Sequential Instance Aapb_int_fft_0.fftTop_inst.autoScale_0.upScale_xhdl1, fanout 30 segments 2 Replicating Sequential Instance Aapb_int_fft_0.fftTop_inst.smTop_0.inBuf_rA_0.swCross_int, fanout 33 segments 2 Replicating Sequential Instance Aapb_int_fft_0.fftTop_inst.smTop_0.twid_wA_0.slowTimer.Q_out[8], fanout 25 segments 2 Replicating Sequential Instance Aapb_int_fft_0.fftTop_inst.smTop_0.twid_wA_0.slowTimer.Q_out[7], fanout 41 segments 2 Replicating Sequential Instance Aapb_int_fft_0.fftTop_inst.smTop_0.twid_wA_0.slowTimer.Q_out[5], fanout 47 segments 2 Replicating Sequential Instance Aapb_int_fft_0.fftTop_inst.smTop_0.twid_wA_0.slowTimer.Q_out[4], fanout 45 segments 2 Replicating Sequential Instance Aapb_int_fft_0.fftTop_inst.smTop_0.twid_wA_0.slowTimer.Q_out[3], fanout 47 segments 2 Finished technology mapping (Time elapsed 0h:00m:04s; Memory used current: 65MB peak: 68MB) @A:BN291 : aapb_int_fft.vhd(165) | Boundary register Aapb_int_fft_0.ifoY_valid has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : aapb_int_fft.vhd(131) | Boundary register Aapb_int_fft_0.flag has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:05s; Memory used current: 65MB peak: 68MB) Added 0 Buffers Added 10 Cells via replication Added 10 Sequential Cells via replication Added 0 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:05s; Memory used current: 66MB peak: 68MB) Writing Analyst data base C:\appnotes\AC355\A2F_AC355_DF\Hardware\A2F500\VHDL\DSP_Coprocessor\synthesis\DSP_Coprocessor.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:06s; Memory used current: 66MB peak: 68MB) Writing EDIF Netlist and constraint files E-2010.09A-1 Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:07s; Memory used current: 67MB peak: 68MB) @W:MT246 : dsp_coprocessor_mss.vhd(653) | Blackbox MSSINT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock DSP_Coprocessor_MSS|MSS_ADLIB_INST_EMCCLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:DSP_Coprocessor_MSS_0.MSS_ADLIB_INST_EMCCLK" @W:MT420 : | Found inferred clock DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:DSP_Coprocessor_MSS_0_FAB_CLK" @W:MT420 : | Found inferred clock DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:DSP_Coprocessor_MSS_0.MSS_ADLIB_INST_FCLK" ##### START OF TIMING REPORT #####[ # Timing Report written on Wed Apr 27 17:03:26 2011 # Top view: DSP_Coprocessor Library name: smartfusion Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree ) Requested Frequency: 100.0 MHz Wire load mode: top Wire load model: smartfusion Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: -8.248 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock 100.0 MHz 54.8 MHz 10.000 18.248 -8.248 inferred Inferred_clkgroup_2 DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock 100.0 MHz 130.1 MHz 10.000 7.689 2.311 inferred Inferred_clkgroup_1 System 100.0 MHz 1194.2 MHz 10.000 0.837 9.163 system system_clkgroup =============================================================================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock | 10.000 9.163 | No paths - | No paths - | No paths - DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock | 10.000 2.311 | No paths - | No paths - | No paths - DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock System | 10.000 8.080 | No paths - | No paths - | No paths - DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock | 10.000 -8.248 | No paths - | No paths - | No paths - ======================================================================================================================================================================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Aapb_int_fft_0.fifo64X16_inst.DFN1P0_EMPTY DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock DFN1P0 Q Aapb_int_fft_0_EMPTY_OUT 0.737 -8.248 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_RADDR_1_inst DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock DFN1C0 Q MEM_RADDR_1_net 0.737 -8.142 Aapb_int_fft_0.PENABLE_reg DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock DFN1C0 Q PENABLE_reg 0.737 -7.926 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_FULL DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock DFN1C0 Q DFN1C0_FULL 0.737 -7.488 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_RADDR_0_inst DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock DFN1C0 Q MEM_RADDR_0_net 0.737 -7.325 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_1_inst DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock DFN1C0 Q MEM_WADDR_1_net 0.737 -6.924 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_RADDR_2_inst DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock DFN1C0 Q MEM_RADDR_2_net 0.737 -6.826 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_RADDR_3_inst DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock DFN1C0 Q MEM_RADDR_3_net 0.737 -6.797 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_0_inst DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock DFN1C0 Q MEM_WADDR_0_net 0.737 -6.602 Aapb_int_fft_0.ifoY_valid DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock DFI1P0 QN WEP 0.737 -6.505 ======================================================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock DFN1P0 D AOI1_0_Y 9.461 -8.248 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_AFULL DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock DFI1C0 D OR2_0_Y 9.427 -7.488 Aapb_int_fft_0.fifo64X16_inst.DFN1P0_EMPTY DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock DFN1P0 D EMPTYINT 9.427 -2.254 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_FULL DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock DFN1C0 D FULLINT 9.461 -1.760 Aapb_int_fft_0.fftTop_inst.smTop_0.outBufA_0.outBuf_rA_0.Q_out[1] DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock DFN1E0C0 D N_7 9.461 -1.607 Aapb_int_fft_0.fftTop_inst.smTop_0.outBufA_0.outBuf_rA_0.Q_out[2] DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock DFN1E0C0 D N_9 9.461 -1.607 Aapb_int_fft_0.fftTop_inst.smTop_0.outBufA_0.outBuf_rA_0.Q_out[3] DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock DFN1E0C0 D N_11 9.461 -1.607 Aapb_int_fft_0.fftTop_inst.smTop_0.outBufA_0.outBuf_rA_0.Q_out[4] DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock DFN1E0C0 D N_13 9.461 -1.607 Aapb_int_fft_0.fftTop_inst.smTop_0.outBufA_0.outBuf_rA_0.Q_out[5] DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock DFN1E0C0 D N_15 9.461 -1.607 Aapb_int_fft_0.fftTop_inst.smTop_0.outBufA_0.outBuf_rA_0.Q_out[6] DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock DFN1E0C0 D N_17_i_0 9.461 -1.607 ====================================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 17.709 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -8.248 Number of logic level(s): 13 Starting point: Aapb_int_fft_0.fifo64X16_inst.DFN1P0_EMPTY / Q Ending point: Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY / D The start point is clocked by DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------- Aapb_int_fft_0.fifo64X16_inst.DFN1P0_EMPTY DFN1P0 Q Out 0.737 0.737 - Aapb_int_fft_0_EMPTY_OUT Net - - 1.184 - 4 Aapb_int_fft_0.fifo64X16_inst.NAND2_1 NAND2 A In - 1.921 - Aapb_int_fft_0.fifo64X16_inst.NAND2_1 NAND2 Y Out 0.514 2.435 - NAND2_1_Y Net - - 0.806 - 3 Aapb_int_fft_0.fifo64X16_inst.NAND2_1_RNIH1DP NOR2A A In - 3.241 - Aapb_int_fft_0.fifo64X16_inst.NAND2_1_RNIH1DP NOR2A Y Out 0.516 3.757 - MEMORYRE Net - - 0.386 - 2 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_RADDR_0_inst_RNIHHLS XOR2 B In - 4.143 - Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_RADDR_0_inst_RNIHHLS XOR2 Y Out 0.937 5.080 - RBINNXTSHIFT_0_net Net - - 0.806 - 3 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_0_inst_RNIM1UV_0 OR2A A In - 5.886 - Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_0_inst_RNIM1UV_0 OR2A Y Out 0.537 6.423 - N_1_4 Net - - 0.386 - 2 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_1_inst_RNI6S372_0 AO13 A In - 6.809 - Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_1_inst_RNI6S372_0 AO13 Y Out 1.062 7.871 - OR3_1_Y Net - - 0.386 - 2 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_2_inst_RNII6UQ3_0 AO13 B In - 8.257 - Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_2_inst_RNII6UQ3_0 AO13 Y Out 0.933 9.190 - AO1_3_Y Net - - 0.806 - 3 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_2_inst_RNI74AF8 NOR3A A In - 9.996 - Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_2_inst_RNI74AF8 NOR3A Y Out 0.641 10.638 - N_1_13 Net - - 0.386 - 2 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_4_inst_RNIB6Q3G OA1B A In - 11.024 - Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_4_inst_RNIB6Q3G OA1B Y Out 0.652 11.675 - N_1_8 Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_5_inst_RNITLCOM AX1D B In - 11.997 - Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_5_inst_RNITLCOM AX1D Y Out 0.992 12.989 - RDIFF_6_net Net - - 0.806 - 3 Aapb_int_fft_0.fifo64X16_inst.OR2A_1 OR2A B In - 13.796 - Aapb_int_fft_0.fifo64X16_inst.OR2A_1 OR2A Y Out 0.646 14.442 - OR2A_1_Y Net - - 0.386 - 2 Aapb_int_fft_0.fifo64X16_inst.NOR3A_0 NOR3A A In - 14.828 - Aapb_int_fft_0.fifo64X16_inst.NOR3A_0 NOR3A Y Out 0.641 15.469 - NOR3A_0_Y Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY_RNO_1 NAND3A A In - 15.791 - Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY_RNO_1 NAND3A Y Out 0.751 16.541 - NAND3A_3_Y Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY_RNO AOI1 C In - 16.863 - Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY_RNO AOI1 Y Out 0.525 17.388 - AOI1_0_Y Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY DFN1P0 D In - 17.709 - ================================================================================================================================= Total path delay (propagation time + setup) of 18.248 is 10.624(58.2%) logic and 7.624(41.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 17.603 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -8.142 Number of logic level(s): 13 Starting point: Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_RADDR_1_inst / Q Ending point: Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY / D The start point is clocked by DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------- Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_RADDR_1_inst DFN1C0 Q Out 0.737 0.737 - MEM_RADDR_1_net Net - - 1.526 - 7 Aapb_int_fft_0.fifo64X16_inst.XOR2_3 XOR2 A In - 2.263 - Aapb_int_fft_0.fifo64X16_inst.XOR2_3 XOR2 Y Out 0.488 2.751 - XOR2_3_Y Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.XOR2_3_RNIBRVS NOR3B B In - 3.073 - Aapb_int_fft_0.fifo64X16_inst.XOR2_3_RNIBRVS NOR3B Y Out 0.624 3.697 - G_9_1 Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.AND2_26_RNI61A91 AO1 A In - 4.018 - Aapb_int_fft_0.fifo64X16_inst.AND2_26_RNI61A91 AO1 Y Out 0.520 4.538 - AO1_15_Y Net - - 0.806 - 3 Aapb_int_fft_0.fifo64X16_inst.AND2_11_RNIPGUL1 AO1 B In - 5.344 - Aapb_int_fft_0.fifo64X16_inst.AND2_11_RNIPGUL1 AO1 Y Out 0.567 5.911 - AO1_16_Y Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.XOR2_64_RNIL96T1 XOR2 B In - 6.232 - Aapb_int_fft_0.fifo64X16_inst.XOR2_64_RNIL96T1 XOR2 Y Out 0.937 7.169 - RBINNXTSHIFT_3_net Net - - 1.184 - 4 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_3_inst_RNITPE02 XOR2 A In - 8.352 - Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_3_inst_RNITPE02 XOR2 Y Out 0.408 8.761 - N_1_7 Net - - 0.806 - 3 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_2_inst_RNI74AF8 NOR3A C In - 9.567 - Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_2_inst_RNI74AF8 NOR3A Y Out 0.716 10.283 - N_1_13 Net - - 0.386 - 2 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_4_inst_RNIB6Q3G OA1B A In - 10.669 - Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_4_inst_RNIB6Q3G OA1B Y Out 0.900 11.569 - N_1_8 Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_5_inst_RNITLCOM AX1D B In - 11.891 - Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_5_inst_RNITLCOM AX1D Y Out 0.992 12.883 - RDIFF_6_net Net - - 0.806 - 3 Aapb_int_fft_0.fifo64X16_inst.OR2A_1 OR2A B In - 13.689 - Aapb_int_fft_0.fifo64X16_inst.OR2A_1 OR2A Y Out 0.646 14.336 - OR2A_1_Y Net - - 0.386 - 2 Aapb_int_fft_0.fifo64X16_inst.NOR3A_0 NOR3A A In - 14.722 - Aapb_int_fft_0.fifo64X16_inst.NOR3A_0 NOR3A Y Out 0.641 15.363 - NOR3A_0_Y Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY_RNO_1 NAND3A A In - 15.685 - Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY_RNO_1 NAND3A Y Out 0.751 16.435 - NAND3A_3_Y Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY_RNO AOI1 C In - 16.757 - Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY_RNO AOI1 Y Out 0.525 17.282 - AOI1_0_Y Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY DFN1P0 D In - 17.603 - =============================================================================================================================== Total path delay (propagation time + setup) of 18.142 is 9.991(55.1%) logic and 8.151(44.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 17.547 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -8.086 Number of logic level(s): 13 Starting point: Aapb_int_fft_0.fifo64X16_inst.DFN1P0_EMPTY / Q Ending point: Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY / D The start point is clocked by DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------- Aapb_int_fft_0.fifo64X16_inst.DFN1P0_EMPTY DFN1P0 Q Out 0.737 0.737 - Aapb_int_fft_0_EMPTY_OUT Net - - 1.184 - 4 Aapb_int_fft_0.fifo64X16_inst.NAND2_1 NAND2 A In - 1.921 - Aapb_int_fft_0.fifo64X16_inst.NAND2_1 NAND2 Y Out 0.514 2.435 - NAND2_1_Y Net - - 0.806 - 3 Aapb_int_fft_0.fifo64X16_inst.NAND2_1_RNIH1DP NOR2A A In - 3.241 - Aapb_int_fft_0.fifo64X16_inst.NAND2_1_RNIH1DP NOR2A Y Out 0.516 3.757 - MEMORYRE Net - - 0.386 - 2 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_RADDR_0_inst_RNIHHLS XOR2 B In - 4.143 - Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_RADDR_0_inst_RNIHHLS XOR2 Y Out 0.937 5.080 - RBINNXTSHIFT_0_net Net - - 0.806 - 3 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_0_inst_RNIM1UV_0 OR2A A In - 5.886 - Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_0_inst_RNIM1UV_0 OR2A Y Out 0.537 6.423 - N_1_4 Net - - 0.386 - 2 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_1_inst_RNI6S372_0 AO13 A In - 6.809 - Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_1_inst_RNI6S372_0 AO13 Y Out 1.062 7.871 - OR3_1_Y Net - - 0.386 - 2 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_2_inst_RNII6UQ3_0 AO13 B In - 8.257 - Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_2_inst_RNII6UQ3_0 AO13 Y Out 0.933 9.190 - AO1_3_Y Net - - 0.806 - 3 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_2_inst_RNI74AF8 NOR3A A In - 9.996 - Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_2_inst_RNI74AF8 NOR3A Y Out 0.641 10.638 - N_1_13 Net - - 0.386 - 2 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_4_inst_RNIB6Q3G OA1B A In - 11.024 - Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_4_inst_RNIB6Q3G OA1B Y Out 0.652 11.675 - N_1_8 Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_5_inst_RNITLCOM AX1D B In - 11.997 - Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_5_inst_RNITLCOM AX1D Y Out 0.992 12.989 - RDIFF_6_net Net - - 0.806 - 3 Aapb_int_fft_0.fifo64X16_inst.OR2A_1 OR2A B In - 13.796 - Aapb_int_fft_0.fifo64X16_inst.OR2A_1 OR2A Y Out 0.646 14.442 - OR2A_1_Y Net - - 0.386 - 2 Aapb_int_fft_0.fifo64X16_inst.NAND3A_1 NAND3A C In - 14.828 - Aapb_int_fft_0.fifo64X16_inst.NAND3A_1 NAND3A Y Out 0.607 15.434 - NAND3A_1_Y Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY_RNO_1 NAND3A C In - 15.756 - Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY_RNO_1 NAND3A Y Out 0.624 16.380 - NAND3A_3_Y Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY_RNO AOI1 C In - 16.701 - Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY_RNO AOI1 Y Out 0.525 17.226 - AOI1_0_Y Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY DFN1P0 D In - 17.547 - ================================================================================================================================= Total path delay (propagation time + setup) of 18.086 is 10.462(57.8%) logic and 7.624(42.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 17.483 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -8.022 Number of logic level(s): 13 Starting point: Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_RADDR_1_inst / Q Ending point: Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY / D The start point is clocked by DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------- Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_RADDR_1_inst DFN1C0 Q Out 0.737 0.737 - MEM_RADDR_1_net Net - - 1.526 - 7 Aapb_int_fft_0.fifo64X16_inst.XOR2_3 XOR2 A In - 2.263 - Aapb_int_fft_0.fifo64X16_inst.XOR2_3 XOR2 Y Out 0.488 2.751 - XOR2_3_Y Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.XOR2_3_RNIBRVS NOR3B B In - 3.073 - Aapb_int_fft_0.fifo64X16_inst.XOR2_3_RNIBRVS NOR3B Y Out 0.624 3.697 - G_9_1 Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.AND2_26_RNI61A91 AO1 A In - 4.018 - Aapb_int_fft_0.fifo64X16_inst.AND2_26_RNI61A91 AO1 Y Out 0.520 4.538 - AO1_15_Y Net - - 0.806 - 3 Aapb_int_fft_0.fifo64X16_inst.AND2_42_RNIHQC92 AO1 B In - 5.344 - Aapb_int_fft_0.fifo64X16_inst.AND2_42_RNIHQC92 AO1 Y Out 0.567 5.911 - AO1_29_Y Net - - 0.806 - 3 Aapb_int_fft_0.fifo64X16_inst.XOR2_39_RNIFJKG2 XOR2 B In - 6.717 - Aapb_int_fft_0.fifo64X16_inst.XOR2_39_RNIFJKG2 XOR2 Y Out 0.937 7.654 - RBINNXTSHIFT_4_net Net - - 0.806 - 3 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_4_inst_RNIO3TJ2 XOR2 A In - 8.460 - Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_4_inst_RNIO3TJ2 XOR2 Y Out 0.408 8.868 - N_1_18 Net - - 0.806 - 3 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_2_inst_RNI74AF8 NOR3A B In - 9.675 - Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_2_inst_RNI74AF8 NOR3A Y Out 0.488 10.163 - N_1_13 Net - - 0.386 - 2 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_4_inst_RNIB6Q3G OA1B A In - 10.549 - Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_4_inst_RNIB6Q3G OA1B Y Out 0.900 11.449 - N_1_8 Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_5_inst_RNITLCOM AX1D B In - 11.771 - Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_5_inst_RNITLCOM AX1D Y Out 0.992 12.763 - RDIFF_6_net Net - - 0.806 - 3 Aapb_int_fft_0.fifo64X16_inst.OR2A_1 OR2A B In - 13.569 - Aapb_int_fft_0.fifo64X16_inst.OR2A_1 OR2A Y Out 0.646 14.216 - OR2A_1_Y Net - - 0.386 - 2 Aapb_int_fft_0.fifo64X16_inst.NOR3A_0 NOR3A A In - 14.602 - Aapb_int_fft_0.fifo64X16_inst.NOR3A_0 NOR3A Y Out 0.641 15.243 - NOR3A_0_Y Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY_RNO_1 NAND3A A In - 15.565 - Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY_RNO_1 NAND3A Y Out 0.751 16.315 - NAND3A_3_Y Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY_RNO AOI1 C In - 16.637 - Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY_RNO AOI1 Y Out 0.525 17.162 - AOI1_0_Y Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY DFN1P0 D In - 17.483 - =============================================================================================================================== Total path delay (propagation time + setup) of 18.022 is 9.763(54.2%) logic and 8.259(45.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 17.441 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -7.980 Number of logic level(s): 13 Starting point: Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_RADDR_1_inst / Q Ending point: Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY / D The start point is clocked by DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|DSP_Coprocessor_MSS_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------- Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_RADDR_1_inst DFN1C0 Q Out 0.737 0.737 - MEM_RADDR_1_net Net - - 1.526 - 7 Aapb_int_fft_0.fifo64X16_inst.XOR2_3 XOR2 A In - 2.263 - Aapb_int_fft_0.fifo64X16_inst.XOR2_3 XOR2 Y Out 0.488 2.751 - XOR2_3_Y Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.XOR2_3_RNIBRVS NOR3B B In - 3.073 - Aapb_int_fft_0.fifo64X16_inst.XOR2_3_RNIBRVS NOR3B Y Out 0.624 3.697 - G_9_1 Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.AND2_26_RNI61A91 AO1 A In - 4.018 - Aapb_int_fft_0.fifo64X16_inst.AND2_26_RNI61A91 AO1 Y Out 0.520 4.538 - AO1_15_Y Net - - 0.806 - 3 Aapb_int_fft_0.fifo64X16_inst.AND2_11_RNIPGUL1 AO1 B In - 5.344 - Aapb_int_fft_0.fifo64X16_inst.AND2_11_RNIPGUL1 AO1 Y Out 0.567 5.911 - AO1_16_Y Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.XOR2_64_RNIL96T1 XOR2 B In - 6.232 - Aapb_int_fft_0.fifo64X16_inst.XOR2_64_RNIL96T1 XOR2 Y Out 0.937 7.169 - RBINNXTSHIFT_3_net Net - - 1.184 - 4 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_3_inst_RNITPE02 XOR2 A In - 8.352 - Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_3_inst_RNITPE02 XOR2 Y Out 0.408 8.761 - N_1_7 Net - - 0.806 - 3 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_2_inst_RNI74AF8 NOR3A C In - 9.567 - Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_2_inst_RNI74AF8 NOR3A Y Out 0.716 10.283 - N_1_13 Net - - 0.386 - 2 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_4_inst_RNIB6Q3G OA1B A In - 10.669 - Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_4_inst_RNIB6Q3G OA1B Y Out 0.900 11.569 - N_1_8 Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_5_inst_RNITLCOM AX1D B In - 11.891 - Aapb_int_fft_0.fifo64X16_inst.DFN1C0_MEM_WADDR_5_inst_RNITLCOM AX1D Y Out 0.992 12.883 - RDIFF_6_net Net - - 0.806 - 3 Aapb_int_fft_0.fifo64X16_inst.OR2A_1 OR2A B In - 13.689 - Aapb_int_fft_0.fifo64X16_inst.OR2A_1 OR2A Y Out 0.646 14.336 - OR2A_1_Y Net - - 0.386 - 2 Aapb_int_fft_0.fifo64X16_inst.NAND3A_1 NAND3A C In - 14.722 - Aapb_int_fft_0.fifo64X16_inst.NAND3A_1 NAND3A Y Out 0.607 15.328 - NAND3A_1_Y Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY_RNO_1 NAND3A C In - 15.650 - Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY_RNO_1 NAND3A Y Out 0.624 16.274 - NAND3A_3_Y Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY_RNO AOI1 C In - 16.595 - Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY_RNO AOI1 Y Out 0.525 17.120 - AOI1_0_Y Net - - 0.322 - 1 Aapb_int_fft_0.fifo64X16_inst.DFN1P0_AEMPTY DFN1P0 D In - 17.441 - =============================================================================================================================== Total path delay (propagation time + setup) of 17.980 is 9.829(54.7%) logic and 8.151(45.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- DSP_Coprocessor_MSS_0.MSS_ADLIB_INST DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[11] Z\\CoreAPB3_0_APBmslave0_PADDR_\[11\]\\ 2.679 2.311 DSP_Coprocessor_MSS_0.MSS_ADLIB_INST DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[10] Z\\CoreAPB3_0_APBmslave0_PADDR_\[10\]\\ 2.679 2.347 DSP_Coprocessor_MSS_0.MSS_ADLIB_INST DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[9] Z\\CoreAPB3_0_APBmslave0_PADDR_\[9\]\\ 2.679 2.491 DSP_Coprocessor_MSS_0.MSS_ADLIB_INST DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPSEL DSP_Coprocessor_MSS_0_MSS_MASTER_APB_PSELx 2.490 2.522 DSP_Coprocessor_MSS_0.MSS_ADLIB_INST DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[8] Z\\CoreAPB3_0_APBmslave0_PADDR_\[8\]\\ 2.679 2.538 DSP_Coprocessor_MSS_0.MSS_ADLIB_INST DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPWRITE CoreAPB3_0_APBmslave0_PWRITE 2.456 4.694 ======================================================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ DSP_Coprocessor_MSS_0.MSS_ADLIB_INST DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[0] Z\\DSP_Coprocessor_MSS_0_MSS_MASTER_APB_PRDATA_\[0\]\\ 10.000 2.311 DSP_Coprocessor_MSS_0.MSS_ADLIB_INST DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[1] Z\\DSP_Coprocessor_MSS_0_MSS_MASTER_APB_PRDATA_\[1\]\\ 10.000 2.311 DSP_Coprocessor_MSS_0.MSS_ADLIB_INST DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[2] Z\\DSP_Coprocessor_MSS_0_MSS_MASTER_APB_PRDATA_\[2\]\\ 10.000 2.311 DSP_Coprocessor_MSS_0.MSS_ADLIB_INST DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[3] Z\\DSP_Coprocessor_MSS_0_MSS_MASTER_APB_PRDATA_\[3\]\\ 10.000 2.311 DSP_Coprocessor_MSS_0.MSS_ADLIB_INST DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[4] Z\\DSP_Coprocessor_MSS_0_MSS_MASTER_APB_PRDATA_\[4\]\\ 10.000 2.311 DSP_Coprocessor_MSS_0.MSS_ADLIB_INST DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[5] Z\\DSP_Coprocessor_MSS_0_MSS_MASTER_APB_PRDATA_\[5\]\\ 10.000 2.311 DSP_Coprocessor_MSS_0.MSS_ADLIB_INST DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[6] Z\\DSP_Coprocessor_MSS_0_MSS_MASTER_APB_PRDATA_\[6\]\\ 10.000 2.311 DSP_Coprocessor_MSS_0.MSS_ADLIB_INST DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[7] Z\\DSP_Coprocessor_MSS_0_MSS_MASTER_APB_PRDATA_\[7\]\\ 10.000 2.311 DSP_Coprocessor_MSS_0.MSS_ADLIB_INST DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[8] Z\\DSP_Coprocessor_MSS_0_MSS_MASTER_APB_PRDATA_\[8\]\\ 10.000 2.311 DSP_Coprocessor_MSS_0.MSS_ADLIB_INST DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[9] Z\\DSP_Coprocessor_MSS_0_MSS_MASTER_APB_PRDATA_\[9\]\\ 10.000 2.311 ==================================================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.000 - Propagation time: 7.689 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 2.311 Number of logic level(s): 3 Starting point: DSP_Coprocessor_MSS_0.MSS_ADLIB_INST / MSSPADDR[11] Ending point: DSP_Coprocessor_MSS_0.MSS_ADLIB_INST / MSSPRDATA[0] The start point is clocked by DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK The end point is clocked by DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------- DSP_Coprocessor_MSS_0.MSS_ADLIB_INST MSS_APB MSSPADDR[11] Out 2.679 2.679 - Z\\CoreAPB3_0_APBmslave0_PADDR_\[11\]\\ Net - - 0.322 - 1 CoreAPB3_0.CAPB3iool_2[0] NOR3A C In - 3.000 - CoreAPB3_0.CAPB3iool_2[0] NOR3A Y Out 0.716 3.716 - CAPB3iool_2[0] Net - - 0.322 - 1 CoreAPB3_0.CAPB3iool[0] NOR2B A In - 4.038 - CoreAPB3_0.CAPB3iool[0] NOR2B Y Out 0.488 4.526 - CoreAPB3_0_APBmslave0_PSELx Net - - 2.353 - 20 CoreAPB3_0.CAPB3O1II.PRDATA_0 NOR2B A In - 6.880 - CoreAPB3_0.CAPB3O1II.PRDATA_0 NOR2B Y Out 0.488 7.368 - Z\\DSP_Coprocessor_MSS_0_MSS_MASTER_APB_PRDATA_\[0\]\\ Net - - 0.322 - 1 DSP_Coprocessor_MSS_0.MSS_ADLIB_INST MSS_APB MSSPRDATA[0] In - 7.689 - ================================================================================================================================ Total path delay (propagation time + setup) of 7.689 is 4.372(56.9%) logic and 3.318(43.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------ DSP_Coprocessor_MSS_0.MSSINT_GPI_0 System MSSINT Y MSSINT_GPI_0_Y 0.000 9.163 DSP_Coprocessor_MSS_0.MSSINT_GPI_1 System MSSINT Y MSSINT_GPI_1_Y 0.000 9.163 DSP_Coprocessor_MSS_0.MSSINT_GPI_2 System MSSINT Y MSSINT_GPI_2_Y 0.000 9.163 DSP_Coprocessor_MSS_0.MSSINT_GPI_3 System MSSINT Y MSSINT_GPI_3_Y 0.000 9.163 ============================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------- DSP_Coprocessor_MSS_0.MSS_ADLIB_INST System MSS_APB GPI[0] MSSINT_GPI_0_Y 9.484 9.163 DSP_Coprocessor_MSS_0.MSS_ADLIB_INST System MSS_APB GPI[1] MSSINT_GPI_1_Y 9.484 9.163 DSP_Coprocessor_MSS_0.MSS_ADLIB_INST System MSS_APB GPI[2] MSSINT_GPI_2_Y 9.484 9.163 DSP_Coprocessor_MSS_0.MSS_ADLIB_INST System MSS_APB GPI[3] MSSINT_GPI_3_Y 9.484 9.163 =================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.516 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.484 - Propagation time: 0.322 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 9.163 Number of logic level(s): 0 Starting point: DSP_Coprocessor_MSS_0.MSSINT_GPI_0 / Y Ending point: DSP_Coprocessor_MSS_0.MSS_ADLIB_INST / GPI[0] The start point is clocked by System [rising] The end point is clocked by DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------- DSP_Coprocessor_MSS_0.MSSINT_GPI_0 MSSINT Y Out 0.000 0.000 - MSSINT_GPI_0_Y Net - - 0.322 - 1 DSP_Coprocessor_MSS_0.MSS_ADLIB_INST MSS_APB GPI[0] In - 0.322 - ======================================================================================================== Total path delay (propagation time + setup) of 0.837 is 0.516(61.6%) logic and 0.322(38.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Target Part: A2F500M3G_FBGA256_Std Report for cell DSP_Coprocessor.def_arch Core Cell usage: cell count area count*area AND2 298 1.0 298.0 AND2A 13 1.0 13.0 AND3 45 1.0 45.0 AO1 134 1.0 134.0 AO12 1 1.0 1.0 AO13 12 1.0 12.0 AO14 1 1.0 1.0 AO15 1 1.0 1.0 AO18 7 1.0 7.0 AO1A 4 1.0 4.0 AO1B 17 1.0 17.0 AO1C 19 1.0 19.0 AO1D 3 1.0 3.0 AOI1 24 1.0 24.0 AOI1B 5 1.0 5.0 AOI5 2 1.0 2.0 AX1 3 1.0 3.0 AX1A 4 1.0 4.0 AX1B 6 1.0 6.0 AX1C 18 1.0 18.0 AX1D 16 1.0 16.0 AX1E 4 1.0 4.0 AXO2 1 1.0 1.0 AXO3 1 1.0 1.0 AXO5 1 1.0 1.0 AXO7 1 1.0 1.0 AXOI1 1 1.0 1.0 AXOI2 1 1.0 1.0 AXOI4 3 1.0 3.0 AXOI5 3 1.0 3.0 BUFF 60 1.0 60.0 CLKINT 3 0.0 0.0 GND 63 0.0 0.0 INV 8 1.0 8.0 MAJ3 72 1.0 72.0 MIN3 7 1.0 7.0 MSSINT 4 0.0 0.0 MSS_CCC 1 0.0 0.0 MX2 388 1.0 388.0 MX2A 12 1.0 12.0 MX2B 9 1.0 9.0 MX2C 77 1.0 77.0 NAND2 2 1.0 2.0 NAND3A 3 1.0 3.0 NOR2 63 1.0 63.0 NOR2A 50 1.0 50.0 NOR2B 87 1.0 87.0 NOR3 9 1.0 9.0 NOR3A 17 1.0 17.0 NOR3B 6 1.0 6.0 NOR3C 15 1.0 15.0 OA1 5 1.0 5.0 OA1A 2 1.0 2.0 OA1B 5 1.0 5.0 OA1C 4 1.0 4.0 OAI1 3 1.0 3.0 OR2 9 1.0 9.0 OR2A 30 1.0 30.0 OR2B 22 1.0 22.0 OR3 18 1.0 18.0 OR3A 6 1.0 6.0 OR3B 8 1.0 8.0 OR3C 7 1.0 7.0 RCOSC 1 0.0 0.0 VCC 63 0.0 0.0 XA1 8 1.0 8.0 XA1A 7 1.0 7.0 XA1B 13 1.0 13.0 XA1C 5 1.0 5.0 XNOR2 84 1.0 84.0 XNOR3 6 1.0 6.0 XO1A 1 1.0 1.0 XOR2 445 1.0 445.0 XOR3 72 1.0 72.0 DFI1 1 1.0 1.0 DFI1C0 2 1.0 2.0 DFI1P0 1 1.0 1.0 DFN1 814 1.0 814.0 DFN1C0 59 1.0 59.0 DFN1E0 2 1.0 2.0 DFN1E0C0 40 1.0 40.0 DFN1E1 2 1.0 2.0 DFN1E1C0 19 1.0 19.0 DFN1E1P0 1 1.0 1.0 DFN1P0 6 1.0 6.0 MSS_APB 1 0.0 0.0 RAM512X18 8 0.0 0.0 ----- ---------- TOTAL 3385 3241.0 IO Cell usage: cell count INBUF_MSS 2 OUTBUF_MSS 1 ----- TOTAL 3 Core Cells : 3241 of 11520 (28%) IO Cells : 3 RAM/ROM Usage Summary Block Rams : 8 of 24 (33%) Mapper successful! Process took 0h:00m:11s realtime, 0h:00m:07s cputime # Wed Apr 27 17:03:26 2011 ###########################################################]