m255
K3
13
cModel Technology
Z0 dH:\Projects\Libero_SP2_A2F500\DSP_Coprocessor\Hardware\A2F200\VHDL\DSP_Coprocessor\simulation
Eaapb_int_fft
Z1 w1282640248
Z2 DPx4 ieee 16 std_logic_textio 0 22 8YS?iX`WD1REQG`ZRYQGB2
Z3 DPx3 std 6 textio 0 22 m2KQDRRhmF833<<DjYdL70
Z4 DPx4 ieee 11 numeric_std 0 22 =NSdli^?T5OD8;4F<blj<3
Z5 DPx4 work 14 fft_components 0 22 BFUJVAb6I=XNPN?V;M<4:3
Z6 DPx4 ieee 15 std_logic_arith 0 22 GJbAT?7@hRQU9IQ702DT]2
Z7 DPx4 ieee 18 std_logic_unsigned 0 22 hEMVMlaNCR^<OOoVNV;m90
Z8 DPx4 ieee 14 std_logic_1164 0 22 GH1=`jDDBJ=`LM;:Ak`kf2
Z9 8H:/Projects/Libero_SP2_A2F500/DSP_Coprocessor/Hardware/A2F200/VHDL/DSP_Coprocessor/hdl/Aapb_int_fft.vhd
Z10 FH:/Projects/Libero_SP2_A2F500/DSP_Coprocessor/Hardware/A2F200/VHDL/DSP_Coprocessor/hdl/Aapb_int_fft.vhd
l0
L27
VOAC:M7CbOd0Cf87@X0co61
Z11 OW;C;6.5d;42
31
Z12 o-93 -explicit -work presynth -O0
!s100 V6eElW@GU^ShgiDij3@De1
Abehav
R2
R3
R4
R5
R6
R7
R8
Z13 DEx4 work 12 aapb_int_fft 0 22 OAC:M7CbOd0Cf87@X0co61
l108
L53
V1Af`Ul6[KbSdCT0c5P55E3
R11
31
Z14 Mx7 4 ieee 14 std_logic_1164
Z15 Mx6 4 ieee 18 std_logic_unsigned
Z16 Mx5 4 ieee 15 std_logic_arith
Z17 Mx4 4 work 14 fft_components
Z18 Mx3 4 ieee 11 numeric_std
Z19 Mx2 3 std 6 textio
Z20 Mx1 4 ieee 16 std_logic_textio
R12
!s100 ^EU@XC5GPOMN37zGa^SP90
Eactar
Z21 w1282639323
R8
Z22 8H:/Projects/Libero_SP2_A2F500/DSP_Coprocessor/Hardware/A2F200/VHDL/DSP_Coprocessor/hdl/actar.vhd
Z23 FH:/Projects/Libero_SP2_A2F500/DSP_Coprocessor/Hardware/A2F200/VHDL/DSP_Coprocessor/hdl/actar.vhd
l0
L8
VAoRU_Tb=h69DDC:T_bho12
R11
31
R12
!s100 j7Y?]ASh]gSF[259UkB050
Adef_arch
R8
DEx4 work 5 actar 0 22 AoRU_Tb=h69DDC:T_bho12
l163
L15
VG:@53akHWingzf7D9:TNF2
R11
31
Z24 Mx1 4 ieee 14 std_logic_1164
R12
!s100 Si7KLNE=A4bQCgZ:MU]^93
Eactram
Z25 w1282639277
R8
Z26 8H:/Projects/Libero_SP2_A2F500/DSP_Coprocessor/Hardware/A2F200/VHDL/DSP_Coprocessor/hdl/actram.vhd
Z27 FH:/Projects/Libero_SP2_A2F500/DSP_Coprocessor/Hardware/A2F200/VHDL/DSP_Coprocessor/hdl/actram.vhd
l0
L8
V:NF0Mkoj^zC?Z9M09b5Xd3
R11
31
R12
!s100 zGcgzli@cUgkB6NBkJiRl3
Adef_arch
R8
DEx4 work 6 actram 0 22 :NF0Mkoj^zC?Z9M09b5Xd3
l41
L17
VP5P64H]e=c=F[bI=DDZUD0
R11
31
R24
R12
!s100 b8`OPDmbf^UICU^^E48;G2
Eagen
Z28 w1282624839
R8
Z29 8H:/Projects/Libero_SP2_A2F500/DSP_Coprocessor/Hardware/A2F200/VHDL/DSP_Coprocessor/hdl/fftDp.vhd
Z30 FH:/Projects/Libero_SP2_A2F500/DSP_Coprocessor/Hardware/A2F200/VHDL/DSP_Coprocessor/hdl/fftDp.vhd
l0
L118
V=;J?]dU7iDhZYZ9@O;CV11
R11
31
R12
!s100 i;STBgOfSf9EfNGiTVeK_3
Artl
R8
DEx4 work 4 agen 0 22 =;J?]dU7iDhZYZ9@O;CV11
l156
L130
Vf6]ej9JN7Gkh]km7T^gCc0
R11
31
R24
R12
!s100 d7MzG?2>bZ<0B3Wi?W[gm3
Eautoscale
R28
R2
R3
R4
R5
R8
R29
R30
l0
L592
V5?PKM[1gjgTSR0QF:ZJSc2
R11
31
R12
!s100 >a:>l>PNgB^6Oe]]=eEm`2
Atranslated
R2
R3
R4
R5
R8
DEx4 work 9 autoscale 0 22 5?PKM[1gjgTSR0QF:ZJSc2
l611
L604
VKPfAa14T?`V`_acMfeZoX1
R11
31
Z31 Mx5 4 ieee 14 std_logic_1164
R17
R18
R19
R20
R12
!s100 dH:1==S>Mc4MoUNGZb^;[3
Ebcounter
R28
R4
R8
Z32 8H:/Projects/Libero_SP2_A2F500/DSP_Coprocessor/Hardware/A2F200/VHDL/DSP_Coprocessor/hdl/primitives.vhd
Z33 FH:/Projects/Libero_SP2_A2F500/DSP_Coprocessor/Hardware/A2F200/VHDL/DSP_Coprocessor/hdl/primitives.vhd
l0
L69
VKPj2<eeN3Mado7>UnDC8O1
R11
31
R12
!s100 QLKTmZ`IWA`1Uo9nQih2B3
Atranslated
R4
R8
DEx4 work 8 bcounter 0 22 KPj2<eeN3Mado7>UnDC8O1
l78
L75
Vb3gilg0FTZVYARj[Q;@G23
R11
31
Z34 Mx2 4 ieee 14 std_logic_1164
Z35 Mx1 4 ieee 11 numeric_std
R12
!s100 iN3T1dIW7dl1cd`hMN_:P1
Ebfly2
R28
R6
R7
R8
R29
R30
l0
L183
VKO3SWc2cAfT^bMWK3j21<1
R11
31
R12
!s100 fnHF339d>]RY8U2a8n`LN3
Atranslated
R6
R7
R8
DEx4 work 5 bfly2 0 22 KO3SWc2cAfT^bMWK3j21<1
l234
L199
VjklQLRJ]6V6lG6;omCAic1
R11
31
Z36 Mx3 4 ieee 14 std_logic_1164
Mx2 4 ieee 18 std_logic_unsigned
Z37 Mx1 4 ieee 15 std_logic_arith
R12
!s100 ZmedF@<z;X:hWS:0?6_@^3
Ecounter
R28
R2
R3
R5
R4
R8
R32
R33
l0
L23
VmBU8hP2VcIE:Q5UL868YD3
R11
31
R12
!s100 Dk?gdblGCom6`f>Lb[1Bo2
Atranslated
R2
R3
R5
R4
R8
DEx4 work 7 counter 0 22 mBU8hP2VcIE:Q5UL868YD3
l37
L33
VAFh?ELiT1QBCkzlD;@P>33
R11
31
R31
Mx4 4 ieee 11 numeric_std
Mx3 4 work 14 fft_components
R19
R20
R12
!s100 f=TVWAh_J@eQiGP;T9L5n0
Edsp_coprocessor
Z38 w1282640715
R8
Z39 8H:/Projects/Libero_SP2_A2F500/DSP_Coprocessor/Hardware/A2F200/VHDL/DSP_Coprocessor/component/work/DSP_Coprocessor/DSP_Coprocessor.vhd
Z40 FH:/Projects/Libero_SP2_A2F500/DSP_Coprocessor/Hardware/A2F200/VHDL/DSP_Coprocessor/component/work/DSP_Coprocessor/DSP_Coprocessor.vhd
l0
L10
Vk?Zj@IAbDKd_S62=oUbTW0
R11
31
R12
!s100 hRoMdnXdXf_fXJ9cQf]EU1
Adef_arch
R2
R3
R4
R5
R6
R7
R13
R8
DEx4 work 15 dsp_coprocessor 0 22 k?Zj@IAbDKd_S62=oUbTW0
l339
L19
V6d74H3;Kojg1n`A49j9Fj2
R11
31
R14
R15
R16
R17
R18
R19
R20
R12
!s100 =IX`Sz:I^6zc]<BUfOzQ20
Edsp_coprocessor_mss
Z41 w1282624797
R8
Z42 8H:/Projects/Libero_SP2_A2F500/DSP_Coprocessor/Hardware/A2F200/VHDL/DSP_Coprocessor/component/work/DSP_Coprocessor_MSS/DSP_Coprocessor_MSS.vhd
Z43 FH:/Projects/Libero_SP2_A2F500/DSP_Coprocessor/Hardware/A2F200/VHDL/DSP_Coprocessor/component/work/DSP_Coprocessor_MSS/DSP_Coprocessor_MSS.vhd
l0
L8
VSe5^P0zM2iS2R`4M3gjd`0
R11
31
R12
!s100 JCJFIk5`5>?_5=2>hm`Zj2
Adef_arch
R8
DEx4 work 19 dsp_coprocessor_mss 0 22 Se5^P0zM2iS2R`4M3gjd`0
l350
L31
VnFEF_Je>bQeJPk;XM@zdo3
R11
31
R24
R12
!s100 T^8nHk<nbc?cM?PlC^B@f1
Edsp_coprocessor_mss_tmp_mss_ccc_0_mss_ccc
Z44 w1282624766
R8
Z45 8H:/Projects/Libero_SP2_A2F500/DSP_Coprocessor/Hardware/A2F200/VHDL/DSP_Coprocessor/component/work/DSP_Coprocessor_MSS/MSS_CCC_0/DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd
Z46 FH:/Projects/Libero_SP2_A2F500/DSP_Coprocessor/Hardware/A2F200/VHDL/DSP_Coprocessor/component/work/DSP_Coprocessor_MSS/MSS_CCC_0/DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC.vhd
l0
L8
V^iUmU@dMJ0h^IUT_Q??nf3
R11
31
R12
!s100 29Tm7Rc;3VDE?gQI5IW_c1
Adef_arch
R8
DEx4 work 41 dsp_coprocessor_mss_tmp_mss_ccc_0_mss_ccc 0 22 ^iUmU@dMJ0h^IUT_Q??nf3
l106
L44
VN1no1ShbUe_oS=K]M]Rdo2
R11
31
R24
R12
!s100 UH;MLYke?::<1>8Tol@VN3
Eedgedetect
R28
R8
R32
R33
l0
L100
V:0JW`7FN]SdKF`j<z`=ge0
R11
31
R12
!s100 i:J[Y=kM:ngVkbVDf@V940
Atranslated
R8
DEx4 work 10 edgedetect 0 22 :0JW`7FN]SdKF`j<z`=ge0
l117
L109
V_:1<IbaldCjcQX;89EWeY2
R11
31
R24
R12
!s100 A12B_R8^Y7a3>9o4ef[Ca2
Pfft_components
R2
R3
R4
R8
R28
Z47 8H:/Projects/Libero_SP2_A2F500/DSP_Coprocessor/Hardware/A2F200/VHDL/DSP_Coprocessor/hdl/fft_components.vhd
Z48 FH:/Projects/Libero_SP2_A2F500/DSP_Coprocessor/Hardware/A2F200/VHDL/DSP_Coprocessor/hdl/fft_components.vhd
l0
L22
VBFUJVAb6I=XNPN?V;M<4:3
R11
31
b1
Z49 Mx4 4 ieee 14 std_logic_1164
R18
R19
R20
R12
!s100 G9:NZf=T2]NkKHME;nbJN0
Bbody
DBx4 work 14 fft_components 0 22 BFUJVAb6I=XNPN?V;M<4:3
R2
R3
R4
R8
l0
L74
VK=M_fF_LnE`fA6IXh0EID1
R11
31
R49
R18
R19
R20
R12
nbody
!s100 VSE?5[]GLLc3=K=oFU^NA3
Effttop
R28
R2
R3
R4
R5
R8
Z50 8H:/Projects/Libero_SP2_A2F500/DSP_Coprocessor/Hardware/A2F200/VHDL/DSP_Coprocessor/hdl/fftTop.vhd
Z51 FH:/Projects/Libero_SP2_A2F500/DSP_Coprocessor/Hardware/A2F200/VHDL/DSP_Coprocessor/hdl/fftTop.vhd
l0
L33
VI81gnC=`GdTzFkL@BkC6M2
R11
31
R12
!s100 _IFfHTVZ58na2;=g:FSo91
Atranslated
R2
R3
R4
R5
R8
DEx4 work 6 ffttop 0 22 I81gnC=`GdTzFkL@BkC6M2
l194
L55
VZF02B^XhFX;f>[hBb98T^0
R11
31
R31
R17
R18
R19
R20
R12
!s100 X^>^acj;73a<odEeP9Jf32
Efifo64x16
Z52 w1282625187
R8
Z53 8H:/Projects/Libero_SP2_A2F500/DSP_Coprocessor/Hardware/A2F200/VHDL/DSP_Coprocessor/smartgen/fifo64x16/fifo64x16.vhd
Z54 FH:/Projects/Libero_SP2_A2F500/DSP_Coprocessor/Hardware/A2F200/VHDL/DSP_Coprocessor/smartgen/fifo64x16/fifo64x16.vhd
l0
L8
VeajN0L0]^JD4ZOT0Y0OW?1
R11
31
R12
!s100 ;MJ6g]g3^9^J5CAhicTe;3
Adef_arch
R8
DEx4 work 9 fifo64x16 0 22 eajN0L0]^JD4ZOT0Y0OW?1
l192
L16
VYC`dcZQNlhk@;?nbmdSWW0
R11
31
R24
R12
!s100 hCZ^?lk>gFnl3AFBK<k?d2
Einbuf_ffta
R28
R2
R3
R4
R5
R6
R7
R8
Z55 8H:/Projects/Libero_SP2_A2F500/DSP_Coprocessor/Hardware/A2F200/VHDL/DSP_Coprocessor/hdl/fftSm.vhd
Z56 FH:/Projects/Libero_SP2_A2F500/DSP_Coprocessor/Hardware/A2F200/VHDL/DSP_Coprocessor/hdl/fftSm.vhd
l0
L282
VZl3NfNeT`Rg[j6zbh?0Lh1
R11
31
R12
!s100 lLL5Izgz39Y9dhT3g>dRe2
Atranslated
R2
R3
R4
R5
R6
R7
R8
DEx4 work 10 inbuf_ffta 0 22 Zl3NfNeT`Rg[j6zbh?0Lh1
l312
L294
V>5Md:]kdSC2=?K03kVdWL0
R11
31
R14
R15
R16
R17
R18
R19
R20
R12
!s100 eoRNU0oB`EZelh2?R2G::1
Einbuf_lda
R28
R2
R3
R4
R5
R8
R55
R56
l0
L193
VkFdAYD8^hbH>JB:[hd>Q50
R11
31
R12
!s100 ULmXYU^di;K0ZQi?Q^WG23
Atranslated
R2
R3
R4
R5
R8
DEx4 work 9 inbuf_lda 0 22 kFdAYD8^hbH>JB:[hd>Q50
l224
L209
VbLKa5:4De6T>4z7>VBIKb1
R11
31
R31
R17
R18
R19
R20
R12
!s100 l?:0[c3QoXeFBC0TYYWK=1
Einbuffer
R28
R8
R29
R30
l0
L308
V1DL67GOPWN3T[mGg8nLRb1
R11
31
R12
!s100 D^1o9gKFkabGEW;8VKWH]1
Atranslated
R8
DEx4 work 8 inbuffer 0 22 1DL67GOPWN3T[mGg8nLRb1
l349
L324
VHjFHcA5Fk7D?42D;3BbQE2
R11
31
R24
R12
!s100 5h`Qka=P>IUf=BcBI0GXl1
Ekitrndup
R28
R4
R8
R29
R30
l0
L72
VcD@i]:agBfC=@d:gc^I];3
R11
31
R12
!s100 ;:nP^2Td^dZZJbY<PlcYl1
Artl
R4
R8
DEx4 work 8 kitrndup 0 22 cD@i]:agBfC=@d:gc^I];3
l88
L82
VSTXWc@m<2g[cNXDUAS`7k3
R11
31
R34
R35
R12
!s100 aE^F9l7_98^abiJ6=@lNS3
Eoutbufa
R28
R2
R3
R4
R5
R6
R7
R8
R55
R56
l0
L410
Vdm;?iCa<25`YZ03QTH=KW1
R11
31
R12
!s100 ID6V78OAY7dzK^oXo:CUz3
Atranslated
R2
R3
R4
R5
R6
R7
R8
DEx4 work 7 outbufa 0 22 dm;?iCa<25`YZ03QTH=KW1
l437
L423
VRVDVnh>O9S<TF>TN4L7hN2
R11
31
R14
R15
R16
R17
R18
R19
R20
R12
!s100 K]8S?:=Um>YBkQNAljT>=3
Eoutbuff
R28
R8
R29
R30
l0
L450
V]ka8OmXm2V0J=^V7BT]533
R11
31
R12
!s100 A]KGc>f0e1h_eabJclQbi2
Atranslated
R8
DEx4 work 7 outbuff 0 22 ]ka8OmXm2V0J=^V7BT]533
l482
L461
VjE6d24031eZ<VWnRb:4NE2
R11
31
R24
R12
!s100 :jmUAcFIi=RelhR=]IcXN0
Epipobuffer
R28
R8
R29
R30
l0
L383
V;SzTdj0LkbYg;2lHBndNg3
R11
31
R12
!s100 MMdCXD7c8?A9RBO@<dNO]0
Atranslated
R8
DEx4 work 10 pipobuffer 0 22 ;SzTdj0LkbYg;2lHBndNg3
l417
L394
V44J=Y[<<G8ljRiN?S4oJL3
R11
31
R24
R12
!s100 7a=767fk9j:i<BzdHcLWN0
Erdffttimer
R28
R2
R3
R4
R5
R8
R55
R56
l0
L67
V=@:kD069BT<>5laS[ha6>3
R11
31
R12
!s100 Q=MQA8f2KD[V<Of;FS<=90
Atranslated
R2
R3
R4
R5
R8
DEx4 work 10 rdffttimer 0 22 =@:kD069BT<>5laS[ha6>3
l92
L81
VGon]63LP:aCm:e[nD^PdZ0
R11
31
R31
R17
R18
R19
R20
R12
!s100 S_I;Nl[m[NO3z1[4BKX?`3
Esm_top
R28
R2
R3
R4
R5
R6
R7
R8
R55
R56
l0
L503
V>amc0?T__^5CFgI[G]cK60
R11
31
R12
!s100 5@S19iX8Xk=BSb3ajXXW@1
Atranslated
R2
R3
R4
R5
R6
R7
R8
DEx4 work 6 sm_top 0 22 >amc0?T__^5CFgI[G]cK60
l656
L526
Vo:aK=MBgY7SKNInN_52Bk0
R11
31
R14
R15
R16
R17
R18
R19
R20
R12
!s100 lWYSiRKbKCaFc<E`?;U`m0
Eswitch
R28
R8
R29
R30
l0
L21
VUV0QKiX55mzbo1M4f=JJV2
R11
31
R12
!s100 I1n5nlQ3ES90IDgYZGb8?0
Atranslated
R8
DEx4 work 6 switch 0 22 UV0QKiX55mzbo1M4f=JJV2
l43
L30
VgfSa_AnXLEUDjmE`iL04E2
R11
31
R24
R12
!s100 V0E>jk=SlY:[_[=6;Ygl72
Etestbench
R38
R8
Z57 8H:/Projects/Libero_SP2_A2F500/DSP_Coprocessor/Hardware/A2F200/VHDL/DSP_Coprocessor/component/work/DSP_Coprocessor/testbench.vhd
Z58 FH:/Projects/Libero_SP2_A2F500/DSP_Coprocessor/Hardware/A2F200/VHDL/DSP_Coprocessor/component/work/DSP_Coprocessor/testbench.vhd
l0
L13
VVA0T[oe<cdTd2f]hNHU`g1
!s100 Xz<X21_IcVC6gc==K=k=a0
R11
31
R12
Abehavioral
R8
DEx4 work 9 testbench 0 22 VA0T[oe<cdTd2f]hNHU`g1
l38
L16
VV=Qc`_Sh0;IYZG<A=z`K50
!s100 glNj]k<jjcSoWf;ziNYQ22
R11
31
R24
R12
Etwid_ra
R28
R2
R3
R4
R5
R6
R7
R8
R55
R56
l0
L22
V4KQn7dig<N1h0FKgb8A7V3
R11
31
R12
!s100 PRXZJ4X?RYWWNLF:>hG>G3
Atranslated
R2
R3
R4
R5
R6
R7
R8
DEx4 work 7 twid_ra 0 22 4KQn7dig<N1h0FKgb8A7V3
l40
L31
V?lI0>55e4Gd@YdCn<6bYK1
R11
31
R14
R15
R16
R17
R18
R19
R20
R12
!s100 DSXVnn0e2zeECjzijXKPB3
Etwid_wamod
R28
R2
R3
R4
R5
R6
R7
R8
R55
R56
l0
L356
V93OQX<dc?=KN@71WRA9d>2
R11
31
R12
!s100 IK31^5N;1z<]GhHCD>QR=0
Atranslated
R2
R3
R4
R5
R6
R7
R8
DEx4 work 10 twid_wamod 0 22 93OQX<dc?=KN@71WRA9d>2
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R11
31
R14
R15
R16
R17
R18
R19
R20
R12
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Etwiddle
R28
R2
R3
R4
R5
R8
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31
R12
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R2
R3
R4
R5
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l31
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31
R31
R17
R18
R19
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R28
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R29
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R11
31
R24
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R24
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R2
R3
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R5
R8
R55
R56
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R11
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R2
R3
R4
R5
R8
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L160
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R11
31
R31
R17
R18
R19
R20
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!s100 mSRIb:bQI4RoVK9E?I9bQ1
