Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Thu Dec 08 10:29:06 2011


Design: DSP_Coprocessor
Family: SmartFusion
Die: A2F200M3F
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                8.053
Frequency (MHz):            124.177
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                18.377
Frequency (MHz):            54.416
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        -5.434
External Hold (ns):         4.176
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               DSP_Coprocessor_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[4]
  Delay (ns):                  10.277
  Slack (ns):                  16.947
  Arrival (ns):                14.452
  Required (ns):               31.399
  Setup (ns):                  -2.224
  Minimum Period (ns):         8.053

Path 2
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[2]
  Delay (ns):                  9.993
  Slack (ns):                  17.222
  Arrival (ns):                14.168
  Required (ns):               31.390
  Setup (ns):                  -2.215
  Minimum Period (ns):         7.778

Path 3
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0]
  Delay (ns):                  9.920
  Slack (ns):                  17.295
  Arrival (ns):                14.095
  Required (ns):               31.390
  Setup (ns):                  -2.215
  Minimum Period (ns):         7.705

Path 4
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  8.275
  Slack (ns):                  17.373
  Arrival (ns):                12.450
  Required (ns):               29.823
  Setup (ns):                  -0.648
  Minimum Period (ns):         7.627

Path 5
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[7]
  Delay (ns):                  9.694
  Slack (ns):                  17.533
  Arrival (ns):                13.869
  Required (ns):               31.402
  Setup (ns):                  -2.227
  Minimum Period (ns):         7.467


Expanded Path 1
  From: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[4]
  data required time                             31.399
  data arrival time                          -   14.452
  slack                                          16.947
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.175          Clock generation
  4.175
               +     3.673          cell: ADLIB:MSS_APB_IP
  7.848                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPADDR[10] (f)
               +     0.155          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPADDR[10]INT_NET
  8.003                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_33:PIN2INT (f)
               +     0.094          cell: ADLIB:MSS_IF
  8.097                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_33:PIN2 (f)
               +     0.400          net: _CoreAPB3_0_APBmslave0_PADDR_[10]_
  8.497                        CoreAPB3_0/CAPB3iool_1_0[0]:C (f)
               +     0.683          cell: ADLIB:OR3A
  9.180                        CoreAPB3_0/CAPB3iool_1_0[0]:Y (f)
               +     0.294          net: CoreAPB3_0/CAPB3iool_1_0[0]
  9.474                        CoreAPB3_0/CAPB3iool[0]:A (f)
               +     0.489          cell: ADLIB:NOR2
  9.963                        CoreAPB3_0/CAPB3iool[0]:Y (r)
               +     2.129          net: CoreAPB3_0_APBmslave0_PSELx
  12.092                       CoreAPB3_0/CAPB3O1II/PRDATA_4:A (r)
               +     0.445          cell: ADLIB:NOR2B
  12.537                       CoreAPB3_0/CAPB3O1II/PRDATA_4:Y (r)
               +     1.254          net: _DSP_Coprocessor_MSS_0_MSS_MASTER_APB_PRDATA_[4]_
  13.791                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_38:PIN5 (r)
               +     0.216          cell: ADLIB:MSS_IF
  14.007                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_38:PIN5INT (r)
               +     0.445          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPRDATA[4]INT_NET
  14.452                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[4] (r)
                                    
  14.452                       data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_fabric_interface_clock
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.175          Clock generation
  29.175
               -    -2.224          Library setup time: ADLIB:MSS_APB_IP
  31.399                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[4]
                                    
  31.399                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_fabric_interface_clock

Path 1
  From:                        Aapb_int_fft_0/PREADY0:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  4.156
  Slack (ns):                  19.764
  Arrival (ns):                10.059
  Required (ns):               29.823
  Setup (ns):                  -0.648

Path 2
  From:                        Aapb_int_fft_0/PREADY1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  4.129
  Slack (ns):                  19.791
  Arrival (ns):                10.032
  Required (ns):               29.823
  Setup (ns):                  -0.648

Path 3
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  4.053
  Slack (ns):                  19.881
  Arrival (ns):                9.942
  Required (ns):               29.823
  Setup (ns):                  -0.648

Path 4
  From:                        Aapb_int_fft_0/EMPTY_OUT_REG/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  4.032
  Slack (ns):                  20.000
  Arrival (ns):                9.886
  Required (ns):               29.886
  Setup (ns):                  -0.711

Path 5
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_0_inst/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0]
  Delay (ns):                  5.441
  Slack (ns):                  20.039
  Arrival (ns):                11.373
  Required (ns):               31.412
  Setup (ns):                  -2.237


Expanded Path 1
  From: Aapb_int_fft_0/PREADY0:CLK
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  data required time                             29.823
  data arrival time                          -   10.059
  slack                                          19.764
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.654          net: FAB_CLK
  5.903                        Aapb_int_fft_0/PREADY0:CLK (r)
               +     0.671          cell: ADLIB:DFN1P0
  6.574                        Aapb_int_fft_0/PREADY0:Q (f)
               +     0.369          net: Aapb_int_fft_0/PREADY0
  6.943                        Aapb_int_fft_0/PREADY1_RNIA7U4:B (f)
               +     0.584          cell: ADLIB:NOR3B
  7.527                        Aapb_int_fft_0/PREADY1_RNIA7U4:Y (f)
               +     0.339          net: Aapb_int_fft_0/un5_pready
  7.866                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int_RNIN76C:A (f)
               +     0.527          cell: ADLIB:MX2C
  8.393                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int_RNIN76C:Y (r)
               +     0.339          net: CoreAPB3_0_APBmslave0_PREADY
  8.732                        CoreAPB3_0/CAPB3O1II/PREADY:B (r)
               +     0.538          cell: ADLIB:OR2B
  9.270                        CoreAPB3_0/CAPB3O1II/PREADY:Y (f)
               +     0.272          net: DSP_Coprocessor_MSS_0_MSS_MASTER_APB_PREADY
  9.542                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_36:PIN5 (f)
               +     0.095          cell: ADLIB:MSS_IF
  9.637                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_36:PIN5INT (f)
               +     0.422          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPREADYINT_NET
  10.059                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY (f)
                                    
  10.059                       data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_fabric_interface_clock
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.175          Clock generation
  29.175
               -    -0.648          Library setup time: ADLIB:MSS_APB_IP
  29.823                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
                                    
  29.823                       data required time


END SET mss_ccc_gla1 to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_pclk1

Path 1
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[2]
  Delay (ns):                  3.636
  Slack (ns):                  19.864
  Arrival (ns):                9.499
  Required (ns):               29.363
  Setup (ns):                  -0.188

Path 2
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1P0_EMPTY:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[3]
  Delay (ns):                  3.075
  Slack (ns):                  20.509
  Arrival (ns):                8.949
  Required (ns):               29.458
  Setup (ns):                  -0.283

Path 3
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[0]
  Delay (ns):                  2.025
  Slack (ns):                  21.322
  Arrival (ns):                7.914
  Required (ns):               29.236
  Setup (ns):                  -0.061

Path 4
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn_int:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[1]
  Delay (ns):                  1.016
  Slack (ns):                  22.318
  Arrival (ns):                6.925
  Required (ns):               29.243
  Setup (ns):                  -0.068


Expanded Path 1
  From: Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:CLK
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[2]
  data required time                             29.363
  data arrival time                          -   9.499
  slack                                          19.864
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.614          net: FAB_CLK
  5.863                        Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:CLK (r)
               +     0.528          cell: ADLIB:DFN1P0
  6.391                        Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:Q (r)
               +     2.892          net: Aapb_int_fft_0_AEMPTY_OUT
  9.283                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_22:PIN5 (r)
               +     0.216          cell: ADLIB:MSS_IF
  9.499                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_22:PIN5INT (r)
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/GPI[2]INT_NET
  9.499                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[2] (r)
                                    
  9.499                        data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_pclk1
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     4.175          Clock generation
  29.175
               -    -0.188          Library setup time: ADLIB:MSS_APB_IP
  29.363                       DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[2]
                                    
  29.363                       data required time


END SET mss_ccc_gla1 to mss_pclk1

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        Aapb_int_fft_0/PENABLE_reg:CLK
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D
  Delay (ns):                  17.864
  Slack (ns):                  6.623
  Arrival (ns):                23.718
  Required (ns):               30.341
  Setup (ns):                  0.522
  Minimum Period (ns):         18.377

Path 2
  From:                        Aapb_int_fft_0/ifoY_valid:CLK
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1C0_AFULL:D
  Delay (ns):                  17.150
  Slack (ns):                  7.366
  Arrival (ns):                23.007
  Required (ns):               30.373
  Setup (ns):                  0.490
  Minimum Period (ns):         17.634

Path 3
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1C0_FULL:CLK
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1C0_AFULL:D
  Delay (ns):                  16.785
  Slack (ns):                  7.731
  Arrival (ns):                22.642
  Required (ns):               30.373
  Setup (ns):                  0.490
  Minimum Period (ns):         17.269

Path 4
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1C0_MEM_WADDR_0_inst:CLK
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1C0_AFULL:D
  Delay (ns):                  16.140
  Slack (ns):                  8.376
  Arrival (ns):                21.997
  Required (ns):               30.373
  Setup (ns):                  0.490
  Minimum Period (ns):         16.624

Path 5
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1C0_MEM_WADDR_1_inst:CLK
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1C0_AFULL:D
  Delay (ns):                  15.252
  Slack (ns):                  9.264
  Arrival (ns):                21.109
  Required (ns):               30.373
  Setup (ns):                  0.490
  Minimum Period (ns):         15.736


Expanded Path 1
  From: Aapb_int_fft_0/PENABLE_reg:CLK
  To: Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D
  data required time                             30.341
  data arrival time                          -   23.718
  slack                                          6.623
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.605          net: FAB_CLK
  5.854                        Aapb_int_fft_0/PENABLE_reg:CLK (r)
               +     0.528          cell: ADLIB:DFN1C0
  6.382                        Aapb_int_fft_0/PENABLE_reg:Q (r)
               +     0.294          net: Aapb_int_fft_0/PENABLE_reg
  6.676                        Aapb_int_fft_0/PENABLE_reg_RNICCCC:C (r)
               +     0.327          cell: ADLIB:NOR3B
  7.003                        Aapb_int_fft_0/PENABLE_reg_RNICCCC:Y (f)
               +     0.296          net: Aapb_int_fft_0/un3_fifo_rd_en_m2_e_3
  7.299                        Aapb_int_fft_0/PENABLE_reg_RNI4HTI:B (f)
               +     0.552          cell: ADLIB:NOR3B
  7.851                        Aapb_int_fft_0/PENABLE_reg_RNI4HTI:Y (f)
               +     2.258          net: Aapb_int_fft_0/REP
  10.109                       Aapb_int_fft_0/fifo64X16_inst/AND2_MEMORYRE:B (f)
               +     0.571          cell: ADLIB:AND2A
  10.680                       Aapb_int_fft_0/fifo64X16_inst/AND2_MEMORYRE:Y (f)
               +     0.907          net: Aapb_int_fft_0/fifo64X16_inst/MEMORYRE
  11.587                       Aapb_int_fft_0/fifo64X16_inst/AND2_55:B (f)
               +     0.574          cell: ADLIB:AND2
  12.161                       Aapb_int_fft_0/fifo64X16_inst/AND2_55:Y (f)
               +     0.369          net: Aapb_int_fft_0/fifo64X16_inst/AND2_55_Y
  12.530                       Aapb_int_fft_0/fifo64X16_inst/AO1_15:B (f)
               +     0.574          cell: ADLIB:NOR2B
  13.104                       Aapb_int_fft_0/fifo64X16_inst/AO1_15:Y (f)
               +     0.437          net: Aapb_int_fft_0/fifo64X16_inst/AO1_15_Y
  13.541                       Aapb_int_fft_0/fifo64X16_inst/AO1_29:C (f)
               +     0.620          cell: ADLIB:NOR3C
  14.161                       Aapb_int_fft_0/fifo64X16_inst/AO1_29:Y (f)
               +     0.993          net: Aapb_int_fft_0/fifo64X16_inst/AO1_29_Y
  15.154                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RBINNXTSHIFT_4_inst:B (f)
               +     0.853          cell: ADLIB:XOR2
  16.007                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RBINNXTSHIFT_4_inst:Y (r)
               +     0.309          net: Aapb_int_fft_0/fifo64X16_inst/RBINNXTSHIFT_4_net
  16.316                       Aapb_int_fft_0/fifo64X16_inst/INV_13:A (r)
               +     0.331          cell: ADLIB:INV
  16.647                       Aapb_int_fft_0/fifo64X16_inst/INV_13:Y (f)
               +     0.366          net: Aapb_int_fft_0/fifo64X16_inst/INV_13_Y
  17.013                       Aapb_int_fft_0/fifo64X16_inst/XOR2_38:B (f)
               +     0.853          cell: ADLIB:XOR2
  17.866                       Aapb_int_fft_0/fifo64X16_inst/XOR2_38:Y (r)
               +     0.366          net: Aapb_int_fft_0/fifo64X16_inst/XOR2_38_Y
  18.232                       Aapb_int_fft_0/fifo64X16_inst/AO1_7:A (r)
               +     0.473          cell: ADLIB:AO1
  18.705                       Aapb_int_fft_0/fifo64X16_inst/AO1_7:Y (r)
               +     0.314          net: Aapb_int_fft_0/fifo64X16_inst/AO1_7_Y
  19.019                       Aapb_int_fft_0/fifo64X16_inst/AO1_10:C (r)
               +     0.596          cell: ADLIB:AO1
  19.615                       Aapb_int_fft_0/fifo64X16_inst/AO1_10:Y (r)
               +     0.384          net: Aapb_int_fft_0/fifo64X16_inst/AO1_10_Y
  19.999                       Aapb_int_fft_0/fifo64X16_inst/AO1_1:B (r)
               +     0.516          cell: ADLIB:AO1
  20.515                       Aapb_int_fft_0/fifo64X16_inst/AO1_1:Y (r)
               +     0.306          net: Aapb_int_fft_0/fifo64X16_inst/AO1_1_Y
  20.821                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RDIFF_6_inst:C (r)
               +     0.897          cell: ADLIB:XNOR3
  21.718                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RDIFF_6_inst:Y (f)
               +     0.353          net: Aapb_int_fft_0/fifo64X16_inst/RDIFF_6_net
  22.071                       Aapb_int_fft_0/fifo64X16_inst/AND3_0:A (f)
               +     0.478          cell: ADLIB:AND3C
  22.549                       Aapb_int_fft_0/fifo64X16_inst/AND3_0:Y (r)
               +     0.306          net: Aapb_int_fft_0/fifo64X16_inst/AND3_0_Y
  22.855                       Aapb_int_fft_0/fifo64X16_inst/AOI1_0:A (r)
               +     0.552          cell: ADLIB:AOI1
  23.407                       Aapb_int_fft_0/fifo64X16_inst/AOI1_0:Y (f)
               +     0.311          net: Aapb_int_fft_0/fifo64X16_inst/AOI1_0_Y
  23.718                       Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D (f)
                                    
  23.718                       data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_ccc_gla1
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  30.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.614          net: FAB_CLK
  30.863                       Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:CLK (r)
               -     0.522          Library setup time: ADLIB:DFN1P0
  30.341                       Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D
                                    
  30.341                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/Q_out[3]:CLR
  Delay (ns):                  4.484
  Slack (ns):                  20.205
  Arrival (ns):                10.392
  Required (ns):               30.597
  Recovery (ns):               0.271
  Minimum Period (ns):         4.795
  Skew (ns):                   0.040

Path 2
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/Q_out[5]:CLR
  Delay (ns):                  4.484
  Slack (ns):                  20.205
  Arrival (ns):                10.392
  Required (ns):               30.597
  Recovery (ns):               0.271
  Minimum Period (ns):         4.795
  Skew (ns):                   0.040

Path 3
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/Q_out[4]:CLR
  Delay (ns):                  4.486
  Slack (ns):                  20.207
  Arrival (ns):                10.394
  Required (ns):               30.601
  Recovery (ns):               0.271
  Minimum Period (ns):         4.793
  Skew (ns):                   0.036

Path 4
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int:CLR
  Delay (ns):                  4.486
  Slack (ns):                  20.224
  Arrival (ns):                10.394
  Required (ns):               30.618
  Recovery (ns):               0.271
  Minimum Period (ns):         4.776
  Skew (ns):                   0.019

Path 5
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rA_0/Q_out[6]:CLR
  Delay (ns):                  4.429
  Slack (ns):                  20.225
  Arrival (ns):                10.337
  Required (ns):               30.562
  Recovery (ns):               0.271
  Minimum Period (ns):         4.775
  Skew (ns):                   0.075


Expanded Path 1
  From: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To: Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/Q_out[3]:CLR
  data required time                             30.597
  data arrival time                          -   10.392
  slack                                          20.205
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.659          net: FAB_CLK
  5.908                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK (r)
               +     0.671          cell: ADLIB:DFN1P0
  6.579                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:Q (f)
               +     1.621          net: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/initRst
  8.200                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8:B (f)
               +     0.445          cell: ADLIB:NOR2A
  8.645                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8:Y (r)
               +     0.296          net: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8
  8.941                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8_0/U_CLKSRC:A (r)
               +     0.829          cell: ADLIB:CLKSRC
  9.770                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8_0/U_CLKSRC:Y (r)
               +     0.622          net: Aapb_int_fft_0/fftTop_inst/smTop_0/nGrst
  10.392                       Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/Q_out[3]:CLR (r)
                                    
  10.392                       data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_ccc_gla1
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  30.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.619          net: FAB_CLK
  30.868                       Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/Q_out[3]:CLK (r)
               -     0.271          Library recovery time: ADLIB:DFN1C0
  30.597                       Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/Q_out[3]:CLR
                                    
  30.597                       data required time


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_gla1

Path 1
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D
  Delay (ns):                  23.257
  Slack (ns):                  2.909
  Arrival (ns):                27.432
  Required (ns):               30.341
  Setup (ns):                  0.522

Path 2
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1P0_EMPTY:D
  Delay (ns):                  19.113
  Slack (ns):                  7.096
  Arrival (ns):                23.288
  Required (ns):               30.384
  Setup (ns):                  0.490

Path 3
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1C0_MEM_RADDR_4_inst:D
  Delay (ns):                  16.417
  Slack (ns):                  9.769
  Arrival (ns):                20.592
  Required (ns):               30.361
  Setup (ns):                  0.490

Path 4
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1C0_MEM_RADDR_6_inst:D
  Delay (ns):                  15.970
  Slack (ns):                  10.228
  Arrival (ns):                20.145
  Required (ns):               30.373
  Setup (ns):                  0.490

Path 5
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1C0_MEM_RADDR_5_inst:D
  Delay (ns):                  15.603
  Slack (ns):                  10.583
  Arrival (ns):                19.778
  Required (ns):               30.361
  Setup (ns):                  0.490


Expanded Path 1
  From: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To: Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D
  data required time                             30.341
  data arrival time                          -   27.432
  slack                                          2.909
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.175          Clock generation
  4.175
               +     3.806          cell: ADLIB:MSS_APB_IP
  7.981                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPADDR[10] (r)
               +     0.122          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPADDR[10]INT_NET
  8.103                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_33:PIN2INT (r)
               +     0.095          cell: ADLIB:MSS_IF
  8.198                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_33:PIN2 (r)
               +     0.428          net: _CoreAPB3_0_APBmslave0_PADDR_[10]_
  8.626                        Aapb_int_fft_0/un3_fifo_rd_en_m2_e_1:B (r)
               +     0.468          cell: ADLIB:NOR2
  9.094                        Aapb_int_fft_0/un3_fifo_rd_en_m2_e_1:Y (f)
               +     1.071          net: Aapb_int_fft_0/un3_fifo_rd_en_m2_e_1
  10.165                       Aapb_int_fft_0/PENABLE_reg_RNICCCC:B (f)
               +     0.552          cell: ADLIB:NOR3B
  10.717                       Aapb_int_fft_0/PENABLE_reg_RNICCCC:Y (f)
               +     0.296          net: Aapb_int_fft_0/un3_fifo_rd_en_m2_e_3
  11.013                       Aapb_int_fft_0/PENABLE_reg_RNI4HTI:B (f)
               +     0.552          cell: ADLIB:NOR3B
  11.565                       Aapb_int_fft_0/PENABLE_reg_RNI4HTI:Y (f)
               +     2.258          net: Aapb_int_fft_0/REP
  13.823                       Aapb_int_fft_0/fifo64X16_inst/AND2_MEMORYRE:B (f)
               +     0.571          cell: ADLIB:AND2A
  14.394                       Aapb_int_fft_0/fifo64X16_inst/AND2_MEMORYRE:Y (f)
               +     0.907          net: Aapb_int_fft_0/fifo64X16_inst/MEMORYRE
  15.301                       Aapb_int_fft_0/fifo64X16_inst/AND2_55:B (f)
               +     0.574          cell: ADLIB:AND2
  15.875                       Aapb_int_fft_0/fifo64X16_inst/AND2_55:Y (f)
               +     0.369          net: Aapb_int_fft_0/fifo64X16_inst/AND2_55_Y
  16.244                       Aapb_int_fft_0/fifo64X16_inst/AO1_15:B (f)
               +     0.574          cell: ADLIB:NOR2B
  16.818                       Aapb_int_fft_0/fifo64X16_inst/AO1_15:Y (f)
               +     0.437          net: Aapb_int_fft_0/fifo64X16_inst/AO1_15_Y
  17.255                       Aapb_int_fft_0/fifo64X16_inst/AO1_29:C (f)
               +     0.620          cell: ADLIB:NOR3C
  17.875                       Aapb_int_fft_0/fifo64X16_inst/AO1_29:Y (f)
               +     0.993          net: Aapb_int_fft_0/fifo64X16_inst/AO1_29_Y
  18.868                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RBINNXTSHIFT_4_inst:B (f)
               +     0.853          cell: ADLIB:XOR2
  19.721                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RBINNXTSHIFT_4_inst:Y (r)
               +     0.309          net: Aapb_int_fft_0/fifo64X16_inst/RBINNXTSHIFT_4_net
  20.030                       Aapb_int_fft_0/fifo64X16_inst/INV_13:A (r)
               +     0.331          cell: ADLIB:INV
  20.361                       Aapb_int_fft_0/fifo64X16_inst/INV_13:Y (f)
               +     0.366          net: Aapb_int_fft_0/fifo64X16_inst/INV_13_Y
  20.727                       Aapb_int_fft_0/fifo64X16_inst/XOR2_38:B (f)
               +     0.853          cell: ADLIB:XOR2
  21.580                       Aapb_int_fft_0/fifo64X16_inst/XOR2_38:Y (r)
               +     0.366          net: Aapb_int_fft_0/fifo64X16_inst/XOR2_38_Y
  21.946                       Aapb_int_fft_0/fifo64X16_inst/AO1_7:A (r)
               +     0.473          cell: ADLIB:AO1
  22.419                       Aapb_int_fft_0/fifo64X16_inst/AO1_7:Y (r)
               +     0.314          net: Aapb_int_fft_0/fifo64X16_inst/AO1_7_Y
  22.733                       Aapb_int_fft_0/fifo64X16_inst/AO1_10:C (r)
               +     0.596          cell: ADLIB:AO1
  23.329                       Aapb_int_fft_0/fifo64X16_inst/AO1_10:Y (r)
               +     0.384          net: Aapb_int_fft_0/fifo64X16_inst/AO1_10_Y
  23.713                       Aapb_int_fft_0/fifo64X16_inst/AO1_1:B (r)
               +     0.516          cell: ADLIB:AO1
  24.229                       Aapb_int_fft_0/fifo64X16_inst/AO1_1:Y (r)
               +     0.306          net: Aapb_int_fft_0/fifo64X16_inst/AO1_1_Y
  24.535                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RDIFF_6_inst:C (r)
               +     0.897          cell: ADLIB:XNOR3
  25.432                       Aapb_int_fft_0/fifo64X16_inst/XOR2_RDIFF_6_inst:Y (f)
               +     0.353          net: Aapb_int_fft_0/fifo64X16_inst/RDIFF_6_net
  25.785                       Aapb_int_fft_0/fifo64X16_inst/AND3_0:A (f)
               +     0.478          cell: ADLIB:AND3C
  26.263                       Aapb_int_fft_0/fifo64X16_inst/AND3_0:Y (r)
               +     0.306          net: Aapb_int_fft_0/fifo64X16_inst/AND3_0_Y
  26.569                       Aapb_int_fft_0/fifo64X16_inst/AOI1_0:A (r)
               +     0.552          cell: ADLIB:AOI1
  27.121                       Aapb_int_fft_0/fifo64X16_inst/AOI1_0:Y (f)
               +     0.311          net: Aapb_int_fft_0/fifo64X16_inst/AOI1_0_Y
  27.432                       Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D (f)
                                    
  27.432                       data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_ccc_gla1
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  30.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.614          net: FAB_CLK
  30.863                       Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:CLK (r)
               -     0.522          Library setup time: ADLIB:DFN1P0
  30.341                       Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:D
                                    
  30.341                       data required time


END SET mss_fabric_interface_clock to mss_ccc_gla1

----------------------------------------------------

SET mss_ccc_gla0 to mss_ccc_gla1

Path 1
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/Q_out[3]:CLR
  Delay (ns):                  9.175
  Slack (ns):                  17.247
  Arrival (ns):                13.350
  Required (ns):               30.597
  Setup (ns):

Path 2
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/Q_out[5]:CLR
  Delay (ns):                  9.175
  Slack (ns):                  17.247
  Arrival (ns):                13.350
  Required (ns):               30.597
  Setup (ns):

Path 3
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/Q_out[4]:CLR
  Delay (ns):                  9.177
  Slack (ns):                  17.249
  Arrival (ns):                13.352
  Required (ns):               30.601
  Setup (ns):

Path 4
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int:CLR
  Delay (ns):                  9.177
  Slack (ns):                  17.266
  Arrival (ns):                13.352
  Required (ns):               30.618
  Setup (ns):

Path 5
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rA_0/Q_out[6]:CLR
  Delay (ns):                  9.120
  Slack (ns):                  17.267
  Arrival (ns):                13.295
  Required (ns):               30.562
  Setup (ns):


Expanded Path 1
  From: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To: Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/Q_out[3]:CLR
  data required time                             30.597
  data arrival time                          -   13.350
  slack                                          17.247
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  3.545
               +     0.630          net: DSP_Coprocessor_MSS_0/GLA0
  4.175                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     3.632          cell: ADLIB:MSS_APB_IP
  7.807                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:M2FRESETn (r)
               +     0.122          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/M2FRESETnINT_NET
  7.929                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_46:PIN2INT (r)
               +     0.095          cell: ADLIB:MSS_IF
  8.024                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_46:PIN2 (r)
               +     3.109          net: DSP_Coprocessor_MSS_0_M2F_RESET_N
  11.133                       Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8:A (r)
               +     0.470          cell: ADLIB:NOR2A
  11.603                       Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8:Y (r)
               +     0.296          net: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8
  11.899                       Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8_0/U_CLKSRC:A (r)
               +     0.829          cell: ADLIB:CLKSRC
  12.728                       Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8_0/U_CLKSRC:Y (r)
               +     0.622          net: Aapb_int_fft_0/fftTop_inst/smTop_0/nGrst
  13.350                       Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/Q_out[3]:CLR (r)
                                    
  13.350                       data arrival time
  ________________________________________________________
  Data required time calculation
  25.000                       mss_ccc_gla1
               +     0.000          Clock source
  25.000                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  30.249
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  30.249                       DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.619          net: FAB_CLK
  30.868                       Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/Q_out[3]:CLK (r)
               -     0.271          Library recovery time: ADLIB:DFN1C0
  30.597                       Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/wA_timer/Q_out[3]:CLR
                                    
  30.597                       data required time


END SET mss_ccc_gla0 to mss_ccc_gla1

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.937
  Slack (ns):
  Arrival (ns):                0.937
  Required (ns):
  Setup (ns):                  -2.196
  External Setup (ns):         -5.434


Expanded Path 1
  From: MSS_RESET_N
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.937
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        DSP_Coprocessor_MSS_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.937          cell: ADLIB:IOPAD_IN
  0.937                        DSP_Coprocessor_MSS_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_RESET_0_MSS_RESET_N_Y
  0.937                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.937                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  N/C
               +     0.630          net: DSP_Coprocessor_MSS_0/GLA0
  N/C                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -2.196          Library setup time: ADLIB:MSS_APB_IP
  N/C                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain DSP_Coprocessor_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

