Timing Report Min Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Thu Dec 08 10:31:19 2011


Design: DSP_Coprocessor
Family: SmartFusion
Die: A2F200M3F
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                8.122
Frequency (MHz):            123.122
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                18.189
Frequency (MHz):            54.978
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        -5.434
External Hold (ns):         4.176
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               DSP_Coprocessor_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0]
  Delay (ns):                  3.572
  Slack (ns):                  2.195
  Arrival (ns):                6.605
  Required (ns):               4.410
  Hold (ns):                   1.377

Path 2
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[3]
  Delay (ns):                  3.585
  Slack (ns):                  2.206
  Arrival (ns):                6.618
  Required (ns):               4.412
  Hold (ns):                   1.379

Path 3
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  3.400
  Slack (ns):                  2.294
  Arrival (ns):                6.433
  Required (ns):               4.139
  Hold (ns):                   1.106

Path 4
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[2]
  Delay (ns):                  3.746
  Slack (ns):                  2.369
  Arrival (ns):                6.779
  Required (ns):               4.410
  Hold (ns):                   1.377

Path 5
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[4]
  Delay (ns):                  3.819
  Slack (ns):                  2.439
  Arrival (ns):                6.852
  Required (ns):               4.413
  Hold (ns):                   1.380


Expanded Path 1
  From: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0]
  data arrival time                              6.605
  data required time                         -   4.410
  slack                                          2.195
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.033          Clock generation
  3.033
               +     1.391          cell: ADLIB:MSS_APB_IP
  4.424                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPSEL (f)
               +     0.079          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPSELINT_NET
  4.503                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_42:PIN1INT (f)
               +     0.042          cell: ADLIB:MSS_IF
  4.545                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_42:PIN1 (f)
               +     0.529          net: DSP_Coprocessor_MSS_0_MSS_MASTER_APB_PSELx
  5.074                        CoreAPB3_0/CAPB3O11_1_0[0]:A (f)
               +     0.199          cell: ADLIB:OR3A
  5.273                        CoreAPB3_0/CAPB3O11_1_0[0]:Y (r)
               +     0.140          net: CoreAPB3_0/CAPB3O11_1_0[0]
  5.413                        CoreAPB3_0/CAPB3O11[0]:A (r)
               +     0.202          cell: ADLIB:NOR2
  5.615                        CoreAPB3_0/CAPB3O11[0]:Y (f)
               +     0.291          net: CoreAPB3_0_APBmslave0_PSELx
  5.906                        CoreAPB3_0/CAPB3llOI/PRDATA_0:B (f)
               +     0.273          cell: ADLIB:NOR2B
  6.179                        CoreAPB3_0/CAPB3llOI/PRDATA_0:Y (f)
               +     0.144          net: PRDATA_0
  6.323                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_36:PIN6 (f)
               +     0.083          cell: ADLIB:MSS_IF
  6.406                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_36:PIN6INT (f)
               +     0.199          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPRDATA[0]INT_NET
  6.605                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0] (f)
                                    
  6.605                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.033          Clock generation
  3.033
               +     1.377          Library hold time: ADLIB:MSS_APB_IP
  4.410                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0]
                                    
  4.410                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_fabric_interface_clock

Path 1
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_13_inst/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[13]
  Delay (ns):                  1.618
  Slack (ns):                  1.544
  Arrival (ns):                5.977
  Required (ns):               4.433
  Hold (ns):                   1.400

Path 2
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_0_inst/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0]
  Delay (ns):                  1.623
  Slack (ns):                  1.544
  Arrival (ns):                5.970
  Required (ns):               4.426
  Hold (ns):                   1.393

Path 3
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_9_inst/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[9]
  Delay (ns):                  1.628
  Slack (ns):                  1.556
  Arrival (ns):                5.987
  Required (ns):               4.431
  Hold (ns):                   1.398

Path 4
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_7_inst/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[7]
  Delay (ns):                  1.717
  Slack (ns):                  1.640
  Arrival (ns):                6.071
  Required (ns):               4.431
  Hold (ns):                   1.398

Path 5
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_10_inst/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[10]
  Delay (ns):                  1.766
  Slack (ns):                  1.682
  Arrival (ns):                6.113
  Required (ns):               4.431
  Hold (ns):                   1.398


Expanded Path 1
  From: Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_13_inst/U1:CLK
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[13]
  data arrival time                              5.977
  data required time                         -   4.433
  slack                                          1.544
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.324          net: FAB_CLK
  4.359                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_13_inst/U1:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  4.608                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_13_inst/U1:Q (r)
               +     0.712          net: DFN1E1C0_Q_13_inst
  5.320                        CoreAPB3_0/CAPB3llOI/PRDATA_13:A (r)
               +     0.209          cell: ADLIB:NOR2B
  5.529                        CoreAPB3_0/CAPB3llOI/PRDATA_13:Y (r)
               +     0.134          net: PRDATA_13
  5.663                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_41:PIN5 (r)
               +     0.102          cell: ADLIB:MSS_IF
  5.765                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_41:PIN5INT (r)
               +     0.212          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPRDATA[13]INT_NET
  5.977                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[13] (r)
                                    
  5.977                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.033          Clock generation
  3.033
               +     1.400          Library hold time: ADLIB:MSS_APB_IP
  4.433                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[13]
                                    
  4.433                        data required time


END SET mss_ccc_gla1 to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_pclk1

Path 1
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[1]
  Delay (ns):                  0.422
  Slack (ns):                  0.730
  Arrival (ns):                4.761
  Required (ns):               4.031
  Hold (ns):                   0.998

Path 2
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[0]
  Delay (ns):                  1.101
  Slack (ns):                  1.376
  Arrival (ns):                5.466
  Required (ns):               4.090
  Hold (ns):                   1.057

Path 3
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1P0_EMPTY:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[3]
  Delay (ns):                  1.692
  Slack (ns):                  2.082
  Arrival (ns):                6.049
  Required (ns):               3.967
  Hold (ns):                   0.934

Path 4
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[2]
  Delay (ns):                  1.958
  Slack (ns):                  2.253
  Arrival (ns):                6.300
  Required (ns):               4.047
  Hold (ns):                   1.014


Expanded Path 1
  From: Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn:CLK
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[1]
  data arrival time                              4.761
  data required time                         -   4.031
  slack                                          0.730
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.304          net: FAB_CLK
  4.339                        Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  4.588                        Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn:Q (r)
               +     0.136          net: Aapb_int_fft_0_FFT_OP_RDY
  4.724                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_21:PIN5 (r)
               +     0.037          cell: ADLIB:MSS_IF
  4.761                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_21:PIN5INT (r)
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/GPI[1]INT_NET
  4.761                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[1] (r)
                                    
  4.761                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_pclk1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     3.033          Clock generation
  3.033
               +     0.998          Library hold time: ADLIB:MSS_APB_IP
  4.031                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[1]
                                    
  4.031                        data required time


END SET mss_ccc_gla1 to mss_pclk1

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        Aapb_int_fft_0/fftTop_inst/outBuff_0/outD[9]:CLK
  To:                          Aapb_int_fft_0/data_out_reg[9]:D
  Delay (ns):                  0.397
  Slack (ns):                  0.216
  Arrival (ns):                4.738
  Required (ns):               4.522
  Hold (ns):                   0.000

Path 2
  From:                        Aapb_int_fft_0/fftTop_inst/outBuff_0/outD[14]:CLK
  To:                          Aapb_int_fft_0/data_out_reg[14]:D
  Delay (ns):                  0.397
  Slack (ns):                  0.216
  Arrival (ns):                4.738
  Required (ns):               4.522
  Hold (ns):                   0.000

Path 3
  From:                        Aapb_int_fft_0/fftTop_inst/outBuff_0/outD[11]:CLK
  To:                          Aapb_int_fft_0/data_out_reg[11]:D
  Delay (ns):                  0.397
  Slack (ns):                  0.216
  Arrival (ns):                4.738
  Required (ns):               4.522
  Hold (ns):                   0.000

Path 4
  From:                        Aapb_int_fft_0/data_out_reg[8]:CLK
  To:                          Aapb_int_fft_0/fifo64X16_inst/RAM512X18_QXI_15_inst:WD8
  Delay (ns):                  0.487
  Slack (ns):                  0.290
  Arrival (ns):                4.897
  Required (ns):               4.607
  Hold (ns):                   0.000

Path 5
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_rA_0/tA[3]:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/twidLUT_1/rA_r[3]:D
  Delay (ns):                  0.395
  Slack (ns):                  0.336
  Arrival (ns):                4.748
  Required (ns):               4.412
  Hold (ns):                   0.000


Expanded Path 1
  From: Aapb_int_fft_0/fftTop_inst/outBuff_0/outD[9]:CLK
  To: Aapb_int_fft_0/data_out_reg[9]:D
  data arrival time                              4.738
  data required time                         -   4.522
  slack                                          0.216
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.306          net: FAB_CLK
  4.341                        Aapb_int_fft_0/fftTop_inst/outBuff_0/outD[9]:CLK (r)
               +     0.249          cell: ADLIB:DFN1
  4.590                        Aapb_int_fft_0/fftTop_inst/outBuff_0/outD[9]:Q (r)
               +     0.148          net: Aapb_int_fft_0/ifoY_im[1]
  4.738                        Aapb_int_fft_0/data_out_reg[9]:D (r)
                                    
  4.738                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.487          net: FAB_CLK
  4.522                        Aapb_int_fft_0/data_out_reg[9]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  4.522                        Aapb_int_fft_0/data_out_reg[9]:D
                                    
  4.522                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rA_0/Q[2]:CLR
  Delay (ns):                  2.365
  Slack (ns):                  2.297
  Arrival (ns):                6.709
  Required (ns):               4.412
  Removal (ns):                0.000
  Skew (ns):                   -0.068

Path 2
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rA_0/Q[5]:CLR
  Delay (ns):                  2.365
  Slack (ns):                  2.297
  Arrival (ns):                6.709
  Required (ns):               4.412
  Removal (ns):                0.000
  Skew (ns):                   -0.068

Path 3
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rA_0/Q[1]:CLR
  Delay (ns):                  2.373
  Slack (ns):                  2.305
  Arrival (ns):                6.717
  Required (ns):               4.412
  Removal (ns):                0.000
  Skew (ns):                   -0.068

Path 4
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rA_0/Q[0]:CLR
  Delay (ns):                  2.373
  Slack (ns):                  2.305
  Arrival (ns):                6.717
  Required (ns):               4.412
  Removal (ns):                0.000
  Skew (ns):                   -0.068

Path 5
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/pipe12:CLR
  Delay (ns):                  2.388
  Slack (ns):                  2.323
  Arrival (ns):                6.732
  Required (ns):               4.409
  Removal (ns):                0.000
  Skew (ns):                   -0.065


Expanded Path 1
  From: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK
  To: Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rA_0/Q[2]:CLR
  data arrival time                              6.709
  data required time                         -   4.412
  slack                                          2.297
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.309          net: FAB_CLK
  4.344                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK (r)
               +     0.320          cell: ADLIB:DFN1P0
  4.664                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:Q (f)
               +     0.208          net: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/initRst
  4.872                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835:B (f)
               +     0.209          cell: ADLIB:NOR2A
  5.081                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835:Y (r)
               +     0.967          net: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835
  6.048                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835_0/U_CLKSRC:A (r)
               +     0.391          cell: ADLIB:CLKSRC
  6.439                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835_0/U_CLKSRC:Y (r)
               +     0.270          net: Aapb_int_fft_0/fftTop_inst/smTop_0/nGrst
  6.709                        Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rA_0/Q[2]:CLR (r)
                                    
  6.709                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.377          net: FAB_CLK
  4.412                        Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rA_0/Q[2]:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1E0C0
  4.412                        Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rA_0/Q[2]:CLR
                                    
  4.412                        data required time


END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_gla1

Path 1
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/PENABLE_reg:D
  Delay (ns):                  2.390
  Slack (ns):                  1.079
  Arrival (ns):                5.423
  Required (ns):               4.344
  Hold (ns):                   0.000

Path 2
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fftTop_inst/inBuf_0/piBuf/memQ/wrapRam_0/actram_R0C0:WD2
  Delay (ns):                  2.972
  Slack (ns):                  1.517
  Arrival (ns):                6.005
  Required (ns):               4.488
  Hold (ns):                   0.000

Path 3
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fftTop_inst/inBuf_0/piBuf/memQ/wrapRam_0/actram_R0C0:WD7
  Delay (ns):                  3.069
  Slack (ns):                  1.614
  Arrival (ns):                6.102
  Required (ns):               4.488
  Hold (ns):                   0.000

Path 4
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fftTop_inst/inBuf_0/piBuf/memP/wrapRam_0/actram_R0C0:WD14
  Delay (ns):                  3.091
  Slack (ns):                  1.635
  Arrival (ns):                6.124
  Required (ns):               4.489
  Hold (ns):                   0.000

Path 5
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fftTop_inst/inBuf_0/piBuf/memP/wrapRam_0/actram_R0C0:WD2
  Delay (ns):                  3.147
  Slack (ns):                  1.691
  Arrival (ns):                6.180
  Required (ns):               4.489
  Hold (ns):                   0.000


Expanded Path 1
  From: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To: Aapb_int_fft_0/PENABLE_reg:D
  data arrival time                              5.423
  data required time                         -   4.344
  slack                                          1.079
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.033          Clock generation
  3.033
               +     1.407          cell: ADLIB:MSS_APB_IP
  4.440                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPENABLE (r)
               +     0.059          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPENABLEINT_NET
  4.499                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_42:PIN2INT (r)
               +     0.045          cell: ADLIB:MSS_IF
  4.544                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_42:PIN2 (r)
               +     0.573          net: CoreAPB3_0_APBmslave0_PENABLE
  5.117                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST_RNI69K1:A (r)
               +     0.158          cell: ADLIB:INV
  5.275                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST_RNI69K1:Y (f)
               +     0.148          net: CoreAPB3_0_APBmslave0_PENABLE_i
  5.423                        Aapb_int_fft_0/PENABLE_reg:D (f)
                                    
  5.423                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.309          net: FAB_CLK
  4.344                        Aapb_int_fft_0/PENABLE_reg:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1P0
  4.344                        Aapb_int_fft_0/PENABLE_reg:D
                                    
  4.344                        data required time


END SET mss_fabric_interface_clock to mss_ccc_gla1

----------------------------------------------------

SET mss_ccc_gla0 to mss_ccc_gla1

Path 1
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_13_inst/U1:CLR
  Delay (ns):                  2.384
  Slack (ns):                  1.037
  Arrival (ns):                5.417
  Required (ns):               4.380
  Hold (ns):

Path 2
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/PSEL_reg:CLR
  Delay (ns):                  2.384
  Slack (ns):                  1.044
  Arrival (ns):                5.417
  Required (ns):               4.373
  Hold (ns):

Path 3
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/EMPTY_OUT_REG/U1:CLR
  Delay (ns):                  2.384
  Slack (ns):                  1.057
  Arrival (ns):                5.417
  Required (ns):               4.360
  Hold (ns):

Path 4
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/PREADY0:PRE
  Delay (ns):                  2.390
  Slack (ns):                  1.063
  Arrival (ns):                5.423
  Required (ns):               4.360
  Hold (ns):

Path 5
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/PREADY1:PRE
  Delay (ns):                  2.390
  Slack (ns):                  1.063
  Arrival (ns):                5.423
  Required (ns):               4.360
  Hold (ns):


Expanded Path 1
  From: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To: Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_13_inst/U1:CLR
  data arrival time                              5.417
  data required time                         -   4.380
  slack                                          1.037
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  2.724
               +     0.309          net: DSP_Coprocessor_MSS_0/GLA0
  3.033                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.710          cell: ADLIB:MSS_APB_IP
  4.743                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:M2FRESETn (r)
               +     0.060          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/M2FRESETnINT_NET
  4.803                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_46:PIN2INT (r)
               +     0.045          cell: ADLIB:MSS_IF
  4.848                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_46:PIN2 (r)
               +     0.569          net: DSP_Coprocessor_MSS_0_M2F_RESET_N
  5.417                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_13_inst/U1:CLR (r)
                                    
  5.417                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.345          net: FAB_CLK
  4.380                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_13_inst/U1:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1C0
  4.380                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_13_inst/U1:CLR
                                    
  4.380                        data required time


END SET mss_ccc_gla0 to mss_ccc_gla1

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.277
  Slack (ns):
  Arrival (ns):                0.277
  Required (ns):
  Hold (ns):                   1.358
  External Hold (ns):          4.176


Expanded Path 1
  From: MSS_RESET_N
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.277
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        DSP_Coprocessor_MSS_0/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.277          cell: ADLIB:IOPAD_IN
  0.277                        DSP_Coprocessor_MSS_0/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_RESET_0_MSS_RESET_N_Y
  0.277                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.277                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  N/C
               +     0.371          net: DSP_Coprocessor_MSS_0/GLA0
  N/C                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.358          Library hold time: ADLIB:MSS_APB_IP
  N/C                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain DSP_Coprocessor_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

