Timing Report Min Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Thu Dec 08 10:29:07 2011


Design: DSP_Coprocessor
Family: SmartFusion
Die: A2F200M3F
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                8.053
Frequency (MHz):            124.177
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                18.377
Frequency (MHz):            54.416
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        -5.434
External Hold (ns):         4.176
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               DSP_Coprocessor_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  3.348
  Slack (ns):                  2.242
  Arrival (ns):                6.381
  Required (ns):               4.139
  Hold (ns):                   1.106

Path 2
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[12]
  Delay (ns):                  3.725
  Slack (ns):                  2.339
  Arrival (ns):                6.758
  Required (ns):               4.419
  Hold (ns):                   1.386

Path 3
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[8]
  Delay (ns):                  3.729
  Slack (ns):                  2.347
  Arrival (ns):                6.762
  Required (ns):               4.415
  Hold (ns):                   1.382

Path 4
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[9]
  Delay (ns):                  3.733
  Slack (ns):                  2.352
  Arrival (ns):                6.766
  Required (ns):               4.414
  Hold (ns):                   1.381

Path 5
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[1]
  Delay (ns):                  3.731
  Slack (ns):                  2.352
  Arrival (ns):                6.764
  Required (ns):               4.412
  Hold (ns):                   1.379


Expanded Path 1
  From: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  data arrival time                              6.381
  data required time                         -   4.139
  slack                                          2.242
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.033          Clock generation
  3.033
               +     1.481          cell: ADLIB:MSS_APB_IP
  4.514                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPWRITE (f)
               +     0.079          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPWRITEINT_NET
  4.593                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_42:PIN3INT (f)
               +     0.041          cell: ADLIB:MSS_IF
  4.634                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_42:PIN3 (f)
               +     0.726          net: CoreAPB3_0_APBmslave0_PWRITE
  5.360                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int_RNIN76C:S (f)
               +     0.206          cell: ADLIB:MX2C
  5.566                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int_RNIN76C:Y (r)
               +     0.167          net: CoreAPB3_0_APBmslave0_PREADY
  5.733                        CoreAPB3_0/CAPB3O1II/PREADY:B (r)
               +     0.257          cell: ADLIB:OR2B
  5.990                        CoreAPB3_0/CAPB3O1II/PREADY:Y (f)
               +     0.135          net: DSP_Coprocessor_MSS_0_MSS_MASTER_APB_PREADY
  6.125                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_36:PIN5 (f)
               +     0.046          cell: ADLIB:MSS_IF
  6.171                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_36:PIN5INT (f)
               +     0.210          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPREADYINT_NET
  6.381                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY (f)
                                    
  6.381                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.033          Clock generation
  3.033
               +     1.106          Library hold time: ADLIB:MSS_APB_IP
  4.139                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
                                    
  4.139                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_fabric_interface_clock

Path 1
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_9_inst/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[9]
  Delay (ns):                  1.621
  Slack (ns):                  1.532
  Arrival (ns):                5.963
  Required (ns):               4.431
  Hold (ns):                   1.398

Path 2
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_1_inst/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[1]
  Delay (ns):                  1.788
  Slack (ns):                  1.718
  Arrival (ns):                6.147
  Required (ns):               4.429
  Hold (ns):                   1.396

Path 3
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_3_inst/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[3]
  Delay (ns):                  1.931
  Slack (ns):                  1.847
  Arrival (ns):                6.275
  Required (ns):               4.428
  Hold (ns):                   1.395

Path 4
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_8_inst/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[8]
  Delay (ns):                  1.921
  Slack (ns):                  1.860
  Arrival (ns):                6.292
  Required (ns):               4.432
  Hold (ns):                   1.399

Path 5
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_14_inst/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[14]
  Delay (ns):                  2.059
  Slack (ns):                  1.980
  Arrival (ns):                6.411
  Required (ns):               4.431
  Hold (ns):                   1.398


Expanded Path 1
  From: Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_9_inst/U1:CLK
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[9]
  data arrival time                              5.963
  data required time                         -   4.431
  slack                                          1.532
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.307          net: FAB_CLK
  4.342                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_9_inst/U1:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  4.591                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_9_inst/U1:Q (r)
               +     0.705          net: _CoreAPB3_0_APBmslave0_PRDATA_[9]_
  5.296                        CoreAPB3_0/CAPB3O1II/PRDATA_9:B (r)
               +     0.221          cell: ADLIB:NOR2B
  5.517                        CoreAPB3_0/CAPB3O1II/PRDATA_9:Y (r)
               +     0.138          net: _DSP_Coprocessor_MSS_0_MSS_MASTER_APB_PRDATA_[9]_
  5.655                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_39:PIN6 (r)
               +     0.090          cell: ADLIB:MSS_IF
  5.745                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_39:PIN6INT (r)
               +     0.218          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPRDATA[9]INT_NET
  5.963                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[9] (r)
                                    
  5.963                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.033          Clock generation
  3.033
               +     1.398          Library hold time: ADLIB:MSS_APB_IP
  4.431                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[9]
                                    
  4.431                        data required time


END SET mss_ccc_gla1 to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_pclk1

Path 1
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn_int:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[1]
  Delay (ns):                  0.485
  Slack (ns):                  0.813
  Arrival (ns):                4.844
  Required (ns):               4.031
  Hold (ns):                   0.998

Path 2
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_int:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[0]
  Delay (ns):                  0.982
  Slack (ns):                  1.242
  Arrival (ns):                5.332
  Required (ns):               4.090
  Hold (ns):                   1.057

Path 3
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1P0_EMPTY:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[3]
  Delay (ns):                  1.495
  Slack (ns):                  1.870
  Arrival (ns):                5.837
  Required (ns):               3.967
  Hold (ns):                   0.934

Path 4
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[2]
  Delay (ns):                  1.770
  Slack (ns):                  2.059
  Arrival (ns):                6.106
  Required (ns):               4.047
  Hold (ns):                   1.014


Expanded Path 1
  From: Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn_int:CLK
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[1]
  data arrival time                              4.844
  data required time                         -   4.031
  slack                                          0.813
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.324          net: FAB_CLK
  4.359                        Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn_int:CLK (r)
               +     0.249          cell: ADLIB:DFN1
  4.608                        Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn_int:Q (r)
               +     0.134          net: Aapb_int_fft_0_FFT_OP_RDY
  4.742                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_21:PIN5 (r)
               +     0.102          cell: ADLIB:MSS_IF
  4.844                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_21:PIN5INT (r)
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/GPI[1]INT_NET
  4.844                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[1] (r)
                                    
  4.844                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_pclk1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     3.033          Clock generation
  3.033
               +     0.998          Library hold time: ADLIB:MSS_APB_IP
  4.031                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[1]
                                    
  4.031                        data required time


END SET mss_ccc_gla1 to mss_pclk1

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        Aapb_int_fft_0/fftTop_inst/outBuff_0/outD_xhdl1[3]:CLK
  To:                          Aapb_int_fft_0/data_out_reg[3]:D
  Delay (ns):                  0.397
  Slack (ns):                  0.270
  Arrival (ns):                4.768
  Required (ns):               4.498
  Hold (ns):                   0.000

Path 2
  From:                        Aapb_int_fft_0/fftTop_inst/outBuff_0/outD_xhdl1[7]:CLK
  To:                          Aapb_int_fft_0/data_out_reg[7]:D
  Delay (ns):                  0.397
  Slack (ns):                  0.333
  Arrival (ns):                4.772
  Required (ns):               4.439
  Hold (ns):                   0.000

Path 3
  From:                        Aapb_int_fft_0/fftTop_inst/outBuff_0/outD_xhdl1[8]:CLK
  To:                          Aapb_int_fft_0/data_out_reg[8]:D
  Delay (ns):                  0.401
  Slack (ns):                  0.341
  Arrival (ns):                4.742
  Required (ns):               4.401
  Hold (ns):                   0.000

Path 4
  From:                        Aapb_int_fft_0/fftTop_inst/outBuff_0/rAmsb_r1:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/outBuff_0/rAmsb_r2:D
  Delay (ns):                  0.401
  Slack (ns):                  0.341
  Arrival (ns):                4.742
  Required (ns):               4.401
  Hold (ns):                   0.000

Path 5
  From:                        Aapb_int_fft_0/fftTop_inst/bfly_0/PrT1_r[1]:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/bfly_0/PrT2_r[1]:D
  Delay (ns):                  0.395
  Slack (ns):                  0.343
  Arrival (ns):                4.754
  Required (ns):               4.411
  Hold (ns):                   0.000


Expanded Path 1
  From: Aapb_int_fft_0/fftTop_inst/outBuff_0/outD_xhdl1[3]:CLK
  To: Aapb_int_fft_0/data_out_reg[3]:D
  data arrival time                              4.768
  data required time                         -   4.498
  slack                                          0.270
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.336          net: FAB_CLK
  4.371                        Aapb_int_fft_0/fftTop_inst/outBuff_0/outD_xhdl1[3]:CLK (r)
               +     0.249          cell: ADLIB:DFN1
  4.620                        Aapb_int_fft_0/fftTop_inst/outBuff_0/outD_xhdl1[3]:Q (r)
               +     0.148          net: Aapb_int_fft_0/ifoY_re[3]
  4.768                        Aapb_int_fft_0/data_out_reg[3]:D (r)
                                    
  4.768                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.463          net: FAB_CLK
  4.498                        Aapb_int_fft_0/data_out_reg[3]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  4.498                        Aapb_int_fft_0/data_out_reg[3]:D
                                    
  4.498                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/stage_timer/Q_out[0]:CLR
  Delay (ns):                  2.151
  Slack (ns):                  2.126
  Arrival (ns):                6.510
  Required (ns):               4.384
  Removal (ns):                0.000
  Skew (ns):                   -0.025

Path 2
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/stage_timer/tc_out:CLR
  Delay (ns):                  2.151
  Slack (ns):                  2.126
  Arrival (ns):                6.510
  Required (ns):               4.384
  Removal (ns):                0.000
  Skew (ns):                   -0.025

Path 3
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/smPong_xhdl14:PRE
  Delay (ns):                  2.144
  Slack (ns):                  2.128
  Arrival (ns):                6.503
  Required (ns):               4.375
  Removal (ns):                0.000
  Skew (ns):                   -0.016

Path 4
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/smBuf_full:CLR
  Delay (ns):                  2.153
  Slack (ns):                  2.132
  Arrival (ns):                6.512
  Required (ns):               4.380
  Removal (ns):                0.000
  Skew (ns):                   -0.021

Path 5
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/preOutBuf_wEn:CLR
  Delay (ns):                  2.153
  Slack (ns):                  2.132
  Arrival (ns):                6.512
  Required (ns):               4.380
  Removal (ns):                0.000
  Skew (ns):                   -0.021


Expanded Path 1
  From: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK
  To: Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/stage_timer/Q_out[0]:CLR
  data arrival time                              6.510
  data required time                         -   4.384
  slack                                          2.126
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.324          net: FAB_CLK
  4.359                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:CLK (r)
               +     0.320          cell: ADLIB:DFN1P0
  4.679                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int:Q (f)
               +     0.806          net: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/initRst
  5.485                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8:B (f)
               +     0.209          cell: ADLIB:NOR2A
  5.694                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8:Y (r)
               +     0.146          net: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8
  5.840                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8_0/U_CLKSRC:A (r)
               +     0.391          cell: ADLIB:CLKSRC
  6.231                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_int_RNIUNP8_0/U_CLKSRC:Y (r)
               +     0.279          net: Aapb_int_fft_0/fftTop_inst/smTop_0/nGrst
  6.510                        Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/stage_timer/Q_out[0]:CLR (r)
                                    
  6.510                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.349          net: FAB_CLK
  4.384                        Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/stage_timer/Q_out[0]:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1E0C0
  4.384                        Aapb_int_fft_0/fftTop_inst/smTop_0/wrFFTtimer_0/stage_timer/Q_out[0]:CLR
                                    
  4.384                        data required time


END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_gla1

Path 1
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/PENABLE_reg:D
  Delay (ns):                  1.981
  Slack (ns):                  0.666
  Arrival (ns):                5.014
  Required (ns):               4.348
  Hold (ns):                   0.000

Path 2
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fftTop_inst/inBuf_0/poBuf/memQ/wrapRam_0/actram_R0C0:WD2
  Delay (ns):                  3.111
  Slack (ns):                  1.655
  Arrival (ns):                6.144
  Required (ns):               4.489
  Hold (ns):                   0.000

Path 3
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/PSEL_reg:D
  Delay (ns):                  3.059
  Slack (ns):                  1.715
  Arrival (ns):                6.092
  Required (ns):               4.377
  Hold (ns):                   0.000

Path 4
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fftTop_inst/inBuf_0/poBuf/memQ/wrapRam_0/actram_R0C0:WD15
  Delay (ns):                  3.177
  Slack (ns):                  1.721
  Arrival (ns):                6.210
  Required (ns):               4.489
  Hold (ns):                   0.000

Path 5
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fftTop_inst/inBuf_0/piBuf/memP/wrapRam_0/actram_R0C0:WD7
  Delay (ns):                  3.197
  Slack (ns):                  1.732
  Arrival (ns):                6.230
  Required (ns):               4.498
  Hold (ns):                   0.000


Expanded Path 1
  From: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To: Aapb_int_fft_0/PENABLE_reg:D
  data arrival time                              5.014
  data required time                         -   4.348
  slack                                          0.666
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.033          Clock generation
  3.033
               +     1.393          cell: ADLIB:MSS_APB_IP
  4.426                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPENABLE (f)
               +     0.077          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPENABLEINT_NET
  4.503                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_42:PIN2INT (f)
               +     0.045          cell: ADLIB:MSS_IF
  4.548                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_42:PIN2 (f)
               +     0.466          net: CoreAPB3_0_APBmslave0_PENABLE
  5.014                        Aapb_int_fft_0/PENABLE_reg:D (f)
                                    
  5.014                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.313          net: FAB_CLK
  4.348                        Aapb_int_fft_0/PENABLE_reg:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  4.348                        Aapb_int_fft_0/PENABLE_reg:D
                                    
  4.348                        data required time


END SET mss_fabric_interface_clock to mss_ccc_gla1

----------------------------------------------------

SET mss_ccc_gla0 to mss_ccc_gla1

Path 1
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/PREADY0:PRE
  Delay (ns):                  2.413
  Slack (ns):                  1.069
  Arrival (ns):                5.446
  Required (ns):               4.377
  Hold (ns):

Path 2
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/PSEL_reg:CLR
  Delay (ns):                  2.413
  Slack (ns):                  1.069
  Arrival (ns):                5.446
  Required (ns):               4.377
  Hold (ns):

Path 3
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/PREADY1:PRE
  Delay (ns):                  2.413
  Slack (ns):                  1.069
  Arrival (ns):                5.446
  Required (ns):               4.377
  Hold (ns):

Path 4
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_9_inst/U1:CLR
  Delay (ns):                  2.405
  Slack (ns):                  1.078
  Arrival (ns):                5.438
  Required (ns):               4.360
  Hold (ns):

Path 5
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/EMPTY_OUT_REG/U1:CLR
  Delay (ns):                  2.413
  Slack (ns):                  1.098
  Arrival (ns):                5.446
  Required (ns):               4.348
  Hold (ns):


Expanded Path 1
  From: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To: Aapb_int_fft_0/PREADY0:PRE
  data arrival time                              5.446
  data required time                         -   4.377
  slack                                          1.069
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  2.724
               +     0.309          net: DSP_Coprocessor_MSS_0/GLA0
  3.033                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.710          cell: ADLIB:MSS_APB_IP
  4.743                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:M2FRESETn (r)
               +     0.060          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/M2FRESETnINT_NET
  4.803                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_46:PIN2INT (r)
               +     0.045          cell: ADLIB:MSS_IF
  4.848                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_46:PIN2 (r)
               +     0.598          net: DSP_Coprocessor_MSS_0_M2F_RESET_N
  5.446                        Aapb_int_fft_0/PREADY0:PRE (r)
                                    
  5.446                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.342          net: FAB_CLK
  4.377                        Aapb_int_fft_0/PREADY0:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1P0
  4.377                        Aapb_int_fft_0/PREADY0:PRE
                                    
  4.377                        data required time


END SET mss_ccc_gla0 to mss_ccc_gla1

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.277
  Slack (ns):
  Arrival (ns):                0.277
  Required (ns):
  Hold (ns):                   1.358
  External Hold (ns):          4.176


Expanded Path 1
  From: MSS_RESET_N
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.277
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        DSP_Coprocessor_MSS_0/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.277          cell: ADLIB:IOPAD_IN
  0.277                        DSP_Coprocessor_MSS_0/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_RESET_0_MSS_RESET_N_Y
  0.277                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.277                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  N/C
               +     0.371          net: DSP_Coprocessor_MSS_0/GLA0
  N/C                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.358          Library hold time: ADLIB:MSS_APB_IP
  N/C                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain DSP_Coprocessor_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

