library verilog;
use verilog.vl_types.all;
entity Aapb_int_fft is
    port(
        PRESETn         : in     vl_logic;
        PCLK            : in     vl_logic;
        PSEL_S0         : in     vl_logic;
        PADDR           : in     vl_logic_vector(31 downto 0);
        PWRITE          : in     vl_logic;
        PENABLE         : in     vl_logic;
        PWDATA          : in     vl_logic_vector(31 downto 0);
        PSLVERR         : out    vl_logic;
        PREADY          : out    vl_logic;
        PRDATA          : out    vl_logic_vector(31 downto 0);
        FFT_IP_RDY      : out    vl_logic;
        FFT_OP_RDY      : out    vl_logic;
        AEMPTY_OUT      : out    vl_logic;
        EMPTY_OUT       : out    vl_logic
    );
end Aapb_int_fft;
