library verilog;
use verilog.vl_types.all;
entity kitRndUp is
    generic(
        OUTBITWIDTH     : integer := 12;
        RND_MODE        : integer := 0
    );
    port(
        nGrst           : in     vl_logic;
        rst             : in     vl_logic;
        clk             : in     vl_logic;
        clkEn           : in     vl_logic;
        inp             : in     vl_logic_vector;
        valInp          : in     vl_logic;
        outp            : out    vl_logic_vector;
        valOutp         : out    vl_logic
    );
end kitRndUp;
