#-- Synopsys, Inc.
#-- Version E-2010.09A-1
#-- Project file C:\A2F_AC355_DF\A2F200\Verilog\DSP_Coprocessor\synthesis\run_options.txt
#-- Written on Thu Dec 08 10:29:19 2011


#project files
add_file -include "C:/A2F_AC355_DF/A2F200/Verilog/DSP_Coprocessor/hdl/fftHeader.v"
add_file -verilog "C:/A2F_AC355_DF/A2F200/Verilog/DSP_Coprocessor/component/Actel/SmartFusionMSS/MSS/2.5.106/mss_comps.v"
add_file -verilog "C:/A2F_AC355_DF/A2F200/Verilog/DSP_Coprocessor/component/work/DSP_Coprocessor_MSS/mss_tshell.v"
add_file -verilog "C:/A2F_AC355_DF/A2F200/Verilog/DSP_Coprocessor/component/work/DSP_Coprocessor_MSS/MSS_CCC_0/DSP_Coprocessor_MSS_tmp_MSS_CCC_0_MSS_CCC.v"
add_file -verilog "C:/A2F_AC355_DF/A2F200/Verilog/DSP_Coprocessor/component/work/DSP_Coprocessor_MSS/DSP_Coprocessor_MSS.v"
add_file -verilog "C:/A2F_AC355_DF/A2F200/Verilog/DSP_Coprocessor/hdl/fftSm.v"
add_file -verilog "C:/A2F_AC355_DF/A2F200/Verilog/DSP_Coprocessor/hdl/actram.v"
add_file -verilog "C:/A2F_AC355_DF/A2F200/Verilog/DSP_Coprocessor/hdl/fftDp.v"
add_file -verilog "C:/A2F_AC355_DF/A2F200/Verilog/DSP_Coprocessor/hdl/actar.v"
add_file -verilog "C:/A2F_AC355_DF/A2F200/Verilog/DSP_Coprocessor/hdl/twiddle.v"
add_file -verilog "C:/A2F_AC355_DF/A2F200/Verilog/DSP_Coprocessor/hdl/fftTop.v"
add_file -verilog "C:/A2F_AC355_DF/A2F200/Verilog/DSP_Coprocessor/smartgen/fifo64x16/fifo64x16.v"
add_file -verilog "C:/A2F_AC355_DF/A2F200/Verilog/DSP_Coprocessor/hdl/Aapb_int_fft.v"
add_file -verilog -lib COREAPB3_LIB "C:/A2F_AC355_DF/A2F200/Verilog/DSP_Coprocessor/component/Actel/DirectCore/CoreAPB3/3.0.103/rtl/vlog/core_obfuscated/coreapb3_muxptob3.v"
add_file -verilog -lib COREAPB3_LIB "C:/A2F_AC355_DF/A2F200/Verilog/DSP_Coprocessor/component/Actel/DirectCore/CoreAPB3/3.0.103/rtl/vlog/core_obfuscated/coreapb3.v"
add_file -verilog "C:/A2F_AC355_DF/A2F200/Verilog/DSP_Coprocessor/component/work/DSP_Coprocessor/DSP_Coprocessor.v"
add_file -constraint "C:/A2F_AC355_DF/A2F200/Verilog/DSP_Coprocessor/component/work/DSP_Coprocessor_MSS/mss_tshell_syn.sdc"


#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std v2001

#device options
set_option -technology SmartFusion
set_option -part A2F200M3F
set_option -package FBGA484
set_option -speed_grade STD
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "DSP_Coprocessor"

# mapper_options
set_option -frequency 100.000
set_option -write_verilog 0
set_option -write_vhdl 0

# Actel 500K
set_option -run_prop_extract 1
set_option -maxfan 24
set_option -maxfan_hard3 0
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -report_path 0
set_option -opcond COMWC
set_option -update_models_cp 0
set_option -preserve_registers 0

# Actel 500K
set_option -globalthreshold 50

# NFilter
set_option -popfeed 0
set_option -constprop 0
set_option -createhierarchy 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./DSP_Coprocessor.edn"
impl -active "synthesis"
