library verilog;
use verilog.vl_types.all;
entity switch is
    generic(
        DWIDTH          : integer := 32
    );
    port(
        clk             : in     vl_logic;
        inP             : in     vl_logic_vector;
        inQ             : in     vl_logic_vector;
        sel             : in     vl_logic;
        outP            : out    vl_logic_vector;
        outQ            : out    vl_logic_vector;
        validIn         : in     vl_logic;
        validOut        : out    vl_logic
    );
end switch;
