library verilog;
use verilog.vl_types.all;
entity twid_rA is
    generic(
        LOGPTS          : integer := 8;
        LOGLOGPTS       : integer := 3
    );
    port(
        clk             : in     vl_logic;
        timer           : in     vl_logic_vector;
        stage           : in     vl_logic_vector;
        tA              : out    vl_logic_vector
    );
end twid_rA;
