library verilog;
use verilog.vl_types.all;
entity edgeDetect is
    generic(
        INPIPE          : integer := 0;
        FEDGE           : integer := 0
    );
    port(
        clk             : in     vl_logic;
        clkEn           : in     vl_logic;
        \in\            : in     vl_logic;
        \out\           : out    vl_logic
    );
end edgeDetect;
