library verilog;
use verilog.vl_types.all;
entity DSP_Coprocessor is
    port(
        UART_0_TXD      : out    vl_logic;
        UART_0_RXD      : in     vl_logic;
        MSS_RESET_N     : in     vl_logic
    );
end DSP_Coprocessor;
