library verilog;
use verilog.vl_types.all;
entity outBuff is
    generic(
        LOGPTS          : integer := 8;
        DWIDTH          : integer := 32
    );
    port(
        clk             : in     vl_logic;
        clkEn           : in     vl_logic;
        wEn             : in     vl_logic;
        inP             : in     vl_logic_vector;
        inQ             : in     vl_logic_vector;
        wA              : in     vl_logic_vector;
        rA              : in     vl_logic_vector;
        outD            : out    vl_logic_vector
    );
end outBuff;
