library verilog;
use verilog.vl_types.all;
entity wrapRam is
    generic(
        LOGPTS          : integer := 8;
        DWIDTH          : integer := 32
    );
    port(
        clk             : in     vl_logic;
        D               : in     vl_logic_vector;
        Q               : out    vl_logic_vector;
        wA              : in     vl_logic_vector;
        rA              : in     vl_logic_vector;
        wEn             : in     vl_logic
    );
end wrapRam;
