library verilog;
use verilog.vl_types.all;
entity actram is
    port(
        DI              : in     vl_logic_vector(15 downto 0);
        DO              : out    vl_logic_vector(15 downto 0);
        WRB             : in     vl_logic;
        RDB             : in     vl_logic;
        WADDR           : in     vl_logic_vector(6 downto 0);
        RADDR           : in     vl_logic_vector(6 downto 0);
        WCLOCK          : in     vl_logic;
        RCLOCK          : in     vl_logic
    );
end actram;
