library verilog;
use verilog.vl_types.all;
entity agen is
    generic(
        WIDTH           : integer := 16;
        TWIDTH          : integer := 16;
        RND_MODE        : integer := 0
    );
    port(
        clk             : in     vl_logic;
        a               : in     vl_logic_vector;
        t               : in     vl_logic_vector;
        \out\           : out    vl_logic_vector
    );
end agen;
