library verilog;
use verilog.vl_types.all;
entity wrFFTtimer is
    generic(
        LOGPTS          : integer := 8;
        LOGLOGPTS       : integer := 3;
        HALFPTS         : integer := 128
    );
    port(
        clk             : in     vl_logic;
        cntEn           : in     vl_logic;
        nGrst           : in     vl_logic;
        rst             : in     vl_logic;
        rstStage        : in     vl_logic;
        rstTime         : in     vl_logic;
        timerTC         : out    vl_logic;
        lastStage       : out    vl_logic;
        stage           : out    vl_logic_vector;
        timer           : out    vl_logic_vector
    );
end wrFFTtimer;
