library verilog;
use verilog.vl_types.all;
entity fftTop is
    generic(
        WIDTH           : integer := 8;
        DWIDTH          : integer := 16;
        TWIDTH          : integer := 8;
        TDWIDTH         : integer := 16;
        LOGPTS          : integer := 8;
        LOGLOGPTS       : integer := 3;
        RND_MODE        : integer := 1;
        SCALE_MODE      : integer := 1;
        PTS             : integer := 256;
        HALFPTS         : integer := 128;
        inBuf_RWDLY     : integer := 12
    );
    port(
        clk             : in     vl_logic;
        ifiStart        : in     vl_logic;
        ifiNreset       : in     vl_logic;
        ifiD_valid      : in     vl_logic;
        ifiD_im         : in     vl_logic_vector;
        ifiD_re         : in     vl_logic_vector;
        ifiRead_y       : in     vl_logic;
        ifoLoad         : out    vl_logic;
        ifoY_im         : out    vl_logic_vector;
        ifoY_re         : out    vl_logic_vector;
        ifoPong         : out    vl_logic;
        ifoY_valid      : out    vl_logic;
        ifoY_rdy        : out    vl_logic
    );
end fftTop;
