library verilog;
use verilog.vl_types.all;
entity inBuffer is
    generic(
        LOGPTS          : integer := 8;
        DWIDTH          : integer := 32
    );
    port(
        clk             : in     vl_logic;
        clkEn           : in     vl_logic;
        rA              : in     vl_logic_vector;
        wA_bfly         : in     vl_logic_vector;
        wA_load         : in     vl_logic_vector;
        ldData          : in     vl_logic_vector;
        pipo            : in     vl_logic;
        wP_bfly         : in     vl_logic_vector;
        wQ_bfly         : in     vl_logic_vector;
        wEn_bfly        : in     vl_logic;
        wEn_even        : in     vl_logic;
        wEn_odd         : in     vl_logic;
        outP            : out    vl_logic_vector;
        outQ            : out    vl_logic_vector
    );
end inBuffer;
