library verilog;
use verilog.vl_types.all;
entity inBuf_fftA is
    generic(
        LOGPTS          : integer := 8;
        LOGLOGPTS       : integer := 3
    );
    port(
        clk             : in     vl_logic;
        clkEn           : in     vl_logic;
        timer           : in     vl_logic_vector;
        stage           : in     vl_logic_vector;
        timerTC         : in     vl_logic;
        lastStage       : in     vl_logic;
        fftDone         : out    vl_logic;
        bflyA           : out    vl_logic_vector;
        swCross         : out    vl_logic
    );
end inBuf_fftA;
