library verilog;
use verilog.vl_types.all;
entity bcounter is
    generic(
        WIDTH           : integer := 7
    );
    port(
        clk             : in     vl_logic;
        nGrst           : in     vl_logic;
        rst             : in     vl_logic;
        cntEn           : in     vl_logic;
        Q               : out    vl_logic_vector
    );
end bcounter;
