library verilog;
use verilog.vl_types.all;
entity sm_top is
    generic(
        PTS             : integer := 256;
        HALFPTS         : integer := 128;
        LOGPTS          : integer := 8;
        LOGLOGPTS       : integer := 3;
        inBuf_RWDLY     : integer := 12
    );
    port(
        clk             : in     vl_logic;
        clkEn           : in     vl_logic;
        ifiStart        : in     vl_logic;
        ifiNreset       : in     vl_logic;
        ifiD_valid      : in     vl_logic;
        ifiRead_y       : in     vl_logic;
        ldA             : out    vl_logic_vector;
        rA              : out    vl_logic_vector;
        wA              : out    vl_logic_vector;
        tA              : out    vl_logic_vector;
        twid_wA         : out    vl_logic_vector;
        outBuf_wA       : out    vl_logic_vector;
        outBuf_rA       : out    vl_logic_vector;
        wEn_even        : out    vl_logic;
        wEn_odd         : out    vl_logic;
        preSwCross      : out    vl_logic;
        twid_wEn        : out    vl_logic;
        inBuf_wEn       : out    vl_logic;
        outBuf_wEn      : out    vl_logic;
        smPong          : out    vl_logic;
        ldValid         : out    vl_logic;
        inBuf_rdValid   : out    vl_logic;
        wLastStage      : out    vl_logic;
        smStartFFTrd    : out    vl_logic;
        smStartLoad     : out    vl_logic;
        ifoLoad         : out    vl_logic;
        ifoY_valid      : out    vl_logic;
        ifoY_rdy        : out    vl_logic
    );
end sm_top;
