Timing Report Min Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Thu Dec 08 10:37:19 2011


Design: DSP_Coprocessor
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                8.030
Frequency (MHz):            124.533
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                14.723
Frequency (MHz):            67.921
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       25.000
Required Frequency (MHz):   40.000
External Setup (ns):        -4.928
External Hold (ns):         4.007
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               DSP_Coprocessor_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  Delay (ns):                  3.504
  Slack (ns):                  2.373
  Arrival (ns):                6.453
  Required (ns):               4.080
  Hold (ns):                   1.131

Path 2
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[4]
  Delay (ns):                  4.078
  Slack (ns):                  2.748
  Arrival (ns):                7.027
  Required (ns):               4.279
  Hold (ns):                   1.330

Path 3
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0]
  Delay (ns):                  4.495
  Slack (ns):                  3.165
  Arrival (ns):                7.444
  Required (ns):               4.279
  Hold (ns):                   1.330

Path 4
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[13]
  Delay (ns):                  4.546
  Slack (ns):                  3.214
  Arrival (ns):                7.495
  Required (ns):               4.281
  Hold (ns):                   1.332

Path 5
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[5]
  Delay (ns):                  4.590
  Slack (ns):                  3.260
  Arrival (ns):                7.539
  Required (ns):               4.279
  Hold (ns):                   1.330


Expanded Path 1
  From: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
  data arrival time                              6.453
  data required time                         -   4.080
  slack                                          2.373
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.949          Clock generation
  2.949
               +     1.278          cell: ADLIB:MSS_APB_IP
  4.227                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPWRITE (r)
               +     0.061          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPWRITEINT_NET
  4.288                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_42:PIN3INT (r)
               +     0.040          cell: ADLIB:MSS_IF
  4.328                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_42:PIN3 (r)
               +     0.718          net: CoreAPB3_0_APBmslave0_PWRITE
  5.046                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_RNIBGQ7:S (r)
               +     0.156          cell: ADLIB:MX2C
  5.202                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn_RNIBGQ7:Y (r)
               +     0.145          net: CoreAPB3_0_APBmslave0_PREADY
  5.347                        CoreAPB3_0/CAPB3llOI/PREADY:B (r)
               +     0.256          cell: ADLIB:OR2B
  5.603                        CoreAPB3_0/CAPB3llOI/PREADY:Y (f)
               +     0.568          net: DSP_Coprocessor_MSS_0_MSS_MASTER_APB_PREADY
  6.171                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_36:PIN5 (f)
               +     0.045          cell: ADLIB:MSS_IF
  6.216                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_36:PIN5INT (f)
               +     0.237          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPREADYINT_NET
  6.453                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY (f)
                                    
  6.453                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.949          Clock generation
  2.949
               +     1.131          Library hold time: ADLIB:MSS_APB_IP
  4.080                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPREADY
                                    
  4.080                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_fabric_interface_clock

Path 1
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_4_inst/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[4]
  Delay (ns):                  1.369
  Slack (ns):                  1.449
  Arrival (ns):                5.728
  Required (ns):               4.279
  Hold (ns):                   1.330

Path 2
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_12_inst/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[12]
  Delay (ns):                  1.515
  Slack (ns):                  1.603
  Arrival (ns):                5.884
  Required (ns):               4.281
  Hold (ns):                   1.332

Path 3
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_0_inst/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0]
  Delay (ns):                  1.656
  Slack (ns):                  1.748
  Arrival (ns):                6.027
  Required (ns):               4.279
  Hold (ns):                   1.330

Path 4
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_10_inst/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[10]
  Delay (ns):                  1.662
  Slack (ns):                  1.751
  Arrival (ns):                6.031
  Required (ns):               4.280
  Hold (ns):                   1.331

Path 5
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_8_inst/U1:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[8]
  Delay (ns):                  1.678
  Slack (ns):                  1.770
  Arrival (ns):                6.051
  Required (ns):               4.281
  Hold (ns):                   1.332


Expanded Path 1
  From: Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_4_inst/U1:CLK
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[4]
  data arrival time                              5.728
  data required time                         -   4.279
  slack                                          1.449
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.324          net: FAB_CLK
  4.359                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_4_inst/U1:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  4.607                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_4_inst/U1:Q (r)
               +     0.181          net: DFN1E1C0_Q_4_inst
  4.788                        CoreAPB3_0/CAPB3llOI/PRDATA_4:A (r)
               +     0.209          cell: ADLIB:NOR2B
  4.997                        CoreAPB3_0/CAPB3llOI/PRDATA_4:Y (r)
               +     0.421          net: PRDATA_4
  5.418                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_38:PIN5 (r)
               +     0.102          cell: ADLIB:MSS_IF
  5.520                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_38:PIN5INT (r)
               +     0.208          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPRDATA[4]INT_NET
  5.728                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[4] (r)
                                    
  5.728                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.949          Clock generation
  2.949
               +     1.330          Library hold time: ADLIB:MSS_APB_IP
  4.279                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[4]
                                    
  4.279                        data required time


END SET mss_ccc_gla1 to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_pclk1

Path 1
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[1]
  Delay (ns):                  0.874
  Slack (ns):                  1.517
  Arrival (ns):                5.262
  Required (ns):               3.745
  Hold (ns):                   0.796

Path 2
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1P0_EMPTY:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[3]
  Delay (ns):                  1.310
  Slack (ns):                  1.857
  Arrival (ns):                5.669
  Required (ns):               3.812
  Hold (ns):                   0.863

Path 3
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ifo_loadOn:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[0]
  Delay (ns):                  1.223
  Slack (ns):                  1.881
  Arrival (ns):                5.639
  Required (ns):               3.758
  Hold (ns):                   0.809

Path 4
  From:                        Aapb_int_fft_0/fifo64X16_inst/DFN1P0_AEMPTY:CLK
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[2]
  Delay (ns):                  1.424
  Slack (ns):                  2.047
  Arrival (ns):                5.813
  Required (ns):               3.766
  Hold (ns):                   0.817


Expanded Path 1
  From: Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn:CLK
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[1]
  data arrival time                              5.262
  data required time                         -   3.745
  slack                                          1.517
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.353          net: FAB_CLK
  4.388                        Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  4.636                        Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/outBuf_rEn:Q (r)
               +     0.589          net: Aapb_int_fft_0_FFT_OP_RDY
  5.225                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_21:PIN5 (r)
               +     0.037          cell: ADLIB:MSS_IF
  5.262                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_21:PIN5INT (r)
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/GPI[1]INT_NET
  5.262                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[1] (r)
                                    
  5.262                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_pclk1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     2.949          Clock generation
  2.949
               +     0.796          Library hold time: ADLIB:MSS_APB_IP
  3.745                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[1]
                                    
  3.745                        data required time


END SET mss_ccc_gla1 to mss_pclk1

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        Aapb_int_fft_0/fftTop_inst/preBflySw_0/rightP_r[4]:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/preBflySw_0/outP[4]:D
  Delay (ns):                  0.393
  Slack (ns):                  0.341
  Arrival (ns):                4.764
  Required (ns):               4.423
  Hold (ns):                   0.000

Path 2
  From:                        Aapb_int_fft_0/fftTop_inst/bfly_0/pipe2[1]:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/bfly_0/pipe3[1]:D
  Delay (ns):                  0.393
  Slack (ns):                  0.342
  Arrival (ns):                4.799
  Required (ns):               4.457
  Hold (ns):                   0.000

Path 3
  From:                        Aapb_int_fft_0/fftTop_inst/bfly_0/PrT2_r[0]:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/bfly_0/PrT3_r[0]:D
  Delay (ns):                  0.393
  Slack (ns):                  0.342
  Arrival (ns):                4.799
  Required (ns):               4.457
  Hold (ns):                   0.000

Path 4
  From:                        Aapb_int_fft_0/fftTop_inst/bfly_0/PrT5_r[1]:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/bfly_0/PrT6_r[1]:D
  Delay (ns):                  0.393
  Slack (ns):                  0.346
  Arrival (ns):                4.772
  Required (ns):               4.426
  Hold (ns):                   0.000

Path 5
  From:                        Aapb_int_fft_0/fftTop_inst/bfly_0/PrT3_r[2]:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/bfly_0/PrT4_r[2]:D
  Delay (ns):                  0.393
  Slack (ns):                  0.346
  Arrival (ns):                4.781
  Required (ns):               4.435
  Hold (ns):                   0.000


Expanded Path 1
  From: Aapb_int_fft_0/fftTop_inst/preBflySw_0/rightP_r[4]:CLK
  To: Aapb_int_fft_0/fftTop_inst/preBflySw_0/outP[4]:D
  data arrival time                              4.764
  data required time                         -   4.423
  slack                                          0.341
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.336          net: FAB_CLK
  4.371                        Aapb_int_fft_0/fftTop_inst/preBflySw_0/rightP_r[4]:CLK (r)
               +     0.248          cell: ADLIB:DFN1
  4.619                        Aapb_int_fft_0/fftTop_inst/preBflySw_0/rightP_r[4]:Q (r)
               +     0.145          net: Aapb_int_fft_0/fftTop_inst/preBflySw_0/rightP_r[4]
  4.764                        Aapb_int_fft_0/fftTop_inst/preBflySw_0/outP[4]:D (r)
                                    
  4.764                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.388          net: FAB_CLK
  4.423                        Aapb_int_fft_0/fftTop_inst/preBflySw_0/outP[4]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1
  4.423                        Aapb_int_fft_0/fftTop_inst/preBflySw_0/outP[4]:D
                                    
  4.423                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/rdFFTtimer_0/rA_timer/Q[3]:CLR
  Delay (ns):                  3.398
  Slack (ns):                  3.306
  Arrival (ns):                7.763
  Required (ns):               4.457
  Removal (ns):                0.000
  Skew (ns):                   -0.092

Path 2
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/rdFFTtimer_0/rA_timer/Q[6]:CLR
  Delay (ns):                  3.398
  Slack (ns):                  3.306
  Arrival (ns):                7.763
  Required (ns):               4.457
  Removal (ns):                0.000
  Skew (ns):                   -0.092

Path 3
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/inBuf_ldA_0/ldCount/tc:CLR
  Delay (ns):                  3.391
  Slack (ns):                  3.314
  Arrival (ns):                7.756
  Required (ns):               4.442
  Removal (ns):                0.000
  Skew (ns):                   -0.077

Path 4
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/outBufA_0/wA[6]:CLR
  Delay (ns):                  3.391
  Slack (ns):                  3.320
  Arrival (ns):                7.756
  Required (ns):               4.436
  Removal (ns):                0.000
  Skew (ns):                   -0.071

Path 5
  From:                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK
  To:                          Aapb_int_fft_0/fftTop_inst/smTop_0/smPong:PRE
  Delay (ns):                  3.390
  Slack (ns):                  3.320
  Arrival (ns):                7.755
  Required (ns):               4.435
  Removal (ns):                0.000
  Skew (ns):                   -0.070


Expanded Path 1
  From: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK
  To: Aapb_int_fft_0/fftTop_inst/smTop_0/rdFFTtimer_0/rA_timer/Q[3]:CLR
  data arrival time                              7.763
  data required time                         -   4.457
  slack                                          3.306
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.330          net: FAB_CLK
  4.365                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:CLK (r)
               +     0.319          cell: ADLIB:DFN1P0
  4.684                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit:Q (f)
               +     0.950          net: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/initRst
  5.634                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835:B (f)
               +     0.209          cell: ADLIB:NOR2A
  5.843                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835:Y (r)
               +     1.215          net: Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835
  7.058                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835_0/U_CLKSRC:A (r)
               +     0.390          cell: ADLIB:CLKSRC
  7.448                        Aapb_int_fft_0/fftTop_inst/smTop_0/twid_wA_0/twidInit_RNIQ835_0/U_CLKSRC:Y (r)
               +     0.315          net: Aapb_int_fft_0/fftTop_inst/smTop_0/nGrst
  7.763                        Aapb_int_fft_0/fftTop_inst/smTop_0/rdFFTtimer_0/rA_timer/Q[3]:CLR (r)
                                    
  7.763                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.422          net: FAB_CLK
  4.457                        Aapb_int_fft_0/fftTop_inst/smTop_0/rdFFTtimer_0/rA_timer/Q[3]:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1E1C0
  4.457                        Aapb_int_fft_0/fftTop_inst/smTop_0/rdFFTtimer_0/rA_timer/Q[3]:CLR
                                    
  4.457                        data required time


END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_gla1

Path 1
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/PENABLE_reg:D
  Delay (ns):                  2.410
  Slack (ns):                  0.985
  Arrival (ns):                5.359
  Required (ns):               4.374
  Hold (ns):                   0.000

Path 2
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fftTop_inst/inBuf_0/piBuf/memP/wrapRam_0/actram_R0C0:WD15
  Delay (ns):                  2.797
  Slack (ns):                  1.208
  Arrival (ns):                5.746
  Required (ns):               4.538
  Hold (ns):                   0.000

Path 3
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fftTop_inst/inBuf_0/piBuf/memP/wrapRam_0/actram_R0C0:WD11
  Delay (ns):                  2.861
  Slack (ns):                  1.272
  Arrival (ns):                5.810
  Required (ns):               4.538
  Hold (ns):                   0.000

Path 4
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fftTop_inst/inBuf_0/poBuf/memP/wrapRam_0/actram_R0C0:WD0
  Delay (ns):                  2.951
  Slack (ns):                  1.362
  Arrival (ns):                5.900
  Required (ns):               4.538
  Hold (ns):                   0.000

Path 5
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          Aapb_int_fft_0/fftTop_inst/inBuf_0/piBuf/memP/wrapRam_0/actram_R0C0:WD7
  Delay (ns):                  2.954
  Slack (ns):                  1.365
  Arrival (ns):                5.903
  Required (ns):               4.538
  Hold (ns):                   0.000


Expanded Path 1
  From: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To: Aapb_int_fft_0/PENABLE_reg:D
  data arrival time                              5.359
  data required time                         -   4.374
  slack                                          0.985
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.949          Clock generation
  2.949
               +     1.283          cell: ADLIB:MSS_APB_IP
  4.232                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPENABLE (r)
               +     0.058          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/MSSPENABLEINT_NET
  4.290                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_42:PIN2INT (r)
               +     0.044          cell: ADLIB:MSS_IF
  4.334                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_42:PIN2 (r)
               +     0.720          net: CoreAPB3_0_APBmslave0_PENABLE
  5.054                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST_RNI69K1:A (r)
               +     0.158          cell: ADLIB:INV
  5.212                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST_RNI69K1:Y (f)
               +     0.147          net: CoreAPB3_0_APBmslave0_PENABLE_i
  5.359                        Aapb_int_fft_0/PENABLE_reg:D (f)
                                    
  5.359                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.339          net: FAB_CLK
  4.374                        Aapb_int_fft_0/PENABLE_reg:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1P0
  4.374                        Aapb_int_fft_0/PENABLE_reg:D
                                    
  4.374                        data required time


END SET mss_fabric_interface_clock to mss_ccc_gla1

----------------------------------------------------

SET mss_ccc_gla0 to mss_ccc_gla1

Path 1
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_1_inst/U1:CLR
  Delay (ns):                  2.173
  Slack (ns):                  0.724
  Arrival (ns):                5.122
  Required (ns):               4.398
  Hold (ns):

Path 2
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/PREADY0:PRE
  Delay (ns):                  2.267
  Slack (ns):                  0.814
  Arrival (ns):                5.216
  Required (ns):               4.402
  Hold (ns):

Path 3
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/fifo64X16_inst/DFN1C0_MEM_RADDR_0_inst:CLR
  Delay (ns):                  2.267
  Slack (ns):                  0.814
  Arrival (ns):                5.216
  Required (ns):               4.402
  Hold (ns):

Path 4
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/PREADY1:PRE
  Delay (ns):                  2.267
  Slack (ns):                  0.814
  Arrival (ns):                5.216
  Required (ns):               4.402
  Hold (ns):

Path 5
  From:                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          Aapb_int_fft_0/EMPTY_OUT_REG/U1:CLR
  Delay (ns):                  2.312
  Slack (ns):                  0.838
  Arrival (ns):                5.261
  Required (ns):               4.423
  Hold (ns):


Expanded Path 1
  From: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK
  To: Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_1_inst/U1:CLR
  data arrival time                              5.122
  data required time                         -   4.398
  slack                                          0.724
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  2.724
               +     0.225          net: DSP_Coprocessor_MSS_0/GLA0
  2.949                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.564          cell: ADLIB:MSS_APB_IP
  4.513                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:M2FRESETn (r)
               +     0.059          net: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/M2FRESETnINT_NET
  4.572                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_46:PIN2INT (r)
               +     0.044          cell: ADLIB:MSS_IF
  4.616                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_46:PIN2 (r)
               +     0.506          net: DSP_Coprocessor_MSS_0_M2F_RESET_N
  5.122                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_1_inst/U1:CLR (r)
                                    
  5.122                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.363          net: FAB_CLK
  4.398                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_1_inst/U1:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1C0
  4.398                        Aapb_int_fft_0/fifo64X16_inst/DFN1E1C0_Q_1_inst/U1:CLR
                                    
  4.398                        data required time


END SET mss_ccc_gla0 to mss_ccc_gla1

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.276
  Slack (ns):
  Arrival (ns):                0.276
  Required (ns):
  Hold (ns):                   1.289
  External Hold (ns):          4.007


Expanded Path 1
  From: MSS_RESET_N
  To: DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.276
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        DSP_Coprocessor_MSS_0/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.276          cell: ADLIB:IOPAD_IN
  0.276                        DSP_Coprocessor_MSS_0/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: DSP_Coprocessor_MSS_0/MSS_RESET_0_MSS_RESET_N_Y
  0.276                        DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.276                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          DSP_Coprocessor_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  N/C
               +     0.270          net: DSP_Coprocessor_MSS_0/GLA0
  N/C                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.289          Library hold time: ADLIB:MSS_APB_IP
  N/C                          DSP_Coprocessor_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain DSP_Coprocessor_MSS_0/MSS_CCC_0/I_RCOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

