library verilog;
use verilog.vl_types.all;
entity counter is
    generic(
        WIDTH           : integer := 7;
        \TC\            : integer := 127
    );
    port(
        clk             : in     vl_logic;
        nGrst           : in     vl_logic;
        rst             : in     vl_logic;
        cntEn           : in     vl_logic;
        tc              : out    vl_logic;
        Q               : out    vl_logic_vector
    );
end counter;
