/*******************************************************************************
 Copyright 2007 Actel Corporation.  All rights reserved.
 
 ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
 ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
 IN ADVANCE IN WRITING.

 Revision 3.0 April 30, 2007 : v3.0 CoreFFT Release
*******************************************************************************/
`timescale 1 ns/100 ps

`ifndef HEADER
  `define HEADER  1
  `define DEBUG   0
  // Define global FFT parameters
  `define PTS     256     // Number of FFT points 
  `define LOGPTS    8     // Log2(PTS) = Total number of stages
  `define LOGLOGPTS 3     // Width of the stage counter 
  `define WIDTH    8    // FFT bit resolution: length of a re or im sample
  `define TWIDTH   8    // Twiddle, sin or cos bit resolution
  `define HALFPTS  `PTS/2      // Num of FFT points (PTS) divided by 2
  `define DWIDTH   2*`WIDTH    // width of a complex input word,
  `define TDWIDTH  2*`TWIDTH   // width of a complex twiddle factor
  `define RND_MODE 1 
  `define SCALE_MODE 1 
  `define inBuf_RWDLY 12    // HW pipeline delay btwn inBuf rA and wA

// ================================ Primitives =================================
// rising-falling edge detector
module edgeDetect (clk, clkEn, in, out);
  // if (INPIPE=1) insert input pipeline reg
  parameter INPIPE = 0;
  // If FEDGE==1 detect falling edge, else - rising edge
  parameter FEDGE = 0;

  input clk, clkEn, in;
  output reg out;

  reg in_pipe, in_t1;
  wire in_w = INPIPE ? (in_pipe) : in;
  wire out_w = FEDGE ? ( (~in_w) & in_t1 ) : ( in_w & (~in_t1) );

  always @ (posedge clk) begin
    in_pipe <= #1 in;
    in_t1   <= #1 in_w;
    out <= #1 out_w;
  end
endmodule

// Counts to TC.  Generates tc when Q == TC
module counter (clk, nGrst, rst, cntEn, tc, Q);
  parameter
    WIDTH = 7,
    TC =    127;
  input clk, cntEn;
  input nGrst, rst;
  output reg tc;
  output reg[WIDTH-1:0] Q;

  always @ (posedge clk or negedge nGrst) begin
    if(!nGrst) 
      begin Q <= 0;  tc <= 0;  end
    else 
      begin
        if(rst)  
          begin Q <= 0;  tc  <= 0;  end
        else
          begin    
            if(cntEn) 
              begin
                tc <= #1 (Q==(TC-1));
                if ( Q == TC)  Q <= #1 0;
                else           Q <= #1 Q + 1;
              end
          end
      end   
  end // always
endmodule

// binary counter
module bcounter (clk, nGrst, rst, cntEn, Q);
  parameter WIDTH = 7;

  input clk, cntEn;
  input nGrst, rst;   // async Global & sync resets
  output reg[WIDTH-1:0] Q;

  always @ (posedge clk or negedge nGrst) begin
    if(!nGrst) Q <= 0;
    else
      if(cntEn) begin
        if(rst)   Q <= 0;
        else      Q <= #1 Q + 1;
        end
  end
endmodule
// =============== End Primitives ===============
`endif
