library verilog;
use verilog.vl_types.all;
entity outBufA is
    generic(
        PTS             : integer := 256;
        LOGPTS          : integer := 8
    );
    port(
        clk             : in     vl_logic;
        clkEn           : in     vl_logic;
        nGrst           : in     vl_logic;
        rst             : in     vl_logic;
        timer           : in     vl_logic_vector;
        outBuf_wEn      : in     vl_logic;
        rdCtl           : in     vl_logic;
        wA              : out    vl_logic_vector;
        rA              : out    vl_logic_vector;
        outBuf_rEn      : out    vl_logic;
        rdValid         : out    vl_logic
    );
end outBufA;
