library verilog;
use verilog.vl_types.all;
entity twid_wA is
    generic(
        LOGPTS          : integer := 8;
        LOGLOGPTS       : integer := 3
    );
    port(
        clk             : in     vl_logic;
        ifiNreset       : in     vl_logic;
        twid_wA         : out    vl_logic_vector;
        twid_wEn        : out    vl_logic;
        rstAfterInit    : out    vl_logic;
        twidInit        : out    vl_logic
    );
end twid_wA;
