library verilog;
use verilog.vl_types.all;
entity actar is
    port(
        DataA           : in     vl_logic_vector(7 downto 0);
        DataB           : in     vl_logic_vector(7 downto 0);
        Mult            : out    vl_logic_vector(15 downto 0);
        Clock           : in     vl_logic
    );
end actar;
