library verilog;
use verilog.vl_types.all;
entity inBuf_ldA is
    generic(
        PTS             : integer := 256;
        LOGPTS          : integer := 8
    );
    port(
        clk             : in     vl_logic;
        clkEn           : in     vl_logic;
        nGrst           : in     vl_logic;
        startLoad       : in     vl_logic;
        ifi_dataRdy     : in     vl_logic;
        ifo_loadOn      : out    vl_logic;
        load_done       : out    vl_logic;
        ldA             : out    vl_logic_vector;
        wEn_even        : out    vl_logic;
        wEn_odd         : out    vl_logic;
        ldValid         : out    vl_logic
    );
end inBuf_ldA;
