-- Version: 9.0 SP2 9.0.3.3

library ieee;
use ieee.std_logic_1164.all;
--library proasic3;
--use proasic3.all;

entity actar is 
    port( DataA : in std_logic_vector(7 downto 0); DataB : in 
        std_logic_vector(7 downto 0); Mult : out 
        std_logic_vector(15 downto 0);Clock : in std_logic) ;
end actar;


architecture DEF_ARCH of  actar is

    component DFN1
        port(D, CLK : in std_logic := 'U'; Q : out std_logic) ;
    end component;

    component MAJ3
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component AND2
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component NOR2
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component AO1
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component XOR2
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component BUFF
        port(A : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component MX2
        port(A, B, S : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component AOI1
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component OR3
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component AND2A
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component AND3
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component XNOR2
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component XOR3
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component VCC
        port( Y : out std_logic);
    end component;

    component GND
        port( Y : out std_logic);
    end component;

    signal S_0_net, S_1_net, S_2_net, S_3_net, E_0_net, E_1_net, 
        E_2_net, E_3_net, EBAR, PP0_0_net, PP0_1_net, PP0_2_net, 
        PP0_3_net, PP0_4_net, PP0_5_net, PP0_6_net, PP0_7_net, 
        PP0_8_net, PP1_0_net, PP1_1_net, PP1_2_net, PP1_3_net, 
        PP1_4_net, PP1_5_net, PP1_6_net, PP1_7_net, PP1_8_net, 
        PP2_0_net, PP2_1_net, PP2_2_net, PP2_3_net, PP2_4_net, 
        PP2_5_net, PP2_6_net, PP2_7_net, PP2_8_net, PP3_0_net, 
        PP3_1_net, PP3_2_net, PP3_3_net, PP3_4_net, PP3_5_net, 
        PP3_6_net, PP3_7_net, PP3_8_net, SumA_0_net, SumA_1_net, 
        SumA_2_net, SumA_3_net, SumA_4_net, SumA_5_net, 
        SumA_6_net, SumA_7_net, SumA_8_net, SumA_9_net, 
        SumA_10_net, SumA_11_net, SumA_12_net, SumA_13_net, 
        SumA_14_net, SumB_0_net, SumB_1_net, SumB_2_net, 
        SumB_3_net, SumB_4_net, SumB_5_net, SumB_6_net, 
        SumB_7_net, SumB_8_net, SumB_9_net, SumB_10_net, 
        SumB_11_net, SumB_12_net, SumB_13_net, SumB_14_net, 
        DFN1_30_Q, DFN1_32_Q, DFN1_11_Q, DFN1_25_Q, DFN1_2_Q, 
        DFN1_35_Q, DFN1_1_Q, DFN1_24_Q, DFN1_4_Q, DFN1_7_Q, 
        DFN1_15_Q, DFN1_0_Q, DFN1_22_Q, DFN1_9_Q, DFN1_37_Q, 
        DFN1_31_Q, DFN1_26_Q, DFN1_36_Q, DFN1_13_Q, DFN1_28_Q, 
        DFN1_20_Q, DFN1_3_Q, DFN1_27_Q, DFN1_12_Q, DFN1_41_Q, 
        DFN1_38_Q, DFN1_29_Q, DFN1_40_Q, DFN1_17_Q, DFN1_33_Q, 
        DFN1_43_Q, DFN1_23_Q, DFN1_5_Q, DFN1_39_Q, DFN1_18_Q, 
        DFN1_14_Q, DFN1_8_Q, DFN1_16_Q, DFN1_42_Q, DFN1_10_Q, 
        DFN1_21_Q, DFN1_6_Q, DFN1_34_Q, DFN1_19_Q, DFN1_44_Q, 
        XOR2_10_Y, AND2_30_Y, XOR2_1_Y, AND2_7_Y, XOR2_43_Y, 
        AND2_3_Y, XOR2_26_Y, AND2_68_Y, XOR2_6_Y, AND2_62_Y, 
        XOR2_4_Y, AND2_15_Y, XOR3_11_Y, MAJ3_2_Y, XOR3_9_Y, 
        MAJ3_4_Y, XOR3_14_Y, MAJ3_13_Y, XOR3_5_Y, MAJ3_14_Y, 
        XOR3_16_Y, MAJ3_10_Y, XOR3_8_Y, MAJ3_3_Y, XOR3_1_Y, 
        MAJ3_1_Y, XOR3_15_Y, MAJ3_0_Y, XOR2_24_Y, AND2_59_Y, 
        XOR3_4_Y, MAJ3_5_Y, XOR3_6_Y, MAJ3_9_Y, XOR3_10_Y, 
        MAJ3_12_Y, XOR3_0_Y, MAJ3_8_Y, XOR3_2_Y, MAJ3_16_Y, 
        XOR3_13_Y, MAJ3_15_Y, XOR3_12_Y, MAJ3_6_Y, XOR2_36_Y, 
        AND2_53_Y, XOR3_3_Y, MAJ3_7_Y, XOR3_7_Y, MAJ3_11_Y, 
        BUFF_6_Y, BUFF_3_Y, BUFF_4_Y, BUFF_10_Y, XOR2_15_Y, 
        XOR2_3_Y, AO1_22_Y, XOR2_21_Y, NOR2_1_Y, AND2_40_Y, 
        MX2_19_Y, AND2_21_Y, MX2_6_Y, MX2_23_Y, XNOR2_7_Y, 
        XOR2_49_Y, NOR2_3_Y, AND2_38_Y, MX2_25_Y, AND2_64_Y, 
        MX2_1_Y, AND2_10_Y, MX2_14_Y, XNOR2_5_Y, XOR2_19_Y, 
        NOR2_0_Y, AND2_32_Y, MX2_2_Y, AND2_20_Y, AND2_56_Y, 
        MX2_24_Y, XNOR2_0_Y, OR3_0_Y, AND3_3_Y, BUFF_2_Y, 
        BUFF_0_Y, BUFF_1_Y, BUFF_5_Y, XOR2_35_Y, XOR2_45_Y, 
        AO1_32_Y, XOR2_50_Y, NOR2_2_Y, AND2_27_Y, MX2_27_Y, 
        AND2_69_Y, MX2_8_Y, MX2_26_Y, XNOR2_1_Y, XOR2_31_Y, 
        NOR2_8_Y, AND2_76_Y, MX2_16_Y, AND2_65_Y, MX2_29_Y, 
        AND2_8_Y, MX2_15_Y, XNOR2_2_Y, XOR2_44_Y, NOR2_4_Y, 
        AND2_79_Y, MX2_31_Y, AND2_39_Y, AND2_81_Y, MX2_4_Y, 
        XNOR2_4_Y, OR3_3_Y, AND3_1_Y, BUFF_12_Y, BUFF_8_Y, 
        BUFF_11_Y, BUFF_14_Y, XOR2_28_Y, XOR2_17_Y, AO1_12_Y, 
        XOR2_5_Y, NOR2_7_Y, AND2_49_Y, MX2_11_Y, AND2_71_Y, 
        MX2_17_Y, MX2_7_Y, XNOR2_8_Y, XOR2_20_Y, NOR2_6_Y, 
        AND2_28_Y, MX2_12_Y, AND2_4_Y, MX2_20_Y, AND2_41_Y, 
        MX2_28_Y, XNOR2_3_Y, XOR2_37_Y, NOR2_5_Y, AND2_54_Y, 
        MX2_30_Y, AND2_45_Y, AND2_25_Y, MX2_9_Y, XNOR2_6_Y, 
        OR3_1_Y, AND3_0_Y, BUFF_7_Y, BUFF_9_Y, BUFF_13_Y, 
        XOR2_53_Y, XOR2_13_Y, AND2A_2_Y, AND2_22_Y, MX2_0_Y, 
        AND2_37_Y, MX2_21_Y, MX2_18_Y, AND2A_1_Y, AND2_63_Y, 
        MX2_13_Y, AND2_5_Y, MX2_22_Y, AND2_47_Y, MX2_3_Y, 
        AND2A_0_Y, AND2_44_Y, MX2_10_Y, AND2_18_Y, AND2_31_Y, 
        MX2_5_Y, OR3_2_Y, AND3_2_Y, AND2_51_Y, AND2_73_Y, 
        AND2_19_Y, AND2_50_Y, AND2_55_Y, AND2_83_Y, AND2_23_Y, 
        AND2_60_Y, AND2_12_Y, AND2_24_Y, AND2_35_Y, AND2_33_Y, 
        AND2_2_Y, AND2_43_Y, XOR2_0_Y, XOR2_8_Y, XOR2_41_Y, 
        XOR2_39_Y, XOR2_2_Y, XOR2_46_Y, XOR2_16_Y, XOR2_7_Y, 
        XOR2_47_Y, XOR2_29_Y, XOR2_42_Y, XOR2_23_Y, XOR2_33_Y, 
        XOR2_9_Y, XOR2_32_Y, AND2_36_Y, AO1_9_Y, AND2_72_Y, 
        AO1_28_Y, AND2_82_Y, AO1_13_Y, AND2_77_Y, AO1_2_Y, 
        AND2_9_Y, AO1_17_Y, AND2_66_Y, AO1_20_Y, AND2_80_Y, 
        AND2_48_Y, AND2_67_Y, AO1_15_Y, AND2_84_Y, AO1_7_Y, 
        AND2_70_Y, AO1_5_Y, AND2_14_Y, AO1_16_Y, AND2_34_Y, 
        AO1_29_Y, AND2_26_Y, AO1_31_Y, AND2_52_Y, AND2_57_Y, 
        AND2_75_Y, AND2_42_Y, AND2_58_Y, AO1_27_Y, AND2_78_Y, 
        AO1_14_Y, AND2_61_Y, AO1_11_Y, AND2_6_Y, AO1_19_Y, 
        AND2_17_Y, AND2_11_Y, AND2_46_Y, AND2_0_Y, AND2_16_Y, 
        AND2_74_Y, AND2_1_Y, AO1_30_Y, AND2_29_Y, AND2_13_Y, 
        AO1_3_Y, AO1_8_Y, AO1_6_Y, AO1_4_Y, AO1_21_Y, AO1_24_Y, 
        AO1_18_Y, AO1_0_Y, AO1_1_Y, AO1_10_Y, AO1_25_Y, AO1_26_Y, 
        AO1_23_Y, XOR2_51_Y, XOR2_18_Y, XOR2_22_Y, XOR2_14_Y, 
        XOR2_12_Y, XOR2_40_Y, XOR2_52_Y, XOR2_34_Y, XOR2_27_Y, 
        XOR2_25_Y, XOR2_48_Y, XOR2_11_Y, XOR2_38_Y, XOR2_30_Y, 
        VCC_1_net, GND_1_net : std_logic ;
    begin   

    VCC_2_net : VCC port map(Y => VCC_1_net);
    GND_2_net : GND port map(Y => GND_1_net);
    DFN1_22 : DFN1
      port map(D => PP1_3_net, CLK => Clock, Q => DFN1_22_Q);
    MAJ3_16 : MAJ3
      port map(A => XOR3_9_Y, B => MAJ3_2_Y, C => XOR2_10_Y, Y => 
        MAJ3_16_Y);
    AND2_2 : AND2
      port map(A => SumA_13_net, B => SumB_13_net, Y => AND2_2_Y);
    NOR2_2 : NOR2
      port map(A => XOR2_50_Y, B => XNOR2_1_Y, Y => NOR2_2_Y);
    AND2_20 : AND2
      port map(A => XOR2_19_Y, B => DataA(0), Y => AND2_20_Y);
    DFN1_SumA_5_inst : DFN1
      port map(D => MAJ3_9_Y, CLK => Clock, Q => SumA_5_net);
    AO1_11 : AO1
      port map(A => AND2_80_Y, B => AO1_29_Y, C => AO1_20_Y, Y => 
        AO1_11_Y);
    XOR2_PP1_4_inst : XOR2
      port map(A => MX2_25_Y, B => BUFF_4_Y, Y => PP1_4_net);
    AND2_11 : AND2
      port map(A => AND2_58_Y, B => XOR2_47_Y, Y => AND2_11_Y);
    XOR2_PP3_6_inst : XOR2
      port map(A => MX2_8_Y, B => BUFF_5_Y, Y => PP3_6_net);
    XOR2_PP0_6_inst : XOR2
      port map(A => MX2_21_Y, B => BUFF_13_Y, Y => PP0_6_net);
    BUFF_10 : BUFF
      port map(A => DataB(3), Y => BUFF_10_Y);
    XOR2_PP2_6_inst : XOR2
      port map(A => MX2_17_Y, B => BUFF_14_Y, Y => PP2_6_net);
    DFN1_SumA_7_inst : DFN1
      port map(D => MAJ3_16_Y, CLK => Clock, Q => SumA_7_net);
    AND2_22 : AND2
      port map(A => DataB(0), B => DataA(7), Y => AND2_22_Y);
    AND2_71 : AND2
      port map(A => XOR2_5_Y, B => DataA(6), Y => AND2_71_Y);
    XOR2_19 : XOR2
      port map(A => BUFF_6_Y, B => DataB(2), Y => XOR2_19_Y);
    XOR2_PP0_5_inst : XOR2
      port map(A => MX2_3_Y, B => BUFF_9_Y, Y => PP0_5_net);
    AND2_44 : AND2
      port map(A => DataB(0), B => DataA(1), Y => AND2_44_Y);
    AO1_31 : AO1
      port map(A => XOR2_32_Y, B => AO1_20_Y, C => AND2_43_Y, 
        Y => AO1_31_Y);
    XOR2_23 : XOR2
      port map(A => SumA_11_net, B => SumB_11_net, Y => XOR2_23_Y);
    XOR2_1 : XOR2
      port map(A => DFN1_31_Q, B => DFN1_4_Q, Y => XOR2_1_Y);
    DFN1_SumB_9_inst : DFN1
      port map(D => XOR3_15_Y, CLK => Clock, Q => SumB_9_net);
    MX2_17 : MX2
      port map(A => AND2_71_Y, B => DataA(5), S => NOR2_7_Y, Y => 
        MX2_17_Y);
    DFN1_3 : DFN1
      port map(D => PP2_3_net, CLK => Clock, Q => DFN1_3_Q);
    AND2_S_3_inst : AND2
      port map(A => XOR2_35_Y, B => DataB(7), Y => S_3_net);
    AO1_EBAR : AO1
      port map(A => XOR2_13_Y, B => OR3_2_Y, C => AND3_2_Y, Y => 
        EBAR);
    BUFF_8 : BUFF
      port map(A => DataB(5), Y => BUFF_8_Y);
    MAJ3_8 : MAJ3
      port map(A => XOR3_1_Y, B => MAJ3_3_Y, C => AND2_62_Y, Y => 
        MAJ3_8_Y);
    MX2_PP2_8_inst : MX2
      port map(A => MX2_7_Y, B => AO1_12_Y, S => NOR2_7_Y, Y => 
        PP2_8_net);
    DFN1_41 : DFN1
      port map(D => PP2_6_net, CLK => Clock, Q => DFN1_41_Q);
    XOR2_PP1_0_inst : XOR2
      port map(A => XOR2_15_Y, B => DataB(3), Y => PP1_0_net);
    XOR2_47 : XOR2
      port map(A => SumA_8_net, B => SumB_8_net, Y => XOR2_47_Y);
    XOR2_38 : XOR2
      port map(A => SumA_13_net, B => SumB_13_net, Y => XOR2_38_Y);
    MX2_21 : MX2
      port map(A => AND2_37_Y, B => DataA(5), S => AND2A_2_Y, 
        Y => MX2_21_Y);
    DFN1_8 : DFN1
      port map(D => S_0_net, CLK => Clock, Q => DFN1_8_Q);
    AO1_7 : AO1
      port map(A => XOR2_16_Y, B => AO1_28_Y, C => AND2_83_Y, 
        Y => AO1_7_Y);
    DFN1_43 : DFN1
      port map(D => PP3_3_net, CLK => Clock, Q => DFN1_43_Q);
    AOI1_E_2_inst : AOI1
      port map(A => XOR2_17_Y, B => OR3_1_Y, C => AND3_0_Y, Y => 
        E_2_net);
    XOR2_PP2_4_inst : XOR2
      port map(A => MX2_12_Y, B => BUFF_11_Y, Y => PP2_4_net);
    AND2_18 : AND2
      port map(A => DataB(0), B => DataA(0), Y => AND2_18_Y);
    AND2_15 : AND2
      port map(A => DFN1_22_Q, B => DFN1_35_Q, Y => AND2_15_Y);
    AND2_84 : AND2
      port map(A => AND2_36_Y, B => AND2_72_Y, Y => AND2_84_Y);
    AO1_25 : AO1
      port map(A => AND2_26_Y, B => AO1_18_Y, C => AO1_29_Y, Y => 
        AO1_25_Y);
    NOR2_6 : NOR2
      port map(A => XOR2_20_Y, B => XNOR2_3_Y, Y => NOR2_6_Y);
    AND2_78 : AND2
      port map(A => AND2_84_Y, B => AND2_14_Y, Y => AND2_78_Y);
    AND2_75 : AND2
      port map(A => AND2_67_Y, B => AND2_82_Y, Y => AND2_75_Y);
    DFN1_Mult_0_inst : DFN1
      port map(D => DFN1_30_Q, CLK => Clock, Q => Mult(0));
    XOR2_45 : XOR2
      port map(A => DataA(7), B => DataB(7), Y => XOR2_45_Y);
    MAJ3_9 : MAJ3
      port map(A => XOR2_4_Y, B => DFN1_42_Q, C => DFN1_28_Q, 
        Y => MAJ3_9_Y);
    AND2_S_0_inst : AND2
      port map(A => XOR2_53_Y, B => DataB(1), Y => S_0_net);
    AND2_1 : AND2
      port map(A => AND2_78_Y, B => AND2_6_Y, Y => AND2_1_Y);
    AND2_49 : AND2
      port map(A => XOR2_5_Y, B => DataA(7), Y => AND2_49_Y);
    AO1_8 : AO1
      port map(A => XOR2_41_Y, B => AO1_3_Y, C => AND2_73_Y, Y => 
        AO1_8_Y);
    DFN1_SumB_14_inst : DFN1
      port map(D => AND2_59_Y, CLK => Clock, Q => SumB_14_net);
    AND2_10 : AND2
      port map(A => XOR2_49_Y, B => DataA(5), Y => AND2_10_Y);
    XOR2_20 : XOR2
      port map(A => BUFF_12_Y, B => DataB(4), Y => XOR2_20_Y);
    AND2_7 : AND2
      port map(A => DFN1_31_Q, B => DFN1_4_Q, Y => AND2_7_Y);
    DFN1_SumB_7_inst : DFN1
      port map(D => XOR3_4_Y, CLK => Clock, Q => SumB_7_net);
    AND2_70 : AND2
      port map(A => AND2_82_Y, B => XOR2_16_Y, Y => AND2_70_Y);
    OR3_1 : OR3
      port map(A => DataB(3), B => DataB(4), C => DataB(5), Y => 
        OR3_1_Y);
    AND2_S_1_inst : AND2
      port map(A => XOR2_15_Y, B => DataB(3), Y => S_1_net);
    DFN1_12 : DFN1
      port map(D => PP2_5_net, CLK => Clock, Q => DFN1_12_Q);
    AND2A_1 : AND2A
      port map(A => DataB(0), B => BUFF_9_Y, Y => AND2A_1_Y);
    AND2_12 : AND2
      port map(A => SumA_9_net, B => SumB_9_net, Y => AND2_12_Y);
    XOR2_52 : XOR2
      port map(A => SumA_7_net, B => SumB_7_net, Y => XOR2_52_Y);
    AND2_72 : AND2
      port map(A => XOR2_41_Y, B => XOR2_39_Y, Y => AND2_72_Y);
    AND2_61 : AND2
      port map(A => AND2_26_Y, B => XOR2_33_Y, Y => AND2_61_Y);
    AO1_15 : AO1
      port map(A => AND2_72_Y, B => AO1_3_Y, C => AO1_9_Y, Y => 
        AO1_15_Y);
    MX2_5 : MX2
      port map(A => AND2_31_Y, B => DataA(1), S => AND2A_0_Y, 
        Y => MX2_5_Y);
    DFN1_SumB_8_inst : DFN1
      port map(D => XOR3_3_Y, CLK => Clock, Q => SumB_8_net);
    MX2_25 : MX2
      port map(A => AND2_38_Y, B => DataA(3), S => NOR2_3_Y, Y => 
        MX2_25_Y);
    MAJ3_13 : MAJ3
      port map(A => AND2_30_Y, B => DFN1_33_Q, C => DFN1_27_Q, 
        Y => MAJ3_13_Y);
    XOR2_24 : XOR2
      port map(A => DFN1_14_Q, B => VCC_1_net, Y => XOR2_24_Y);
    AND2_57 : AND2
      port map(A => AND2_67_Y, B => XOR2_2_Y, Y => AND2_57_Y);
    XOR2_21 : XOR2
      port map(A => BUFF_6_Y, B => DataB(2), Y => XOR2_21_Y);
    BUFF_2 : BUFF
      port map(A => DataB(5), Y => BUFF_2_Y);
    DFN1_44 : DFN1
      port map(D => EBAR, CLK => Clock, Q => DFN1_44_Q);
    XOR2_PP0_7_inst : XOR2
      port map(A => MX2_0_Y, B => BUFF_13_Y, Y => PP0_7_net);
    AND2_46 : AND2
      port map(A => AND2_58_Y, B => AND2_9_Y, Y => AND2_46_Y);
    DFN1_25 : DFN1
      port map(D => PP0_3_net, CLK => Clock, Q => DFN1_25_Q);
    XOR2_PP3_7_inst : XOR2
      port map(A => MX2_27_Y, B => BUFF_5_Y, Y => PP3_7_net);
    DFN1_SumB_11_inst : DFN1
      port map(D => XOR3_0_Y, CLK => Clock, Q => SumB_11_net);
    DFN1_30 : DFN1
      port map(D => PP0_0_net, CLK => Clock, Q => DFN1_30_Q);
    DFN1_26 : DFN1
      port map(D => PP1_7_net, CLK => Clock, Q => DFN1_26_Q);
    XOR2_16 : XOR2
      port map(A => SumA_6_net, B => SumB_6_net, Y => XOR2_16_Y);
    MAJ3_12 : MAJ3
      port map(A => XOR3_11_Y, B => AND2_15_Y, C => DFN1_40_Q, 
        Y => MAJ3_12_Y);
    AND2_68 : AND2
      port map(A => DFN1_36_Q, B => DFN1_44_Q, Y => AND2_68_Y);
    AND2_65 : AND2
      port map(A => XOR2_31_Y, B => DataA(3), Y => AND2_65_Y);
    AO1_24 : AO1
      port map(A => AND2_70_Y, B => AO1_15_Y, C => AO1_7_Y, Y => 
        AO1_24_Y);
    AND2_43 : AND2
      port map(A => SumA_14_net, B => SumB_14_net, Y => AND2_43_Y);
    DFN1_27 : DFN1
      port map(D => PP2_4_net, CLK => Clock, Q => DFN1_27_Q);
    NOR2_3 : NOR2
      port map(A => XOR2_49_Y, B => XNOR2_5_Y, Y => NOR2_3_Y);
    AND3_3 : AND3
      port map(A => DataB(1), B => DataB(2), C => DataB(3), Y => 
        AND3_3_Y);
    MX2_20 : MX2
      port map(A => AND2_4_Y, B => DataA(2), S => NOR2_6_Y, Y => 
        MX2_20_Y);
    MX2_19 : MX2
      port map(A => AND2_40_Y, B => DataA(6), S => NOR2_1_Y, Y => 
        MX2_19_Y);
    AND2_6 : AND2
      port map(A => AND2_26_Y, B => AND2_80_Y, Y => AND2_6_Y);
    AND3_0 : AND3
      port map(A => DataB(3), B => DataB(4), C => DataB(5), Y => 
        AND3_0_Y);
    AND2_60 : AND2
      port map(A => SumA_8_net, B => SumB_8_net, Y => AND2_60_Y);
    AND2_83 : AND2
      port map(A => SumA_6_net, B => SumB_6_net, Y => AND2_83_Y);
    XOR2_Mult_5_inst : XOR2
      port map(A => XOR2_14_Y, B => AO1_6_Y, Y => Mult(5));
    DFN1_SumB_1_inst : DFN1
      port map(D => DFN1_7_Q, CLK => Clock, Q => SumB_1_net);
    AND2_62 : AND2
      port map(A => DFN1_6_Q, B => DFN1_21_Q, Y => AND2_62_Y);
    XOR2_33 : XOR2
      port map(A => SumA_12_net, B => SumB_12_net, Y => XOR2_33_Y);
    XNOR2_2 : XNOR2
      port map(A => DataB(6), B => BUFF_1_Y, Y => XNOR2_2_Y);
    MX2_31 : MX2
      port map(A => AND2_79_Y, B => DataA(0), S => NOR2_4_Y, Y => 
        MX2_31_Y);
    XOR2_49 : XOR2
      port map(A => BUFF_6_Y, B => DataB(2), Y => XOR2_49_Y);
    XOR3_13 : XOR3
      port map(A => DFN1_18_Q, B => DFN1_34_Q, C => MAJ3_1_Y, 
        Y => XOR3_13_Y);
    AO1_14 : AO1
      port map(A => XOR2_33_Y, B => AO1_29_Y, C => AND2_33_Y, 
        Y => AO1_14_Y);
    XOR2_4 : XOR2
      port map(A => DFN1_22_Q, B => DFN1_35_Q, Y => XOR2_4_Y);
    AND3_1 : AND3
      port map(A => DataB(5), B => DataB(6), C => DataB(7), Y => 
        AND3_1_Y);
    MX2_14 : MX2
      port map(A => AND2_10_Y, B => DataA(4), S => NOR2_3_Y, Y => 
        MX2_14_Y);
    XOR2_Mult_7_inst : XOR2
      port map(A => XOR2_40_Y, B => AO1_21_Y, Y => Mult(7));
    AND2_24 : AND2
      port map(A => SumA_10_net, B => SumB_10_net, Y => AND2_24_Y);
    XOR2_PP3_3_inst : XOR2
      port map(A => MX2_29_Y, B => BUFF_1_Y, Y => PP3_3_net);
    XNOR2_0 : XNOR2
      port map(A => DataB(2), B => BUFF_3_Y, Y => XNOR2_0_Y);
    MAJ3_0 : MAJ3
      port map(A => XOR3_16_Y, B => MAJ3_14_Y, C => XOR2_26_Y, 
        Y => MAJ3_0_Y);
    AND2_31 : AND2
      port map(A => DataB(0), B => DataA(2), Y => AND2_31_Y);
    MAJ3_14 : MAJ3
      port map(A => AND2_7_Y, B => DFN1_43_Q, C => DFN1_12_Q, 
        Y => MAJ3_14_Y);
    XOR2_PP1_5_inst : XOR2
      port map(A => MX2_14_Y, B => BUFF_4_Y, Y => PP1_5_net);
    XOR2_18 : XOR2
      port map(A => SumA_2_net, B => SumB_2_net, Y => XOR2_18_Y);
    DFN1_6 : DFN1
      port map(D => E_1_net, CLK => Clock, Q => DFN1_6_Q);
    BUFF_14 : BUFF
      port map(A => DataB(5), Y => BUFF_14_Y);
    MX2_PP1_8_inst : MX2
      port map(A => MX2_23_Y, B => AO1_22_Y, S => NOR2_1_Y, Y => 
        PP1_8_net);
    XOR2_Mult_15_inst : XOR2
      port map(A => XOR2_30_Y, B => AO1_23_Y, Y => Mult(15));
    OR3_2 : OR3
      port map(A => GND_1_net, B => DataB(0), C => DataB(1), Y => 
        OR3_2_Y);
    XOR2_8 : XOR2
      port map(A => SumA_1_net, B => SumB_1_net, Y => XOR2_8_Y);
    DFN1_15 : DFN1
      port map(D => PP1_1_net, CLK => Clock, Q => DFN1_15_Q);
    NOR2_0 : NOR2
      port map(A => XOR2_19_Y, B => XNOR2_0_Y, Y => NOR2_0_Y);
    XOR2_30 : XOR2
      port map(A => SumA_14_net, B => SumB_14_net, Y => XOR2_30_Y);
    DFN1_16 : DFN1
      port map(D => S_1_net, CLK => Clock, Q => DFN1_16_Q);
    XOR3_10 : XOR3
      port map(A => AND2_15_Y, B => DFN1_40_Q, C => XOR3_11_Y, 
        Y => XOR3_10_Y);
    XOR2_PP3_2_inst : XOR2
      port map(A => MX2_4_Y, B => BUFF_0_Y, Y => PP3_2_net);
    AND2_38 : AND2
      port map(A => XOR2_49_Y, B => DataA(4), Y => AND2_38_Y);
    AND2_35 : AND2
      port map(A => SumA_11_net, B => SumB_11_net, Y => AND2_35_Y);
    DFN1_7 : DFN1
      port map(D => PP1_0_net, CLK => Clock, Q => DFN1_7_Q);
    XOR2_Mult_13_inst : XOR2
      port map(A => XOR2_11_Y, B => AO1_25_Y, Y => Mult(13));
    DFN1_17 : DFN1
      port map(D => PP3_1_net, CLK => Clock, Q => DFN1_17_Q);
    MX2_8 : MX2
      port map(A => AND2_69_Y, B => DataA(5), S => NOR2_2_Y, Y => 
        MX2_8_Y);
    DFN1_21 : DFN1
      port map(D => E_0_net, CLK => Clock, Q => DFN1_21_Q);
    AND2_29 : AND2
      port map(A => AND2_78_Y, B => AND2_17_Y, Y => AND2_29_Y);
    OR3_3 : OR3
      port map(A => DataB(5), B => DataB(6), C => DataB(7), Y => 
        OR3_3_Y);
    XOR2_34 : XOR2
      port map(A => SumA_8_net, B => SumB_8_net, Y => XOR2_34_Y);
    DFN1_23 : DFN1
      port map(D => PP3_4_net, CLK => Clock, Q => DFN1_23_Q);
    MAJ3_4 : MAJ3
      port map(A => DFN1_10_Q, B => DFN1_17_Q, C => DFN1_3_Q, 
        Y => MAJ3_4_Y);
    XOR2_31 : XOR2
      port map(A => BUFF_2_Y, B => DataB(6), Y => XOR2_31_Y);
    XOR3_14 : XOR3
      port map(A => DFN1_33_Q, B => DFN1_27_Q, C => AND2_30_Y, 
        Y => XOR3_14_Y);
    AND2_3 : AND2
      port map(A => DFN1_26_Q, B => DFN1_44_Q, Y => AND2_3_Y);
    XOR3_11 : XOR3
      port map(A => DFN1_9_Q, B => DFN1_1_Q, C => DFN1_20_Q, Y => 
        XOR3_11_Y);
    AND2_30 : AND2
      port map(A => DFN1_37_Q, B => DFN1_24_Q, Y => AND2_30_Y);
    XNOR2_6 : XNOR2
      port map(A => DataB(4), B => BUFF_8_Y, Y => XNOR2_6_Y);
    AND2_14 : AND2
      port map(A => AND2_82_Y, B => AND2_77_Y, Y => AND2_14_Y);
    AND2_74 : AND2
      port map(A => AND2_78_Y, B => AND2_61_Y, Y => AND2_74_Y);
    AND2_32 : AND2
      port map(A => XOR2_19_Y, B => DataA(1), Y => AND2_32_Y);
    XOR2_PP3_5_inst : XOR2
      port map(A => MX2_15_Y, B => BUFF_1_Y, Y => PP3_5_net);
    BUFF_5 : BUFF
      port map(A => DataB(7), Y => BUFF_5_Y);
    XOR2_PP2_2_inst : XOR2
      port map(A => MX2_9_Y, B => BUFF_8_Y, Y => PP2_2_net);
    XOR3_4 : XOR3
      port map(A => MAJ3_4_Y, B => XOR2_1_Y, C => XOR3_14_Y, Y => 
        XOR3_4_Y);
    MX2_30 : MX2
      port map(A => AND2_54_Y, B => DataA(0), S => NOR2_5_Y, Y => 
        MX2_30_Y);
    XOR2_46 : XOR2
      port map(A => SumA_5_net, B => SumB_5_net, Y => XOR2_46_Y);
    DFN1_SumB_12_inst : DFN1
      port map(D => XOR3_13_Y, CLK => Clock, Q => SumB_12_net);
    MX2_22 : MX2
      port map(A => AND2_5_Y, B => DataA(2), S => AND2A_1_Y, Y => 
        MX2_22_Y);
    AO1_2 : AO1
      port map(A => XOR2_29_Y, B => AND2_60_Y, C => AND2_12_Y, 
        Y => AO1_2_Y);
    AND2_26 : AND2
      port map(A => AND2_9_Y, B => AND2_66_Y, Y => AND2_26_Y);
    DFN1_32 : DFN1
      port map(D => PP0_1_net, CLK => Clock, Q => DFN1_32_Q);
    AOI1_E_3_inst : AOI1
      port map(A => XOR2_45_Y, B => OR3_3_Y, C => AND3_1_Y, Y => 
        E_3_net);
    XOR2_9 : XOR2
      port map(A => SumA_13_net, B => SumB_13_net, Y => XOR2_9_Y);
    DFN1_SumA_1_inst : DFN1
      port map(D => DFN1_11_Q, CLK => Clock, Q => SumA_1_net);
    AND2_23 : AND2
      port map(A => SumA_7_net, B => SumB_7_net, Y => AND2_23_Y);
    XNOR2_4 : XNOR2
      port map(A => DataB(6), B => BUFF_0_Y, Y => XNOR2_4_Y);
    NOR2_1 : NOR2
      port map(A => XOR2_21_Y, B => XNOR2_7_Y, Y => NOR2_1_Y);
    XOR2_5 : XOR2
      port map(A => BUFF_12_Y, B => DataB(4), Y => XOR2_5_Y);
    XOR2_PP0_1_inst : XOR2
      port map(A => MX2_10_Y, B => BUFF_7_Y, Y => PP0_1_net);
    MX2_0 : MX2
      port map(A => AND2_22_Y, B => DataA(6), S => AND2A_2_Y, 
        Y => MX2_0_Y);
    DFN1_SumA_14_inst : DFN1
      port map(D => DFN1_19_Q, CLK => Clock, Q => SumA_14_net);
    AO1_28 : AO1
      port map(A => XOR2_46_Y, B => AND2_50_Y, C => AND2_55_Y, 
        Y => AO1_28_Y);
    XOR2_PP2_0_inst : XOR2
      port map(A => XOR2_28_Y, B => DataB(5), Y => PP2_0_net);
    AND2_19 : AND2
      port map(A => SumA_3_net, B => SumB_3_net, Y => AND2_19_Y);
    DFN1_24 : DFN1
      port map(D => PP0_7_net, CLK => Clock, Q => DFN1_24_Q);
    AND2_79 : AND2
      port map(A => XOR2_44_Y, B => DataA(1), Y => AND2_79_Y);
    XOR2_22 : XOR2
      port map(A => SumA_3_net, B => SumB_3_net, Y => XOR2_22_Y);
    AO1_1 : AO1
      port map(A => AND2_9_Y, B => AO1_18_Y, C => AO1_2_Y, Y => 
        AO1_1_Y);
    MX2_28 : MX2
      port map(A => AND2_41_Y, B => DataA(4), S => NOR2_6_Y, Y => 
        MX2_28_Y);
    MAJ3_11 : MAJ3
      port map(A => XOR3_8_Y, B => MAJ3_10_Y, C => XOR2_6_Y, Y => 
        MAJ3_11_Y);
    AOI1_E_1_inst : AOI1
      port map(A => XOR2_3_Y, B => OR3_0_Y, C => AND3_3_Y, Y => 
        E_1_net);
    XOR2_PP1_3_inst : XOR2
      port map(A => MX2_1_Y, B => BUFF_4_Y, Y => PP1_3_net);
    XOR2_13 : XOR2
      port map(A => DataA(7), B => DataB(1), Y => XOR2_13_Y);
    DFN1_11 : DFN1
      port map(D => PP0_2_net, CLK => Clock, Q => DFN1_11_Q);
    DFN1_SumB_10_inst : DFN1
      port map(D => XOR3_7_Y, CLK => Clock, Q => SumB_10_net);
    AND2_51 : AND2
      port map(A => SumA_1_net, B => SumB_1_net, Y => AND2_51_Y);
    DFN1_4 : DFN1
      port map(D => PP0_8_net, CLK => Clock, Q => DFN1_4_Q);
    DFN1_13 : DFN1
      port map(D => PP2_0_net, CLK => Clock, Q => DFN1_13_Q);
    DFN1_28 : DFN1
      port map(D => PP2_1_net, CLK => Clock, Q => DFN1_28_Q);
    AO1_3 : AO1
      port map(A => XOR2_8_Y, B => AND2_13_Y, C => AND2_51_Y, 
        Y => AO1_3_Y);
    AND2_64 : AND2
      port map(A => XOR2_49_Y, B => DataA(3), Y => AND2_64_Y);
    AND2_47 : AND2
      port map(A => DataB(0), B => DataA(5), Y => AND2_47_Y);
    DFN1_SumB_5_inst : DFN1
      port map(D => XOR3_10_Y, CLK => Clock, Q => SumB_5_net);
    AO1_18 : AO1
      port map(A => AND2_14_Y, B => AO1_15_Y, C => AO1_5_Y, Y => 
        AO1_18_Y);
    XOR2_48 : XOR2
      port map(A => SumA_11_net, B => SumB_11_net, Y => XOR2_48_Y);
    MX2_26 : MX2
      port map(A => BUFF_5_Y, B => XOR2_45_Y, S => XOR2_50_Y, 
        Y => MX2_26_Y);
    DFN1_SumA_11_inst : DFN1
      port map(D => MAJ3_11_Y, CLK => Clock, Q => SumA_11_net);
    AND2A_2 : AND2A
      port map(A => DataB(0), B => BUFF_13_Y, Y => AND2A_2_Y);
    AND2_16 : AND2
      port map(A => AND2_58_Y, B => AND2_26_Y, Y => AND2_16_Y);
    XOR2_PP1_6_inst : XOR2
      port map(A => MX2_6_Y, B => BUFF_10_Y, Y => PP1_6_net);
    AND2_76 : AND2
      port map(A => XOR2_31_Y, B => DataA(4), Y => AND2_76_Y);
    AND2_13 : AND2
      port map(A => SumA_0_net, B => SumB_0_net, Y => AND2_13_Y);
    XOR2_PP1_1_inst : XOR2
      port map(A => MX2_2_Y, B => BUFF_3_Y, Y => PP1_1_net);
    AND2_73 : AND2
      port map(A => SumA_2_net, B => SumB_2_net, Y => AND2_73_Y);
    XNOR2_1 : XNOR2
      port map(A => DataB(6), B => BUFF_5_Y, Y => XNOR2_1_Y);
    XOR2_10 : XOR2
      port map(A => DFN1_37_Q, B => DFN1_24_Q, Y => XOR2_10_Y);
    AND2_58 : AND2
      port map(A => AND2_84_Y, B => AND2_14_Y, Y => AND2_58_Y);
    AND2_55 : AND2
      port map(A => SumA_5_net, B => SumB_5_net, Y => AND2_55_Y);
    MX2_2 : MX2
      port map(A => AND2_32_Y, B => DataA(0), S => NOR2_0_Y, Y => 
        MX2_2_Y);
    MX2_23 : MX2
      port map(A => BUFF_10_Y, B => XOR2_3_Y, S => XOR2_21_Y, 
        Y => MX2_23_Y);
    DFN1_SumB_0_inst : DFN1
      port map(D => DFN1_8_Q, CLK => Clock, Q => SumB_0_net);
    AND2_69 : AND2
      port map(A => XOR2_50_Y, B => DataA(6), Y => AND2_69_Y);
    DFN1_SumB_4_inst : DFN1
      port map(D => XOR3_6_Y, CLK => Clock, Q => SumB_4_net);
    XOR2_27 : XOR2
      port map(A => SumA_9_net, B => SumB_9_net, Y => XOR2_27_Y);
    XOR3_3 : XOR3
      port map(A => MAJ3_13_Y, B => XOR2_43_Y, C => XOR3_5_Y, 
        Y => XOR3_3_Y);
    MAJ3_3 : MAJ3
      port map(A => AND2_68_Y, B => DFN1_5_Q, C => DFN1_38_Q, 
        Y => MAJ3_3_Y);
    BUFF_12 : BUFF
      port map(A => DataB(3), Y => BUFF_12_Y);
    XOR2_7 : XOR2
      port map(A => SumA_7_net, B => SumB_7_net, Y => XOR2_7_Y);
    AND2_5 : AND2
      port map(A => DataB(0), B => DataA(3), Y => AND2_5_Y);
    XOR2_14 : XOR2
      port map(A => SumA_4_net, B => SumB_4_net, Y => XOR2_14_Y);
    AND2_50 : AND2
      port map(A => SumA_4_net, B => SumB_4_net, Y => AND2_50_Y);
    XOR2_PP3_0_inst : XOR2
      port map(A => XOR2_35_Y, B => DataB(7), Y => PP3_0_net);
    DFN1_14 : DFN1
      port map(D => PP3_8_net, CLK => Clock, Q => DFN1_14_Q);
    XOR2_Mult_3_inst : XOR2
      port map(A => XOR2_18_Y, B => AO1_3_Y, Y => Mult(3));
    XOR2_Mult_8_inst : XOR2
      port map(A => XOR2_52_Y, B => AO1_24_Y, Y => Mult(8));
    XNOR2_3 : XNOR2
      port map(A => DataB(4), B => BUFF_11_Y, Y => XNOR2_3_Y);
    XOR2_PP0_4_inst : XOR2
      port map(A => MX2_13_Y, B => BUFF_9_Y, Y => PP0_4_net);
    XOR2_11 : XOR2
      port map(A => SumA_12_net, B => SumB_12_net, Y => XOR2_11_Y);
    AND2_52 : AND2
      port map(A => AND2_80_Y, B => XOR2_32_Y, Y => AND2_52_Y);
    XOR3_6 : XOR3
      port map(A => DFN1_42_Q, B => DFN1_28_Q, C => XOR2_4_Y, 
        Y => XOR3_6_Y);
    XOR2_25 : XOR2
      port map(A => SumA_10_net, B => SumB_10_net, Y => XOR2_25_Y);
    AO1_22 : AO1
      port map(A => XOR2_3_Y, B => OR3_0_Y, C => AND3_3_Y, Y => 
        AO1_22_Y);
    DFN1_35 : DFN1
      port map(D => PP0_5_net, CLK => Clock, Q => DFN1_35_Q);
    DFN1_36 : DFN1
      port map(D => PP1_8_net, CLK => Clock, Q => DFN1_36_Q);
    BUFF_0 : BUFF
      port map(A => DataB(7), Y => BUFF_0_Y);
    DFN1_SumB_2_inst : DFN1
      port map(D => XOR2_36_Y, CLK => Clock, Q => SumB_2_net);
    DFN1_18 : DFN1
      port map(D => PP3_7_net, CLK => Clock, Q => DFN1_18_Q);
    MX2_27 : MX2
      port map(A => AND2_27_Y, B => DataA(6), S => NOR2_2_Y, Y => 
        MX2_27_Y);
    DFN1_40 : DFN1
      port map(D => PP3_0_net, CLK => Clock, Q => DFN1_40_Q);
    DFN1_37 : DFN1
      port map(D => PP1_5_net, CLK => Clock, Q => DFN1_37_Q);
    AND2_34 : AND2
      port map(A => AND2_9_Y, B => XOR2_42_Y, Y => AND2_34_Y);
    AND2_66 : AND2
      port map(A => XOR2_42_Y, B => XOR2_23_Y, Y => AND2_66_Y);
    MX2_11 : MX2
      port map(A => AND2_49_Y, B => DataA(6), S => NOR2_7_Y, Y => 
        MX2_11_Y);
    AO1_6 : AO1
      port map(A => AND2_72_Y, B => AO1_3_Y, C => AO1_9_Y, Y => 
        AO1_6_Y);
    XOR2_Mult_4_inst : XOR2
      port map(A => XOR2_22_Y, B => AO1_8_Y, Y => Mult(4));
    DFN1_29 : DFN1
      port map(D => PP2_8_net, CLK => Clock, Q => DFN1_29_Q);
    NOR2_4 : NOR2
      port map(A => XOR2_44_Y, B => XNOR2_4_Y, Y => NOR2_4_Y);
    XOR2_Mult_1_inst : XOR2
      port map(A => SumA_0_net, B => SumB_0_net, Y => Mult(1));
    AND3_2 : AND3
      port map(A => GND_1_net, B => DataB(0), C => DataB(1), Y => 
        AND3_2_Y);
    AND2_63 : AND2
      port map(A => DataB(0), B => DataA(4), Y => AND2_63_Y);
    AO1_12 : AO1
      port map(A => XOR2_17_Y, B => OR3_1_Y, C => AND3_0_Y, Y => 
        AO1_12_Y);
    XOR2_32 : XOR2
      port map(A => SumA_14_net, B => SumB_14_net, Y => XOR2_32_Y);
    XOR2_Mult_10_inst : XOR2
      port map(A => XOR2_27_Y, B => AO1_0_Y, Y => Mult(10));
    XOR2_Mult_2_inst : XOR2
      port map(A => XOR2_51_Y, B => AND2_13_Y, Y => Mult(2));
    OR3_0 : OR3
      port map(A => DataB(1), B => DataB(2), C => DataB(3), Y => 
        OR3_0_Y);
    XOR2_PP0_2_inst : XOR2
      port map(A => MX2_5_Y, B => BUFF_7_Y, Y => PP0_2_net);
    XOR3_12 : XOR3
      port map(A => DFN1_0_Q, B => DFN1_2_Q, C => DFN1_13_Q, Y => 
        XOR3_12_Y);
    AND2_9 : AND2
      port map(A => XOR2_47_Y, B => XOR2_29_Y, Y => AND2_9_Y);
    MX2_6 : MX2
      port map(A => AND2_21_Y, B => DataA(5), S => NOR2_1_Y, Y => 
        MX2_6_Y);
    MX2_PP3_8_inst : MX2
      port map(A => MX2_26_Y, B => AO1_32_Y, S => NOR2_2_Y, Y => 
        PP3_8_net);
    AO1_32 : AO1
      port map(A => XOR2_45_Y, B => OR3_3_Y, C => AND3_1_Y, Y => 
        AO1_32_Y);
    XOR2_43 : XOR2
      port map(A => DFN1_26_Q, B => DFN1_44_Q, Y => XOR2_43_Y);
    XOR2_PP3_4_inst : XOR2
      port map(A => MX2_16_Y, B => BUFF_1_Y, Y => PP3_4_net);
    DFN1_SumA_8_inst : DFN1
      port map(D => MAJ3_5_Y, CLK => Clock, Q => SumA_8_net);
    DFN1_9 : DFN1
      port map(D => PP1_4_net, CLK => Clock, Q => DFN1_9_Q);
    MX2_7 : MX2
      port map(A => BUFF_14_Y, B => XOR2_17_Y, S => XOR2_5_Y, 
        Y => MX2_7_Y);
    DFN1_SumB_6_inst : DFN1
      port map(D => XOR3_2_Y, CLK => Clock, Q => SumB_6_net);
    AO1_9 : AO1
      port map(A => XOR2_39_Y, B => AND2_73_Y, C => AND2_19_Y, 
        Y => AO1_9_Y);
    DFN1_SumA_6_inst : DFN1
      port map(D => MAJ3_12_Y, CLK => Clock, Q => SumA_6_net);
    NOR2_8 : NOR2
      port map(A => XOR2_31_Y, B => XNOR2_2_Y, Y => NOR2_8_Y);
    AND2_39 : AND2
      port map(A => XOR2_44_Y, B => DataA(0), Y => AND2_39_Y);
    XOR2_Mult_6_inst : XOR2
      port map(A => XOR2_12_Y, B => AO1_4_Y, Y => Mult(6));
    BUFF_9 : BUFF
      port map(A => DataB(1), Y => BUFF_9_Y);
    MX2_15 : MX2
      port map(A => AND2_8_Y, B => DataA(4), S => NOR2_8_Y, Y => 
        MX2_15_Y);
    MAJ3_6 : MAJ3
      port map(A => DFN1_13_Q, B => DFN1_0_Q, C => DFN1_2_Q, Y => 
        MAJ3_6_Y);
    XOR2_PP2_3_inst : XOR2
      port map(A => MX2_20_Y, B => BUFF_11_Y, Y => PP2_3_net);
    AND2_27 : AND2
      port map(A => XOR2_50_Y, B => DataA(7), Y => AND2_27_Y);
    DFN1_SumA_12_inst : DFN1
      port map(D => MAJ3_8_Y, CLK => Clock, Q => SumA_12_net);
    MX2_3 : MX2
      port map(A => AND2_47_Y, B => DataA(4), S => AND2A_1_Y, 
        Y => MX2_3_Y);
    XOR2_Mult_12_inst : XOR2
      port map(A => XOR2_48_Y, B => AO1_10_Y, Y => Mult(12));
    AO1_20 : AO1
      port map(A => XOR2_9_Y, B => AND2_33_Y, C => AND2_2_Y, Y => 
        AO1_20_Y);
    DFN1_SumA_0_inst : DFN1
      port map(D => DFN1_32_Q, CLK => Clock, Q => SumA_0_net);
    AO1_0 : AO1
      port map(A => XOR2_47_Y, B => AO1_18_Y, C => AND2_60_Y, 
        Y => AO1_0_Y);
    XOR3_9 : XOR3
      port map(A => DFN1_17_Q, B => DFN1_3_Q, C => DFN1_10_Q, 
        Y => XOR3_9_Y);
    XOR2_29 : XOR2
      port map(A => SumA_9_net, B => SumB_9_net, Y => XOR2_29_Y);
    XOR2_40 : XOR2
      port map(A => SumA_6_net, B => SumB_6_net, Y => XOR2_40_Y);
    BUFF_6 : BUFF
      port map(A => DataB(1), Y => BUFF_6_Y);
    XOR3_0 : XOR3
      port map(A => MAJ3_3_Y, B => AND2_62_Y, C => XOR3_1_Y, Y => 
        XOR3_0_Y);
    BUFF_7 : BUFF
      port map(A => DataB(1), Y => BUFF_7_Y);
    MX2_9 : MX2
      port map(A => AND2_25_Y, B => DataA(1), S => NOR2_5_Y, Y => 
        MX2_9_Y);
    XOR2_2 : XOR2
      port map(A => SumA_4_net, B => SumB_4_net, Y => XOR2_2_Y);
    DFN1_31 : DFN1
      port map(D => PP1_6_net, CLK => Clock, Q => DFN1_31_Q);
    DFN1_2 : DFN1
      port map(D => PP0_4_net, CLK => Clock, Q => DFN1_2_Q);
    XOR2_37 : XOR2
      port map(A => BUFF_12_Y, B => DataB(4), Y => XOR2_37_Y);
    DFN1_19 : DFN1
      port map(D => E_3_net, CLK => Clock, Q => DFN1_19_Q);
    AND2_36 : AND2
      port map(A => XOR2_0_Y, B => XOR2_8_Y, Y => AND2_36_Y);
    AND2A_0 : AND2A
      port map(A => DataB(0), B => BUFF_7_Y, Y => AND2A_0_Y);
    XOR2_PP2_1_inst : XOR2
      port map(A => MX2_30_Y, B => BUFF_8_Y, Y => PP2_1_net);
    AO1_26 : AO1
      port map(A => AND2_61_Y, B => AO1_27_Y, C => AO1_14_Y, Y => 
        AO1_26_Y);
    DFN1_33 : DFN1
      port map(D => PP3_2_net, CLK => Clock, Q => DFN1_33_Q);
    XOR3_5 : XOR3
      port map(A => DFN1_43_Q, B => DFN1_12_Q, C => AND2_7_Y, 
        Y => XOR3_5_Y);
    MX2_10 : MX2
      port map(A => AND2_44_Y, B => DataA(0), S => AND2A_0_Y, 
        Y => MX2_10_Y);
    AO1_23 : AO1
      port map(A => AND2_6_Y, B => AO1_27_Y, C => AO1_11_Y, Y => 
        AO1_23_Y);
    AND2_33 : AND2
      port map(A => SumA_12_net, B => SumB_12_net, Y => AND2_33_Y);
    XOR2_44 : XOR2
      port map(A => BUFF_2_Y, B => DataB(6), Y => XOR2_44_Y);
    AO1_10 : AO1
      port map(A => AND2_34_Y, B => AO1_18_Y, C => AO1_16_Y, Y => 
        AO1_10_Y);
    XOR2_41 : XOR2
      port map(A => SumA_2_net, B => SumB_2_net, Y => XOR2_41_Y);
    XOR2_35 : XOR2
      port map(A => AND2_39_Y, B => BUFF_0_Y, Y => XOR2_35_Y);
    XOR2_PP1_7_inst : XOR2
      port map(A => MX2_19_Y, B => BUFF_10_Y, Y => PP1_7_net);
    MX2_29 : MX2
      port map(A => AND2_65_Y, B => DataA(2), S => NOR2_8_Y, Y => 
        MX2_29_Y);
    DFN1_SumB_13_inst : DFN1
      port map(D => MAJ3_15_Y, CLK => Clock, Q => SumB_13_net);
    XOR3_15 : XOR3
      port map(A => MAJ3_14_Y, B => XOR2_26_Y, C => XOR3_16_Y, 
        Y => XOR3_15_Y);
    DFN1_SumA_10_inst : DFN1
      port map(D => MAJ3_0_Y, CLK => Clock, Q => SumA_10_net);
    XOR2_PP2_5_inst : XOR2
      port map(A => MX2_28_Y, B => BUFF_11_Y, Y => PP2_5_net);
    MAJ3_15 : MAJ3
      port map(A => MAJ3_1_Y, B => DFN1_18_Q, C => DFN1_34_Q, 
        Y => MAJ3_15_Y);
    AND2_S_2_inst : AND2
      port map(A => XOR2_28_Y, B => DataB(5), Y => S_2_net);
    NOR2_5 : NOR2
      port map(A => XOR2_37_Y, B => XNOR2_6_Y, Y => NOR2_5_Y);
    AO1_30 : AO1
      port map(A => AND2_17_Y, B => AO1_27_Y, C => AO1_19_Y, Y => 
        AO1_30_Y);
    XOR3_8 : XOR3
      port map(A => DFN1_5_Q, B => DFN1_38_Q, C => AND2_68_Y, 
        Y => XOR3_8_Y);
    AND2_41 : AND2
      port map(A => XOR2_20_Y, B => DataA(5), Y => AND2_41_Y);
    AND2_0 : AND2
      port map(A => AND2_58_Y, B => AND2_34_Y, Y => AND2_0_Y);
    AO1_16 : AO1
      port map(A => XOR2_42_Y, B => AO1_2_Y, C => AND2_24_Y, Y => 
        AO1_16_Y);
    XOR2_PP1_2_inst : XOR2
      port map(A => MX2_24_Y, B => BUFF_3_Y, Y => PP1_2_net);
    AND2_17 : AND2
      port map(A => AND2_26_Y, B => AND2_52_Y, Y => AND2_17_Y);
    BUFF_3 : BUFF
      port map(A => DataB(3), Y => BUFF_3_Y);
    AO1_29 : AO1
      port map(A => AND2_66_Y, B => AO1_2_Y, C => AO1_17_Y, Y => 
        AO1_29_Y);
    XOR2_6 : XOR2
      port map(A => DFN1_6_Q, B => DFN1_21_Q, Y => XOR2_6_Y);
    AND2_77 : AND2
      port map(A => XOR2_16_Y, B => XOR2_7_Y, Y => AND2_77_Y);
    MX2_PP0_8_inst : MX2
      port map(A => MX2_18_Y, B => EBAR, S => AND2A_2_Y, Y => 
        PP0_8_net);
    MX2_24 : MX2
      port map(A => AND2_56_Y, B => DataA(1), S => NOR2_0_Y, Y => 
        MX2_24_Y);
    AND2_54 : AND2
      port map(A => XOR2_37_Y, B => DataA(1), Y => AND2_54_Y);
    AO1_13 : AO1
      port map(A => XOR2_7_Y, B => AND2_83_Y, C => AND2_23_Y, 
        Y => AO1_13_Y);
    DFN1_42 : DFN1
      port map(D => S_2_net, CLK => Clock, Q => DFN1_42_Q);
    XOR2_53 : XOR2
      port map(A => AND2_18_Y, B => BUFF_7_Y, Y => XOR2_53_Y);
    AND2_81 : AND2
      port map(A => XOR2_44_Y, B => DataA(2), Y => AND2_81_Y);
    XOR2_Mult_9_inst : XOR2
      port map(A => XOR2_34_Y, B => AO1_18_Y, Y => Mult(9));
    MAJ3_5 : MAJ3
      port map(A => XOR3_14_Y, B => MAJ3_4_Y, C => XOR2_1_Y, Y => 
        MAJ3_5_Y);
    DFN1_34 : DFN1
      port map(D => E_2_net, CLK => Clock, Q => DFN1_34_Q);
    DFN1_SumA_9_inst : DFN1
      port map(D => MAJ3_7_Y, CLK => Clock, Q => SumA_9_net);
    DFN1_0 : DFN1
      port map(D => PP1_2_net, CLK => Clock, Q => DFN1_0_Q);
    XNOR2_7 : XNOR2
      port map(A => DataB(2), B => BUFF_10_Y, Y => XNOR2_7_Y);
    XOR2_12 : XOR2
      port map(A => SumA_5_net, B => SumB_5_net, Y => XOR2_12_Y);
    AND2_48 : AND2
      port map(A => AND2_36_Y, B => XOR2_41_Y, Y => AND2_48_Y);
    AND2_45 : AND2
      port map(A => XOR2_37_Y, B => DataA(0), Y => AND2_45_Y);
    AO1_19 : AO1
      port map(A => AND2_52_Y, B => AO1_29_Y, C => AO1_31_Y, Y => 
        AO1_19_Y);
    XOR2_PP3_1_inst : XOR2
      port map(A => MX2_31_Y, B => BUFF_0_Y, Y => PP3_1_net);
    DFN1_1 : DFN1
      port map(D => PP0_6_net, CLK => Clock, Q => DFN1_1_Q);
    XOR2_26 : XOR2
      port map(A => DFN1_36_Q, B => DFN1_44_Q, Y => XOR2_26_Y);
    DFN1_20 : DFN1
      port map(D => PP2_2_net, CLK => Clock, Q => DFN1_20_Q);
    DFN1_38 : DFN1
      port map(D => PP2_7_net, CLK => Clock, Q => DFN1_38_Q);
    AND2_59 : AND2
      port map(A => DFN1_14_Q, B => VCC_1_net, Y => AND2_59_Y);
    AND2_4 : AND2
      port map(A => XOR2_20_Y, B => DataA(3), Y => AND2_4_Y);
    AND2_40 : AND2
      port map(A => XOR2_21_Y, B => DataA(7), Y => AND2_40_Y);
    BUFF_4 : BUFF
      port map(A => DataB(3), Y => BUFF_4_Y);
    XOR2_50 : XOR2
      port map(A => BUFF_2_Y, B => DataB(6), Y => XOR2_50_Y);
    MAJ3_7 : MAJ3
      port map(A => XOR3_5_Y, B => MAJ3_13_Y, C => XOR2_43_Y, 
        Y => MAJ3_7_Y);
    AND2_42 : AND2
      port map(A => AND2_84_Y, B => AND2_70_Y, Y => AND2_42_Y);
    AOI1_E_0_inst : AOI1
      port map(A => XOR2_13_Y, B => OR3_2_Y, C => AND3_2_Y, Y => 
        E_0_net);
    XNOR2_5 : XNOR2
      port map(A => DataB(2), B => BUFF_4_Y, Y => XNOR2_5_Y);
    MX2_4 : MX2
      port map(A => AND2_81_Y, B => DataA(1), S => NOR2_4_Y, Y => 
        MX2_4_Y);
    AO1_5 : AO1
      port map(A => AND2_77_Y, B => AO1_28_Y, C => AO1_13_Y, Y => 
        AO1_5_Y);
    AND2_67 : AND2
      port map(A => AND2_36_Y, B => AND2_72_Y, Y => AND2_67_Y);
    BUFF_13 : BUFF
      port map(A => DataB(1), Y => BUFF_13_Y);
    XOR3_2 : XOR3
      port map(A => MAJ3_2_Y, B => XOR2_10_Y, C => XOR3_9_Y, Y => 
        XOR3_2_Y);
    XOR2_39 : XOR2
      port map(A => SumA_3_net, B => SumB_3_net, Y => XOR2_39_Y);
    AND2_8 : AND2
      port map(A => XOR2_31_Y, B => DataA(5), Y => AND2_8_Y);
    AND2_80 : AND2
      port map(A => XOR2_33_Y, B => XOR2_9_Y, Y => AND2_80_Y);
    NOR2_7 : NOR2
      port map(A => XOR2_5_Y, B => XNOR2_8_Y, Y => NOR2_7_Y);
    XOR2_3 : XOR2
      port map(A => DataA(7), B => DataB(3), Y => XOR2_3_Y);
    MX2_12 : MX2
      port map(A => AND2_28_Y, B => DataA(3), S => NOR2_6_Y, Y => 
        MX2_12_Y);
    XOR3_1 : XOR3
      port map(A => DFN1_29_Q, B => VCC_1_net, C => DFN1_39_Q, 
        Y => XOR3_1_Y);
    XOR2_51 : XOR2
      port map(A => SumA_1_net, B => SumB_1_net, Y => XOR2_51_Y);
    AO1_27 : AO1
      port map(A => AND2_14_Y, B => AO1_15_Y, C => AO1_5_Y, Y => 
        AO1_27_Y);
    AND2_82 : AND2
      port map(A => XOR2_2_Y, B => XOR2_46_Y, Y => AND2_82_Y);
    MAJ3_10 : MAJ3
      port map(A => AND2_3_Y, B => DFN1_23_Q, C => DFN1_41_Q, 
        Y => MAJ3_10_Y);
    XOR2_PP0_0_inst : XOR2
      port map(A => XOR2_53_Y, B => DataB(1), Y => PP0_0_net);
    AND2_56 : AND2
      port map(A => XOR2_19_Y, B => DataA(2), Y => AND2_56_Y);
    XOR2_Mult_14_inst : XOR2
      port map(A => XOR2_38_Y, B => AO1_26_Y, Y => Mult(14));
    XOR2_17 : XOR2
      port map(A => DataA(7), B => DataB(5), Y => XOR2_17_Y);
    AND2_53 : AND2
      port map(A => DFN1_15_Q, B => DFN1_25_Q, Y => AND2_53_Y);
    XOR2_28 : XOR2
      port map(A => AND2_45_Y, B => BUFF_8_Y, Y => XOR2_28_Y);
    XOR2_15 : XOR2
      port map(A => AND2_20_Y, B => BUFF_3_Y, Y => XOR2_15_Y);
    MX2_18 : MX2
      port map(A => BUFF_13_Y, B => XOR2_13_Y, S => DataB(0), 
        Y => MX2_18_Y);
    AO1_17 : AO1
      port map(A => XOR2_23_Y, B => AND2_24_Y, C => AND2_35_Y, 
        Y => AO1_17_Y);
    DFN1_SumB_3_inst : DFN1
      port map(D => XOR3_12_Y, CLK => Clock, Q => SumB_3_net);
    DFN1_10 : DFN1
      port map(D => S_3_net, CLK => Clock, Q => DFN1_10_Q);
    BUFF_11 : BUFF
      port map(A => DataB(5), Y => BUFF_11_Y);
    MAJ3_2 : MAJ3
      port map(A => DFN1_20_Q, B => DFN1_9_Q, C => DFN1_1_Q, Y => 
        MAJ3_2_Y);
    XOR2_PP0_3_inst : XOR2
      port map(A => MX2_22_Y, B => BUFF_9_Y, Y => PP0_3_net);
    XOR2_PP2_7_inst : XOR2
      port map(A => MX2_11_Y, B => BUFF_14_Y, Y => PP2_7_net);
    XOR2_Mult_11_inst : XOR2
      port map(A => XOR2_25_Y, B => AO1_1_Y, Y => Mult(11));
    AND2_21 : AND2
      port map(A => XOR2_21_Y, B => DataA(6), Y => AND2_21_Y);
    XOR3_7 : XOR3
      port map(A => MAJ3_10_Y, B => XOR2_6_Y, C => XOR3_8_Y, Y => 
        XOR3_7_Y);
    DFN1_SumA_3_inst : DFN1
      port map(D => AND2_53_Y, CLK => Clock, Q => SumA_3_net);
    DFN1_39 : DFN1
      port map(D => PP3_6_net, CLK => Clock, Q => DFN1_39_Q);
    DFN1_SumA_2_inst : DFN1
      port map(D => DFN1_16_Q, CLK => Clock, Q => SumA_2_net);
    MX2_16 : MX2
      port map(A => AND2_76_Y, B => DataA(3), S => NOR2_8_Y, Y => 
        MX2_16_Y);
    XOR2_0 : XOR2
      port map(A => SumA_0_net, B => SumB_0_net, Y => XOR2_0_Y);
    MAJ3_1 : MAJ3
      port map(A => DFN1_39_Q, B => DFN1_29_Q, C => VCC_1_net, 
        Y => MAJ3_1_Y);
    AO1_4 : AO1
      port map(A => XOR2_2_Y, B => AO1_6_Y, C => AND2_50_Y, Y => 
        AO1_4_Y);
    AND2_37 : AND2
      port map(A => DataB(0), B => DataA(6), Y => AND2_37_Y);
    XOR2_42 : XOR2
      port map(A => SumA_10_net, B => SumB_10_net, Y => XOR2_42_Y);
    AO1_21 : AO1
      port map(A => AND2_82_Y, B => AO1_6_Y, C => AO1_28_Y, Y => 
        AO1_21_Y);
    DFN1_SumA_4_inst : DFN1
      port map(D => MAJ3_6_Y, CLK => Clock, Q => SumA_4_net);
    XOR2_36 : XOR2
      port map(A => DFN1_15_Q, B => DFN1_25_Q, Y => XOR2_36_Y);
    BUFF_1 : BUFF
      port map(A => DataB(7), Y => BUFF_1_Y);
    XNOR2_8 : XNOR2
      port map(A => DataB(4), B => BUFF_14_Y, Y => XNOR2_8_Y);
    MX2_1 : MX2
      port map(A => AND2_64_Y, B => DataA(2), S => NOR2_3_Y, Y => 
        MX2_1_Y);
    XOR3_16 : XOR3
      port map(A => DFN1_23_Q, B => DFN1_41_Q, C => AND2_3_Y, 
        Y => XOR3_16_Y);
    AND2_28 : AND2
      port map(A => XOR2_20_Y, B => DataA(4), Y => AND2_28_Y);
    AND2_25 : AND2
      port map(A => XOR2_37_Y, B => DataA(2), Y => AND2_25_Y);
    MX2_13 : MX2
      port map(A => AND2_63_Y, B => DataA(3), S => AND2A_1_Y, 
        Y => MX2_13_Y);
    DFN1_SumA_13_inst : DFN1
      port map(D => XOR2_24_Y, CLK => Clock, Q => SumA_13_net);
    DFN1_5 : DFN1
      port map(D => PP3_5_net, CLK => Clock, Q => DFN1_5_Q);
end DEF_ARCH;
