library verilog;
use verilog.vl_types.all;
entity bfly2 is
    generic(
        WIDTH           : integer := 16;
        TWIDTH          : integer := 16;
        DWIDTH          : integer := 32;
        TDWIDTH         : integer := 32;
        RND_MODE        : integer := 0
    );
    port(
        clk             : in     vl_logic;
        upScale         : in     vl_logic;
        inP             : in     vl_logic_vector;
        inQ             : in     vl_logic_vector;
        T               : in     vl_logic_vector;
        outP            : out    vl_logic_vector;
        outQ            : out    vl_logic_vector;
        validIn         : in     vl_logic;
        validOut        : out    vl_logic;
        swCrossIn       : in     vl_logic;
        swCrossOut      : out    vl_logic
    );
end bfly2;
