library verilog;
use verilog.vl_types.all;
entity rdFFTtimer is
    generic(
        HALFPTS         : integer := 128;
        LOGPTS          : integer := 8;
        LOGLOGPTS       : integer := 3;
        inBuf_RWDLY     : integer := 12
    );
    port(
        clk             : in     vl_logic;
        cntEn           : in     vl_logic;
        rst             : in     vl_logic;
        nGrst           : in     vl_logic;
        startFFT        : in     vl_logic;
        fft_runs        : in     vl_logic;
        timerTC         : out    vl_logic;
        lastStage       : out    vl_logic;
        stage           : out    vl_logic_vector;
        timer           : out    vl_logic_vector;
        rdValid         : out    vl_logic
    );
end rdFFTtimer;
