-- Version: 9.0 SP2 9.0.3.3

library ieee;
use ieee.std_logic_1164.all;
library smartfusion;
use smartfusion.all;

entity fifo64x16 is 
    port( DATA : in std_logic_vector(15 downto 0); Q : out 
        std_logic_vector(15 downto 0);WE, RE, CLK : in std_logic
        ;  FULL, EMPTY : out std_logic;  RESET : in std_logic;  
        AEMPTY, AFULL : out std_logic) ;
end fifo64x16;


architecture DEF_ARCH of  fifo64x16 is

    component INV
        port(A : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component AND2
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component DFN1P0
        port(D, CLK, PRE : in std_logic := 'U'; Q : out std_logic
        ) ;
    end component;

    component XNOR2
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component AO1
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component XOR2
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component DFN1C0
        port(D, CLK, CLR : in std_logic := 'U'; Q : out std_logic
        ) ;
    end component;

    component AO1C
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component OR2A
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component DFN1E1C0
        port(D, CLK, CLR, E : in std_logic := 'U'; Q : out 
        std_logic) ;
    end component;

    component AOI1
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component OR3
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component AND3
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component OR2
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component NAND3A
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component NOR2A
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component RAM512X18
    generic (MEMORYFILE:string := "");

        port(RADDR8, RADDR7, RADDR6, RADDR5, RADDR4, RADDR3, 
        RADDR2, RADDR1, RADDR0, WADDR8, WADDR7, WADDR6, WADDR5, 
        WADDR4, WADDR3, WADDR2, WADDR1, WADDR0, WD17, WD16, WD15, 
        WD14, WD13, WD12, WD11, WD10, WD9, WD8, WD7, WD6, WD5, 
        WD4, WD3, WD2, WD1, WD0, RW0, RW1, WW0, WW1, PIPE, REN, 
        WEN, RCLK, WCLK, RESET : in std_logic := 'U'; RD17, RD16, 
        RD15, RD14, RD13, RD12, RD11, RD10, RD9, RD8, RD7, RD6, 
        RD5, RD4, RD3, RD2, RD1, RD0 : out std_logic) ;
    end component;

    component NOR3A
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component NAND2
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component AO1D
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component AND2A
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component VCC
        port( Y : out std_logic);
    end component;

    component GND
        port( Y : out std_logic);
    end component;

    signal FULL_1_net, EMPTY_1_net, WEP, REP, MEM_RADDR_0_net, 
        RBINNXTSHIFT_0_net, MEM_WADDR_0_net, WBINNXTSHIFT_0_net, 
        MEM_RADDR_1_net, RBINNXTSHIFT_1_net, MEM_WADDR_1_net, 
        WBINNXTSHIFT_1_net, MEM_RADDR_2_net, RBINNXTSHIFT_2_net, 
        MEM_WADDR_2_net, WBINNXTSHIFT_2_net, MEM_RADDR_3_net, 
        RBINNXTSHIFT_3_net, MEM_WADDR_3_net, WBINNXTSHIFT_3_net, 
        MEM_RADDR_4_net, RBINNXTSHIFT_4_net, MEM_WADDR_4_net, 
        WBINNXTSHIFT_4_net, MEM_RADDR_5_net, RBINNXTSHIFT_5_net, 
        MEM_WADDR_5_net, WBINNXTSHIFT_5_net, MEM_RADDR_6_net, 
        RBINNXTSHIFT_6_net, MEM_WADDR_6_net, WBINNXTSHIFT_6_net, 
        FULLINT, MEMORYWE, MEMWENEG, WDIFF_0_net, WDIFF_1_net, 
        WDIFF_2_net, WDIFF_3_net, WDIFF_4_net, WDIFF_5_net, 
        WDIFF_6_net, AFVALCONST_0_net, AFVALCONST_1_net, 
        WGRY_0_net, WGRY_1_net, WGRY_2_net, WGRY_3_net, 
        WGRY_4_net, WGRY_5_net, WGRY_6_net, EMPTYINT, MEMORYRE, 
        MEMRENEG, RDIFF_0_net, RDIFF_1_net, RDIFF_2_net, 
        RDIFF_3_net, RDIFF_4_net, RDIFF_5_net, RDIFF_6_net, 
        AEVALCONST_0_net, AEVALCONST_2_net, DVLDI, DVLDX, 
        RGRY_0_net, RGRY_1_net, RGRY_2_net, RGRY_3_net, 
        RGRY_4_net, RGRY_5_net, RGRY_6_net, QXI_0_net, QXI_1_net, 
        QXI_2_net, QXI_3_net, QXI_4_net, QXI_5_net, QXI_6_net, 
        QXI_7_net, QXI_8_net, QXI_9_net, QXI_10_net, QXI_11_net, 
        QXI_12_net, QXI_13_net, QXI_14_net, QXI_15_net, NAND2_1_Y, 
        AOI1_0_Y, AND3_0_Y, NAND3A_3_Y, AO1D_0_Y, OR2A_6_Y, 
        AO1C_0_Y, AO1C_10_Y, OR2A_0_Y, AO1C_8_Y, NOR2A_0_Y, 
        AO1C_4_Y, AO1C_2_Y, OR2A_1_Y, AO1C_11_Y, NOR3A_0_Y, 
        OR2A_7_Y, NAND3A_1_Y, XNOR2_18_Y, XNOR2_2_Y, XNOR2_7_Y, 
        NOR2A_2_Y, INV_0_Y, INV_10_Y, INV_3_Y, INV_13_Y, INV_12_Y, 
        INV_8_Y, INV_7_Y, AND2_19_Y, AND2_14_Y, AND2_39_Y, 
        AND2_33_Y, AND2_57_Y, AND2_27_Y, AND2_30_Y, AND2_54_Y, 
        XOR2_5_Y, XOR2_6_Y, XOR2_0_Y, XOR2_38_Y, XOR2_14_Y, 
        XOR2_33_Y, AND2_40_Y, AO1_7_Y, AND2_32_Y, AO1_14_Y, 
        AND2_1_Y, AND2_53_Y, AO1_23_Y, AND2_41_Y, AND2_49_Y, 
        AND2_5_Y, OR3_1_Y, AO1_3_Y, AO1_8_Y, AO1_10_Y, AO1_1_Y, 
        XOR2_31_Y, XOR2_8_Y, XOR2_21_Y, XOR2_61_Y, XOR2_25_Y, 
        XOR2_40_Y, AOI1_1_Y, OR2_0_Y, AND3_1_Y, NAND3A_2_Y, 
        AO1D_1_Y, OR2A_4_Y, AO1C_6_Y, AO1C_7_Y, OR2A_5_Y, 
        AO1C_1_Y, NOR2A_3_Y, AO1C_5_Y, AO1C_3_Y, OR2A_2_Y, 
        AO1C_9_Y, NOR3A_1_Y, OR2A_3_Y, NAND3A_0_Y, XNOR2_9_Y, 
        XNOR2_3_Y, XNOR2_12_Y, XOR2_32_Y, XOR2_28_Y, XOR2_18_Y, 
        XOR2_53_Y, XOR2_47_Y, XOR2_29_Y, XOR2_42_Y, AND2_37_Y, 
        AND2_7_Y, AND2_3_Y, AND2_44_Y, AND2_8_Y, AND2_45_Y, 
        XOR2_37_Y, XOR2_30_Y, XOR2_17_Y, XOR2_60_Y, XOR2_58_Y, 
        XOR2_56_Y, XOR2_1_Y, AND2_24_Y, AO1_19_Y, AND2_12_Y, 
        AO1_5_Y, AND2_58_Y, AND2_50_Y, AND2_13_Y, AND2_9_Y, 
        AND2_48_Y, AO1_20_Y, AND2_47_Y, AND2_20_Y, AO1_0_Y, 
        AO1_28_Y, AO1_6_Y, AO1_21_Y, AO1_17_Y, XOR2_19_Y, 
        XOR2_57_Y, XOR2_26_Y, XOR2_48_Y, XOR2_12_Y, XOR2_62_Y, 
        AND2A_0_Y, XOR2_13_Y, XOR2_22_Y, XOR2_44_Y, XOR2_45_Y, 
        XOR2_59_Y, XOR2_63_Y, XOR2_54_Y, AND2_26_Y, AND2_11_Y, 
        AND2_42_Y, AND2_2_Y, AND2_10_Y, AND2_0_Y, XOR2_55_Y, 
        XOR2_3_Y, XOR2_7_Y, XOR2_2_Y, XOR2_9_Y, XOR2_24_Y, 
        XOR2_51_Y, AND2_61_Y, AO1_24_Y, AND2_52_Y, AO1_11_Y, 
        AND2_31_Y, AND2_18_Y, AND2_6_Y, AND2_16_Y, AND2_15_Y, 
        AO1_27_Y, AND2_46_Y, AND2_55_Y, AO1_15_Y, AO1_16_Y, 
        AO1_29_Y, AO1_9_Y, AO1_26_Y, XOR2_16_Y, XOR2_49_Y, 
        XOR2_64_Y, XOR2_39_Y, XOR2_36_Y, XOR2_50_Y, NAND2_0_Y, 
        NOR2A_1_Y, INV_4_Y, INV_11_Y, INV_5_Y, INV_2_Y, INV_1_Y, 
        INV_9_Y, INV_6_Y, AND2_43_Y, AND2_35_Y, AND2_4_Y, 
        AND2_60_Y, AND2_21_Y, AND2_56_Y, AND2_59_Y, AND2_17_Y, 
        XOR2_10_Y, XOR2_11_Y, XOR2_4_Y, XOR2_46_Y, XOR2_20_Y, 
        XOR2_41_Y, AND2_38_Y, AO1_4_Y, AND2_29_Y, AO1_2_Y, 
        AND2_36_Y, AND2_23_Y, AO1_22_Y, AND2_51_Y, AND2_34_Y, 
        AND2_25_Y, OR3_0_Y, AO1_13_Y, AO1_18_Y, AO1_12_Y, 
        AO1_25_Y, XOR2_34_Y, XOR2_15_Y, XOR2_35_Y, XOR2_23_Y, 
        XOR2_27_Y, XOR2_52_Y, AND3_2_Y, XOR2_43_Y, XNOR2_1_Y, 
        XNOR2_13_Y, XNOR2_15_Y, XNOR2_14_Y, XNOR2_0_Y, XNOR2_4_Y, 
        AND3_3_Y, AND2_22_Y, AND3_5_Y, XNOR2_16_Y, XNOR2_8_Y, 
        XNOR2_5_Y, XNOR2_10_Y, XNOR2_11_Y, XNOR2_17_Y, XNOR2_6_Y, 
        AND3_4_Y, AND2_28_Y, VCC_1_net, GND_1_net : std_logic ;
    begin   

    AEVALCONST_0_net <= AFVALCONST_0_net;
    AEVALCONST_2_net <= AFVALCONST_1_net;
    VCC_1_net <= AFVALCONST_1_net;
    GND_1_net <= AFVALCONST_0_net;
    FULL <= FULL_1_net;
    
    EMPTY <= EMPTY_1_net;
    
    VCC_2_net : VCC port map(Y => AFVALCONST_1_net);
    GND_2_net : GND port map(Y => AFVALCONST_0_net);
    INV_0 : INV
      port map(A => RBINNXTSHIFT_1_net, Y => INV_0_Y);
    AND2_2 : AND2
      port map(A => MEM_RADDR_4_net, B => GND_1_net, Y => 
        AND2_2_Y);
    DFN1P0_AEMPTY : DFN1P0
      port map(D => AOI1_0_Y, CLK => CLK, PRE => RESET, Q => 
        AEMPTY);
    AND2_20 : AND2
      port map(A => MEM_WADDR_0_net, B => MEMORYWE, Y => 
        AND2_20_Y);
    XNOR2_13 : XNOR2
      port map(A => MEM_RADDR_1_net, B => WBINNXTSHIFT_1_net, 
        Y => XNOR2_13_Y);
    AO1_11 : AO1
      port map(A => XOR2_24_Y, B => AND2_2_Y, C => AND2_10_Y, 
        Y => AO1_11_Y);
    AND2_11 : AND2
      port map(A => MEM_RADDR_2_net, B => GND_1_net, Y => 
        AND2_11_Y);
    AND2_22 : AND2
      port map(A => XNOR2_0_Y, B => XNOR2_4_Y, Y => AND2_22_Y);
    XOR2_WBINNXTSHIFT_2_inst : XOR2
      port map(A => XOR2_57_Y, B => AO1_0_Y, Y => 
        WBINNXTSHIFT_2_net);
    DFN1C0_FULL : DFN1C0
      port map(D => FULLINT, CLK => CLK, CLR => RESET, Q => 
        FULL_1_net);
    XNOR2_9 : XNOR2
      port map(A => AFVALCONST_1_net, B => WDIFF_4_net, Y => 
        XNOR2_9_Y);
    AO1C_3 : AO1C
      port map(A => WDIFF_3_net, B => AFVALCONST_0_net, C => 
        AO1C_5_Y, Y => AO1C_3_Y);
    AO1C_8 : AO1C
      port map(A => RDIFF_2_net, B => AEVALCONST_2_net, C => 
        OR2A_0_Y, Y => AO1C_8_Y);
    OR2A_7 : OR2A
      port map(A => RDIFF_6_net, B => AEVALCONST_0_net, Y => 
        OR2A_7_Y);
    XOR2_19 : XOR2
      port map(A => MEM_WADDR_1_net, B => GND_1_net, Y => 
        XOR2_19_Y);
    AND2_44 : AND2
      port map(A => MEM_WADDR_4_net, B => GND_1_net, Y => 
        AND2_44_Y);
    XOR2_1 : XOR2
      port map(A => MEM_WADDR_6_net, B => GND_1_net, Y => 
        XOR2_1_Y);
    XOR2_23 : XOR2
      port map(A => WBINNXTSHIFT_4_net, B => INV_2_Y, Y => 
        XOR2_23_Y);
    DFN1E1C0_Q_1_inst : DFN1E1C0
      port map(D => QXI_1_net, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(1));
    DFN1E1C0_Q_4_inst : DFN1E1C0
      port map(D => QXI_4_net, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(4));
    INV_1 : INV
      port map(A => MEM_RADDR_5_net, Y => INV_1_Y);
    DFN1E1C0_Q_7_inst : DFN1E1C0
      port map(D => QXI_7_net, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(7));
    XOR2_47 : XOR2
      port map(A => WBINNXTSHIFT_4_net, B => WBINNXTSHIFT_5_net, 
        Y => XOR2_47_Y);
    XOR2_38 : XOR2
      port map(A => MEM_WADDR_4_net, B => INV_13_Y, Y => 
        XOR2_38_Y);
    XOR2_RBINNXTSHIFT_0_inst : XOR2
      port map(A => MEM_RADDR_0_net, B => MEMORYRE, Y => 
        RBINNXTSHIFT_0_net);
    AO1_7 : AO1
      port map(A => XOR2_38_Y, B => AND2_57_Y, C => AND2_27_Y, 
        Y => AO1_7_Y);
    AO1C_1 : AO1C
      port map(A => AFVALCONST_0_net, B => WDIFF_2_net, C => 
        OR2A_5_Y, Y => AO1C_1_Y);
    DFN1C0_WGRY_6_inst : DFN1C0
      port map(D => XOR2_42_Y, CLK => CLK, CLR => RESET, Q => 
        WGRY_6_net);
    AND2_18 : AND2
      port map(A => AND2_61_Y, B => AND2_52_Y, Y => AND2_18_Y);
    AND2_15 : AND2
      port map(A => AND2_18_Y, B => XOR2_9_Y, Y => AND2_15_Y);
    AO1_25 : AO1
      port map(A => XOR2_20_Y, B => AO1_12_Y, C => AND2_59_Y, 
        Y => AO1_25_Y);
    INV_7 : INV
      port map(A => NOR2A_2_Y, Y => INV_7_Y);
    XOR2_RDIFF_3_inst : XOR2
      port map(A => XOR2_21_Y, B => AO1_3_Y, Y => RDIFF_3_net);
    AO1C_7 : AO1C
      port map(A => AFVALCONST_0_net, B => WDIFF_3_net, C => 
        AO1C_6_Y, Y => AO1C_7_Y);
    XOR2_45 : XOR2
      port map(A => RBINNXTSHIFT_3_net, B => RBINNXTSHIFT_4_net, 
        Y => XOR2_45_Y);
    AND2_1 : AND2
      port map(A => XOR2_14_Y, B => XOR2_33_Y, Y => AND2_1_Y);
    DFN1C0_MEM_WADDR_0_inst : DFN1C0
      port map(D => WBINNXTSHIFT_0_net, CLK => CLK, CLR => RESET, 
        Q => MEM_WADDR_0_net);
    AND2_49 : AND2
      port map(A => AND2_40_Y, B => XOR2_0_Y, Y => AND2_49_Y);
    DFN1C0_MEM_WADDR_3_inst : DFN1C0
      port map(D => WBINNXTSHIFT_3_net, CLK => CLK, CLR => RESET, 
        Q => MEM_WADDR_3_net);
    DFN1C0_MEM_RADDR_1_inst : DFN1C0
      port map(D => RBINNXTSHIFT_1_net, CLK => CLK, CLR => RESET, 
        Q => MEM_RADDR_1_net);
    AO1_8 : AO1
      port map(A => XOR2_0_Y, B => AO1_3_Y, C => AND2_57_Y, Y => 
        AO1_8_Y);
    AND2_10 : AND2
      port map(A => MEM_RADDR_5_net, B => GND_1_net, Y => 
        AND2_10_Y);
    AND2_7 : AND2
      port map(A => MEM_WADDR_2_net, B => GND_1_net, Y => 
        AND2_7_Y);
    XOR2_20 : XOR2
      port map(A => WBINNXTSHIFT_5_net, B => INV_1_Y, Y => 
        XOR2_20_Y);
    XOR2_63 : XOR2
      port map(A => RBINNXTSHIFT_5_net, B => RBINNXTSHIFT_6_net, 
        Y => XOR2_63_Y);
    AO1C_10 : AO1C
      port map(A => RDIFF_3_net, B => AEVALCONST_0_net, C => 
        AO1C_0_Y, Y => AO1C_10_Y);
    AOI1_1 : AOI1
      port map(A => AND3_1_Y, B => AO1D_1_Y, C => NAND3A_2_Y, 
        Y => AOI1_1_Y);
    OR3_1 : OR3
      port map(A => AND2_19_Y, B => AND2_14_Y, C => AND2_39_Y, 
        Y => OR3_1_Y);
    AND2_12 : AND2
      port map(A => XOR2_17_Y, B => XOR2_60_Y, Y => AND2_12_Y);
    DFN1C0_WGRY_5_inst : DFN1C0
      port map(D => XOR2_29_Y, CLK => CLK, CLR => RESET, Q => 
        WGRY_5_net);
    XOR2_52 : XOR2
      port map(A => WBINNXTSHIFT_6_net, B => INV_9_Y, Y => 
        XOR2_52_Y);
    AO1C_4 : AO1C
      port map(A => RDIFF_3_net, B => AEVALCONST_0_net, C => 
        NOR2A_0_Y, Y => AO1C_4_Y);
    AND2_61 : AND2
      port map(A => XOR2_55_Y, B => XOR2_3_Y, Y => AND2_61_Y);
    DFN1C0_MEM_WADDR_4_inst : DFN1C0
      port map(D => WBINNXTSHIFT_4_net, CLK => CLK, CLR => RESET, 
        Q => MEM_WADDR_4_net);
    XOR2_WBINNXTSHIFT_0_inst : XOR2
      port map(A => MEM_WADDR_0_net, B => MEMORYWE, Y => 
        WBINNXTSHIFT_0_net);
    AO1_15 : AO1
      port map(A => XOR2_3_Y, B => AND2_55_Y, C => AND2_26_Y, 
        Y => AO1_15_Y);
    AND2_EMPTYINT : AND2
      port map(A => AND3_5_Y, B => XNOR2_16_Y, Y => EMPTYINT);
    XOR2_24 : XOR2
      port map(A => MEM_RADDR_5_net, B => GND_1_net, Y => 
        XOR2_24_Y);
    AND2_57 : AND2
      port map(A => MEM_WADDR_3_net, B => INV_3_Y, Y => AND2_57_Y);
    XOR2_21 : XOR2
      port map(A => MEM_WADDR_3_net, B => INV_3_Y, Y => XOR2_21_Y);
    XOR2_WDIFF_5_inst : XOR2
      port map(A => XOR2_27_Y, B => AO1_12_Y, Y => WDIFF_5_net);
    INV_11 : INV
      port map(A => MEM_RADDR_2_net, Y => INV_11_Y);
    AND2_46 : AND2
      port map(A => AND2_6_Y, B => XOR2_51_Y, Y => AND2_46_Y);
    XOR2_16 : XOR2
      port map(A => MEM_RADDR_1_net, B => GND_1_net, Y => 
        XOR2_16_Y);
    XOR2_60 : XOR2
      port map(A => MEM_WADDR_3_net, B => GND_1_net, Y => 
        XOR2_60_Y);
    AO1_24 : AO1
      port map(A => XOR2_2_Y, B => AND2_11_Y, C => AND2_42_Y, 
        Y => AO1_24_Y);
    AND2_43 : AND2
      port map(A => WBINNXTSHIFT_1_net, B => INV_4_Y, Y => 
        AND2_43_Y);
    AND3_3 : AND3
      port map(A => XNOR2_1_Y, B => XNOR2_13_Y, C => XNOR2_15_Y, 
        Y => AND3_3_Y);
    INV_5 : INV
      port map(A => MEM_RADDR_3_net, Y => INV_5_Y);
    OR2_0 : OR2
      port map(A => AOI1_1_Y, B => FULL_1_net, Y => OR2_0_Y);
    MEMWEBUBBLE : INV
      port map(A => MEMORYWE, Y => MEMWENEG);
    AND2_6 : AND2
      port map(A => AND2_18_Y, B => AND2_31_Y, Y => AND2_6_Y);
    XOR2_64 : XOR2
      port map(A => MEM_RADDR_3_net, B => GND_1_net, Y => 
        XOR2_64_Y);
    AND3_0 : AND3
      port map(A => XNOR2_18_Y, B => XNOR2_2_Y, C => XNOR2_7_Y, 
        Y => AND3_0_Y);
    AND2_60 : AND2
      port map(A => WBINNXTSHIFT_2_net, B => INV_11_Y, Y => 
        AND2_60_Y);
    DFN1C0_MEM_RADDR_2_inst : DFN1C0
      port map(D => RBINNXTSHIFT_2_net, CLK => CLK, CLR => RESET, 
        Q => MEM_RADDR_2_net);
    XOR2_61 : XOR2
      port map(A => MEM_WADDR_4_net, B => INV_13_Y, Y => 
        XOR2_61_Y);
    OR2A_4 : OR2A
      port map(A => AFVALCONST_1_net, B => WDIFF_1_net, Y => 
        OR2A_4_Y);
    XOR2_57 : XOR2
      port map(A => MEM_WADDR_2_net, B => GND_1_net, Y => 
        XOR2_57_Y);
    DFN1C0_RGRY_2_inst : DFN1C0
      port map(D => XOR2_44_Y, CLK => CLK, CLR => RESET, Q => 
        RGRY_2_net);
    XOR2_33 : XOR2
      port map(A => MEM_WADDR_6_net, B => INV_8_Y, Y => XOR2_33_Y);
    INV_3 : INV
      port map(A => RBINNXTSHIFT_3_net, Y => INV_3_Y);
    XNOR2_2 : XNOR2
      port map(A => RDIFF_5_net, B => AEVALCONST_0_net, Y => 
        XNOR2_2_Y);
    XOR2_49 : XOR2
      port map(A => MEM_RADDR_2_net, B => GND_1_net, Y => 
        XOR2_49_Y);
    AO1_14 : AO1
      port map(A => XOR2_33_Y, B => AND2_30_Y, C => AND2_54_Y, 
        Y => AO1_14_Y);
    XOR2_4 : XOR2
      port map(A => WBINNXTSHIFT_3_net, B => INV_5_Y, Y => 
        XOR2_4_Y);
    XOR2_WDIFF_0_inst : XOR2
      port map(A => WBINNXTSHIFT_0_net, B => MEM_RADDR_0_net, 
        Y => WDIFF_0_net);
    AND3_1 : AND3
      port map(A => XNOR2_9_Y, B => XNOR2_3_Y, C => XNOR2_12_Y, 
        Y => AND3_1_Y);
    XOR2_55 : XOR2
      port map(A => MEM_RADDR_0_net, B => MEMORYRE, Y => 
        XOR2_55_Y);
    AND2_24 : AND2
      port map(A => XOR2_37_Y, B => XOR2_30_Y, Y => AND2_24_Y);
    AO1C_5 : AO1C
      port map(A => AFVALCONST_0_net, B => WDIFF_3_net, C => 
        NOR2A_3_Y, Y => AO1C_5_Y);
    XNOR2_0 : XNOR2
      port map(A => MEM_RADDR_4_net, B => WBINNXTSHIFT_4_net, 
        Y => XNOR2_0_Y);
    AND2_31 : AND2
      port map(A => XOR2_9_Y, B => XOR2_24_Y, Y => AND2_31_Y);
    OR2A_3 : OR2A
      port map(A => AFVALCONST_0_net, B => WDIFF_6_net, Y => 
        OR2A_3_Y);
    XOR2_18 : XOR2
      port map(A => WBINNXTSHIFT_2_net, B => WBINNXTSHIFT_3_net, 
        Y => XOR2_18_Y);
    OR2A_6 : OR2A
      port map(A => RDIFF_1_net, B => AEVALCONST_0_net, Y => 
        OR2A_6_Y);
    XOR2_RBINNXTSHIFT_4_inst : XOR2
      port map(A => XOR2_39_Y, B => AO1_29_Y, Y => 
        RBINNXTSHIFT_4_net);
    DFN1C0_RGRY_1_inst : DFN1C0
      port map(D => XOR2_22_Y, CLK => CLK, CLR => RESET, Q => 
        RGRY_1_net);
    DFN1C0_WGRY_3_inst : DFN1C0
      port map(D => XOR2_53_Y, CLK => CLK, CLR => RESET, Q => 
        WGRY_3_net);
    XOR2_8 : XOR2
      port map(A => MEM_WADDR_2_net, B => INV_10_Y, Y => XOR2_8_Y);
    DFN1E1C0_Q_6_inst : DFN1E1C0
      port map(D => QXI_6_net, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(6));
    NAND3A_0 : NAND3A
      port map(A => WDIFF_5_net, B => AFVALCONST_1_net, C => 
        OR2A_2_Y, Y => NAND3A_0_Y);
    XOR2_RBINNXTSHIFT_6_inst : XOR2
      port map(A => XOR2_50_Y, B => AO1_26_Y, Y => 
        RBINNXTSHIFT_6_net);
    XOR2_30 : XOR2
      port map(A => MEM_WADDR_1_net, B => GND_1_net, Y => 
        XOR2_30_Y);
    NOR2A_2 : NOR2A
      port map(A => RBINNXTSHIFT_0_net, B => MEM_WADDR_0_net, 
        Y => NOR2A_2_Y);
    AO1C_11 : AO1C
      port map(A => RDIFF_5_net, B => AEVALCONST_0_net, C => 
        RDIFF_4_net, Y => AO1C_11_Y);
    OR2A_2 : OR2A
      port map(A => WDIFF_6_net, B => AFVALCONST_0_net, Y => 
        OR2A_2_Y);
    AND2_38 : AND2
      port map(A => XOR2_10_Y, B => XOR2_11_Y, Y => AND2_38_Y);
    AND2_35 : AND2
      port map(A => WBINNXTSHIFT_1_net, B => INV_6_Y, Y => 
        AND2_35_Y);
    XOR2_RDIFF_0_inst : XOR2
      port map(A => MEM_WADDR_0_net, B => RBINNXTSHIFT_0_net, 
        Y => RDIFF_0_net);
    MEMREBUBBLE : INV
      port map(A => MEMORYRE, Y => MEMRENEG);
    XNOR2_RDIFF_1_inst : XNOR2
      port map(A => XOR2_31_Y, B => NOR2A_2_Y, Y => RDIFF_1_net);
    AND2_29 : AND2
      port map(A => XOR2_4_Y, B => XOR2_46_Y, Y => AND2_29_Y);
    DFN1C0_MEM_RADDR_4_inst : DFN1C0
      port map(D => RBINNXTSHIFT_4_net, CLK => CLK, CLR => RESET, 
        Q => MEM_RADDR_4_net);
    XOR2_34 : XOR2
      port map(A => WBINNXTSHIFT_1_net, B => INV_4_Y, Y => 
        XOR2_34_Y);
    XOR2_31 : XOR2
      port map(A => MEM_WADDR_1_net, B => INV_0_Y, Y => XOR2_31_Y);
    RAM512X18_QXI_15_inst : RAM512X18
      port map(RADDR8 => GND_1_net, RADDR7 => GND_1_net, 
        RADDR6 => GND_1_net, RADDR5 => MEM_RADDR_5_net, RADDR4 => 
        MEM_RADDR_4_net, RADDR3 => MEM_RADDR_3_net, RADDR2 => 
        MEM_RADDR_2_net, RADDR1 => MEM_RADDR_1_net, RADDR0 => 
        MEM_RADDR_0_net, WADDR8 => GND_1_net, WADDR7 => GND_1_net, 
        WADDR6 => GND_1_net, WADDR5 => MEM_WADDR_5_net, WADDR4 => 
        MEM_WADDR_4_net, WADDR3 => MEM_WADDR_3_net, WADDR2 => 
        MEM_WADDR_2_net, WADDR1 => MEM_WADDR_1_net, WADDR0 => 
        MEM_WADDR_0_net, WD17 => GND_1_net, WD16 => GND_1_net, 
        WD15 => DATA(15), WD14 => DATA(14), WD13 => DATA(13), 
        WD12 => DATA(12), WD11 => DATA(11), WD10 => DATA(10), 
        WD9 => DATA(9), WD8 => DATA(8), WD7 => DATA(7), WD6 => 
        DATA(6), WD5 => DATA(5), WD4 => DATA(4), WD3 => DATA(3), 
        WD2 => DATA(2), WD1 => DATA(1), WD0 => DATA(0), RW0 => 
        GND_1_net, RW1 => VCC_1_net, WW0 => GND_1_net, WW1 => 
        VCC_1_net, PIPE => GND_1_net, REN => MEMRENEG, WEN => 
        MEMWENEG, RCLK => CLK, WCLK => CLK, RESET => RESET, 
        RD17 => OPEN , RD16 => OPEN , RD15 => QXI_15_net, RD14 => 
        QXI_14_net, RD13 => QXI_13_net, RD12 => QXI_12_net, 
        RD11 => QXI_11_net, RD10 => QXI_10_net, RD9 => QXI_9_net, 
        RD8 => QXI_8_net, RD7 => QXI_7_net, RD6 => QXI_6_net, 
        RD5 => QXI_5_net, RD4 => QXI_4_net, RD3 => QXI_3_net, 
        RD2 => QXI_2_net, RD1 => QXI_1_net, RD0 => QXI_0_net);
    WEBUBBLE : INV
      port map(A => WE, Y => WEP);
    AND2_3 : AND2
      port map(A => MEM_WADDR_3_net, B => GND_1_net, Y => 
        AND2_3_Y);
    AND2_30 : AND2
      port map(A => MEM_WADDR_5_net, B => INV_12_Y, Y => 
        AND2_30_Y);
    XOR2_WBINNXTSHIFT_4_inst : XOR2
      port map(A => XOR2_48_Y, B => AO1_6_Y, Y => 
        WBINNXTSHIFT_4_net);
    XNOR2_6 : XNOR2
      port map(A => RBINNXTSHIFT_5_net, B => MEM_WADDR_5_net, 
        Y => XNOR2_6_Y);
    AND2_14 : AND2
      port map(A => MEM_WADDR_1_net, B => INV_7_Y, Y => AND2_14_Y);
    INV_4 : INV
      port map(A => MEM_RADDR_1_net, Y => INV_4_Y);
    AND2_32 : AND2
      port map(A => XOR2_0_Y, B => XOR2_38_Y, Y => AND2_32_Y);
    OR2A_1 : OR2A
      port map(A => AEVALCONST_0_net, B => RDIFF_6_net, Y => 
        OR2A_1_Y);
    DFN1C0_MEM_RADDR_5_inst : DFN1C0
      port map(D => RBINNXTSHIFT_5_net, CLK => CLK, CLR => RESET, 
        Q => MEM_RADDR_5_net);
    XOR2_WBINNXTSHIFT_6_inst : XOR2
      port map(A => XOR2_62_Y, B => AO1_17_Y, Y => 
        WBINNXTSHIFT_6_net);
    NAND3A_2 : NAND3A
      port map(A => NOR3A_1_Y, B => OR2A_3_Y, C => NAND3A_0_Y, 
        Y => NAND3A_2_Y);
    XOR2_46 : XOR2
      port map(A => WBINNXTSHIFT_4_net, B => INV_2_Y, Y => 
        XOR2_46_Y);
    XNOR2_11 : XNOR2
      port map(A => RBINNXTSHIFT_3_net, B => MEM_WADDR_3_net, 
        Y => XNOR2_11_Y);
    AO1_2 : AO1
      port map(A => XOR2_41_Y, B => AND2_59_Y, C => AND2_17_Y, 
        Y => AO1_2_Y);
    DFN1C0_WGRY_0_inst : DFN1C0
      port map(D => XOR2_32_Y, CLK => CLK, CLR => RESET, Q => 
        WGRY_0_net);
    AND2_26 : AND2
      port map(A => MEM_RADDR_1_net, B => GND_1_net, Y => 
        AND2_26_Y);
    XOR2_9 : XOR2
      port map(A => MEM_RADDR_4_net, B => GND_1_net, Y => 
        XOR2_9_Y);
    XOR2_WDIFF_2_inst : XOR2
      port map(A => XOR2_15_Y, B => OR3_0_Y, Y => WDIFF_2_net);
    AND3_5 : AND3
      port map(A => XNOR2_11_Y, B => AND3_4_Y, C => AND2_28_Y, 
        Y => AND3_5_Y);
    INV_12 : INV
      port map(A => RBINNXTSHIFT_5_net, Y => INV_12_Y);
    XOR2_59 : XOR2
      port map(A => RBINNXTSHIFT_4_net, B => RBINNXTSHIFT_5_net, 
        Y => XOR2_59_Y);
    AND2_23 : AND2
      port map(A => AND2_38_Y, B => AND2_29_Y, Y => AND2_23_Y);
    XNOR2_4 : XNOR2
      port map(A => MEM_RADDR_5_net, B => WBINNXTSHIFT_5_net, 
        Y => XNOR2_4_Y);
    AO1C_9 : AO1C
      port map(A => AFVALCONST_1_net, B => WDIFF_5_net, C => 
        AFVALCONST_1_net, Y => AO1C_9_Y);
    XOR2_5 : XOR2
      port map(A => MEM_WADDR_1_net, B => INV_0_Y, Y => XOR2_5_Y);
    AO1_28 : AO1
      port map(A => XOR2_17_Y, B => AO1_0_Y, C => AND2_7_Y, Y => 
        AO1_28_Y);
    AND2_19 : AND2
      port map(A => MEM_WADDR_1_net, B => INV_0_Y, Y => AND2_19_Y);
    DFN1C0_MEM_RADDR_6_inst : DFN1C0
      port map(D => RBINNXTSHIFT_6_net, CLK => CLK, CLR => RESET, 
        Q => MEM_RADDR_6_net);
    DFN1E1C0_Q_0_inst : DFN1E1C0
      port map(D => QXI_0_net, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(0));
    XOR2_22 : XOR2
      port map(A => RBINNXTSHIFT_1_net, B => RBINNXTSHIFT_2_net, 
        Y => XOR2_22_Y);
    AO1_1 : AO1
      port map(A => XOR2_14_Y, B => AO1_10_Y, C => AND2_30_Y, 
        Y => AO1_1_Y);
    XOR2_13 : XOR2
      port map(A => RBINNXTSHIFT_0_net, B => RBINNXTSHIFT_1_net, 
        Y => XOR2_13_Y);
    INV_6 : INV
      port map(A => NOR2A_1_Y, Y => INV_6_Y);
    XNOR2_18 : XNOR2
      port map(A => RDIFF_4_net, B => AEVALCONST_0_net, Y => 
        XNOR2_18_Y);
    AND2_51 : AND2
      port map(A => AND2_23_Y, B => AND2_36_Y, Y => AND2_51_Y);
    REBUBBLE : INV
      port map(A => RE, Y => REP);
    AO1_3 : AO1
      port map(A => XOR2_6_Y, B => OR3_1_Y, C => AND2_33_Y, Y => 
        AO1_3_Y);
    AND2_47 : AND2
      port map(A => AND2_13_Y, B => XOR2_1_Y, Y => AND2_47_Y);
    AO1_18 : AO1
      port map(A => XOR2_4_Y, B => AO1_13_Y, C => AND2_21_Y, Y => 
        AO1_18_Y);
    XOR2_48 : XOR2
      port map(A => MEM_WADDR_4_net, B => GND_1_net, Y => 
        XOR2_48_Y);
    XOR2_RBINNXTSHIFT_3_inst : XOR2
      port map(A => XOR2_64_Y, B => AO1_16_Y, Y => 
        RBINNXTSHIFT_3_net);
    AO1C_0 : AO1C
      port map(A => AEVALCONST_0_net, B => RDIFF_0_net, C => 
        OR2A_6_Y, Y => AO1C_0_Y);
    AND2_16 : AND2
      port map(A => AND2_61_Y, B => XOR2_7_Y, Y => AND2_16_Y);
    XOR2_WDIFF_3_inst : XOR2
      port map(A => XOR2_35_Y, B => AO1_13_Y, Y => WDIFF_3_net);
    OR2A_5 : OR2A
      port map(A => WDIFF_1_net, B => AFVALCONST_1_net, Y => 
        OR2A_5_Y);
    XOR2_62 : XOR2
      port map(A => MEM_WADDR_6_net, B => GND_1_net, Y => 
        XOR2_62_Y);
    AND2_13 : AND2
      port map(A => AND2_50_Y, B => AND2_58_Y, Y => AND2_13_Y);
    XOR2_10 : XOR2
      port map(A => WBINNXTSHIFT_1_net, B => INV_4_Y, Y => 
        XOR2_10_Y);
    XNOR2_1 : XNOR2
      port map(A => MEM_RADDR_0_net, B => WBINNXTSHIFT_0_net, 
        Y => XNOR2_1_Y);
    AND2_58 : AND2
      port map(A => XOR2_58_Y, B => XOR2_56_Y, Y => AND2_58_Y);
    AND2_55 : AND2
      port map(A => MEM_RADDR_0_net, B => MEMORYRE, Y => 
        AND2_55_Y);
    INV_8 : INV
      port map(A => RBINNXTSHIFT_6_net, Y => INV_8_Y);
    DFN1C0_RGRY_4_inst : DFN1C0
      port map(D => XOR2_59_Y, CLK => CLK, CLR => RESET, Q => 
        RGRY_4_net);
    DFN1C0_MEM_WADDR_2_inst : DFN1C0
      port map(D => WBINNXTSHIFT_2_net, CLK => CLK, CLR => RESET, 
        Q => MEM_WADDR_2_net);
    XOR2_27 : XOR2
      port map(A => WBINNXTSHIFT_5_net, B => INV_1_Y, Y => 
        XOR2_27_Y);
    AND2_MEMORYRE : AND2
      port map(A => NAND2_1_Y, B => REP, Y => MEMORYRE);
    XOR2_WBINNXTSHIFT_3_inst : XOR2
      port map(A => XOR2_26_Y, B => AO1_28_Y, Y => 
        WBINNXTSHIFT_3_net);
    XOR2_7 : XOR2
      port map(A => MEM_RADDR_2_net, B => GND_1_net, Y => 
        XOR2_7_Y);
    AND2_5 : AND2
      port map(A => AND2_53_Y, B => XOR2_14_Y, Y => AND2_5_Y);
    XOR2_56 : XOR2
      port map(A => MEM_WADDR_5_net, B => GND_1_net, Y => 
        XOR2_56_Y);
    XOR2_14 : XOR2
      port map(A => MEM_WADDR_5_net, B => INV_12_Y, Y => 
        XOR2_14_Y);
    AND2_50 : AND2
      port map(A => AND2_24_Y, B => AND2_12_Y, Y => AND2_50_Y);
    XNOR2_3 : XNOR2
      port map(A => AFVALCONST_1_net, B => WDIFF_5_net, Y => 
        XNOR2_3_Y);
    XOR2_11 : XOR2
      port map(A => WBINNXTSHIFT_2_net, B => INV_11_Y, Y => 
        XOR2_11_Y);
    NAND3A_3 : NAND3A
      port map(A => NOR3A_0_Y, B => OR2A_7_Y, C => NAND3A_1_Y, 
        Y => NAND3A_3_Y);
    AND2_52 : AND2
      port map(A => XOR2_7_Y, B => XOR2_2_Y, Y => AND2_52_Y);
    XOR2_25 : XOR2
      port map(A => MEM_WADDR_5_net, B => INV_12_Y, Y => 
        XOR2_25_Y);
    XNOR2_15 : XNOR2
      port map(A => MEM_RADDR_2_net, B => WBINNXTSHIFT_2_net, 
        Y => XNOR2_15_Y);
    AO1_22 : AO1
      port map(A => AND2_36_Y, B => AO1_12_Y, C => AO1_2_Y, Y => 
        AO1_22_Y);
    DFN1E1C0_Q_11_inst : DFN1E1C0
      port map(D => QXI_11_net, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(11));
    AND2_34 : AND2
      port map(A => AND2_38_Y, B => XOR2_4_Y, Y => AND2_34_Y);
    AO1_6 : AO1
      port map(A => AND2_12_Y, B => AO1_0_Y, C => AO1_19_Y, Y => 
        AO1_6_Y);
    DFN1E1C0_Q_10_inst : DFN1E1C0
      port map(D => QXI_10_net, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(10));
    DFN1C0_MEM_RADDR_3_inst : DFN1C0
      port map(D => RBINNXTSHIFT_3_net, CLK => CLK, CLR => RESET, 
        Q => MEM_RADDR_3_net);
    AND3_2 : AND3
      port map(A => XNOR2_14_Y, B => AND3_3_Y, C => AND2_22_Y, 
        Y => AND3_2_Y);
    AO1_12 : AO1
      port map(A => AND2_29_Y, B => AO1_13_Y, C => AO1_4_Y, Y => 
        AO1_12_Y);
    NOR3A_1 : NOR3A
      port map(A => OR2A_2_Y, B => AO1C_9_Y, C => WDIFF_4_net, 
        Y => NOR3A_1_Y);
    XOR2_32 : XOR2
      port map(A => WBINNXTSHIFT_0_net, B => WBINNXTSHIFT_1_net, 
        Y => XOR2_32_Y);
    OR3_0 : OR3
      port map(A => AND2_43_Y, B => AND2_35_Y, C => AND2_4_Y, 
        Y => OR3_0_Y);
    DFN1E1C0_Q_9_inst : DFN1E1C0
      port map(D => QXI_9_net, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(9));
    AND2_9 : AND2
      port map(A => AND2_24_Y, B => XOR2_17_Y, Y => AND2_9_Y);
    DFN1E1C0_Q_5_inst : DFN1E1C0
      port map(D => QXI_5_net, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(5));
    NOR3A_0 : NOR3A
      port map(A => OR2A_1_Y, B => AO1C_11_Y, C => 
        AEVALCONST_0_net, Y => NOR3A_0_Y);
    DFN1C0_AFULL : DFN1C0
      port map(D => OR2_0_Y, CLK => CLK, CLR => RESET, Q => AFULL);
    XOR2_58 : XOR2
      port map(A => MEM_WADDR_4_net, B => GND_1_net, Y => 
        XOR2_58_Y);
    XOR2_RDIFF_2_inst : XOR2
      port map(A => XOR2_8_Y, B => OR3_1_Y, Y => RDIFF_2_net);
    XOR2_43 : XOR2
      port map(A => MEM_RADDR_6_net, B => WBINNXTSHIFT_6_net, 
        Y => XOR2_43_Y);
    INV_2 : INV
      port map(A => MEM_RADDR_4_net, Y => INV_2_Y);
    AO1_9 : AO1
      port map(A => XOR2_9_Y, B => AO1_29_Y, C => AND2_2_Y, Y => 
        AO1_9_Y);
    AND2_39 : AND2
      port map(A => INV_0_Y, B => INV_7_Y, Y => AND2_39_Y);
    DFN1C0_DVLDX : DFN1C0
      port map(D => DVLDI, CLK => CLK, CLR => RESET, Q => DVLDX);
    NAND3A_1 : NAND3A
      port map(A => AEVALCONST_0_net, B => RDIFF_5_net, C => 
        OR2A_1_Y, Y => NAND3A_1_Y);
    NAND2_0 : NAND2
      port map(A => FULL_1_net, B => VCC_1_net, Y => NAND2_0_Y);
    DFN1C0_RGRY_6_inst : DFN1C0
      port map(D => XOR2_54_Y, CLK => CLK, CLR => RESET, Q => 
        RGRY_6_net);
    AND2_27 : AND2
      port map(A => MEM_WADDR_4_net, B => INV_13_Y, Y => 
        AND2_27_Y);
    AO1D_1 : AO1D
      port map(A => AO1C_7_Y, B => AO1C_1_Y, C => AO1C_3_Y, Y => 
        AO1D_1_Y);
    DFN1C0_DVLDI : DFN1C0
      port map(D => AND2A_0_Y, CLK => CLK, CLR => RESET, Q => 
        DVLDI);
    XNOR2_10 : XNOR2
      port map(A => RBINNXTSHIFT_2_net, B => MEM_WADDR_2_net, 
        Y => XNOR2_10_Y);
    DFN1E1C0_Q_12_inst : DFN1E1C0
      port map(D => QXI_12_net, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(12));
    AND2_MEMORYWE : AND2
      port map(A => NAND2_0_Y, B => WEP, Y => MEMORYWE);
    AO1_20 : AO1
      port map(A => XOR2_1_Y, B => AO1_17_Y, C => AND2_45_Y, Y => 
        AO1_20_Y);
    INV_13 : INV
      port map(A => RBINNXTSHIFT_4_net, Y => INV_13_Y);
    DFN1C0_WGRY_2_inst : DFN1C0
      port map(D => XOR2_18_Y, CLK => CLK, CLR => RESET, Q => 
        WGRY_2_net);
    AO1_0 : AO1
      port map(A => XOR2_30_Y, B => AND2_20_Y, C => AND2_37_Y, 
        Y => AO1_0_Y);
    XOR2_29 : XOR2
      port map(A => WBINNXTSHIFT_5_net, B => WBINNXTSHIFT_6_net, 
        Y => XOR2_29_Y);
    XOR2_40 : XOR2
      port map(A => MEM_WADDR_6_net, B => INV_8_Y, Y => XOR2_40_Y);
    XOR2_2 : XOR2
      port map(A => MEM_RADDR_3_net, B => GND_1_net, Y => 
        XOR2_2_Y);
    DFN1C0_RGRY_5_inst : DFN1C0
      port map(D => XOR2_63_Y, CLK => CLK, CLR => RESET, Q => 
        RGRY_5_net);
    XNOR2_WDIFF_1_inst : XNOR2
      port map(A => XOR2_34_Y, B => NOR2A_1_Y, Y => WDIFF_1_net);
    AND2_36 : AND2
      port map(A => XOR2_20_Y, B => XOR2_41_Y, Y => AND2_36_Y);
    XOR2_37 : XOR2
      port map(A => MEM_WADDR_0_net, B => MEMORYWE, Y => 
        XOR2_37_Y);
    AND2A_0 : AND2A
      port map(A => EMPTY_1_net, B => REP, Y => AND2A_0_Y);
    AO1_26 : AO1
      port map(A => AND2_31_Y, B => AO1_29_Y, C => AO1_11_Y, Y => 
        AO1_26_Y);
    XOR2_RBINNXTSHIFT_5_inst : XOR2
      port map(A => XOR2_36_Y, B => AO1_9_Y, Y => 
        RBINNXTSHIFT_5_net);
    NOR2A_3 : NOR2A
      port map(A => AFVALCONST_0_net, B => WDIFF_2_net, Y => 
        NOR2A_3_Y);
    AO1_23 : AO1
      port map(A => AND2_1_Y, B => AO1_10_Y, C => AO1_14_Y, Y => 
        AO1_23_Y);
    AOI1_0 : AOI1
      port map(A => AND3_0_Y, B => AO1D_0_Y, C => NAND3A_3_Y, 
        Y => AOI1_0_Y);
    AND2_33 : AND2
      port map(A => MEM_WADDR_2_net, B => INV_10_Y, Y => 
        AND2_33_Y);
    XOR2_44 : XOR2
      port map(A => RBINNXTSHIFT_2_net, B => RBINNXTSHIFT_3_net, 
        Y => XOR2_44_Y);
    AO1_10 : AO1
      port map(A => AND2_32_Y, B => AO1_3_Y, C => AO1_7_Y, Y => 
        AO1_10_Y);
    XOR2_41 : XOR2
      port map(A => WBINNXTSHIFT_6_net, B => INV_9_Y, Y => 
        XOR2_41_Y);
    XOR2_35 : XOR2
      port map(A => WBINNXTSHIFT_3_net, B => INV_5_Y, Y => 
        XOR2_35_Y);
    DFN1C0_WGRY_1_inst : DFN1C0
      port map(D => XOR2_28_Y, CLK => CLK, CLR => RESET, Q => 
        WGRY_1_net);
    DFN1P0_EMPTY : DFN1P0
      port map(D => EMPTYINT, CLK => CLK, PRE => RESET, Q => 
        EMPTY_1_net);
    DFN1E1C0_Q_3_inst : DFN1E1C0
      port map(D => QXI_3_net, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(3));
    NOR2A_1 : NOR2A
      port map(A => MEM_RADDR_0_net, B => WBINNXTSHIFT_0_net, 
        Y => NOR2A_1_Y);
    AND2_41 : AND2
      port map(A => AND2_53_Y, B => AND2_1_Y, Y => AND2_41_Y);
    AND2_0 : AND2
      port map(A => MEM_RADDR_6_net, B => GND_1_net, Y => 
        AND2_0_Y);
    AO1_16 : AO1
      port map(A => XOR2_7_Y, B => AO1_15_Y, C => AND2_11_Y, Y => 
        AO1_16_Y);
    AND2_17 : AND2
      port map(A => WBINNXTSHIFT_6_net, B => INV_9_Y, Y => 
        AND2_17_Y);
    AO1_29 : AO1
      port map(A => AND2_52_Y, B => AO1_15_Y, C => AO1_24_Y, Y => 
        AO1_29_Y);
    NOR2A_0 : NOR2A
      port map(A => RDIFF_2_net, B => AEVALCONST_2_net, Y => 
        NOR2A_0_Y);
    XOR2_6 : XOR2
      port map(A => MEM_WADDR_2_net, B => INV_10_Y, Y => XOR2_6_Y);
    AND2_54 : AND2
      port map(A => MEM_WADDR_6_net, B => INV_8_Y, Y => AND2_54_Y);
    AO1_13 : AO1
      port map(A => XOR2_11_Y, B => OR3_0_Y, C => AND2_60_Y, Y => 
        AO1_13_Y);
    DFN1E1C0_Q_13_inst : DFN1E1C0
      port map(D => QXI_13_net, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(13));
    DFN1C0_MEM_WADDR_6_inst : DFN1C0
      port map(D => WBINNXTSHIFT_6_net, CLK => CLK, CLR => RESET, 
        Q => MEM_WADDR_6_net);
    XOR2_WBINNXTSHIFT_5_inst : XOR2
      port map(A => XOR2_12_Y, B => AO1_21_Y, Y => 
        WBINNXTSHIFT_5_net);
    XOR2_53 : XOR2
      port map(A => WBINNXTSHIFT_3_net, B => WBINNXTSHIFT_4_net, 
        Y => XOR2_53_Y);
    XOR2_RDIFF_6_inst : XOR2
      port map(A => XOR2_40_Y, B => AO1_1_Y, Y => RDIFF_6_net);
    OR2A_0 : OR2A
      port map(A => AEVALCONST_0_net, B => RDIFF_1_net, Y => 
        OR2A_0_Y);
    XNOR2_12 : XNOR2
      port map(A => AFVALCONST_0_net, B => WDIFF_6_net, Y => 
        XNOR2_12_Y);
    XNOR2_7 : XNOR2
      port map(A => RDIFF_6_net, B => AEVALCONST_0_net, Y => 
        XNOR2_7_Y);
    XOR2_12 : XOR2
      port map(A => MEM_WADDR_5_net, B => GND_1_net, Y => 
        XOR2_12_Y);
    AND2_48 : AND2
      port map(A => AND2_50_Y, B => XOR2_58_Y, Y => AND2_48_Y);
    AND2_45 : AND2
      port map(A => MEM_WADDR_6_net, B => GND_1_net, Y => 
        AND2_45_Y);
    AO1_19 : AO1
      port map(A => XOR2_60_Y, B => AND2_7_Y, C => AND2_3_Y, Y => 
        AO1_19_Y);
    XOR2_26 : XOR2
      port map(A => MEM_WADDR_3_net, B => GND_1_net, Y => 
        XOR2_26_Y);
    AND2_59 : AND2
      port map(A => WBINNXTSHIFT_5_net, B => INV_1_Y, Y => 
        AND2_59_Y);
    XOR2_RDIFF_4_inst : XOR2
      port map(A => XOR2_61_Y, B => AO1_8_Y, Y => RDIFF_4_net);
    AND2_4 : AND2
      port map(A => INV_4_Y, B => INV_6_Y, Y => AND2_4_Y);
    AND2_FULLINT : AND2
      port map(A => AND3_2_Y, B => XOR2_43_Y, Y => FULLINT);
    AND2_40 : AND2
      port map(A => XOR2_5_Y, B => XOR2_6_Y, Y => AND2_40_Y);
    XOR2_WDIFF_6_inst : XOR2
      port map(A => XOR2_52_Y, B => AO1_25_Y, Y => WDIFF_6_net);
    XOR2_50 : XOR2
      port map(A => MEM_RADDR_6_net, B => GND_1_net, Y => 
        XOR2_50_Y);
    AND2_42 : AND2
      port map(A => MEM_RADDR_3_net, B => GND_1_net, Y => 
        AND2_42_Y);
    DFN1E1C0_Q_2_inst : DFN1E1C0
      port map(D => QXI_2_net, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(2));
    XNOR2_5 : XNOR2
      port map(A => RBINNXTSHIFT_1_net, B => MEM_WADDR_1_net, 
        Y => XNOR2_5_Y);
    AO1_5 : AO1
      port map(A => XOR2_56_Y, B => AND2_44_Y, C => AND2_8_Y, 
        Y => AO1_5_Y);
    XNOR2_16 : XNOR2
      port map(A => RBINNXTSHIFT_6_net, B => MEM_WADDR_6_net, 
        Y => XNOR2_16_Y);
    XOR2_WDIFF_4_inst : XOR2
      port map(A => XOR2_23_Y, B => AO1_18_Y, Y => WDIFF_4_net);
    DFN1C0_RGRY_3_inst : DFN1C0
      port map(D => XOR2_45_Y, CLK => CLK, CLR => RESET, Q => 
        RGRY_3_net);
    XOR2_39 : XOR2
      port map(A => MEM_RADDR_4_net, B => GND_1_net, Y => 
        XOR2_39_Y);
    AND2_8 : AND2
      port map(A => MEM_WADDR_5_net, B => GND_1_net, Y => 
        AND2_8_Y);
    XOR2_3 : XOR2
      port map(A => MEM_RADDR_1_net, B => GND_1_net, Y => 
        XOR2_3_Y);
    XOR2_54 : XOR2
      port map(A => RBINNXTSHIFT_6_net, B => GND_1_net, Y => 
        XOR2_54_Y);
    AO1_27 : AO1
      port map(A => XOR2_51_Y, B => AO1_26_Y, C => AND2_0_Y, Y => 
        AO1_27_Y);
    XOR2_51 : XOR2
      port map(A => MEM_RADDR_6_net, B => GND_1_net, Y => 
        XOR2_51_Y);
    AND2_56 : AND2
      port map(A => WBINNXTSHIFT_4_net, B => INV_2_Y, Y => 
        AND2_56_Y);
    INV_10 : INV
      port map(A => RBINNXTSHIFT_2_net, Y => INV_10_Y);
    DFN1C0_MEM_WADDR_1_inst : DFN1C0
      port map(D => WBINNXTSHIFT_1_net, CLK => CLK, CLR => RESET, 
        Q => MEM_WADDR_1_net);
    XOR2_RBINNXTSHIFT_1_inst : XOR2
      port map(A => XOR2_16_Y, B => AND2_55_Y, Y => 
        RBINNXTSHIFT_1_net);
    XOR2_17 : XOR2
      port map(A => MEM_WADDR_2_net, B => GND_1_net, Y => 
        XOR2_17_Y);
    AND2_53 : AND2
      port map(A => AND2_40_Y, B => AND2_32_Y, Y => AND2_53_Y);
    DFN1E1C0_Q_15_inst : DFN1E1C0
      port map(D => QXI_15_net, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(15));
    XOR2_28 : XOR2
      port map(A => WBINNXTSHIFT_1_net, B => WBINNXTSHIFT_2_net, 
        Y => XOR2_28_Y);
    INV_9 : INV
      port map(A => MEM_RADDR_6_net, Y => INV_9_Y);
    DFN1E1C0_Q_14_inst : DFN1E1C0
      port map(D => QXI_14_net, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(14));
    DFN1C0_MEM_WADDR_5_inst : DFN1C0
      port map(D => WBINNXTSHIFT_5_net, CLK => CLK, CLR => RESET, 
        Q => MEM_WADDR_5_net);
    XOR2_15 : XOR2
      port map(A => WBINNXTSHIFT_2_net, B => INV_11_Y, Y => 
        XOR2_15_Y);
    DFN1C0_MEM_RADDR_0_inst : DFN1C0
      port map(D => RBINNXTSHIFT_0_net, CLK => CLK, CLR => RESET, 
        Q => MEM_RADDR_0_net);
    XOR2_RDIFF_5_inst : XOR2
      port map(A => XOR2_25_Y, B => AO1_10_Y, Y => RDIFF_5_net);
    AO1_17 : AO1
      port map(A => AND2_58_Y, B => AO1_6_Y, C => AO1_5_Y, Y => 
        AO1_17_Y);
    XNOR2_17 : XNOR2
      port map(A => RBINNXTSHIFT_4_net, B => MEM_WADDR_4_net, 
        Y => XNOR2_17_Y);
    AO1D_0 : AO1D
      port map(A => AO1C_10_Y, B => AO1C_8_Y, C => AO1C_2_Y, Y => 
        AO1D_0_Y);
    DFN1E1C0_Q_8_inst : DFN1E1C0
      port map(D => QXI_8_net, CLK => CLK, CLR => RESET, E => 
        DVLDI, Q => Q(8));
    AND3_4 : AND3
      port map(A => XNOR2_8_Y, B => XNOR2_5_Y, C => XNOR2_10_Y, 
        Y => AND3_4_Y);
    DFN1C0_RGRY_0_inst : DFN1C0
      port map(D => XOR2_13_Y, CLK => CLK, CLR => RESET, Q => 
        RGRY_0_net);
    XOR2_WBINNXTSHIFT_1_inst : XOR2
      port map(A => XOR2_19_Y, B => AND2_20_Y, Y => 
        WBINNXTSHIFT_1_net);
    AND2_21 : AND2
      port map(A => WBINNXTSHIFT_3_net, B => INV_5_Y, Y => 
        AND2_21_Y);
    DFN1C0_WGRY_4_inst : DFN1C0
      port map(D => XOR2_47_Y, CLK => CLK, CLR => RESET, Q => 
        WGRY_4_net);
    XOR2_0 : XOR2
      port map(A => MEM_WADDR_3_net, B => INV_3_Y, Y => XOR2_0_Y);
    NAND2_1 : NAND2
      port map(A => EMPTY_1_net, B => VCC_1_net, Y => NAND2_1_Y);
    AO1_4 : AO1
      port map(A => XOR2_46_Y, B => AND2_21_Y, C => AND2_56_Y, 
        Y => AO1_4_Y);
    AND2_37 : AND2
      port map(A => MEM_WADDR_1_net, B => GND_1_net, Y => 
        AND2_37_Y);
    XNOR2_14 : XNOR2
      port map(A => MEM_RADDR_3_net, B => WBINNXTSHIFT_3_net, 
        Y => XNOR2_14_Y);
    XOR2_42 : XOR2
      port map(A => WBINNXTSHIFT_6_net, B => GND_1_net, Y => 
        XOR2_42_Y);
    XOR2_RBINNXTSHIFT_2_inst : XOR2
      port map(A => XOR2_49_Y, B => AO1_15_Y, Y => 
        RBINNXTSHIFT_2_net);
    AO1_21 : AO1
      port map(A => XOR2_58_Y, B => AO1_6_Y, C => AND2_44_Y, Y => 
        AO1_21_Y);
    XOR2_36 : XOR2
      port map(A => MEM_RADDR_5_net, B => GND_1_net, Y => 
        XOR2_36_Y);
    XNOR2_8 : XNOR2
      port map(A => RBINNXTSHIFT_0_net, B => MEM_WADDR_0_net, 
        Y => XNOR2_8_Y);
    AND2_28 : AND2
      port map(A => XNOR2_17_Y, B => XNOR2_6_Y, Y => AND2_28_Y);
    AND2_25 : AND2
      port map(A => AND2_23_Y, B => XOR2_20_Y, Y => AND2_25_Y);
    AO1C_6 : AO1C
      port map(A => WDIFF_0_net, B => AFVALCONST_0_net, C => 
        OR2A_4_Y, Y => AO1C_6_Y);
    AO1C_2 : AO1C
      port map(A => AEVALCONST_0_net, B => RDIFF_3_net, C => 
        AO1C_4_Y, Y => AO1C_2_Y);
end DEF_ARCH;
