`timescale 1 ns/100 ps
// Version: 10.0 10.0.9.37


module ACE_PDMA(
       UART_0_TXD,
       UART_0_RXD,
       MSS_RESET_N,
       VM_Direct,
       VAREF0
    );
output UART_0_TXD;
input  UART_0_RXD;
input  MSS_RESET_N;
input  VM_Direct;
input  VAREF0;

    wire GND_net, VCC_net;
    
    VCC VCC (.Y(VCC_net));
    ACE_PDMA_MSS ACE_PDMA_MSS_0 (.UART_0_TXD(UART_0_TXD), .UART_0_RXD(
        UART_0_RXD), .MSS_RESET_N(MSS_RESET_N), .VM_Direct(VM_Direct), 
        .VAREF0(VAREF0));
    GND GND (.Y(GND_net));
    
endmodule
