Timing Report Min Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Thu Dec 08 14:59:31 2011


Design: Top_Waveform
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.661
External Hold (ns):         1.288
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_glb
Period (ns):                36.239
Frequency (MHz):            27.595
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               MSS_Waveform_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.277
  Slack (ns):
  Arrival (ns):                0.277
  Required (ns):
  Hold (ns):                   1.294
  External Hold (ns):          1.288


Expanded Path 1
  From: MSS_RESET_N
  To: MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.277
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        MSS_Waveform_0/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.277          cell: ADLIB:IOPAD_IN
  0.277                        MSS_Waveform_0/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: MSS_Waveform_0/MSS_RESET_0_MSS_RESET_N_Y
  0.277                        MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.277                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.271          net: MSS_Waveform_0/GLA0
  N/C                          MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.294          Library hold time: ADLIB:MSS_APB_IP
  N/C                          MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glb

SET Register to Register

Path 1
  From:                        COREABC_0/ABClOOOI:CLK
  To:                          COREABC_0/ABCOIOOI:D
  Delay (ns):                  0.399
  Slack (ns):
  Arrival (ns):                0.730
  Required (ns):
  Hold (ns):                   0.000

Path 2
  From:                        COREABC_0/ABCO111[1]:CLK
  To:                          COREABC_0/ABCO111[1]:D
  Delay (ns):                  0.733
  Slack (ns):
  Arrival (ns):                1.058
  Required (ns):
  Hold (ns):                   0.000

Path 3
  From:                        COREABC_0/STKPTR[1]:CLK
  To:                          COREABC_0/STKPTR[1]:D
  Delay (ns):                  0.759
  Slack (ns):
  Arrival (ns):                1.071
  Required (ns):
  Hold (ns):                   0.000

Path 4
  From:                        COREABC_0/SMADDR[1]:CLK
  To:                          COREABC_0/genblk19.UROM.INSTR_ADDR[0]:D
  Delay (ns):                  0.814
  Slack (ns):
  Arrival (ns):                1.139
  Required (ns):
  Hold (ns):                   0.000

Path 5
  From:                        COREABC_0/STKPTR[3]:CLK
  To:                          COREABC_0/STKPTR[3]:D
  Delay (ns):                  0.815
  Slack (ns):
  Arrival (ns):                1.127
  Required (ns):
  Hold (ns):                   0.000


Expanded Path 1
  From: COREABC_0/ABClOOOI:CLK
  To: COREABC_0/ABCOIOOI:D
  data arrival time                              0.730
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.331          net: FAB_CLK
  0.331                        COREABC_0/ABClOOOI:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  0.580                        COREABC_0/ABClOOOI:Q (r)
               +     0.150          net: COREABC_0/ABClOOOI
  0.730                        COREABC_0/ABCOIOOI:D (r)
                                    
  0.730                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.345          net: FAB_CLK
  N/C                          COREABC_0/ABCOIOOI:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          COREABC_0/ABCOIOOI:D


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        COREABC_0/ABCOIOOI:CLK
  To:                          COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10:RESET
  Delay (ns):                  3.456
  Slack (ns):
  Arrival (ns):                3.785
  Required (ns):
  Removal (ns):                0.170
  Skew (ns):                   -0.107

Path 2
  From:                        COREABC_0/ABCOIOOI:CLK
  To:                          COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl1I1.ABCOOl1/ABCll10:RESET
  Delay (ns):                  3.456
  Slack (ns):
  Arrival (ns):                3.785
  Required (ns):
  Removal (ns):                0.170
  Skew (ns):                   -0.106

Path 3
  From:                        COREABC_0/ABCOIOOI:CLK
  To:                          COREABC_0/ZREGISTER[4]:CLR
  Delay (ns):                  3.303
  Slack (ns):
  Arrival (ns):                3.632
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.024

Path 4
  From:                        COREABC_0/ABCOIOOI:CLK
  To:                          COREABC_0/ZREGISTER[3]:CLR
  Delay (ns):                  3.311
  Slack (ns):
  Arrival (ns):                3.640
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.031

Path 5
  From:                        COREABC_0/ABCOIOOI:CLK
  To:                          COREABC_0/ZREGISTER[2]:CLR
  Delay (ns):                  3.311
  Slack (ns):
  Arrival (ns):                3.640
  Required (ns):
  Removal (ns):                0.000
  Skew (ns):                   -0.031


Expanded Path 1
  From: COREABC_0/ABCOIOOI:CLK
  To: COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10:RESET
  data arrival time                              3.785
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.329          net: FAB_CLK
  0.329                        COREABC_0/ABCOIOOI:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  0.578                        COREABC_0/ABCOIOOI:Q (r)
               +     2.002          net: COREABC_0/ABCOIOOI
  2.580                        COREABC_0/ABCOIOOI_RNINBN1/U_CLKSRC:A (r)
               +     0.743          cell: ADLIB:CLKSRC
  3.323                        COREABC_0/ABCOIOOI_RNINBN1/U_CLKSRC:Y (r)
               +     0.462          net: COREABC_0_PRESETN
  3.785                        COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10:RESET (r)
                                    
  3.785                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.436          net: FAB_CLK
  N/C                          COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10:WCLK (r)
               +     0.170          Library removal time: ADLIB:RAM512X18
  N/C                          COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10:RESET


END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MSS_Waveform_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

