Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Thu Dec 08 14:59:31 2011


Design: Top_Waveform
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.661
External Hold (ns):         1.288
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_glb
Period (ns):                36.239
Frequency (MHz):            27.595
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               MSS_Waveform_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.937
  Slack (ns):
  Arrival (ns):                0.937
  Required (ns):
  Setup (ns):                  -2.139
  External Setup (ns):         -1.661


Expanded Path 1
  From: MSS_RESET_N
  To: MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.937
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        MSS_Waveform_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.937          cell: ADLIB:IOPAD_IN
  0.937                        MSS_Waveform_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: MSS_Waveform_0/MSS_RESET_0_MSS_RESET_N_Y
  0.937                        MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.937                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.459          net: MSS_Waveform_0/GLA0
  N/C                          MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -2.139          Library setup time: ADLIB:MSS_APB_IP
  N/C                          MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glb

SET Register to Register

Path 1
  From:                        COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10:RCLK
  To:                          COREABC_0/ABCIl01:D
  Delay (ns):                  35.599
  Slack (ns):
  Arrival (ns):                36.411
  Required (ns):
  Setup (ns):                  0.490
  Minimum Period (ns):         36.239

Path 2
  From:                        COREABC_0/genblk19.UROM.INSTR_CMD[0]:CLK
  To:                          COREABC_0/ABCIl01:D
  Delay (ns):                  34.934
  Slack (ns):
  Arrival (ns):                35.609
  Required (ns):
  Setup (ns):                  0.490
  Minimum Period (ns):         35.437

Path 3
  From:                        COREABC_0/genblk19.UROM.INSTR_CMD[1]:CLK
  To:                          COREABC_0/ABCIl01:D
  Delay (ns):                  34.897
  Slack (ns):
  Arrival (ns):                35.572
  Required (ns):
  Setup (ns):                  0.490
  Minimum Period (ns):         35.400

Path 4
  From:                        COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10:RCLK
  To:                          COREABC_0/ACCUMULATOR[31]:D
  Delay (ns):                  34.433
  Slack (ns):
  Arrival (ns):                35.245
  Required (ns):
  Setup (ns):                  0.490
  Minimum Period (ns):         35.073

Path 5
  From:                        COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10:RCLK
  To:                          COREABC_0/ABCll01:D
  Delay (ns):                  34.433
  Slack (ns):
  Arrival (ns):                35.245
  Required (ns):
  Setup (ns):                  0.490
  Minimum Period (ns):         35.065


Expanded Path 1
  From: COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10:RCLK
  To: COREABC_0/ABCIl01:D
  data required time                             N/C
  data arrival time                          -   36.411
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.812          net: FAB_CLK
  0.812                        COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10:RCLK (r)
               +     2.632          cell: ADLIB:RAM512X18
  3.444                        COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10:RD0 (r)
               +     1.454          net: COREABC_0/ABCIl11[0]
  4.898                        COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10_RNISGLP:B (r)
               +     0.617          cell: ADLIB:MX2C
  5.515                        COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10_RNISGLP:Y (f)
               +     1.060          net: COREABC_0/ABCll10_RNISGLP
  6.575                        COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I1_CO1_m7_i_o4:B (f)
               +     0.574          cell: ADLIB:OR2B
  7.149                        COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I1_CO1_m7_i_o4:Y (r)
               +     0.306          net: COREABC_0/ADD_32x32_slow_I1_CO1_N_12
  7.455                        COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I1_CO1_m7_i_a4:C (r)
               +     0.606          cell: ADLIB:OR3C
  8.061                        COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I1_CO1_m7_i_a4:Y (f)
               +     0.306          net: COREABC_0/ADD_32x32_slow_I1_CO1_N_13
  8.367                        COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I1_CO1_m7_i:C (f)
               +     0.620          cell: ADLIB:OR3C
  8.987                        COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I1_CO1_m7_i:Y (r)
               +     0.349          net: COREABC_0/N384
  9.336                        COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I2_un1_CO1_m4_i:B (r)
               +     0.850          cell: ADLIB:MAJ3
  10.186                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I2_un1_CO1_m4_i:Y (r)
               +     0.353          net: COREABC_0/ADD_32x32_slow_I2_un1_CO1_m4_i
  10.539                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I5_CO1_m1:A (r)
               +     0.313          cell: ADLIB:XOR2
  10.852                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I5_CO1_m1:Y (r)
               +     0.306          net: COREABC_0/ADD_32x32_slow_I5_CO1_N_2_i_0
  11.158                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I5_CO1_m7:C (r)
               +     0.606          cell: ADLIB:OR3C
  11.764                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I5_CO1_m7:Y (f)
               +     0.368          net: COREABC_0/ADD_32x32_slow_I5_CO1_m7
  12.132                       COREABC_0/ACCUMULATOR_RNINMPIB[7]:C (f)
               +     0.660          cell: ADLIB:XA1A
  12.792                       COREABC_0/ACCUMULATOR_RNINMPIB[7]:Y (f)
               +     0.294          net: COREABC_0/ACCUMULATOR_RNINMPIB[7]
  13.086                       COREABC_0/ACCUMULATOR_RNI4VV6O[7]:S (f)
               +     0.437          cell: ADLIB:MX2
  13.523                       COREABC_0/ACCUMULATOR_RNI4VV6O[7]:Y (r)
               +     0.306          net: COREABC_0/d_N_4_5
  13.829                       COREABC_0/ACCUMULATOR_RNIO1H2Q[8]:B (r)
               +     0.533          cell: ADLIB:MX2
  14.362                       COREABC_0/ACCUMULATOR_RNIO1H2Q[8]:Y (r)
               +     0.306          net: COREABC_0/ACCUMULATOR_RNIO1H2Q[8]
  14.668                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I8_un1_CO1_1:A (r)
               +     0.517          cell: ADLIB:MX2B
  15.185                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I8_un1_CO1_1:Y (r)
               +     1.159          net: COREABC_0/ADD_32x32_slow_I8_un1_CO1_1
  16.344                       COREABC_0/ACCUMULATOR_RNIR29OL1[10]:B (r)
               +     0.895          cell: ADLIB:MIN3
  17.239                       COREABC_0/ACCUMULATOR_RNIR29OL1[10]:Y (f)
               +     0.291          net: COREABC_0/d_N_4_3
  17.530                       COREABC_0/ACCUMULATOR_RNIHOUEN1[11]:C (f)
               +     0.446          cell: ADLIB:AO13
  17.976                       COREABC_0/ACCUMULATOR_RNIHOUEN1[11]:Y (r)
               +     0.294          net: COREABC_0/ACCUMULATOR_RNIHOUEN1[11]
  18.270                       COREABC_0/ACCUMULATOR_RNI1OSKG3[11]:A (r)
               +     0.606          cell: ADLIB:MX2A
  18.876                       COREABC_0/ACCUMULATOR_RNI1OSKG3[11]:Y (f)
               +     0.897          net: COREABC_0/ACCUMULATOR_RNI1OSKG3[11]
  19.773                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I18_un1_CO1_1:B (f)
               +     0.563          cell: ADLIB:MX2C
  20.336                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I18_un1_CO1_1:Y (r)
               +     0.829          net: COREABC_0/ADD_32x32_slow_I18_un1_CO1_1
  21.165                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I19_CO1:A (r)
               +     0.478          cell: ADLIB:MAJ3
  21.643                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I19_CO1:Y (r)
               +     0.967          net: COREABC_0/N420
  22.610                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I20_un1_CO1:C (r)
               +     0.558          cell: ADLIB:AO18
  23.168                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I20_un1_CO1:Y (f)
               +     0.365          net: COREABC_0/I20_un1_CO1_i
  23.533                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I21_CO1:C (f)
               +     0.421          cell: ADLIB:AO18
  23.954                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I21_CO1:Y (r)
               +     0.407          net: COREABC_0/N424
  24.361                       COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl1I1.ABCOOl1/ABCll10_RNIQBO399:A (r)
               +     0.666          cell: ADLIB:OA1A
  25.027                       COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl1I1.ABCOOl1/ABCll10_RNIQBO399:Y (f)
               +     1.070          net: COREABC_0/r_N_2_i_0
  26.097                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I25_CO1_1:B (f)
               +     0.520          cell: ADLIB:MX2
  26.617                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I25_CO1_1:Y (f)
               +     0.351          net: COREABC_0/ADD_32x32_slow_I25_CO1_0
  26.968                       COREABC_0/ACCUMULATOR_RNIG5Q8P9[24]:B (f)
               +     0.543          cell: ADLIB:AO1B
  27.511                       COREABC_0/ACCUMULATOR_RNIG5Q8P9[24]:Y (f)
               +     0.306          net: COREABC_0/ACCUMULATOR_RNIG5Q8P9[24]
  27.817                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I26_un1_CO1_1:A (f)
               +     0.563          cell: ADLIB:MX2C
  28.380                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I26_un1_CO1_1:Y (r)
               +     0.334          net: COREABC_0/ADD_32x32_slow_I26_un1_CO1_1
  28.714                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I27_CO1_i:A (r)
               +     0.478          cell: ADLIB:MAJ3
  29.192                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I27_CO1_i:Y (r)
               +     0.863          net: COREABC_0/N_11
  30.055                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I28_un1_CO1_i_o3:B (r)
               +     0.895          cell: ADLIB:MAJ3
  30.950                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I28_un1_CO1_i_o3:Y (r)
               +     0.369          net: COREABC_0/N_12
  31.319                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I29_CO1_i_o3:A (r)
               +     0.691          cell: ADLIB:AO13
  32.010                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I29_CO1_i_o3:Y (r)
               +     0.351          net: COREABC_0/N_13
  32.361                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I30_un1_CO1_i:C (r)
               +     0.649          cell: ADLIB:MIN3
  33.010                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I30_un1_CO1_i:Y (f)
               +     0.306          net: COREABC_0/N_9
  33.316                       COREABC_0/genblk19.UROM.INSTR_SCMD_RNI4EHA6T[0]:A (f)
               +     0.581          cell: ADLIB:XAI1
  33.897                       COREABC_0/genblk19.UROM.INSTR_SCMD_RNI4EHA6T[0]:Y (r)
               +     0.296          net: COREABC_0/un1_ACCUMULATOR_m_i[31]
  34.193                       COREABC_0/ACCUMULATOR_RNI7S4KRT[31]:C (r)
               +     0.683          cell: ADLIB:OR3C
  34.876                       COREABC_0/ACCUMULATOR_RNI7S4KRT[31]:Y (f)
               +     0.661          net: COREABC_0/ABClIl1[31]
  35.537                       COREABC_0/ABCIl01_RNO:C (f)
               +     0.568          cell: ADLIB:NOR3A
  36.105                       COREABC_0/ABCIl01_RNO:Y (r)
               +     0.306          net: COREABC_0/ABCO0I_4[0]
  36.411                       COREABC_0/ABCIl01:D (r)
                                    
  36.411                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.662          net: FAB_CLK
  N/C                          COREABC_0/ABCIl01:CLK (r)
               -     0.490          Library setup time: ADLIB:DFN1E1C0
  N/C                          COREABC_0/ABCIl01:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        COREABC_0/ABCOIOOI:CLK
  To:                          COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10:RESET
  Delay (ns):                  7.127
  Slack (ns):
  Arrival (ns):                7.797
  Required (ns):
  Recovery (ns):               1.780
  Minimum Period (ns):         8.765
  Skew (ns):                   -0.142

Path 2
  From:                        COREABC_0/ABCOIOOI:CLK
  To:                          COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl1I1.ABCOOl1/ABCll10:RESET
  Delay (ns):                  7.127
  Slack (ns):
  Arrival (ns):                7.797
  Required (ns):
  Recovery (ns):               1.780
  Minimum Period (ns):         8.765
  Skew (ns):                   -0.142

Path 3
  From:                        COREABC_0/ABCOIOOI:CLK
  To:                          COREABC_0/ABCO111[1]:PRE
  Delay (ns):                  6.856
  Slack (ns):
  Arrival (ns):                7.526
  Required (ns):
  Recovery (ns):               0.271
  Minimum Period (ns):         7.135
  Skew (ns):                   0.008

Path 4
  From:                        COREABC_0/ABCOIOOI:CLK
  To:                          COREABC_0/ABCO111[0]:PRE
  Delay (ns):                  6.856
  Slack (ns):
  Arrival (ns):                7.526
  Required (ns):
  Recovery (ns):               0.271
  Minimum Period (ns):         7.135
  Skew (ns):                   0.008

Path 5
  From:                        COREABC_0/ABCOIOOI:CLK
  To:                          COREABC_0/STKPTR[2]:PRE
  Delay (ns):                  6.815
  Slack (ns):
  Arrival (ns):                7.485
  Required (ns):
  Recovery (ns):               0.271
  Minimum Period (ns):         7.126
  Skew (ns):                   0.040


Expanded Path 1
  From: COREABC_0/ABCOIOOI:CLK
  To: COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10:RESET
  data required time                             N/C
  data arrival time                          -   7.797
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.670          net: FAB_CLK
  0.670                        COREABC_0/ABCOIOOI:CLK (r)
               +     0.528          cell: ADLIB:DFN1C0
  1.198                        COREABC_0/ABCOIOOI:Q (r)
               +     4.079          net: COREABC_0/ABCOIOOI
  5.277                        COREABC_0/ABCOIOOI_RNINBN1/U_CLKSRC:A (r)
               +     1.578          cell: ADLIB:CLKSRC
  6.855                        COREABC_0/ABCOIOOI_RNINBN1/U_CLKSRC:Y (r)
               +     0.942          net: COREABC_0_PRESETN
  7.797                        COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10:RESET (r)
                                    
  7.797                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.812          net: FAB_CLK
  N/C                          COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10:RCLK (r)
               -     1.780          Library recovery time: ADLIB:RAM512X18
  N/C                          COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10:RESET


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MSS_Waveform_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

