Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Thu Dec 08 14:59:37 2011


Design: Top_Waveform
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.661
External Hold (ns):         1.288
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_glb
Period (ns):                37.950
Frequency (MHz):            26.350
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               MSS_Waveform_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.937
  Slack (ns):
  Arrival (ns):                0.937
  Required (ns):
  Setup (ns):                  -2.139
  External Setup (ns):         -1.661


Expanded Path 1
  From: MSS_RESET_N
  To: MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.937
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        MSS_Waveform_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.937          cell: ADLIB:IOPAD_IN
  0.937                        MSS_Waveform_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: MSS_Waveform_0/MSS_RESET_0_MSS_RESET_N_Y
  0.937                        MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.937                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.459          net: MSS_Waveform_0/GLA0
  N/C                          MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -2.139          Library setup time: ADLIB:MSS_APB_IP
  N/C                          MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glb

SET Register to Register

Path 1
  From:                        COREABC_0/INstr_cmd[2]:CLK
  To:                          COREABC_0/ABClil1:D
  Delay (ns):                  37.460
  Slack (ns):
  Arrival (ns):                38.140
  Required (ns):
  Setup (ns):                  0.490
  Minimum Period (ns):         37.950

Path 2
  From:                        COREABC_0/iNSTR_SCMd[1]:CLK
  To:                          COREABC_0/ABClil1:D
  Delay (ns):                  37.375
  Slack (ns):
  Arrival (ns):                38.054
  Required (ns):
  Setup (ns):                  0.490
  Minimum Period (ns):         37.864

Path 3
  From:                        COREABC_0/INstr_cmd[1]:CLK
  To:                          COREABC_0/ABClil1:D
  Delay (ns):                  37.374
  Slack (ns):
  Arrival (ns):                38.054
  Required (ns):
  Setup (ns):                  0.490
  Minimum Period (ns):         37.864

Path 4
  From:                        COREABC_0/iNSTR_SCMd[2]:CLK
  To:                          COREABC_0/ABClil1:D
  Delay (ns):                  37.332
  Slack (ns):
  Arrival (ns):                38.011
  Required (ns):
  Setup (ns):                  0.490
  Minimum Period (ns):         37.821

Path 5
  From:                        COREABC_0/INstr_cmd[0]:CLK
  To:                          COREABC_0/ABClil1:D
  Delay (ns):                  37.154
  Slack (ns):
  Arrival (ns):                37.833
  Required (ns):
  Setup (ns):                  0.490
  Minimum Period (ns):         37.643


Expanded Path 1
  From: COREABC_0/INstr_cmd[2]:CLK
  To: COREABC_0/ABClil1:D
  data required time                             N/C
  data arrival time                          -   38.140
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.680          net: FAB_CLK
  0.680                        COREABC_0/INstr_cmd[2]:CLK (r)
               +     0.671          cell: ADLIB:DFN1
  1.351                        COREABC_0/INstr_cmd[2]:Q (f)
               +     0.306          net: COREABC_0/INstr_cmd[2]
  1.657                        COREABC_0/INstr_cmd_RNI8MCD[2]:C (f)
               +     0.606          cell: ADLIB:OR3B
  2.263                        COREABC_0/INstr_cmd_RNI8MCD[2]:Y (f)
               +     0.306          net: COREABC_0/ABCOI01_0_tz[0]
  2.569                        COREABC_0/iNSTR_SCMd_RNIJMQD_0[1]:B (f)
               +     0.592          cell: ADLIB:OR2
  3.161                        COREABC_0/iNSTR_SCMd_RNIJMQD_0[1]:Y (f)
               +     0.896          net: COREABC_0/un3_abclli1
  4.057                        COREABC_0/iNSTR_SCMd_RNIPM1E[2]:A (f)
               +     0.331          cell: ADLIB:OR2A
  4.388                        COREABC_0/iNSTR_SCMd_RNIPM1E[2]:Y (r)
               +     3.401          net: COREABC_0/iNSTR_SCMd_RNIPM1E[2]
  7.789                        COREABC_0/iNSTR_SCMd_RNIPM1E_0[2]/U_CLKSRC:A (r)
               +     0.829          cell: ADLIB:CLKSRC
  8.618                        COREABC_0/iNSTR_SCMd_RNIPM1E_0[2]/U_CLKSRC:Y (r)
               +     0.678          net: COREABC_0/N_1_i_0
  9.296                        COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I2_un1_CO1_m14_i_o5_0:A (r)
               +     0.445          cell: ADLIB:OR2B
  9.741                        COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I2_un1_CO1_m14_i_o5_0:Y (f)
               +     0.296          net: COREABC_0/ADD_32x32_slow_I2_un1_CO1_N_20
  10.037                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I2_un1_CO1_m14_i_0:B (f)
               +     0.829          cell: ADLIB:AOI1B
  10.866                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I2_un1_CO1_m14_i_0:Y (r)
               +     0.294          net: COREABC_0/ADD_32x32_slow_I2_un1_CO1_m14_i_0
  11.160                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I2_un1_CO1_m14_i:A (r)
               +     0.478          cell: ADLIB:NOR3C
  11.638                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I2_un1_CO1_m14_i:Y (r)
               +     0.656          net: COREABC_0/I2_un1_CO1_i_0
  12.294                       COREABC_0/ACCUMULAtor_RNI6VA8B[4]:A (r)
               +     0.361          cell: ADLIB:AO18
  12.655                       COREABC_0/ACCUMULAtor_RNI6VA8B[4]:Y (f)
               +     0.306          net: COREABC_0/d_N_4_2
  12.961                       COREABC_0/ACCUMULAtor_RNILD1NC[5]:B (f)
               +     0.563          cell: ADLIB:MX2C
  13.524                       COREABC_0/ACCUMULAtor_RNILD1NC[5]:Y (r)
               +     0.296          net: COREABC_0/ACCUMULAtor_RNILD1NC[5]
  13.820                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I5_CO1_1:A (r)
               +     0.606          cell: ADLIB:MX2
  14.426                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I5_CO1_1:Y (r)
               +     0.369          net: COREABC_0/N392
  14.795                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I6_un1_CO1:C (r)
               +     0.558          cell: ADLIB:AO18
  15.353                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I6_un1_CO1:Y (f)
               +     0.953          net: COREABC_0/I6_un1_CO1
  16.306                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I7_CO1:C (f)
               +     0.421          cell: ADLIB:AO18
  16.727                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I7_CO1:Y (r)
               +     0.406          net: COREABC_0/N396
  17.133                       COREABC_0/ACCUMULAtor_RNI0UNDU[8]:B (r)
               +     0.666          cell: ADLIB:AO13
  17.799                       COREABC_0/ACCUMULAtor_RNI0UNDU[8]:Y (r)
               +     0.313          net: COREABC_0/ACCUMULAtor_RNI0UNDU[8]
  18.112                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I11_CO1_1:B (r)
               +     0.617          cell: ADLIB:MX2
  18.729                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I11_CO1_1:Y (r)
               +     0.320          net: COREABC_0/ADD_32x32_slow_I11_CO1_0_i
  19.049                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I11_CO1:C (r)
               +     0.596          cell: ADLIB:AO1C
  19.645                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I11_CO1:Y (f)
               +     1.281          net: COREABC_0/N404
  20.926                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I15_CO1_m3:B (f)
               +     0.750          cell: ADLIB:XAI1
  21.676                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I15_CO1_m3:Y (f)
               +     0.368          net: COREABC_0/ADD_32x32_slow_I15_CO1_m3
  22.044                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I15_CO1_m6:B (f)
               +     0.574          cell: ADLIB:NOR2B
  22.618                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I15_CO1_m6:Y (f)
               +     0.294          net: COREABC_0/ADD_32x32_slow_I15_CO1_m6
  22.912                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I15_CO1_1:S (f)
               +     0.473          cell: ADLIB:MX2C
  23.385                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I15_CO1_1:Y (f)
               +     2.068          net: COREABC_0/N412
  25.453                       COREABC_0/ACCUMULAtor_RNIVNL4Q6[17]:A (f)
               +     0.446          cell: ADLIB:AO18
  25.899                       COREABC_0/ACCUMULAtor_RNIVNL4Q6[17]:Y (r)
               +     0.296          net: COREABC_0/d_N_4_3
  26.195                       COREABC_0/ACCUMULAtor_RNIHNDJR6[18]:B (r)
               +     0.617          cell: ADLIB:MX2C
  26.812                       COREABC_0/ACCUMULAtor_RNIHNDJR6[18]:Y (f)
               +     0.369          net: COREABC_0/ACCUMULAtor_RNIHNDJR6[18]
  27.181                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I26_un1_CO1:A (f)
               +     0.563          cell: ADLIB:MX2C
  27.744                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I26_un1_CO1:Y (r)
               +     0.351          net: COREABC_0/I26_un1_CO1
  28.095                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I27_CO1_i_a3:B (r)
               +     0.606          cell: ADLIB:AO1
  28.701                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I27_CO1_i_a3:Y (r)
               +     0.294          net: COREABC_0/N_18
  28.995                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I27_CO1_i:C (r)
               +     0.362          cell: ADLIB:AOI1D
  29.357                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I27_CO1_i:Y (r)
               +     1.116          net: COREABC_0/N_11_i_0
  30.473                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I28_un1_CO1_i_o3_0_tz:A (r)
               +     0.331          cell: ADLIB:OR2
  30.804                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I28_un1_CO1_i_o3_0_tz:Y (r)
               +     0.296          net: COREABC_0/ADD_32x32_slow_I28_un1_CO1_i_o3_0_tz
  31.100                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I28_un1_CO1_i_o3_0:C (r)
               +     0.683          cell: ADLIB:OR3C
  31.783                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I28_un1_CO1_i_o3_0:Y (f)
               +     0.306          net: COREABC_0/ADD_32x32_slow_I28_un1_CO1_i_o3_0
  32.089                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I28_un1_CO1_i_o3:C (f)
               +     0.642          cell: ADLIB:AO1B
  32.731                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I28_un1_CO1_i_o3:Y (r)
               +     0.351          net: COREABC_0/N_12
  33.082                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I29_CO1_i_o3:B (r)
               +     0.850          cell: ADLIB:MAJ3
  33.932                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I29_CO1_i_o3:Y (r)
               +     0.369          net: COREABC_0/N_13
  34.301                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I30_un1_CO1_i:C (r)
               +     0.658          cell: ADLIB:MIN3
  34.959                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I30_un1_CO1_i:Y (f)
               +     0.306          net: COREABC_0/N_9
  35.265                       COREABC_0/INstr_cmd_RNIMNT88R1[1]:A (f)
               +     0.581          cell: ADLIB:XAI1
  35.846                       COREABC_0/INstr_cmd_RNIMNT88R1[1]:Y (r)
               +     0.296          net: COREABC_0/un1_ACCUMULAtor_m_i[31]
  36.142                       COREABC_0/ACCUMULAtor_RNIIQQAOR1[30]:C (r)
               +     0.683          cell: ADLIB:OR3C
  36.825                       COREABC_0/ACCUMULAtor_RNIIQQAOR1[30]:Y (f)
               +     0.441          net: COREABC_0/ABCILO1[31]
  37.266                       COREABC_0/ABClil1_RNO:C (f)
               +     0.568          cell: ADLIB:NOR3A
  37.834                       COREABC_0/ABClil1_RNO:Y (r)
               +     0.306          net: COREABC_0/abclil1_net_1
  38.140                       COREABC_0/ABClil1:D (r)
                                    
  38.140                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.680          net: FAB_CLK
  N/C                          COREABC_0/ABClil1:CLK (r)
               -     0.490          Library setup time: ADLIB:DFN1E1C0
  N/C                          COREABC_0/ABClil1:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        COREABC_0/ABCLL01:CLK
  To:                          COREABC_0/ABCO01.ABCii1/ABCII00.ABCO000.ABCl000/ABCI0l0:RESET
  Delay (ns):                  7.295
  Slack (ns):
  Arrival (ns):                7.972
  Required (ns):
  Recovery (ns):               1.780
  Minimum Period (ns):         8.940
  Skew (ns):                   -0.135

Path 2
  From:                        COREABC_0/ABCLL01:CLK
  To:                          COREABC_0/ABCO01.ABCii1/ABCII00.ABCII1/ABCI0l0:RESET
  Delay (ns):                  7.295
  Slack (ns):
  Arrival (ns):                7.972
  Required (ns):
  Recovery (ns):               1.780
  Minimum Period (ns):         8.940
  Skew (ns):                   -0.135

Path 3
  From:                        COREABC_0/ABCLL01:CLK
  To:                          COREABC_0/ABCLOI1:CLR
  Delay (ns):                  7.024
  Slack (ns):
  Arrival (ns):                7.701
  Required (ns):
  Recovery (ns):               0.271
  Minimum Period (ns):         7.315
  Skew (ns):                   0.020

Path 4
  From:                        COREABC_0/ABCLL01:CLK
  To:                          COREABC_0/ABCooi1:CLR
  Delay (ns):                  7.031
  Slack (ns):
  Arrival (ns):                7.708
  Required (ns):
  Recovery (ns):               0.271
  Minimum Period (ns):         7.313
  Skew (ns):                   0.011

Path 5
  From:                        COREABC_0/ABCLL01:CLK
  To:                          COREABC_0/ABClll1:PRE
  Delay (ns):                  7.031
  Slack (ns):
  Arrival (ns):                7.708
  Required (ns):
  Recovery (ns):               0.271
  Minimum Period (ns):         7.308
  Skew (ns):                   0.006


Expanded Path 1
  From: COREABC_0/ABCLL01:CLK
  To: COREABC_0/ABCO01.ABCii1/ABCII00.ABCO000.ABCl000/ABCI0l0:RESET
  data required time                             N/C
  data arrival time                          -   7.972
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.677          net: FAB_CLK
  0.677                        COREABC_0/ABCLL01:CLK (r)
               +     0.528          cell: ADLIB:DFN1C0
  1.205                        COREABC_0/ABCLL01:Q (r)
               +     4.247          net: COREABC_0/ABCLL01
  5.452                        COREABC_0/ABCLL01_RNIN7Q5/U_CLKSRC:A (r)
               +     1.578          cell: ADLIB:CLKSRC
  7.030                        COREABC_0/ABCLL01_RNIN7Q5/U_CLKSRC:Y (r)
               +     0.942          net: COREABC_0_PRESETN
  7.972                        COREABC_0/ABCO01.ABCii1/ABCII00.ABCO000.ABCl000/ABCI0l0:RESET (r)
                                    
  7.972                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.812          net: FAB_CLK
  N/C                          COREABC_0/ABCO01.ABCii1/ABCII00.ABCO000.ABCl000/ABCI0l0:RCLK (r)
               -     1.780          Library recovery time: ADLIB:RAM512X18
  N/C                          COREABC_0/ABCO01.ABCii1/ABCII00.ABCO000.ABCl000/ABCI0l0:RESET


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MSS_Waveform_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

