#Build: Synplify Pro D-2009.12A, Build 040R, Jan 20 2010 #install: D:\Actel\Libero_v9.0\Synopsys\synplify_D200912A #OS: Windows XP 5.1 #Hostname: WXPL-ODIGAS #Implementation: synthesis #Tue Aug 31 18:49:08 2010 $ Start of Compile #Tue Aug 31 18:49:08 2010 Synopsys Verilog Compiler, version comp475rc, Build 060R, built Jan 15 2010 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved @I::"D:\Actel\Libero_v9.0\Synopsys\synplify_D200912A\lib\proasic\smartfusion.v" @I::"D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\hdl\APB_sine_LUT.v" @I:"D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\hdl\APB_sine_LUT.v":"D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\hdl\sine_LUT.v" @I::"D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\Actel\SmartFusionMSS\MSS\2.2.101\mss_comps.v" @I::"D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\work\MSS_Waveform\MSS_CCC_0\MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v" @I::"D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\work\MSS_Waveform\MSS_Waveform.v" @I::"D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vlog\core_obfuscated\ram256x16_pa3.v" @I::"D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vlog\core_obfuscated\ram256x8_rtl.v" @I::"D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vlog\core_obfuscated\ramblocks.v" @I::"D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vlog\core_obfuscated\acmtable.v" @I::"D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vlog\core_obfuscated\instructions.v" @I:"D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vlog\core_obfuscated\instructions.v":"D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vlog\core_obfuscated\support.v" @I::"D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vlog\core_obfuscated\iram512x9_pa3.v" @N:CG334 : iram512x9_pa3.v(198) | Read directive translate_off @N:CG333 : iram512x9_pa3.v(199) | Read directive translate_on @I::"D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vlog\core_obfuscated\instructram.v" @I::"D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vlog\core_obfuscated\instructnvm_bb.v" @I::"D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vlog\core_obfuscated\debugblk.v" @N:CG334 : debugblk.v(5933) | Read directive translate_off @N:CG333 : debugblk.v(9027) | Read directive translate_on @I::"D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vlog\core_obfuscated\coreabc.v" @N:CG334 : coreabc.v(9865) | Read directive translate_off @N:CG333 : coreabc.v(9870) | Read directive translate_on @N:CG334 : coreabc.v(11560) | Read directive translate_off @N:CG333 : coreabc.v(11795) | Read directive translate_on @I::"D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3_muxptob3.v" @I::"D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v" @I::"D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\work\Top_Waveform\Top_Waveform.v" Verilog syntax check successful! File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vlog\core_obfuscated\ram256x16_pa3.v changed - recompiling File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vlog\core_obfuscated\ram256x8_rtl.v changed - recompiling File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vlog\core_obfuscated\ramblocks.v changed - recompiling File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vlog\core_obfuscated\acmtable.v changed - recompiling File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vlog\core_obfuscated\instructions.v changed - recompiling File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vlog\core_obfuscated\support.v changed - recompiling File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vlog\core_obfuscated\iram512x9_pa3.v changed - recompiling File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vlog\core_obfuscated\instructram.v changed - recompiling File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vlog\core_obfuscated\instructnvm_bb.v changed - recompiling File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vlog\core_obfuscated\debugblk.v changed - recompiling File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vlog\core_obfuscated\coreabc.v changed - recompiling File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3_muxptob3.v changed - recompiling File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v changed - recompiling File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\component\work\Top_Waveform\Top_Waveform.v changed - recompiling Selecting top level module Top_Waveform @W:CG775 : coreapb3.v(13) | Found Component CoreAPB3 in library COREAPB3_LIB @N:CG364 : coreapb3_muxptob3.v(13) | Synthesizing module CAPB3O @N:CG364 : coreapb3.v(13) | Synthesizing module CoreAPB3 APB_DWIDTH=6'b100000 RANGESIZE=21'b000010000000000000000 IADDR_ENABLE=1'b1 APBSLOT0ENABLE=1'b1 APBSLOT1ENABLE=1'b1 APBSLOT2ENABLE=1'b1 APBSLOT3ENABLE=1'b0 APBSLOT4ENABLE=1'b0 APBSLOT5ENABLE=1'b0 APBSLOT6ENABLE=1'b0 APBSLOT7ENABLE=1'b0 APBSLOT8ENABLE=1'b0 APBSLOT9ENABLE=1'b0 APBSLOT10ENABLE=1'b0 APBSLOT11ENABLE=1'b0 APBSLOT12ENABLE=1'b0 APBSLOT13ENABLE=1'b0 APBSLOT14ENABLE=1'b0 APBSLOT15ENABLE=1'b0 CAPB3O1I=32'b00000000000000000000000000010000 CAPB3I1I=32'b00000000000000000000000000001111 CAPB3l1I=16'b0000000000001100 CAPB3OOl=16'b0000000000001000 CAPB3IOl=16'b0000000000000100 CAPB3lOl=16'b0000000000000000 CAPB3OIl=16'b0000000000000100 CAPB3IIl=16'b0000000000000000 CAPB3lIl=16'b0000000000000000 CAPB3Oll=16'b0000000000000001 CAPB3Ill=16'b0000000000000010 CAPB3lll=16'b0000000000000100 CAPB3O0l=16'b0000000000000000 CAPB3I0l=16'b0000000000000000 CAPB3l0l=16'b0000000000000000 CAPB3O1l=16'b0000000000000000 CAPB3I1l=16'b0000000000000000 CAPB3l1l=16'b0000000000000000 CAPB3OO0=16'b0000000000000000 CAPB3IO0=16'b0000000000000000 CAPB3lO0=16'b0000000000000000 CAPB3OI0=16'b0000000000000000 CAPB3II0=16'b0000000000000000 CAPB3lI0=16'b0000000000000000 CAPB3Ol0=16'b0000000000000000 Generated name = CoreAPB3_Z1 @W:CL113 : coreapb3.v(1928) | Feedback mux created for signal CAPB3OIOI.genblk22.CAPB3lIOI.genblk24.genblk26.CAPB3OlOI[15:0]. @W:CL251 : coreapb3.v(1928) | All reachable assignments to CAPB3OIOI.genblk22.CAPB3lIOI.genblk24.genblk26.CAPB3OlOI[15:0] assign 0, register removed by optimization @N:CG364 : smartfusion.v(1814) | Synthesizing module VCC @N:CG364 : sine_LUT.v(5) | Synthesizing module sine_lut @N:CG364 : APB_sine_LUT.v(8) | Synthesizing module APB_sine_LUT @N:CG364 : mss_comps.v(23) | Synthesizing module INBUF_MSS @N:CG364 : smartfusion.v(2614) | Synthesizing module OUTBUF_A @N:CG364 : mss_comps.v(151) | Synthesizing module MSS_CCC @N:CG364 : mss_comps.v(1) | Synthesizing module MSS_XTLOSC @N:CG364 : smartfusion.v(1133) | Synthesizing module GND @N:CG364 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(5) | Synthesizing module MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC @N:CG364 : mss_comps.v(680) | Synthesizing module MSS_APB @N:CG364 : smartfusion.v(2609) | Synthesizing module INBUF_A @N:CG364 : MSS_Waveform.v(5) | Synthesizing module MSS_Waveform @N:CG364 : coreabc.v(10) | Synthesizing module Top_Waveform_COREABC_0_COREABC FAMILY=32'b00000000000000000000000000001111 APB_AWIDTH=32'b00000000000000000000000000010000 APB_DWIDTH=32'b00000000000000000000000000100000 APB_SDEPTH=32'b00000000000000000000000000000011 ICWIDTH=32'b00000000000000000000000000000100 ZRWIDTH=32'b00000000000000000000000000001000 IFWIDTH=32'b00000000000000000000000000000000 IIWIDTH=32'b00000000000000000000000000000001 IOWIDTH=32'b00000000000000000000000000000001 STWIDTH=32'b00000000000000000000000000000100 EN_RAM=32'b00000000000000000000000000000001 EN_AND=32'b00000000000000000000000000000001 EN_XOR=32'b00000000000000000000000000000001 EN_OR=32'b00000000000000000000000000000001 EN_ADD=32'b00000000000000000000000000000001 EN_INC=32'b00000000000000000000000000000001 EN_SHL=32'b00000000000000000000000000000001 EN_SHR=32'b00000000000000000000000000000001 EN_CALL=32'b00000000000000000000000000000001 EN_PUSH=32'b00000000000000000000000000000001 EN_MULT=32'b00000000000000000000000000000000 EN_ACM=32'b00000000000000000000000000000000 EN_DATAM=32'b00000000000000000000000000000010 EN_INT=32'b00000000000000000000000000000000 EN_IOREAD=32'b00000000000000000000000000000001 EN_IOWRT=32'b00000000000000000000000000000001 EN_ALURAM=32'b00000000000000000000000000000000 EN_INDIRECT=32'b00000000000000000000000000000001 ISRADDR=32'b00000000000000000000000000000001 DEBUG=32'b00000000000000000000000000000001 INSMODE=32'b00000000000000000000000000000000 INITWIDTH=32'b00000000000000000000000000001011 TESTMODE=32'b00000000000000000000000000000000 ACT_CALIBRATIONDATA=32'b00000000000000000000000000000001 IMEM_APB_ACCESS=32'b00000000000000000000000000000000 UNIQ_STRING_LENGTH=32'b00000000000000000000000000010110 BLANK=32'b11111111111111111111111111111111 iNOP=32'b00000000000000000000000100000000 iLOAD=32'b00000000000000000000001000000000 iINCB=32'b00000000000000000000001100000000 iAND=32'b00000000000000000000010000000000 iOR=32'b00000000000000000000010100000000 iXOR=32'b00000000000000000000011000000000 iADD=32'b00000000000000000000011100000000 iSUB=32'b00000000000000000000100000000000 iSHL0=32'b00000000000000000000100100000000 iSHL1=32'b00000000000000000000101000000000 iSHLE=32'b00000000000000000000101100000000 iROL=32'b00000000000000000000110000000000 iSHR0=32'b00000000000000000000110100000000 iSHR1=32'b00000000000000000000111000000000 iSHRE=32'b00000000000000000000111100000000 iROR=32'b00000000000000000001000000000000 iCMP=32'b00000000000000000001000100000000 iCMPLEQ=32'b00000000000000000001001000000000 iBITCLR=32'b00000000000000000001001100000000 iBITSET=32'b00000000000000000001010000000000 iBITTST=32'b00000000000000000001010100000000 iAPBREAD=32'b00000000000000000001011000000000 iAPBWRT=32'b00000000000000000001011100000000 iLOADZ=32'b00000000000000000001100000000000 iDECZ=32'b00000000000000000001100100000000 iINCZ=32'b00000000000000000001101000000000 iIOWRT=32'b00000000000000000001101100000000 iRAMREAD=32'b00000000000000000001110000000000 iRAMWRT=32'b00000000000000000001110100000000 iPUSH=32'b00000000000000000001111000000000 iPOP=32'b00000000000000000001111100000000 iIOREAD=32'b00000000000000000010000000000000 iUSER=32'b00000000000000000010000100000000 iJUMPB=32'b00000000000000000010001000000000 iCALLB=32'b00000000000000000010001100000000 iRETURNB=32'b00000000000000000010010000000000 iRETISRB=32'b00000000000000000010010100000000 iWAITB=32'b00000000000000000010011000000000 iHALTB=32'b00000000000000000010011000000000 iMULT=32'b00000000000000000010011100000000 iDEC=32'b00000000000000000010100000000000 iAPBREADZ=32'b00000000000000000010100100000000 iAPBWRTZ=32'b00000000000000000010101000000000 iADDZ=32'b00000000000000000010101100000000 iSUBZ=32'b00000000000000000010110000000000 iDAT=32'b00000000000000000000000000001010 iDAT8=32'b00000000000000000000000000001011 iDAT16=32'b00000000000000000000000000001100 iDAT32=32'b00000000000000000000000000001101 iACM=32'b00000000000000000000000000001110 iACC=32'b00000000000000000000000000001111 iRAM=32'b00000000000000000000000000010000 ABClI=32'b00000000000000000000000000001010 DAT8=32'b00000000000000000000000000001011 DAT16=32'b00000000000000000000000000001100 DAT32=32'b00000000000000000000000000001101 ACM=32'b00000000000000000000000000001110 ACC=32'b00000000000000000000000000001111 RAM=32'b00000000000000000000000000010000 iIFNOT=32'b00000000000000000000000000000000 iNOTIF=32'b00000000000000000000000000000000 iIF=32'b00000000000000000000000000000001 iUNTIL=32'b00000000000000000000000000000000 iNOTUNTIL=32'b00000000000000000000000000000001 iUNTILNOT=32'b00000000000000000000000000000001 iWHILE=32'b00000000000000000000000000000001 iZZERO=8'b00001000 iNEGATIVE=8'b00000100 iZERO=8'b00000010 iLTE_ZERO=8'b00000110 iALWAYS=8'b00000001 iINPUT0=12'b000000010000 iINPUT1=12'b000000100000 iINPUT2=12'b000001000000 iINPUT3=12'b000010000000 iINPUT4=12'b000100000000 iINPUT5=12'b001000000000 iINPUT6=12'b010000000000 iINPUT7=12'b100000000000 iINPUT8=16'b0001000000000000 iINPUT9=16'b0010000000000000 iINPUT10=16'b0100000000000000 iINPUT11=16'b1000000000000000 iINPUT12=20'b00010000000000000000 iINPUT13=20'b00100000000000000000 iINPUT14=20'b01000000000000000000 iINPUT15=20'b10000000000000000000 iINPUT16=24'b000100000000000000000000 iINPUT17=24'b001000000000000000000000 iINPUT18=24'b010000000000000000000000 iINPUT19=24'b100000000000000000000000 iINPUT20=28'b0001000000000000000000000000 iINPUT21=28'b0010000000000000000000000000 iINPUT22=28'b0100000000000000000000000000 iINPUT23=28'b1000000000000000000000000000 iINPUT24=32'b00010000000000000000000000000000 iINPUT25=32'b00100000000000000000000000000000 iINPUT26=32'b01000000000000000000000000000000 iINPUT27=32'b10000000000000000000000000000000 iANYINPUT=32'b01111111111111111111111111110000 ALWAYS=8'b00000001 ZZERO=8'b00001000 NEGATIVE=8'b00000100 ZERO=8'b00000010 LTE_ZERO=8'b00000110 INPUT0=12'b000000010000 INPUT1=12'b000000100000 INPUT2=12'b000001000000 INPUT3=12'b000010000000 INPUT4=12'b000100000000 INPUT5=12'b001000000000 INPUT6=12'b010000000000 INPUT7=12'b100000000000 INPUT8=16'b0001000000000000 INPUT9=16'b0010000000000000 INPUT10=16'b0011000000000000 INPUT11=16'b1000000000000000 INPUT12=20'b00010000000000000000 INPUT13=20'b00100000000000000000 INPUT14=20'b01000000000000000000 INPUT15=20'b10000000000000000000 INPUT16=24'b000100000000000000000000 INPUT17=24'b001000000000000000000000 INPUT18=24'b001100000000000000000000 INPUT19=24'b100000000000000000000000 INPUT20=28'b0001000000000000000000000000 INPUT21=28'b0010000000000000000000000000 INPUT22=28'b0100000000000000000000000000 INPUT23=28'b1000000000000000000000000000 INPUT24=32'b00010000000000000000000000000000 INPUT25=32'b00100000000000000000000000000000 INPUT26=32'b01000000000000000000000000000000 INPUT27=32'b01000000000000000000000000000000 ANYINPUT=32'b01111111111111111111111111110000 iLOADLOOP=32'b00000000000000000001100000000000 iDECLOOP=32'b00000000000000000001100100000000 iINCLOOP=32'b00000000000000000001101000000000 iLOOPZ=32'b00000000000000000000000000001000 LOOPZ=32'b00000000000000000000000000001000 EN_USER=32'b00000000000000000000000000000000 IWWIDTH=32'b00000000000000000000000000111010 ABCII=32'b00000000000000000000000000100000 ABCOI=32'b00000000000000000000000000010000 APB_SWIDTH=32'b00000000000000000000000000000010 ABClIl=32'b00000000000000000000000000111000 ABCII11=2'b00 ABClI11=2'b01 ABCOl11=2'b10 ABCIl11=2'b11 Generated name = Top_Waveform_COREABC_0_COREABC_Z2 @N:CG364 : ramblocks.v(10) | Synthesizing module Top_Waveform_COREABC_0_RAMBLOCKS DWIDTH=32'b00000000000000000000000000100000 FAMILY=32'b00000000000000000000000000001111 Generated name = Top_Waveform_COREABC_0_RAMBLOCKS_32s_15s @N:CG364 : smartfusion.v(2207) | Synthesizing module RAM512X18 @N:CG364 : smartfusion.v(1253) | Synthesizing module INV @N:CG364 : ram256x16_pa3.v(10) | Synthesizing module Top_Waveform_COREABC_0_RAM256X16 @W:CG360 : ramblocks.v(90) | No assignment to wire ABCI010 @W:CG360 : ramblocks.v(130) | No assignment to wire ABCOOO1 @N:CG364 : instructions.v(26) | Synthesizing module Top_Waveform_COREABC_0_INSTRUCTIONS AWIDTH=32'b00000000000000000000000000010000 DWIDTH=32'b00000000000000000000000000100000 SWIDTH=32'b00000000000000000000000000000010 ICWIDTH=32'b00000000000000000000000000000100 IIWIDTH=32'b00000000000000000000000000000001 IFWIDTH=32'b00000000000000000000000000000000 IWWIDTH=32'b00000000000000000000000000111010 EN_MULT=32'b00000000000000000000000000000000 EN_INC=32'b00000000000000000000000000000001 TESTMODE=32'b00000000000000000000000000000000 BLANK=32'b11111111111111111111111111111111 iNOP=32'b00000000000000000000000100000000 iLOAD=32'b00000000000000000000001000000000 iINCB=32'b00000000000000000000001100000000 iAND=32'b00000000000000000000010000000000 iOR=32'b00000000000000000000010100000000 iXOR=32'b00000000000000000000011000000000 iADD=32'b00000000000000000000011100000000 iSUB=32'b00000000000000000000100000000000 iSHL0=32'b00000000000000000000100100000000 iSHL1=32'b00000000000000000000101000000000 iSHLE=32'b00000000000000000000101100000000 iROL=32'b00000000000000000000110000000000 iSHR0=32'b00000000000000000000110100000000 iSHR1=32'b00000000000000000000111000000000 iSHRE=32'b00000000000000000000111100000000 iROR=32'b00000000000000000001000000000000 iCMP=32'b00000000000000000001000100000000 iCMPLEQ=32'b00000000000000000001001000000000 iBITCLR=32'b00000000000000000001001100000000 iBITSET=32'b00000000000000000001010000000000 iBITTST=32'b00000000000000000001010100000000 iAPBREAD=32'b00000000000000000001011000000000 iAPBWRT=32'b00000000000000000001011100000000 iLOADZ=32'b00000000000000000001100000000000 iDECZ=32'b00000000000000000001100100000000 iINCZ=32'b00000000000000000001101000000000 iIOWRT=32'b00000000000000000001101100000000 iRAMREAD=32'b00000000000000000001110000000000 iRAMWRT=32'b00000000000000000001110100000000 iPUSH=32'b00000000000000000001111000000000 iPOP=32'b00000000000000000001111100000000 iIOREAD=32'b00000000000000000010000000000000 iUSER=32'b00000000000000000010000100000000 iJUMPB=32'b00000000000000000010001000000000 iCALLB=32'b00000000000000000010001100000000 iRETURNB=32'b00000000000000000010010000000000 iRETISRB=32'b00000000000000000010010100000000 iWAITB=32'b00000000000000000010011000000000 iHALTB=32'b00000000000000000010011000000000 iMULT=32'b00000000000000000010011100000000 iDEC=32'b00000000000000000010100000000000 iAPBREADZ=32'b00000000000000000010100100000000 iAPBWRTZ=32'b00000000000000000010101000000000 iADDZ=32'b00000000000000000010101100000000 iSUBZ=32'b00000000000000000010110000000000 iDAT=32'b00000000000000000000000000001010 iDAT8=32'b00000000000000000000000000001011 iDAT16=32'b00000000000000000000000000001100 iDAT32=32'b00000000000000000000000000001101 iACM=32'b00000000000000000000000000001110 iACC=32'b00000000000000000000000000001111 iRAM=32'b00000000000000000000000000010000 ABClI=32'b00000000000000000000000000001010 DAT8=32'b00000000000000000000000000001011 DAT16=32'b00000000000000000000000000001100 DAT32=32'b00000000000000000000000000001101 ACM=32'b00000000000000000000000000001110 ACC=32'b00000000000000000000000000001111 RAM=32'b00000000000000000000000000010000 iIFNOT=32'b00000000000000000000000000000000 iNOTIF=32'b00000000000000000000000000000000 iIF=32'b00000000000000000000000000000001 iUNTIL=32'b00000000000000000000000000000000 iNOTUNTIL=32'b00000000000000000000000000000001 iUNTILNOT=32'b00000000000000000000000000000001 iWHILE=32'b00000000000000000000000000000001 iZZERO=8'b00001000 iNEGATIVE=8'b00000100 iZERO=8'b00000010 iLTE_ZERO=8'b00000110 iALWAYS=8'b00000001 iINPUT0=12'b000000010000 iINPUT1=12'b000000100000 iINPUT2=12'b000001000000 iINPUT3=12'b000010000000 iINPUT4=12'b000100000000 iINPUT5=12'b001000000000 iINPUT6=12'b010000000000 iINPUT7=12'b100000000000 iINPUT8=16'b0001000000000000 iINPUT9=16'b0010000000000000 iINPUT10=16'b0100000000000000 iINPUT11=16'b1000000000000000 iINPUT12=20'b00010000000000000000 iINPUT13=20'b00100000000000000000 iINPUT14=20'b01000000000000000000 iINPUT15=20'b10000000000000000000 iINPUT16=24'b000100000000000000000000 iINPUT17=24'b001000000000000000000000 iINPUT18=24'b010000000000000000000000 iINPUT19=24'b100000000000000000000000 iINPUT20=28'b0001000000000000000000000000 iINPUT21=28'b0010000000000000000000000000 iINPUT22=28'b0100000000000000000000000000 iINPUT23=28'b1000000000000000000000000000 iINPUT24=32'b00010000000000000000000000000000 iINPUT25=32'b00100000000000000000000000000000 iINPUT26=32'b01000000000000000000000000000000 iINPUT27=32'b10000000000000000000000000000000 iANYINPUT=32'b01111111111111111111111111110000 ALWAYS=8'b00000001 ZZERO=8'b00001000 NEGATIVE=8'b00000100 ZERO=8'b00000010 LTE_ZERO=8'b00000110 INPUT0=12'b000000010000 INPUT1=12'b000000100000 INPUT2=12'b000001000000 INPUT3=12'b000010000000 INPUT4=12'b000100000000 INPUT5=12'b001000000000 INPUT6=12'b010000000000 INPUT7=12'b100000000000 INPUT8=16'b0001000000000000 INPUT9=16'b0010000000000000 INPUT10=16'b0011000000000000 INPUT11=16'b1000000000000000 INPUT12=20'b00010000000000000000 INPUT13=20'b00100000000000000000 INPUT14=20'b01000000000000000000 INPUT15=20'b10000000000000000000 INPUT16=24'b000100000000000000000000 INPUT17=24'b001000000000000000000000 INPUT18=24'b001100000000000000000000 INPUT19=24'b100000000000000000000000 INPUT20=28'b0001000000000000000000000000 INPUT21=28'b0010000000000000000000000000 INPUT22=28'b0100000000000000000000000000 INPUT23=28'b1000000000000000000000000000 INPUT24=32'b00010000000000000000000000000000 INPUT25=32'b00100000000000000000000000000000 INPUT26=32'b01000000000000000000000000000000 INPUT27=32'b01000000000000000000000000000000 ANYINPUT=32'b01111111111111111111111111110000 iLOADLOOP=32'b00000000000000000001100000000000 iDECLOOP=32'b00000000000000000001100100000000 iINCLOOP=32'b00000000000000000001101000000000 iLOOPZ=32'b00000000000000000000000000001000 LOOPZ=32'b00000000000000000000000000001000 EN_USER=32'b00000000000000000000000000000000 AW=32'b00000000000000000000000000010000 DW=32'b00000000000000000000000000100000 SW=32'b00000000000000000000000000000010 IW=32'b00000000000000000000000000000100 FW=32'b00000000000000000000000000000101 iJUMP=32'b00000000000000000010001000000000 iCALL=32'b00000000000000000010001100000000 iRETURN=32'b00000000000000000010010000000000 iRETISR=32'b00000000000000000010010100000000 iWAIT=32'b00000000000000000010011000000000 iHALT=32'b00000000000000000010011000000000 iINC=32'b00000000000000000000001100000000 iACM_CTRLSTAT=8'b00000000 iACM_ADDR_ADDR=8'b00000100 iACM_DATA_ADDR=8'b00001000 iADC_CTRL2_HI_ADDR=8'b00010000 iADC_STAT_HI_ADDR=8'b00100000 Sym_DAC0_BYTE0_OFFSET=32'b00000000000000000000000001100100 Sym_DELAY=32'b00000000000000000000000010010110 Label_MAIN=32'b00000000000000000000000000000011 Label_LOOP=32'b00000000000000000000000000000011 Label_WAIT=32'b00000000000000000000000000000110 Generated name = Top_Waveform_COREABC_0_INSTRUCTIONS_Z3 @W:CG133 : coreabc.v(8579) | No assignment to ABCOlIOI @W:CG133 : coreabc.v(8591) | No assignment to A @W:CG133 : coreabc.v(8603) | No assignment to B @W:CG360 : coreabc.v(6524) | No assignment to wire DEBUG1 @W:CG360 : coreabc.v(6527) | No assignment to wire DEBUG2 @W:CG133 : coreabc.v(6652) | No assignment to ABCl111 @W:CG133 : coreabc.v(6662) | No assignment to ABCOOOOI @W:CG134 : coreabc.v(6692) | No assignment to bit 4 of ABClOOOI @W:CG134 : coreabc.v(6692) | No assignment to bit 5 of ABClOOOI @W:CG134 : coreabc.v(6692) | No assignment to bit 6 of ABClOOOI @W:CG134 : coreabc.v(6692) | No assignment to bit 7 of ABClOOOI @W:CG134 : coreabc.v(6692) | No assignment to bit 8 of ABClOOOI @W:CG134 : coreabc.v(6692) | No assignment to bit 9 of ABClOOOI @W:CG134 : coreabc.v(6692) | No assignment to bit 10 of ABClOOOI @W:CG134 : coreabc.v(6692) | No assignment to bit 11 of ABClOOOI @W:CG134 : coreabc.v(6692) | No assignment to bit 12 of ABClOOOI @W:CG134 : coreabc.v(6692) | No assignment to bit 13 of ABClOOOI @W:CG134 : coreabc.v(6692) | No assignment to bit 14 of ABClOOOI @W:CG134 : coreabc.v(6692) | No assignment to bit 15 of ABClOOOI @W:CL169 : coreabc.v(10126) | Pruning Register ABCIO11 @W:CL169 : coreabc.v(7747) | Pruning Register genblk19.UROM.ABCIIlI[7:0] @W:CL208 : coreabc.v(10126) | All reachable assignments to bit 8 of ZREGISTER[8:0] assign 0, register removed by optimization @W:CL208 : coreabc.v(10126) | All reachable assignments to bit 4 of STKPTR[7:0] assign 1, register removed by optimization @W:CL208 : coreabc.v(10126) | All reachable assignments to bit 5 of STKPTR[7:0] assign 1, register removed by optimization @W:CL208 : coreabc.v(10126) | All reachable assignments to bit 6 of STKPTR[7:0] assign 1, register removed by optimization @W:CL208 : coreabc.v(10126) | All reachable assignments to bit 7 of STKPTR[7:0] assign 1, register removed by optimization @W:CL207 : coreabc.v(10126) | All reachable assignments to ISR assign 0, register removed by optimization @W:CL207 : coreabc.v(10126) | All reachable assignments to ABCOI01 assign 0, register removed by optimization @W:CL207 : coreabc.v(9099) | All reachable assignments to ABCOO01 assign 0, register removed by optimization @W:CL207 : coreabc.v(9099) | All reachable assignments to ABCIO01 assign 0, register removed by optimization @W:CL189 : coreabc.v(7639) | Register bit genblk19.UROM.INSTR_SLOT[2] is always 0, optimizing ... @W:CL260 : coreabc.v(7639) | Pruning Register bit 2 of genblk19.UROM.INSTR_SLOT[2:0] @N:CG364 : Top_Waveform.v(5) | Synthesizing module Top_Waveform @N:CL177 : coreabc.v(7639) | Sharing sequential element genblk19.UROM.ABCI0I1. @N:CL201 : coreabc.v(10126) | Trying to extract state machine for register ABCOI11 Extracted state machine for register ABCOI11 State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL159 : coreabc.v(327) | Input PSLVERR_M is unused @W:CL159 : coreabc.v(360) | Input INTREQ is unused @W:CL159 : coreabc.v(369) | Input INITDATVAL is unused @W:CL159 : coreabc.v(372) | Input INITDONE is unused @W:CL159 : coreabc.v(382) | Input INITADDR is unused @W:CL159 : coreabc.v(390) | Input INITDATA is unused @W:CL159 : coreabc.v(393) | Input PSEL_S is unused @W:CL159 : coreabc.v(396) | Input PENABLE_S is unused @W:CL159 : coreabc.v(399) | Input PWRITE_S is unused @W:CL159 : coreabc.v(409) | Input PADDR_S is unused @W:CL159 : coreabc.v(419) | Input PWDATA_S is unused @W:CL157 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(62) | *Output RCOSC_CLKOUT has undriven bits - a simulation mismatch is possible @W:CL157 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(63) | *Output MAINXIN_CLKOUT has undriven bits - a simulation mismatch is possible @W:CL157 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(64) | *Output LPXIN_CLKOUT has undriven bits - a simulation mismatch is possible @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(36) | Input CLKA is unused @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(37) | Input CLKA_PAD is unused @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(38) | Input CLKA_PADP is unused @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(39) | Input CLKA_PADN is unused @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(40) | Input CLKB is unused @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(41) | Input CLKB_PAD is unused @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(42) | Input CLKB_PADP is unused @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(43) | Input CLKB_PADN is unused @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(44) | Input CLKC is unused @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(45) | Input CLKC_PAD is unused @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(46) | Input CLKC_PADP is unused @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(47) | Input CLKC_PADN is unused @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(49) | Input LPXIN is unused @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(50) | Input MAC_CLK is unused @W:CL159 : APB_sine_LUT.v(11) | Input PENABLE is unused @W:CL159 : APB_sine_LUT.v(15) | Input PWDATA is unused @W:CL246 : coreapb3.v(217) | Input port bits 23 to 20 of PADDR[23:0] are unused @W:CL159 : coreapb3.v(356) | Input PRDATAS1 is unused @W:CL159 : coreapb3.v(370) | Input PRDATAS3 is unused @W:CL159 : coreapb3.v(377) | Input PRDATAS4 is unused @W:CL159 : coreapb3.v(384) | Input PRDATAS5 is unused @W:CL159 : coreapb3.v(391) | Input PRDATAS6 is unused @W:CL159 : coreapb3.v(398) | Input PRDATAS7 is unused @W:CL159 : coreapb3.v(405) | Input PRDATAS8 is unused @W:CL159 : coreapb3.v(412) | Input PRDATAS9 is unused @W:CL159 : coreapb3.v(419) | Input PRDATAS10 is unused @W:CL159 : coreapb3.v(426) | Input PRDATAS11 is unused @W:CL159 : coreapb3.v(433) | Input PRDATAS12 is unused @W:CL159 : coreapb3.v(440) | Input PRDATAS13 is unused @W:CL159 : coreapb3.v(447) | Input PRDATAS14 is unused @W:CL159 : coreapb3.v(454) | Input PRDATAS15 is unused @W:CL159 : coreapb3.v(458) | Input PREADYS1 is unused @W:CL159 : coreapb3.v(462) | Input PREADYS3 is unused @W:CL159 : coreapb3.v(464) | Input PREADYS4 is unused @W:CL159 : coreapb3.v(466) | Input PREADYS5 is unused @W:CL159 : coreapb3.v(468) | Input PREADYS6 is unused @W:CL159 : coreapb3.v(470) | Input PREADYS7 is unused @W:CL159 : coreapb3.v(472) | Input PREADYS8 is unused @W:CL159 : coreapb3.v(474) | Input PREADYS9 is unused @W:CL159 : coreapb3.v(476) | Input PREADYS10 is unused @W:CL159 : coreapb3.v(478) | Input PREADYS11 is unused @W:CL159 : coreapb3.v(480) | Input PREADYS12 is unused @W:CL159 : coreapb3.v(482) | Input PREADYS13 is unused @W:CL159 : coreapb3.v(484) | Input PREADYS14 is unused @W:CL159 : coreapb3.v(486) | Input PREADYS15 is unused @W:CL159 : coreapb3.v(490) | Input PSLVERRS1 is unused @W:CL159 : coreapb3.v(494) | Input PSLVERRS3 is unused @W:CL159 : coreapb3.v(496) | Input PSLVERRS4 is unused @W:CL159 : coreapb3.v(498) | Input PSLVERRS5 is unused @W:CL159 : coreapb3.v(500) | Input PSLVERRS6 is unused @W:CL159 : coreapb3.v(502) | Input PSLVERRS7 is unused @W:CL159 : coreapb3.v(504) | Input PSLVERRS8 is unused @W:CL159 : coreapb3.v(506) | Input PSLVERRS9 is unused @W:CL159 : coreapb3.v(508) | Input PSLVERRS10 is unused @W:CL159 : coreapb3.v(510) | Input PSLVERRS11 is unused @W:CL159 : coreapb3.v(512) | Input PSLVERRS12 is unused @W:CL159 : coreapb3.v(514) | Input PSLVERRS13 is unused @W:CL159 : coreapb3.v(516) | Input PSLVERRS14 is unused @W:CL159 : coreapb3.v(518) | Input PSLVERRS15 is unused @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Aug 31 18:49:09 2010 ###########################################################] Synopsys Actel Technology Mapper, Version map500act, Build 058R, Built Jan 18 2010 09:16:23 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved Product Version D-2009.12A @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled @W:MO111 : mss_waveform_tmp_mss_ccc_0_mss_ccc.v(62) | tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC) @W:MO111 : mss_waveform_tmp_mss_ccc_0_mss_ccc.v(63) | tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC) @W:MO111 : mss_waveform_tmp_mss_ccc_0_mss_ccc.v(64) | tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC) Automatic dissolve at startup in view:COREAPB3_LIB.CoreAPB3_Z1(verilog) of CAPB3llOI(CAPB3O) Automatic dissolve at startup in view:work.MSS_Waveform(verilog) of MSS_CCC_0(MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC) Automatic dissolve at startup in view:work.Top_Waveform_COREABC_0_RAMBLOCKS_32s_15s(verilog) of genblk4\.ABCIOI1\.ABClII1\.ABCOlI1(Top_Waveform_COREABC_0_RAM256X16) Automatic dissolve at startup in view:work.Top_Waveform_COREABC_0_RAMBLOCKS_32s_15s(verilog) of genblk4\.ABCIOI1\.ABClOI1(Top_Waveform_COREABC_0_RAM256X16) Automatic dissolve at startup in view:work.Top_Waveform_COREABC_0_COREABC_Z2(verilog) of genblk15\.ABCIO0I\.ABCOO0I(Top_Waveform_COREABC_0_RAMBLOCKS_32s_15s) Automatic dissolve at startup in view:work.Top_Waveform(verilog) of MSS_Waveform_0(MSS_Waveform) Automatic dissolve at startup in view:work.Top_Waveform(verilog) of CoreAPB3_0(CoreAPB3_Z1) Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 58MB) @N:MO106 : sine_lut.v(22) | Found ROM, 'table_value_2[7:0]', 256 words by 8 bits Encoding state machine work.Top_Waveform_COREABC_0_COREABC_Z2(verilog)-ABCOI11[3:0] original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MF176 : | Default generator successful @N:MF176 : | Default generator successful @N:MF176 : | Default generator successful @N:MF238 : coreabc.v(6674) | Found 4 bit incrementor, 'un1_SMADDR[3:0]' @N:MF238 : coreabc.v(10036) | Found 4 bit incrementor, 'un1_ABCO0OI[3:0]' @W:MO129 : coreabc.v(7639) | Sequential instance COREABC_0.genblk19.UROM.INSTR_ADDR[3] has been reduced to a combinational gate by constant propagation @W:MO129 : coreabc.v(7639) | Sequential instance COREABC_0.genblk19.UROM.INSTR_ADDR[4] has been reduced to a combinational gate by constant propagation @W:MO129 : coreabc.v(7639) | Sequential instance COREABC_0.genblk19.UROM.INSTR_ADDR[7] has been reduced to a combinational gate by constant propagation @W:MO129 : coreabc.v(7639) | Sequential instance COREABC_0.genblk19.UROM.INSTR_ADDR[8] has been reduced to a combinational gate by constant propagation @W:MO129 : coreabc.v(7639) | Sequential instance COREABC_0.genblk19.UROM.INSTR_ADDR[9] has been reduced to a combinational gate by constant propagation @W:MO129 : coreabc.v(7639) | Sequential instance COREABC_0.genblk19.UROM.INSTR_ADDR[10] has been reduced to a combinational gate by constant propagation @W:MO129 : coreabc.v(7639) | Sequential instance COREABC_0.genblk19.UROM.INSTR_ADDR[11] has been reduced to a combinational gate by constant propagation @W:MO129 : coreabc.v(7639) | Sequential instance COREABC_0.genblk19.UROM.INSTR_ADDR[12] has been reduced to a combinational gate by constant propagation @W:MO129 : coreabc.v(7639) | Sequential instance COREABC_0.genblk19.UROM.INSTR_ADDR[13] has been reduced to a combinational gate by constant propagation @W:MO129 : coreabc.v(7639) | Sequential instance COREABC_0.genblk19.UROM.INSTR_ADDR[14] has been reduced to a combinational gate by constant propagation @W:MO129 : coreabc.v(7639) | Sequential instance COREABC_0.genblk19.UROM.INSTR_ADDR[15] has been reduced to a combinational gate by constant propagation @N:MO106 : instructions.v(82) | Found ROM, 'doins[5:0]', 10 words by 6 bits Finished factoring (Time elapsed 0h:00m:02s; Memory used current: 64MB peak: 65MB) @N:BN116 : coreabc.v(10126) | Removing sequential instance COREABC_0.IO_OUT[0] of view:PrimLib.dffr(prim) because there are no references to its outputs @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[1], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_ADDR[2] @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_ADDR[5], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_ADDR[6] @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[29], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[31] @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[28], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[31] @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[27], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[31] @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[26], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[31] @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[25], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[31] @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[24], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[31] @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[23], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[31] @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[22], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[31] @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[21], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[31] @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[20], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[31] @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[19], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[31] @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[18], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[31] @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[16], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[31] @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[15], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[31] @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[14], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[31] @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[13], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[31] @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[12], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[31] @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[11], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[31] @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[10], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[31] @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[9], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[31] @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[8], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[31] @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[6], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[31] @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[5], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[31] @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[3], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[31] @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[4], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[7] @W:BN132 : coreabc.v(7639) | Removing sequential instance COREABC_0.genblk19.UROM.INSTR_DATA[17], because it is equivalent to instance COREABC_0.genblk19.UROM.INSTR_DATA[30] Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:02s; Memory used current: 63MB peak: 65MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:02s; Memory used current: 62MB peak: 66MB) Starting Early Timing Optimization (Time elapsed 0h:00m:02s; Memory used current: 62MB peak: 66MB) Finished Early Timing Optimization (Time elapsed 0h:00m:32s; Memory used current: 67MB peak: 68MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:32s; Memory used current: 67MB peak: 68MB) Finished preparing to map (Time elapsed 0h:00m:34s; Memory used current: 71MB peak: 72MB) High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes ---------------------------------------------------------------------------------------------------- COREABC_0.ABCO011 / Q 84 : 82 asynchronous set/reset COREABC_0.PADDR_M_1_i_m3[0] / Y 47 COREABC_0.PADDR_M_1_i_m3[1] / Y 45 COREABC_0.PADDR_M_1_i_m3[2] / Y 56 CoreAPB3_0.CAPB3O11_i_o2[0] / Y 40 COREABC_0.genblk19.UROM.INSTR_DATA[31] / Q 74 COREABC_0.PADDR_M_1_i[7] / Y 62 COREABC_0.PADDR_M_1_i[4] / Y 28 COREABC_0.PADDR_M_1_i[3] / Y 42 COREABC_0.un1_ABCl0I18_1_i / Y 36 COREABC_0.ABCO1I1_2_sqmuxa_i / Y 32 COREABC_0.ABCO1I1_3_sqmuxa_0_a2 / Y 32 COREABC_0.ABCO1I1_5_sqmuxa_i / Y 32 COREABC_0.ABCO1I1_6_sqmuxa / Y 32 COREABC_0.ABCO1I1_7_sqmuxa_0 / Y 32 COREABC_0.ABCOI1122.ABCOI1122_0_a2 / Y 33 COREABC_0.ABCIlI_9_0_o3_0_N_2_i_0 / Y 76 COREABC_0.ABCO1I1_1_sqmuxa_0_0_a2 / Y 31 COREABC_0.ACCUMULATOR4 / Y 32 COREABC_0.genblk15.ABCIO0I.ABCI11164_i_a2 / Y 32 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I15_P0N_a1tt_m2_0_a3 / Y 102 COREABC_0.ABClll1_1 / Y 32 ==================================================================================================== @N:FP130 : | Promoting Net COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I0_CO1_N_4 on CLKINT I_132 @N:FP130 : | Promoting Net COREABC_0_PRESETN on CLKINT I_133 @N:FP130 : | Promoting Net COREABC_0.N_161 on CLKINT I_134 Replicating Combinational Instance COREABC_0.ABClll1_1, fanout 32 segments 2 Replicating Combinational Instance COREABC_0.genblk15.ABCIO0I.ABCI11164_i_a2, fanout 32 segments 2 Replicating Combinational Instance COREABC_0.ACCUMULATOR4, fanout 32 segments 2 Replicating Combinational Instance COREABC_0.ABCO1I1_1_sqmuxa_0_0_a2, fanout 31 segments 2 Replicating Combinational Instance COREABC_0.ABCOI1122.ABCOI1122_0_a2, fanout 33 segments 2 Replicating Combinational Instance COREABC_0.ABCO1I1_7_sqmuxa_0, fanout 32 segments 2 Replicating Combinational Instance COREABC_0.ABCO1I1_6_sqmuxa, fanout 32 segments 2 Replicating Combinational Instance COREABC_0.ABCO1I1_5_sqmuxa_i, fanout 32 segments 2 Replicating Combinational Instance COREABC_0.ABCO1I1_3_sqmuxa_0_a2, fanout 32 segments 2 Replicating Combinational Instance COREABC_0.ABCO1I1_2_sqmuxa_i, fanout 32 segments 2 Replicating Combinational Instance COREABC_0.un1_ABCl0I18_1_i, fanout 36 segments 2 Replicating Combinational Instance COREABC_0.PADDR_M_1_i[3], fanout 42 segments 2 Replicating Combinational Instance COREABC_0.PADDR_M_1_i[4], fanout 28 segments 2 Replicating Combinational Instance COREABC_0.PADDR_M_1_i[7], fanout 62 segments 3 Replicating Sequential Instance COREABC_0.genblk19.UROM.INSTR_DATA[31], fanout 74 segments 4 Replicating Combinational Instance CoreAPB3_0.CAPB3O11_i_o2[0], fanout 40 segments 2 Replicating Combinational Instance COREABC_0.PADDR_M_1_i_m3[2], fanout 56 segments 3 Replicating Combinational Instance COREABC_0.PADDR_M_1_i_m3[1], fanout 45 segments 2 Replicating Combinational Instance COREABC_0.PADDR_M_1_i_m3[0], fanout 47 segments 2 Buffering MSS_Waveform_0_FAB_CLK, fanout 109 segments 5 Replicating Sequential Instance COREABC_0.genblk19.UROM.INSTR_SCMD[2], fanout 32 segments 2 Replicating Sequential Instance COREABC_0.genblk19.UROM.INSTR_SCMD[0], fanout 25 segments 2 Buffering MSS_Waveform_0_FAB_CLK, fanout 26 segments 2 Finished technology mapping (Time elapsed 0h:00m:34s; Memory used current: 75MB peak: 76MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:34s; Memory used current: 75MB peak: 76MB) Added 5 Buffers Added 25 Cells via replication Added 5 Sequential Cells via replication Added 20 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:34s; Memory used current: 75MB peak: 76MB) Writing Analyst data base D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\Verilog\Waveform_Gen\synthesis\Top_Waveform.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:35s; Memory used current: 73MB peak: 76MB) Writing EDIF Netlist and constraint files D-2009.12A Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:35s; Memory used current: 75MB peak: 76MB) @W:MT420 : | Found inferred clock Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:MSS_Waveform_0_FAB_CLK" @W:MT246 : mss_waveform.v(57) | Blackbox MSS_APB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : mss_waveform_tmp_mss_ccc_0_mss_ccc.v(97) | Blackbox MSS_XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) ##### START OF TIMING REPORT #####[ # Timing Report written on Tue Aug 31 18:49:47 2010 # Top view: Top_Waveform Library name: smartfusion Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree ) Requested Frequency: 100.0 MHz Wire load mode: top Wire load model: smartfusion Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: -15.643 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock 100.0 MHz 39.0 MHz 10.000 25.643 -15.643 inferred Inferred_clkgroup_0 System 100.0 MHz 171.5 MHz 10.000 5.831 4.169 system default_clkgroup ==================================================================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock | 10.000 -15.643 | No paths - | No paths - | No paths - ================================================================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- COREABC_0.genblk19\.UROM\.INSTR_CMD[1] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1 Q INSTR_CMD[1] 0.737 -15.643 COREABC_0.genblk19\.UROM\.INSTR_CMD[0] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1 Q INSTR_CMD[0] 0.737 -15.321 COREABC_0.genblk19\.UROM\.INSTR_CMD[2] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1 Q INSTR_CMD[2] 0.737 -15.213 COREABC_0.genblk19\.UROM\.INSTR_SCMD_0[2] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1 Q INSTR_SCMD_0[2] 0.737 -14.061 COREABC_0.genblk19\.UROM\.INSTR_SCMD[1] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1 Q INSTR_SCMD[1] 0.737 -13.947 COREABC_0.genblk19\.UROM\.INSTR_SCMD[2] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1 Q INSTR_SCMD[2] 0.737 -13.722 COREABC_0.genblk15\.ABCIO0I\.ABCOO0I.genblk4\.ABCIOI1\.ABClOI1.ABCIl10 Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock RAM512X18 RD2 ABCI101[2] 2.963 -12.007 COREABC_0.genblk19\.UROM\.INSTR_DATA_1[31] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1 Q INSTR_DATA_1[3] 0.737 -11.958 COREABC_0.genblk15\.ABCIO0I\.ABCOO0I.genblk4\.ABCIOI1\.ABClOI1.ABCIl10 Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock RAM512X18 RD3 ABCI101[3] 2.963 -11.727 COREABC_0.genblk15\.ABCIO0I\.ABCOO0I.genblk4\.ABCIOI1\.ABClOI1.ABCIl10 Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock RAM512X18 RD8 ABCI101[8] 2.963 -11.672 ==================================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- COREABC_0.ABCI1l1 Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1E1C0 D ABCO0I_4[0] 9.496 -15.643 COREABC_0.ACCUMULATOR[22] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1E1C0 D ABCl0I1[22] 9.461 -13.198 COREABC_0.ACCUMULATOR[28] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1E1C0 D ABCl0I1[28] 9.496 -11.800 COREABC_0.ACCUMULATOR[29] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1E1C0 D ABCl0I1[29] 9.461 -11.705 COREABC_0.ABCl1l1 Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1E1C0 D ABCl0I1[31] 9.461 -11.590 COREABC_0.ACCUMULATOR[31] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1E1C0 D ABCl0I1[31] 9.461 -11.590 COREABC_0.ACCUMULATOR[24] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1E1C0 D ABCl0I1[24] 9.496 -11.375 COREABC_0.ACCUMULATOR[25] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1E1C0 D ABCl0I1[25] 9.496 -11.349 COREABC_0.ACCUMULATOR[26] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1E1C0 D ABCl0I1[26] 9.461 -11.023 COREABC_0.ACCUMULATOR[27] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1E1C0 D ABCl0I1[27] 9.496 -10.925 ======================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.504 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.496 - Propagation time: 25.139 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -15.643 Number of logic level(s): 19 Starting point: COREABC_0.genblk19\.UROM\.INSTR_CMD[1] / Q Ending point: COREABC_0.ABCI1l1 / D The start point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------- COREABC_0.genblk19\.UROM\.INSTR_CMD[1] DFN1 Q Out 0.737 0.737 - INSTR_CMD[1] Net - - 2.172 - 16 COREABC_0.genblk19\.UROM\.INSTR_CMD_RNIKHD1[2] OR3B B In - 2.909 - COREABC_0.genblk19\.UROM\.INSTR_CMD_RNIKHD1[2] OR3B Y Out 0.607 3.516 - ABCO001_6_0_a3_0_1 Net - - 1.423 - 6 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I15_P0N_a1tt_m2_0_a3 OR2A A In - 4.939 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I15_P0N_a1tt_m2_0_a3 OR2A Y Out 0.537 5.476 - ADD_32x32_fast_I15_P0N_a1tt_m2_0_a3 Net - - 0.322 - 1 I_132 CLKINT A In - 5.798 - I_132 CLKINT Y Out 0.174 5.972 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I0_CO1_N_4 Net - - 1.601 - 104 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I23_P0N_a1 OR3B B In - 7.572 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I23_P0N_a1 OR3B Y Out 0.607 8.179 - N_2_28_i Net - - 1.994 - 12 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I5_P0N_0 OR3B B In - 10.172 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I5_P0N_0 OR3B Y Out 0.624 10.796 - N396 Net - - 0.386 - 2 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I83_Y NOR2B A In - 11.182 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I83_Y NOR2B Y Out 0.514 11.696 - N526 Net - - 0.386 - 2 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I143_Y NOR2B B In - 12.082 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I143_Y NOR2B Y Out 0.627 12.710 - N589 Net - - 0.806 - 3 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I198_un1_Y OR2B A In - 13.516 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I198_un1_Y OR2B Y Out 0.514 14.030 - I198_un1_Y_i Net - - 0.322 - 1 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I198_Y OR3C C In - 14.352 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I198_Y OR3C Y Out 0.666 15.018 - N652 Net - - 0.806 - 3 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I259_un1_Y_0 NOR2B B In - 15.824 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I259_un1_Y_0 NOR2B Y Out 0.627 16.451 - ADD_32x32_fast_I259_un1_Y_0 Net - - 0.322 - 1 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I259_un1_Y NOR2B A In - 16.773 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I259_un1_Y NOR2B Y Out 0.514 17.287 - I259_un1_Y Net - - 0.322 - 1 r_b0_0_o2_0 NOR2 B In - 17.609 - r_b0_0_o2_0 NOR2 Y Out 0.646 18.255 - r_b0_0_o2_0 Net - - 0.386 - 2 r_b0_0_o2 OR2B A In - 18.641 - r_b0_0_o2 OR2B Y Out 0.488 19.129 - r_N_9 Net - - 0.386 - 2 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I302_Y_0 XOR2 B In - 19.515 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I302_Y_0 XOR2 Y Out 0.937 20.452 - un1_ACCUMULATOR[22] Net - - 0.322 - 1 COREABC_0.genblk19\.UROM\.INSTR_SCMD_RNILUAS83[0] OR2A A In - 20.773 - COREABC_0.genblk19\.UROM\.INSTR_SCMD_RNILUAS83[0] OR2A Y Out 0.537 21.310 - un1_ACCUMULATOR_m_i[22] Net - - 0.322 - 1 COREABC_0.genblk19\.UROM\.INSTR_CMD_RNIKSP3L3[0] OR3C C In - 21.632 - COREABC_0.genblk19\.UROM\.INSTR_CMD_RNIKSP3L3[0] OR3C Y Out 0.641 22.273 - ABCl0I1[22] Net - - 0.386 - 2 COREABC_0.ABCI1l1_RNO_2 NOR3A B In - 22.659 - COREABC_0.ABCI1l1_RNO_2 NOR3A Y Out 0.360 23.019 - ABCO0I_4_24[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO_0 NOR3B A In - 23.340 - COREABC_0.ABCI1l1_RNO_0 NOR3B Y Out 0.641 23.981 - ABCO0I_4_29[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO NOR2B A In - 24.303 - COREABC_0.ABCI1l1_RNO NOR2B Y Out 0.514 24.817 - ABCO0I_4[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1 DFN1E1C0 D In - 25.139 - ================================================================================================================================ Total path delay (propagation time + setup) of 25.643 is 12.017(46.9%) logic and 13.625(53.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 0.504 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.496 - Propagation time: 25.061 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -15.565 Number of logic level(s): 19 Starting point: COREABC_0.genblk19\.UROM\.INSTR_CMD[1] / Q Ending point: COREABC_0.ABCI1l1 / D The start point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------- COREABC_0.genblk19\.UROM\.INSTR_CMD[1] DFN1 Q Out 0.737 0.737 - INSTR_CMD[1] Net - - 2.172 - 16 COREABC_0.genblk19\.UROM\.INSTR_CMD_RNIKHD1[2] OR3B B In - 2.909 - COREABC_0.genblk19\.UROM\.INSTR_CMD_RNIKHD1[2] OR3B Y Out 0.607 3.516 - ABCO001_6_0_a3_0_1 Net - - 1.423 - 6 COREABC_0.genblk19\.UROM\.INSTR_SCMD_RNIA8AC[1] AOI1 C In - 4.939 - COREABC_0.genblk19\.UROM\.INSTR_SCMD_RNIA8AC[1] AOI1 Y Out 0.487 5.426 - INSTR_SCMD_RNIA8AC[1] Net - - 1.994 - 12 COREABC_0.genblk15\.ABCIO0I\.ABCOO0I.genblk4\.ABCIOI1\.ABClOI1.ABCIl10_RNIQU6L MX2C S In - 7.419 - COREABC_0.genblk15\.ABCIO0I\.ABCOO0I.genblk4\.ABCIOI1\.ABClOI1.ABCIl10_RNIQU6L MX2C Y Out 0.480 7.899 - un1_ACCUMULATOR_v_i_0_1_m2_0_a2_0 Net - - 0.322 - 1 COREABC_0.genblk15\.ABCIO0I\.ABCOO0I.genblk4\.ABCIOI1\.ABClOI1.ABCIl10_RNI6C1U NOR2A B In - 8.220 - COREABC_0.genblk15\.ABCIO0I\.ABCOO0I.genblk4\.ABCIOI1\.ABClOI1.ABCIl10_RNI6C1U NOR2A Y Out 0.386 8.606 - ABCIl10_RNI6C1U Net - - 1.184 - 4 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I2_P0N OR2 A In - 9.790 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I2_P0N OR2 Y Out 0.507 10.297 - N387 Net - - 0.806 - 3 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I87_Y NOR2B B In - 11.104 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I87_Y NOR2B Y Out 0.627 11.731 - N530 Net - - 0.386 - 2 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I143_Y NOR2B A In - 12.117 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I143_Y NOR2B Y Out 0.514 12.631 - N589 Net - - 0.806 - 3 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I198_un1_Y OR2B A In - 13.438 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I198_un1_Y OR2B Y Out 0.514 13.952 - I198_un1_Y_i Net - - 0.322 - 1 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I198_Y OR3C C In - 14.274 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I198_Y OR3C Y Out 0.666 14.939 - N652 Net - - 0.806 - 3 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I259_un1_Y_0 NOR2B B In - 15.746 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I259_un1_Y_0 NOR2B Y Out 0.627 16.373 - ADD_32x32_fast_I259_un1_Y_0 Net - - 0.322 - 1 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I259_un1_Y NOR2B A In - 16.695 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I259_un1_Y NOR2B Y Out 0.514 17.209 - I259_un1_Y Net - - 0.322 - 1 r_b0_0_o2_0 NOR2 B In - 17.530 - r_b0_0_o2_0 NOR2 Y Out 0.646 18.177 - r_b0_0_o2_0 Net - - 0.386 - 2 r_b0_0_o2 OR2B A In - 18.563 - r_b0_0_o2 OR2B Y Out 0.488 19.051 - r_N_9 Net - - 0.386 - 2 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I302_Y_0 XOR2 B In - 19.437 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I302_Y_0 XOR2 Y Out 0.937 20.374 - un1_ACCUMULATOR[22] Net - - 0.322 - 1 COREABC_0.genblk19\.UROM\.INSTR_SCMD_RNILUAS83[0] OR2A A In - 20.695 - COREABC_0.genblk19\.UROM\.INSTR_SCMD_RNILUAS83[0] OR2A Y Out 0.537 21.232 - un1_ACCUMULATOR_m_i[22] Net - - 0.322 - 1 COREABC_0.genblk19\.UROM\.INSTR_CMD_RNIKSP3L3[0] OR3C C In - 21.554 - COREABC_0.genblk19\.UROM\.INSTR_CMD_RNIKSP3L3[0] OR3C Y Out 0.641 22.195 - ABCl0I1[22] Net - - 0.386 - 2 COREABC_0.ABCI1l1_RNO_2 NOR3A B In - 22.581 - COREABC_0.ABCI1l1_RNO_2 NOR3A Y Out 0.360 22.940 - ABCO0I_4_24[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO_0 NOR3B A In - 23.262 - COREABC_0.ABCI1l1_RNO_0 NOR3B Y Out 0.641 23.903 - ABCO0I_4_29[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO NOR2B A In - 24.225 - COREABC_0.ABCI1l1_RNO NOR2B Y Out 0.514 24.739 - ABCO0I_4[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1 DFN1E1C0 D In - 25.061 - ============================================================================================================================================= Total path delay (propagation time + setup) of 25.565 is 11.936(46.7%) logic and 13.629(53.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 24.876 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -15.415 Number of logic level(s): 19 Starting point: COREABC_0.genblk19\.UROM\.INSTR_CMD[1] / Q Ending point: COREABC_0.ABCI1l1 / D The start point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------- COREABC_0.genblk19\.UROM\.INSTR_CMD[1] DFN1 Q Out 0.737 0.737 - INSTR_CMD[1] Net - - 2.172 - 16 COREABC_0.genblk19\.UROM\.INSTR_CMD_RNIKHD1[2] OR3B B In - 2.909 - COREABC_0.genblk19\.UROM\.INSTR_CMD_RNIKHD1[2] OR3B Y Out 0.607 3.516 - ABCO001_6_0_a3_0_1 Net - - 1.423 - 6 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I15_P0N_a1tt_m2_0_a3 OR2A A In - 4.939 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I15_P0N_a1tt_m2_0_a3 OR2A Y Out 0.537 5.476 - ADD_32x32_fast_I15_P0N_a1tt_m2_0_a3 Net - - 0.322 - 1 I_132 CLKINT A In - 5.798 - I_132 CLKINT Y Out 0.174 5.972 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I0_CO1_N_4 Net - - 1.601 - 104 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I23_P0N_a1 OR3B B In - 7.572 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I23_P0N_a1 OR3B Y Out 0.607 8.179 - N_2_28_i Net - - 1.994 - 12 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I5_P0N_0 OR3B B In - 10.172 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I5_P0N_0 OR3B Y Out 0.624 10.796 - N396 Net - - 0.386 - 2 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I83_Y NOR2B A In - 11.182 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I83_Y NOR2B Y Out 0.514 11.696 - N526 Net - - 0.386 - 2 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I143_Y NOR2B B In - 12.082 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I143_Y NOR2B Y Out 0.627 12.710 - N589 Net - - 0.806 - 3 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I198_un1_Y OR2B A In - 13.516 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I198_un1_Y OR2B Y Out 0.514 14.030 - I198_un1_Y_i Net - - 0.322 - 1 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I198_Y OR3C C In - 14.352 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I198_Y OR3C Y Out 0.666 15.018 - N652 Net - - 0.806 - 3 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I259_un1_Y_0 NOR2B B In - 15.824 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I259_un1_Y_0 NOR2B Y Out 0.627 16.451 - ADD_32x32_fast_I259_un1_Y_0 Net - - 0.322 - 1 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I259_un1_Y NOR2B A In - 16.773 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I259_un1_Y NOR2B Y Out 0.514 17.287 - I259_un1_Y Net - - 0.322 - 1 r_b0_0_o2_0 NOR2 B In - 17.609 - r_b0_0_o2_0 NOR2 Y Out 0.646 18.255 - r_b0_0_o2_0 Net - - 0.386 - 2 r_b0_0_o2 OR2B A In - 18.641 - r_b0_0_o2 OR2B Y Out 0.488 19.129 - r_N_9 Net - - 0.386 - 2 r_b0_0_x2 XNOR2 A In - 19.515 - r_b0_0_x2 XNOR2 Y Out 0.488 20.003 - N_3_0_i Net - - 0.322 - 1 COREABC_0.genblk19\.UROM\.INSTR_SCMD_RNII2C465[0] MX2C B In - 20.325 - COREABC_0.genblk19\.UROM\.INSTR_SCMD_RNII2C465[0] MX2C Y Out 0.586 20.911 - ABCl0I1[28] Net - - 0.386 - 2 COREABC_0.ABCI1l1_RNO_12 NOR3A B In - 21.296 - COREABC_0.ABCI1l1_RNO_12 NOR3A Y Out 0.488 21.785 - ABCO0I_4_21[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO_6 NOR3B B In - 22.106 - COREABC_0.ABCI1l1_RNO_6 NOR3B Y Out 0.624 22.730 - ABCO0I_4_26[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO_1 NOR3C C In - 23.052 - COREABC_0.ABCI1l1_RNO_1 NOR3C Y Out 0.666 23.717 - ABCO0I_4_28[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO NOR2B B In - 24.039 - COREABC_0.ABCI1l1_RNO NOR2B Y Out 0.516 24.555 - ABCO0I_4[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1 DFN1E1C0 D In - 24.876 - ================================================================================================================================ Total path delay (propagation time + setup) of 25.415 is 11.790(46.4%) logic and 13.625(53.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 24.798 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -15.337 Number of logic level(s): 19 Starting point: COREABC_0.genblk19\.UROM\.INSTR_CMD[1] / Q Ending point: COREABC_0.ABCI1l1 / D The start point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------- COREABC_0.genblk19\.UROM\.INSTR_CMD[1] DFN1 Q Out 0.737 0.737 - INSTR_CMD[1] Net - - 2.172 - 16 COREABC_0.genblk19\.UROM\.INSTR_CMD_RNIKHD1[2] OR3B B In - 2.909 - COREABC_0.genblk19\.UROM\.INSTR_CMD_RNIKHD1[2] OR3B Y Out 0.607 3.516 - ABCO001_6_0_a3_0_1 Net - - 1.423 - 6 COREABC_0.genblk19\.UROM\.INSTR_SCMD_RNIA8AC[1] AOI1 C In - 4.939 - COREABC_0.genblk19\.UROM\.INSTR_SCMD_RNIA8AC[1] AOI1 Y Out 0.487 5.426 - INSTR_SCMD_RNIA8AC[1] Net - - 1.994 - 12 COREABC_0.genblk15\.ABCIO0I\.ABCOO0I.genblk4\.ABCIOI1\.ABClOI1.ABCIl10_RNIQU6L MX2C S In - 7.419 - COREABC_0.genblk15\.ABCIO0I\.ABCOO0I.genblk4\.ABCIOI1\.ABClOI1.ABCIl10_RNIQU6L MX2C Y Out 0.480 7.899 - un1_ACCUMULATOR_v_i_0_1_m2_0_a2_0 Net - - 0.322 - 1 COREABC_0.genblk15\.ABCIO0I\.ABCOO0I.genblk4\.ABCIOI1\.ABClOI1.ABCIl10_RNI6C1U NOR2A B In - 8.220 - COREABC_0.genblk15\.ABCIO0I\.ABCOO0I.genblk4\.ABCIOI1\.ABClOI1.ABCIl10_RNI6C1U NOR2A Y Out 0.386 8.606 - ABCIl10_RNI6C1U Net - - 1.184 - 4 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I2_P0N OR2 A In - 9.790 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I2_P0N OR2 Y Out 0.507 10.297 - N387 Net - - 0.806 - 3 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I87_Y NOR2B B In - 11.104 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I87_Y NOR2B Y Out 0.627 11.731 - N530 Net - - 0.386 - 2 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I143_Y NOR2B A In - 12.117 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I143_Y NOR2B Y Out 0.514 12.631 - N589 Net - - 0.806 - 3 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I198_un1_Y OR2B A In - 13.438 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I198_un1_Y OR2B Y Out 0.514 13.952 - I198_un1_Y_i Net - - 0.322 - 1 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I198_Y OR3C C In - 14.274 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I198_Y OR3C Y Out 0.666 14.939 - N652 Net - - 0.806 - 3 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I259_un1_Y_0 NOR2B B In - 15.746 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I259_un1_Y_0 NOR2B Y Out 0.627 16.373 - ADD_32x32_fast_I259_un1_Y_0 Net - - 0.322 - 1 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I259_un1_Y NOR2B A In - 16.695 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I259_un1_Y NOR2B Y Out 0.514 17.209 - I259_un1_Y Net - - 0.322 - 1 r_b0_0_o2_0 NOR2 B In - 17.530 - r_b0_0_o2_0 NOR2 Y Out 0.646 18.177 - r_b0_0_o2_0 Net - - 0.386 - 2 r_b0_0_o2 OR2B A In - 18.563 - r_b0_0_o2 OR2B Y Out 0.488 19.051 - r_N_9 Net - - 0.386 - 2 r_b0_0_x2 XNOR2 A In - 19.437 - r_b0_0_x2 XNOR2 Y Out 0.488 19.925 - N_3_0_i Net - - 0.322 - 1 COREABC_0.genblk19\.UROM\.INSTR_SCMD_RNII2C465[0] MX2C B In - 20.247 - COREABC_0.genblk19\.UROM\.INSTR_SCMD_RNII2C465[0] MX2C Y Out 0.586 20.832 - ABCl0I1[28] Net - - 0.386 - 2 COREABC_0.ABCI1l1_RNO_12 NOR3A B In - 21.218 - COREABC_0.ABCI1l1_RNO_12 NOR3A Y Out 0.488 21.706 - ABCO0I_4_21[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO_6 NOR3B B In - 22.028 - COREABC_0.ABCI1l1_RNO_6 NOR3B Y Out 0.624 22.652 - ABCO0I_4_26[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO_1 NOR3C C In - 22.973 - COREABC_0.ABCI1l1_RNO_1 NOR3C Y Out 0.666 23.639 - ABCO0I_4_28[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO NOR2B B In - 23.960 - COREABC_0.ABCI1l1_RNO NOR2B Y Out 0.516 24.477 - ABCO0I_4[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1 DFN1E1C0 D In - 24.798 - ============================================================================================================================================= Total path delay (propagation time + setup) of 25.337 is 11.708(46.2%) logic and 13.629(53.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 0.504 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.496 - Propagation time: 24.817 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -15.321 Number of logic level(s): 19 Starting point: COREABC_0.genblk19\.UROM\.INSTR_CMD[0] / Q Ending point: COREABC_0.ABCI1l1 / D The start point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------- COREABC_0.genblk19\.UROM\.INSTR_CMD[0] DFN1 Q Out 0.737 0.737 - INSTR_CMD[0] Net - - 1.994 - 12 COREABC_0.genblk19\.UROM\.INSTR_CMD_RNIKHD1[2] OR3B A In - 2.730 - COREABC_0.genblk19\.UROM\.INSTR_CMD_RNIKHD1[2] OR3B Y Out 0.464 3.194 - ABCO001_6_0_a3_0_1 Net - - 1.423 - 6 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I15_P0N_a1tt_m2_0_a3 OR2A A In - 4.618 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I15_P0N_a1tt_m2_0_a3 OR2A Y Out 0.537 5.155 - ADD_32x32_fast_I15_P0N_a1tt_m2_0_a3 Net - - 0.322 - 1 I_132 CLKINT A In - 5.476 - I_132 CLKINT Y Out 0.174 5.650 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I0_CO1_N_4 Net - - 1.601 - 104 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I23_P0N_a1 OR3B B In - 7.251 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I23_P0N_a1 OR3B Y Out 0.607 7.857 - N_2_28_i Net - - 1.994 - 12 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I5_P0N_0 OR3B B In - 9.851 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I5_P0N_0 OR3B Y Out 0.624 10.475 - N396 Net - - 0.386 - 2 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I83_Y NOR2B A In - 10.861 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I83_Y NOR2B Y Out 0.514 11.375 - N526 Net - - 0.386 - 2 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I143_Y NOR2B B In - 11.761 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I143_Y NOR2B Y Out 0.627 12.388 - N589 Net - - 0.806 - 3 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I198_un1_Y OR2B A In - 13.195 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I198_un1_Y OR2B Y Out 0.514 13.709 - I198_un1_Y_i Net - - 0.322 - 1 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I198_Y OR3C C In - 14.030 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I198_Y OR3C Y Out 0.666 14.696 - N652 Net - - 0.806 - 3 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I259_un1_Y_0 NOR2B B In - 15.502 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I259_un1_Y_0 NOR2B Y Out 0.627 16.130 - ADD_32x32_fast_I259_un1_Y_0 Net - - 0.322 - 1 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I259_un1_Y NOR2B A In - 16.451 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I259_un1_Y NOR2B Y Out 0.514 16.966 - I259_un1_Y Net - - 0.322 - 1 r_b0_0_o2_0 NOR2 B In - 17.287 - r_b0_0_o2_0 NOR2 Y Out 0.646 17.934 - r_b0_0_o2_0 Net - - 0.386 - 2 r_b0_0_o2 OR2B A In - 18.320 - r_b0_0_o2 OR2B Y Out 0.488 18.808 - r_N_9 Net - - 0.386 - 2 COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I302_Y_0 XOR2 B In - 19.194 - COREABC_0.un1_ACCUMULATOR.ADD_32x32_fast_I302_Y_0 XOR2 Y Out 0.937 20.130 - un1_ACCUMULATOR[22] Net - - 0.322 - 1 COREABC_0.genblk19\.UROM\.INSTR_SCMD_RNILUAS83[0] OR2A A In - 20.452 - COREABC_0.genblk19\.UROM\.INSTR_SCMD_RNILUAS83[0] OR2A Y Out 0.537 20.989 - un1_ACCUMULATOR_m_i[22] Net - - 0.322 - 1 COREABC_0.genblk19\.UROM\.INSTR_CMD_RNIKSP3L3[0] OR3C C In - 21.310 - COREABC_0.genblk19\.UROM\.INSTR_CMD_RNIKSP3L3[0] OR3C Y Out 0.641 21.952 - ABCl0I1[22] Net - - 0.386 - 2 COREABC_0.ABCI1l1_RNO_2 NOR3A B In - 22.337 - COREABC_0.ABCI1l1_RNO_2 NOR3A Y Out 0.360 22.697 - ABCO0I_4_24[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO_0 NOR3B A In - 23.019 - COREABC_0.ABCI1l1_RNO_0 NOR3B Y Out 0.641 23.660 - ABCO0I_4_29[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO NOR2B A In - 23.981 - COREABC_0.ABCI1l1_RNO NOR2B Y Out 0.514 24.496 - ABCO0I_4[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1 DFN1E1C0 D In - 24.817 - ================================================================================================================================ Total path delay (propagation time + setup) of 25.321 is 11.875(46.9%) logic and 13.446(53.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------ MSS_Waveform_0.MSS_ADLIB_INST System MSS_APB FABPRDATA[0] FABPRDATA[0] 0.000 -2.328 MSS_Waveform_0.MSS_ADLIB_INST System MSS_APB FABPRDATA[1] FABPRDATA[1] 0.000 -2.167 MSS_Waveform_0.MSS_ADLIB_INST System MSS_APB FABPRDATA[2] FABPRDATA[2] 0.000 -1.119 MSS_Waveform_0.MSS_ADLIB_INST System MSS_APB FABPRDATA[4] FABPRDATA[4] 0.000 -0.750 MSS_Waveform_0.MSS_ADLIB_INST System MSS_APB FABPRDATA[5] FABPRDATA[5] 0.000 -0.705 MSS_Waveform_0.MSS_ADLIB_INST System MSS_APB FABPRDATA[16] FABPRDATA[16] 0.000 -0.298 MSS_Waveform_0.MSS_ADLIB_INST System MSS_APB FABPRDATA[6] FABPRDATA[6] 0.000 -0.279 MSS_Waveform_0.MSS_ADLIB_INST System MSS_APB FABPRDATA[20] FABPRDATA[20] 0.000 -0.175 MSS_Waveform_0.MSS_ADLIB_INST System MSS_APB FABPRDATA[13] FABPRDATA[13] 0.000 -0.022 MSS_Waveform_0.MSS_ADLIB_INST System MSS_APB FABPRDATA[3] FABPRDATA[3] 0.000 0.129 ================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------- COREABC_0.ABCI1l1 System DFN1E1C0 D ABCO0I_4[0] 9.461 -2.328 COREABC_0.ACCUMULATOR[16] System DFN1E1C0 D ABCl0I1[16] 9.461 3.210 COREABC_0.ACCUMULATOR[1] System DFN1E1C0 D ABCl0I1[1] 9.496 3.278 COREABC_0.ACCUMULATOR[0] System DFN1E1C0 D ABCl0I1[0] 9.461 3.302 COREABC_0.ACCUMULATOR[24] System DFN1E1C0 D ABCl0I1[24] 9.461 3.636 COREABC_0.ACCUMULATOR[4] System DFN1E1C0 D ABCl0I1[4] 9.496 3.937 COREABC_0.ACCUMULATOR[5] System DFN1E1C0 D ABCl0I1[5] 9.496 3.937 COREABC_0.ACCUMULATOR[15] System DFN1E1C0 D ABCl0I1[15] 9.496 3.977 MSS_Waveform_0.MSS_ADLIB_INST System MSS_APB PLLLOCK MSS_ADLIB_INST_PLLLOCK 10.000 4.169 COREABC_0.ACCUMULATOR[12] System DFN1E1C0 D ABCl0I1[12] 9.461 4.187 ======================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 11.790 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -2.328 Number of logic level(s): 13 Starting point: MSS_Waveform_0.MSS_ADLIB_INST / FABPRDATA[0] Ending point: COREABC_0.ABCI1l1 / D The start point is clocked by System [rising] The end point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------ MSS_Waveform_0.MSS_ADLIB_INST MSS_APB FABPRDATA[0] Out 0.000 0.000 - FABPRDATA[0] Net - - 0.322 - 1 COREABC_0.genblk19\.UROM\.INSTR_SLOT_RNINDUC[1] MX2 A In - 0.322 - COREABC_0.genblk19\.UROM\.INSTR_SLOT_RNINDUC[1] MX2 Y Out 0.579 0.900 - PRDATA_M_m_0[0] Net - - 0.322 - 1 COREABC_0.genblk19\.UROM\.INSTR_SLOT_RNI3T8R[1] OR3B A In - 1.222 - COREABC_0.genblk19\.UROM\.INSTR_SLOT_RNI3T8R[1] OR3B Y Out 0.464 1.686 - PRDATA_M_m[0] Net - - 0.322 - 1 COREABC_0.ACCUMULATOR_RNIAT2D2[31] NOR2B A In - 2.007 - COREABC_0.ACCUMULATOR_RNIAT2D2[31] NOR2B Y Out 0.488 2.495 - ABCl0I1_iv_0[0] Net - - 0.322 - 1 COREABC_0.ACCUMULATOR_RNIG25N2[1] AOI1B C In - 2.817 - COREABC_0.ACCUMULATOR_RNIG25N2[1] AOI1B Y Out 0.398 3.215 - ABCl0I1_iv_1[0] Net - - 0.322 - 1 COREABC_0.ACCUMULATOR_RNIIA354[1] OA1A C In - 3.537 - COREABC_0.ACCUMULATOR_RNIIA354[1] OA1A Y Out 0.398 3.934 - ABCl0I1_iv_2[0] Net - - 0.322 - 1 COREABC_0.ACCUMULATOR_RNIA0U57[0] NOR3C A In - 4.256 - COREABC_0.ACCUMULATOR_RNIA0U57[0] NOR3C Y Out 0.525 4.781 - ABCl0I1_iv_4[0] Net - - 0.322 - 1 COREABC_0.ACCUMULATOR_RNIEGQ1A[0] OR3C C In - 5.102 - COREABC_0.ACCUMULATOR_RNIEGQ1A[0] OR3C Y Out 0.666 5.768 - ABCl0I1[0] Net - - 0.386 - 2 COREABC_0.ABCI1l1_RNO_16 NOR3 B In - 6.154 - COREABC_0.ABCI1l1_RNO_16 NOR3 Y Out 0.714 6.868 - ABCO0I_4_1[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO_13 NOR3A A In - 7.189 - COREABC_0.ABCI1l1_RNO_13 NOR3A Y Out 0.664 7.853 - ABCO0I_4_3[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO_10 NOR3A A In - 8.175 - COREABC_0.ABCI1l1_RNO_10 NOR3A Y Out 0.664 8.839 - ABCO0I_4_8[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO_4 NOR3B B In - 9.160 - COREABC_0.ABCI1l1_RNO_4 NOR3B Y Out 0.624 9.784 - ABCO0I_4_20[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO_1 NOR3C A In - 10.106 - COREABC_0.ABCI1l1_RNO_1 NOR3C Y Out 0.525 10.631 - ABCO0I_4_28[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO NOR2B B In - 10.952 - COREABC_0.ABCI1l1_RNO NOR2B Y Out 0.516 11.468 - ABCO0I_4[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1 DFN1E1C0 D In - 11.790 - ======================================================================================================================== Total path delay (propagation time + setup) of 12.328 is 7.763(63.0%) logic and 4.565(37.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 11.628 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -2.167 Number of logic level(s): 12 Starting point: MSS_Waveform_0.MSS_ADLIB_INST / FABPRDATA[1] Ending point: COREABC_0.ABCI1l1 / D The start point is clocked by System [rising] The end point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------ MSS_Waveform_0.MSS_ADLIB_INST MSS_APB FABPRDATA[1] Out 0.000 0.000 - FABPRDATA[1] Net - - 0.322 - 1 COREABC_0.genblk19\.UROM\.INSTR_SLOT_RNIOHUC[1] MX2 A In - 0.322 - COREABC_0.genblk19\.UROM\.INSTR_SLOT_RNIOHUC[1] MX2 Y Out 0.579 0.900 - PRDATA_M_m_0[1] Net - - 0.322 - 1 COREABC_0.genblk19\.UROM\.INSTR_SLOT_RNIDPAQ[1] NOR2A A In - 1.222 - COREABC_0.genblk19\.UROM\.INSTR_SLOT_RNIDPAQ[1] NOR2A Y Out 0.627 1.849 - PRDATA_M_m_1[1] Net - - 0.322 - 1 COREABC_0.ACCUMULATOR_RNI1OLE1[0] AOI1B A In - 2.171 - COREABC_0.ACCUMULATOR_RNI1OLE1[0] AOI1B Y Out 0.933 3.104 - ABCl0I1_iv_0[1] Net - - 0.322 - 1 COREABC_0.ACCUMULATOR_RNI4IHL1[2] NOR2B B In - 3.425 - COREABC_0.ACCUMULATOR_RNI4IHL1[2] NOR2B Y Out 0.516 3.942 - ABCl0I1_iv_1[1] Net - - 0.322 - 1 COREABC_0.ACCUMULATOR_RNI77IL4[1] NOR3C B In - 4.263 - COREABC_0.ACCUMULATOR_RNI77IL4[1] NOR3C Y Out 0.624 4.887 - ABCl0I1_iv_3[1] Net - - 0.322 - 1 COREABC_0.ACCUMULATOR_RNIQGL4A[1] OR3C B In - 5.208 - COREABC_0.ACCUMULATOR_RNIQGL4A[1] OR3C Y Out 0.624 5.832 - ABCl0I1[1] Net - - 0.386 - 2 COREABC_0.ABCI1l1_RNO_16 NOR3 A In - 6.218 - COREABC_0.ABCI1l1_RNO_16 NOR3 Y Out 0.488 6.706 - ABCO0I_4_1[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO_13 NOR3A A In - 7.028 - COREABC_0.ABCI1l1_RNO_13 NOR3A Y Out 0.664 7.692 - ABCO0I_4_3[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO_10 NOR3A A In - 8.013 - COREABC_0.ABCI1l1_RNO_10 NOR3A Y Out 0.664 8.677 - ABCO0I_4_8[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO_4 NOR3B B In - 8.999 - COREABC_0.ABCI1l1_RNO_4 NOR3B Y Out 0.624 9.623 - ABCO0I_4_20[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO_1 NOR3C A In - 9.944 - COREABC_0.ABCI1l1_RNO_1 NOR3C Y Out 0.525 10.469 - ABCO0I_4_28[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO NOR2B B In - 10.790 - COREABC_0.ABCI1l1_RNO NOR2B Y Out 0.516 11.307 - ABCO0I_4[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1 DFN1E1C0 D In - 11.628 - ======================================================================================================================== Total path delay (propagation time + setup) of 12.167 is 7.923(65.1%) logic and 4.244(34.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 10.580 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -1.119 Number of logic level(s): 11 Starting point: MSS_Waveform_0.MSS_ADLIB_INST / FABPRDATA[2] Ending point: COREABC_0.ABCI1l1 / D The start point is clocked by System [rising] The end point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------ MSS_Waveform_0.MSS_ADLIB_INST MSS_APB FABPRDATA[2] Out 0.000 0.000 - FABPRDATA[2] Net - - 0.322 - 1 COREABC_0.genblk19\.UROM\.INSTR_SLOT_RNIPLUC[1] MX2 A In - 0.322 - COREABC_0.genblk19\.UROM\.INSTR_SLOT_RNIPLUC[1] MX2 Y Out 0.579 0.900 - PRDATA_M_m_0[2] Net - - 0.322 - 1 COREABC_0.genblk19\.UROM\.INSTR_SLOT_RNI559R[1] OR3B A In - 1.222 - COREABC_0.genblk19\.UROM\.INSTR_SLOT_RNI559R[1] OR3B Y Out 0.464 1.686 - PRDATA_M_m[2] Net - - 0.322 - 1 COREABC_0.ACCUMULATOR_RNIBDOO1[1] NOR3C B In - 2.007 - COREABC_0.ACCUMULATOR_RNIBDOO1[1] NOR3C Y Out 0.624 2.631 - ABCl0I1_iv_1[2] Net - - 0.322 - 1 COREABC_0.ACCUMULATOR_RNI9BJP4[2] NOR3C B In - 2.953 - COREABC_0.ACCUMULATOR_RNI9BJP4[2] NOR3C Y Out 0.624 3.576 - ABCl0I1_iv_3[2] Net - - 0.322 - 1 COREABC_0.ACCUMULATOR_RNIEL3CB[2] OR3C B In - 3.898 - COREABC_0.ACCUMULATOR_RNIEL3CB[2] OR3C Y Out 0.624 4.522 - ABCl0I1[2] Net - - 0.386 - 2 COREABC_0.ABCI1l1_RNO_16 NOR3 C In - 4.908 - COREABC_0.ABCI1l1_RNO_16 NOR3 Y Out 0.751 5.659 - ABCO0I_4_1[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO_13 NOR3A A In - 5.980 - COREABC_0.ABCI1l1_RNO_13 NOR3A Y Out 0.664 6.644 - ABCO0I_4_3[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO_10 NOR3A A In - 6.965 - COREABC_0.ABCI1l1_RNO_10 NOR3A Y Out 0.664 7.629 - ABCO0I_4_8[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO_4 NOR3B B In - 7.951 - COREABC_0.ABCI1l1_RNO_4 NOR3B Y Out 0.624 8.575 - ABCO0I_4_20[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO_1 NOR3C A In - 8.896 - COREABC_0.ABCI1l1_RNO_1 NOR3C Y Out 0.525 9.421 - ABCO0I_4_28[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO NOR2B B In - 9.742 - COREABC_0.ABCI1l1_RNO NOR2B Y Out 0.516 10.259 - ABCO0I_4[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1 DFN1E1C0 D In - 10.580 - ======================================================================================================================== Total path delay (propagation time + setup) of 11.119 is 7.196(64.7%) logic and 3.922(35.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 10.212 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.750 Number of logic level(s): 11 Starting point: MSS_Waveform_0.MSS_ADLIB_INST / FABPRDATA[4] Ending point: COREABC_0.ABCI1l1 / D The start point is clocked by System [rising] The end point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------ MSS_Waveform_0.MSS_ADLIB_INST MSS_APB FABPRDATA[4] Out 0.000 0.000 - FABPRDATA[4] Net - - 0.322 - 1 COREABC_0.genblk19\.UROM\.INSTR_SLOT_RNIRTUC[1] MX2 A In - 0.322 - COREABC_0.genblk19\.UROM\.INSTR_SLOT_RNIRTUC[1] MX2 Y Out 0.579 0.900 - PRDATA_M_m_0[4] Net - - 0.322 - 1 COREABC_0.genblk19\.UROM\.INSTR_SLOT_RNI7D9R[1] OR3B A In - 1.222 - COREABC_0.genblk19\.UROM\.INSTR_SLOT_RNI7D9R[1] OR3B Y Out 0.464 1.686 - PRDATA_M_m[4] Net - - 0.322 - 1 COREABC_0.ACCUMULATOR_RNI7GME1[3] OA1A C In - 2.007 - COREABC_0.ACCUMULATOR_RNI7GME1[3] OA1A Y Out 0.398 2.405 - ABCl0I1_iv_0[4] Net - - 0.322 - 1 COREABC_0.ACCUMULATOR_RNI3D793[3] NOR3C A In - 2.727 - COREABC_0.ACCUMULATOR_RNI3D793[3] NOR3C Y Out 0.525 3.252 - ABCl0I1_iv_2[4] Net - - 0.322 - 1 COREABC_0.genblk15\.ABCIO0I\.ABCOO0I.genblk4\.ABCIOI1\.ABClOI1.ABCIl10_RNILSHL7 NOR3C B In - 3.573 - COREABC_0.genblk15\.ABCIO0I\.ABCOO0I.genblk4\.ABCIOI1\.ABClOI1.ABCIl10_RNILSHL7 NOR3C Y Out 0.624 4.197 - ABCl0I1_iv_5[4] Net - - 0.322 - 1 COREABC_0.genblk19\.UROM\.INSTR_SCMD_0_RNIA0HDF[0] AO1C C In - 4.518 - COREABC_0.genblk19\.UROM\.INSTR_SCMD_0_RNIA0HDF[0] AO1C Y Out 0.655 5.174 - ABCl0I1[4] Net - - 0.386 - 2 COREABC_0.ABCI1l1_RNO_13 NOR3A C In - 5.559 - COREABC_0.ABCI1l1_RNO_13 NOR3A Y Out 0.716 6.275 - ABCO0I_4_3[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO_10 NOR3A A In - 6.597 - COREABC_0.ABCI1l1_RNO_10 NOR3A Y Out 0.664 7.261 - ABCO0I_4_8[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO_4 NOR3B B In - 7.582 - COREABC_0.ABCI1l1_RNO_4 NOR3B Y Out 0.624 8.206 - ABCO0I_4_20[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO_1 NOR3C A In - 8.528 - COREABC_0.ABCI1l1_RNO_1 NOR3C Y Out 0.525 9.053 - ABCO0I_4_28[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO NOR2B B In - 9.374 - COREABC_0.ABCI1l1_RNO NOR2B Y Out 0.516 9.890 - ABCO0I_4[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1 DFN1E1C0 D In - 10.212 - ====================================================================================================================================================== Total path delay (propagation time + setup) of 10.750 is 6.828(63.5%) logic and 3.922(36.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 10.166 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.705 Number of logic level(s): 11 Starting point: MSS_Waveform_0.MSS_ADLIB_INST / FABPRDATA[5] Ending point: COREABC_0.ABCI1l1 / D The start point is clocked by System [rising] The end point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------ MSS_Waveform_0.MSS_ADLIB_INST MSS_APB FABPRDATA[5] Out 0.000 0.000 - FABPRDATA[5] Net - - 0.322 - 1 COREABC_0.genblk19\.UROM\.INSTR_SLOT_RNIS1VC[1] MX2 A In - 0.322 - COREABC_0.genblk19\.UROM\.INSTR_SLOT_RNIS1VC[1] MX2 Y Out 0.579 0.900 - PRDATA_M_m_0[5] Net - - 0.322 - 1 COREABC_0.genblk19\.UROM\.INSTR_SLOT_RNI8H9R[1] OR3B A In - 1.222 - COREABC_0.genblk19\.UROM\.INSTR_SLOT_RNI8H9R[1] OR3B Y Out 0.464 1.686 - PRDATA_M_m[5] Net - - 0.322 - 1 COREABC_0.ACCUMULATOR_RNI9OME1[4] OA1A C In - 2.007 - COREABC_0.ACCUMULATOR_RNI9OME1[4] OA1A Y Out 0.398 2.405 - ABCl0I1_iv_0[5] Net - - 0.322 - 1 COREABC_0.ACCUMULATOR_RNIGC483[4] NOR3C A In - 2.727 - COREABC_0.ACCUMULATOR_RNIGC483[4] NOR3C Y Out 0.525 3.252 - ABCl0I1_iv_2[5] Net - - 0.322 - 1 COREABC_0.genblk15\.ABCIO0I\.ABCOO0I.genblk4\.ABCIOI1\.ABClOI1.ABCIl10_RNIVH4H7 NOR3C B In - 3.573 - COREABC_0.genblk15\.ABCIO0I\.ABCOO0I.genblk4\.ABCIOI1\.ABClOI1.ABCIl10_RNIVH4H7 NOR3C Y Out 0.624 4.197 - ABCl0I1_iv_5[5] Net - - 0.322 - 1 COREABC_0.genblk19\.UROM\.INSTR_SCMD_0_RNI00I7N[0] AO1C C In - 4.518 - COREABC_0.genblk19\.UROM\.INSTR_SCMD_0_RNI00I7N[0] AO1C Y Out 0.655 5.174 - ABCl0I1[5] Net - - 0.386 - 2 COREABC_0.ABCI1l1_RNO_14 NOR3 A In - 5.559 - COREABC_0.ABCI1l1_RNO_14 NOR3 Y Out 0.488 6.048 - ABCO0I_4_6[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO_11 NOR3A A In - 6.369 - COREABC_0.ABCI1l1_RNO_11 NOR3A Y Out 0.664 7.033 - ABCO0I_4_15[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO_6 NOR3B A In - 7.355 - COREABC_0.ABCI1l1_RNO_6 NOR3B Y Out 0.666 8.020 - ABCO0I_4_26[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO_1 NOR3C C In - 8.342 - COREABC_0.ABCI1l1_RNO_1 NOR3C Y Out 0.666 9.007 - ABCO0I_4_28[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1_RNO NOR2B B In - 9.329 - COREABC_0.ABCI1l1_RNO NOR2B Y Out 0.516 9.845 - ABCO0I_4[0] Net - - 0.322 - 1 COREABC_0.ABCI1l1 DFN1E1C0 D In - 10.166 - ====================================================================================================================================================== Total path delay (propagation time + setup) of 10.705 is 6.783(63.4%) logic and 3.922(36.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Target Part: A2F200M3F_FBGA256_Std Report for cell Top_Waveform.verilog Core Cell usage: cell count area count*area AND2 13 1.0 13.0 AND3 2 1.0 2.0 AO1 36 1.0 36.0 AO12 1 1.0 1.0 AO13 6 1.0 6.0 AO14 2 1.0 2.0 AO16 1 1.0 1.0 AO17 1 1.0 1.0 AO18 1 1.0 1.0 AO1A 20 1.0 20.0 AO1B 29 1.0 29.0 AO1C 18 1.0 18.0 AO1D 8 1.0 8.0 AOI1 15 1.0 15.0 AOI1B 19 1.0 19.0 AOI5 2 1.0 2.0 AX1 3 1.0 3.0 AX1A 2 1.0 2.0 AX1B 10 1.0 10.0 AX1C 13 1.0 13.0 AX1D 5 1.0 5.0 AX1E 23 1.0 23.0 AXO1 1 1.0 1.0 AXO6 1 1.0 1.0 AXOI1 1 1.0 1.0 AXOI2 3 1.0 3.0 AXOI3 1 1.0 1.0 AXOI4 2 1.0 2.0 AXOI5 1 1.0 1.0 AXOI7 3 1.0 3.0 BUFF 5 1.0 5.0 CLKINT 3 0.0 0.0 GND 12 0.0 0.0 INV 4 1.0 4.0 MAJ3 4 1.0 4.0 MAJ3X 1 1.0 1.0 MAJ3XI 1 1.0 1.0 MIN3X 1 1.0 1.0 MSS_APB 1 0.0 0.0 MSS_CCC 1 0.0 0.0 MX2 142 1.0 142.0 MX2A 21 1.0 21.0 MX2B 25 1.0 25.0 MX2C 64 1.0 64.0 NAND2 9 1.0 9.0 NOR2 41 1.0 41.0 NOR2A 63 1.0 63.0 NOR2B 90 1.0 90.0 NOR3 11 1.0 11.0 NOR3A 22 1.0 22.0 NOR3B 26 1.0 26.0 NOR3C 96 1.0 96.0 OA1 8 1.0 8.0 OA1A 56 1.0 56.0 OA1B 5 1.0 5.0 OA1C 6 1.0 6.0 OAI1 6 1.0 6.0 OR2 59 1.0 59.0 OR2A 53 1.0 53.0 OR2B 159 1.0 159.0 OR3 5 1.0 5.0 OR3A 17 1.0 17.0 OR3B 64 1.0 64.0 OR3C 48 1.0 48.0 VCC 12 0.0 0.0 XA1B 3 1.0 3.0 XAI1 18 1.0 18.0 XAI1A 2 1.0 2.0 XNOR2 6 1.0 6.0 XNOR3 3 1.0 3.0 XO1 9 1.0 9.0 XO1A 5 1.0 5.0 XOR2 47 1.0 47.0 XOR3 3 1.0 3.0 ZOR3 1 1.0 1.0 DFN1 22 1.0 22.0 DFN1C0 6 1.0 6.0 DFN1E0C0 9 1.0 9.0 DFN1E1C0 58 1.0 58.0 DFN1P0 11 1.0 11.0 RAM512X18 2 0.0 0.0 ----- ---------- TOTAL 1589 1558.0 IO Cell usage: cell count INBUF_A 1 INBUF_MSS 1 MSS_XTLOSC 1 OUTBUF_A 1 ----- TOTAL 4 Core Cells : 1558 of 4608 (34%) IO Cells : 4 of 66 (6%) RAM/ROM Usage Summary Block Rams : 2 of 8 (25%) Mapper successful! Process took 0h:00m:36s realtime, 0h:00m:35s cputime # Tue Aug 31 18:49:47 2010 ###########################################################]