Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Thu Dec 08 14:41:29 2011


Design: Top_Waveform
Family: SmartFusion
Die: A2F200M3F
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.574
External Hold (ns):         1.448
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_glb
Period (ns):                30.678
Frequency (MHz):            32.597
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               MSS_Waveform_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.781
  Slack (ns):
  Arrival (ns):                0.781
  Required (ns):
  Setup (ns):                  -1.830
  External Setup (ns):         -1.574


Expanded Path 1
  From: MSS_RESET_N
  To: MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.781
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        MSS_Waveform_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.781          cell: ADLIB:IOPAD_IN
  0.781                        MSS_Waveform_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: MSS_Waveform_0/MSS_RESET_0_MSS_RESET_N_Y
  0.781                        MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.781                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.525          net: MSS_Waveform_0/GLA0
  N/C                          MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -1.830          Library setup time: ADLIB:MSS_APB_IP
  N/C                          MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glb

SET Register to Register

Path 1
  From:                        COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10:RCLK
  To:                          COREABC_0/ABCIl01:D
  Delay (ns):                  30.086
  Slack (ns):
  Arrival (ns):                30.779
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         30.678

Path 2
  From:                        COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10:RCLK
  To:                          COREABC_0/ABCll01:D
  Delay (ns):                  29.358
  Slack (ns):
  Arrival (ns):                30.051
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         29.952

Path 3
  From:                        COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10:RCLK
  To:                          COREABC_0/ACCUMULATOR[31]:D
  Delay (ns):                  29.362
  Slack (ns):
  Arrival (ns):                30.055
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         29.947

Path 4
  From:                        COREABC_0/genblk19.UROM.INSTR_SCMD[1]:CLK
  To:                          COREABC_0/ABCIl01:D
  Delay (ns):                  29.498
  Slack (ns):
  Arrival (ns):                29.996
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         29.895

Path 5
  From:                        COREABC_0/genblk19.UROM.INSTR_CMD[1]:CLK
  To:                          COREABC_0/ABCIl01:D
  Delay (ns):                  29.479
  Slack (ns):
  Arrival (ns):                29.977
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         29.876


Expanded Path 1
  From: COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10:RCLK
  To: COREABC_0/ABCIl01:D
  data required time                             N/C
  data arrival time                          -   30.779
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.693          net: FAB_CLK
  0.693                        COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10:RCLK (r)
               +     2.159          cell: ADLIB:RAM512X18
  2.852                        COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10:RD1 (f)
               +     1.467          net: COREABC_0/ABCIl11[1]
  4.319                        COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10_RNI2NEA:A (f)
               +     0.625          cell: ADLIB:XA1B
  4.944                        COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10_RNI2NEA:Y (f)
               +     0.250          net: COREABC_0/ABCll10_RNI2NEA
  5.194                        COREABC_0/genblk19.UROM.INSTR_ADDR_RNIVJ921[2]:S (f)
               +     0.364          cell: ADLIB:MX2
  5.558                        COREABC_0/genblk19.UROM.INSTR_ADDR_RNIVJ921[2]:Y (r)
               +     0.318          net: COREABC_0/ABClIOOI[1]
  5.876                        COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I1_CO1_m7_i_a4_0:C (r)
               +     0.505          cell: ADLIB:OR3C
  6.381                        COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I1_CO1_m7_i_a4_0:Y (f)
               +     0.267          net: COREABC_0/ADD_32x32_slow_I1_CO1_N_14
  6.648                        COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I1_CO1_m7_i:B (f)
               +     0.486          cell: ADLIB:OR3C
  7.134                        COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I1_CO1_m7_i:Y (r)
               +     0.300          net: COREABC_0/N384
  7.434                        COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I2_un1_CO1_m4_i:B (r)
               +     0.708          cell: ADLIB:MAJ3
  8.142                        COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I2_un1_CO1_m4_i:Y (r)
               +     0.798          net: COREABC_0/ADD_32x32_slow_I2_un1_CO1_m4_i
  8.940                        COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I5_CO1_m1:A (r)
               +     0.261          cell: ADLIB:XOR2
  9.201                        COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I5_CO1_m1:Y (r)
               +     0.279          net: COREABC_0/ADD_32x32_slow_I5_CO1_N_2_i_0
  9.480                        COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I5_CO1_m7:C (r)
               +     0.505          cell: ADLIB:OR3C
  9.985                        COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I5_CO1_m7:Y (f)
               +     0.309          net: COREABC_0/ADD_32x32_slow_I5_CO1_m7
  10.294                       COREABC_0/ACCUMULATOR_RNINMPIB[7]:C (f)
               +     0.550          cell: ADLIB:XA1A
  10.844                       COREABC_0/ACCUMULATOR_RNINMPIB[7]:Y (f)
               +     0.262          net: COREABC_0/ACCUMULATOR_RNINMPIB[7]
  11.106                       COREABC_0/ACCUMULATOR_RNI4VV6O[7]:S (f)
               +     0.394          cell: ADLIB:MX2
  11.500                       COREABC_0/ACCUMULATOR_RNI4VV6O[7]:Y (f)
               +     0.271          net: COREABC_0/d_N_4_5
  11.771                       COREABC_0/ACCUMULATOR_RNIO1H2Q[8]:B (f)
               +     0.434          cell: ADLIB:MX2
  12.205                       COREABC_0/ACCUMULATOR_RNIO1H2Q[8]:Y (f)
               +     0.271          net: COREABC_0/ACCUMULATOR_RNIO1H2Q[8]
  12.476                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I8_un1_CO1_1:A (f)
               +     0.439          cell: ADLIB:MX2B
  12.915                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I8_un1_CO1_1:Y (f)
               +     0.934          net: COREABC_0/ADD_32x32_slow_I8_un1_CO1_1
  13.849                       COREABC_0/ACCUMULATOR_RNIR29OL1[10]:B (f)
               +     0.555          cell: ADLIB:MIN3
  14.404                       COREABC_0/ACCUMULATOR_RNIR29OL1[10]:Y (r)
               +     0.257          net: COREABC_0/d_N_4_3
  14.661                       COREABC_0/ACCUMULATOR_RNIHOUEN1[11]:C (r)
               +     0.398          cell: ADLIB:AO13
  15.059                       COREABC_0/ACCUMULATOR_RNIHOUEN1[11]:Y (f)
               +     0.255          net: COREABC_0/ACCUMULATOR_RNIHOUEN1[11]
  15.314                       COREABC_0/ACCUMULATOR_RNI1OSKG3[11]:A (f)
               +     0.469          cell: ADLIB:MX2A
  15.783                       COREABC_0/ACCUMULATOR_RNI1OSKG3[11]:Y (r)
               +     0.680          net: COREABC_0/ACCUMULATOR_RNI1OSKG3[11]
  16.463                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I18_un1_CO1_1:B (r)
               +     0.514          cell: ADLIB:MX2C
  16.977                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I18_un1_CO1_1:Y (f)
               +     0.745          net: COREABC_0/ADD_32x32_slow_I18_un1_CO1_1
  17.722                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I19_CO1:A (f)
               +     0.372          cell: ADLIB:MAJ3
  18.094                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I19_CO1:Y (f)
               +     0.292          net: COREABC_0/N420
  18.386                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I20_un1_CO1:C (f)
               +     0.422          cell: ADLIB:AO18
  18.808                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I20_un1_CO1:Y (r)
               +     0.292          net: COREABC_0/I20_un1_CO1_i
  19.100                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I21_CO1:C (r)
               +     0.453          cell: ADLIB:AO18
  19.553                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I21_CO1:Y (f)
               +     0.364          net: COREABC_0/N424
  19.917                       COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl1I1.ABCOOl1/ABCll10_RNIQBO399:A (f)
               +     0.746          cell: ADLIB:OA1A
  20.663                       COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl1I1.ABCOOl1/ABCll10_RNIQBO399:Y (r)
               +     0.992          net: COREABC_0/r_N_2_i_0
  21.655                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I25_CO1_1:B (r)
               +     0.444          cell: ADLIB:MX2
  22.099                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I25_CO1_1:Y (r)
               +     0.360          net: COREABC_0/ADD_32x32_slow_I25_CO1_0
  22.459                       COREABC_0/ACCUMULATOR_RNIG5Q8P9[24]:B (r)
               +     0.344          cell: ADLIB:AO1B
  22.803                       COREABC_0/ACCUMULATOR_RNIG5Q8P9[24]:Y (r)
               +     0.247          net: COREABC_0/ACCUMULATOR_RNIG5Q8P9[24]
  23.050                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I26_un1_CO1_1:A (r)
               +     0.505          cell: ADLIB:MX2C
  23.555                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I26_un1_CO1_1:Y (f)
               +     0.938          net: COREABC_0/ADD_32x32_slow_I26_un1_CO1_1
  24.493                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I27_CO1_i:A (f)
               +     0.372          cell: ADLIB:MAJ3
  24.865                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I27_CO1_i:Y (f)
               +     0.292          net: COREABC_0/N_11
  25.157                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I28_un1_CO1_i_o3:B (f)
               +     0.555          cell: ADLIB:MAJ3
  25.712                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I28_un1_CO1_i_o3:Y (f)
               +     0.763          net: COREABC_0/N_12
  26.475                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I29_CO1_i_o3:A (f)
               +     0.805          cell: ADLIB:AO13
  27.280                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I29_CO1_i_o3:Y (f)
               +     0.308          net: COREABC_0/N_13
  27.588                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I30_un1_CO1_i:C (f)
               +     0.489          cell: ADLIB:MIN3
  28.077                       COREABC_0/un1_ACCUMULATOR_ADD_32x32_slow_I30_un1_CO1_i:Y (r)
               +     0.247          net: COREABC_0/N_9
  28.324                       COREABC_0/genblk19.UROM.INSTR_SCMD_RNI4EHA6T[0]:A (r)
               +     0.543          cell: ADLIB:XAI1
  28.867                       COREABC_0/genblk19.UROM.INSTR_SCMD_RNI4EHA6T[0]:Y (r)
               +     0.247          net: COREABC_0/un1_ACCUMULATOR_m_i[31]
  29.114                       COREABC_0/ACCUMULATOR_RNI7S4KRT[31]:C (r)
               +     0.570          cell: ADLIB:OR3C
  29.684                       COREABC_0/ACCUMULATOR_RNI7S4KRT[31]:Y (f)
               +     0.367          net: COREABC_0/ABClIl1[31]
  30.051                       COREABC_0/ABCIl01_RNO:C (f)
               +     0.473          cell: ADLIB:NOR3A
  30.524                       COREABC_0/ABCIl01_RNO:Y (r)
               +     0.255          net: COREABC_0/ABCO0I_4[0]
  30.779                       COREABC_0/ABCIl01:D (r)
                                    
  30.779                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.510          net: FAB_CLK
  N/C                          COREABC_0/ABCIl01:CLK (r)
               -     0.409          Library setup time: ADLIB:DFN1E1C0
  N/C                          COREABC_0/ABCIl01:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        COREABC_0/ABCOIOOI:CLK
  To:                          COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10:RESET
  Delay (ns):                  3.643
  Slack (ns):
  Arrival (ns):                4.140
  Required (ns):
  Recovery (ns):               1.483
  Minimum Period (ns):         4.930
  Skew (ns):                   -0.196

Path 2
  From:                        COREABC_0/ABCOIOOI:CLK
  To:                          COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl1I1.ABCOOl1/ABCll10:RESET
  Delay (ns):                  3.642
  Slack (ns):
  Arrival (ns):                4.139
  Required (ns):
  Recovery (ns):               1.483
  Minimum Period (ns):         4.929
  Skew (ns):                   -0.196

Path 3
  From:                        COREABC_0/ABCOIOOI:CLK
  To:                          COREABC_0/STKPTR[1]:PRE
  Delay (ns):                  3.509
  Slack (ns):
  Arrival (ns):                4.006
  Required (ns):
  Recovery (ns):               0.225
  Minimum Period (ns):         3.737
  Skew (ns):                   0.003

Path 4
  From:                        COREABC_0/ABCOIOOI:CLK
  To:                          COREABC_0/ABCII01:PRE
  Delay (ns):                  3.436
  Slack (ns):
  Arrival (ns):                3.933
  Required (ns):
  Recovery (ns):               0.225
  Minimum Period (ns):         3.661
  Skew (ns):                   0.000

Path 5
  From:                        COREABC_0/ABCOIOOI:CLK
  To:                          COREABC_0/STKPTR[2]:PRE
  Delay (ns):                  3.417
  Slack (ns):
  Arrival (ns):                3.914
  Required (ns):
  Recovery (ns):               0.225
  Minimum Period (ns):         3.660
  Skew (ns):                   0.018


Expanded Path 1
  From: COREABC_0/ABCOIOOI:CLK
  To: COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10:RESET
  data required time                             N/C
  data arrival time                          -   4.140
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.497          net: FAB_CLK
  0.497                        COREABC_0/ABCOIOOI:CLK (r)
               +     0.440          cell: ADLIB:DFN1C0
  0.937                        COREABC_0/ABCOIOOI:Q (r)
               +     1.912          net: COREABC_0/ABCOIOOI
  2.849                        COREABC_0/ABCOIOOI_RNINBN1/U_CLKSRC:A (r)
               +     0.583          cell: ADLIB:CLKSRC
  3.432                        COREABC_0/ABCOIOOI_RNINBN1/U_CLKSRC:Y (r)
               +     0.708          net: COREABC_0_PRESETN
  4.140                        COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10:RESET (r)
                                    
  4.140                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.693          net: FAB_CLK
  N/C                          COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10:RCLK (r)
               -     1.483          Library recovery time: ADLIB:RAM512X18
  N/C                          COREABC_0/genblk15.ABCIO0I.ABCOO0I/genblk4.ABCI0I1.ABCl0I1/ABCll10:RESET


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MSS_Waveform_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

