#Build: Synplify Pro D-2009.12A, Build 040R, Jan 20 2010 #install: D:\Actel\Libero_v9.0\Synopsys\synplify_D200912A #OS: Windows XP 5.1 #Hostname: WXPL-ODIGAS #Implementation: synthesis #Tue Aug 31 18:54:32 2010 $ Start of Compile #Tue Aug 31 18:54:32 2010 Synopsys VHDL Compiler, version comp475rc, Build 060R, built Jan 15 2010 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved @N:CD720 : std.vhd(123) | Setting time resolution to ns Top entity isn't set yet! @W:CD645 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.vhd(5) | Ignoring undefined library smartfusion @W:CD643 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.vhd(6) | Ignoring use clause - smartfusion not found ... @W:CD645 : MSS_Waveform.vhd(5) | Ignoring undefined library smartfusion @W:CD643 : MSS_Waveform.vhd(6) | Ignoring use clause - smartfusion not found ... @W:CD645 : Top_Waveform.vhd(5) | Ignoring undefined library smartfusion @W:CD643 : Top_Waveform.vhd(6) | Ignoring use clause - smartfusion not found ... VHDL syntax check successful! File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\VHDL\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vhdl\core_obfuscated\ram256x16_pa3.vhd changed - recompiling File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\VHDL\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vhdl\core_obfuscated\ram256x8_rtl.vhd changed - recompiling File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\VHDL\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vhdl\core_obfuscated\support.vhd changed - recompiling File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\VHDL\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vhdl\core_obfuscated\iram512x9_pa3.vhd changed - recompiling File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\VHDL\Waveform_Gen\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3_muxptob3.vhd changed - recompiling File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\VHDL\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vhdl\core_obfuscated\ramblocks.vhd changed - recompiling File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\VHDL\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vhdl\core_obfuscated\acmtable.vhd changed - recompiling File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\VHDL\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vhdl\core_obfuscated\instructions.vhd changed - recompiling File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\VHDL\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vhdl\core_obfuscated\instructram.vhd changed - recompiling File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\VHDL\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vhdl\core_obfuscated\instructnvm_bb.vhd changed - recompiling File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\VHDL\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vhdl\core_obfuscated\debugblk.vhd changed - recompiling File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\VHDL\Waveform_Gen\component\work\Top_Waveform\COREABC_0\rtl\vhdl\core_obfuscated\coreabc.vhd changed - recompiling File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\VHDL\Waveform_Gen\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vhdl\core_obfuscated\coreapb3.vhd changed - recompiling File D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\VHDL\Waveform_Gen\component\work\Top_Waveform\Top_Waveform.vhd changed - recompiling @N:CD630 : Top_Waveform.vhd(12) | Synthesizing work.top_waveform.def_arch @W:CD280 : Top_Waveform.vhd(121) | Unbound component VCC mapped to black box @W:CD280 : Top_Waveform.vhd(144) | Unbound component GND mapped to black box @N:CD630 : coreabc.vhd(14) | Synthesizing coreabc_lib.top_waveform_coreabc_0_coreabc.rtl @N:CD233 : coreabc.vhd(216) | Using sequential encoding for type abcili1 @W:CD434 : coreabc.vhd(301) | Signal abcl0i1 in the sensitivity list is not used in the process @W:CD434 : coreabc.vhd(537) | Signal accumulator in the sensitivity list is not used in the process @W:CD434 : coreabc.vhd(537) | Signal abci1i1 in the sensitivity list is not used in the process @W:CD604 : coreabc.vhd(599) | OTHERS clause is not synthesized @W:CD434 : coreabc.vhd(556) | Signal instr_data in the sensitivity list is not used in the process @W:CD434 : coreabc.vhd(556) | Signal abciio1 in the sensitivity list is not used in the process @W:CD434 : coreabc.vhd(647) | Signal io_in in the sensitivity list is not used in the process @W:CD434 : coreabc.vhd(693) | Signal abco0o1 in the sensitivity list is not used in the process @W:CD434 : coreabc.vhd(693) | Signal acmdata in the sensitivity list is not used in the process @W:CD434 : coreabc.vhd(708) | Signal abcooo1 in the sensitivity list is not used in the process @W:CD434 : coreabc.vhd(708) | Signal accumulator in the sensitivity list is not used in the process @W:CD434 : coreabc.vhd(708) | Signal instr_data in the sensitivity list is not used in the process @W:CD604 : coreabc.vhd(890) | OTHERS clause is not synthesized @W:CG296 : coreabc.vhd(956) | Incomplete sensitivity list - assuming completeness @W:CG290 : coreabc.vhd(961) | Referenced variable abcoo01 is not in sensitivity list @W:CD638 : coreabc.vhd(206) | Signal debug1 is undriven @W:CD638 : coreabc.vhd(208) | Signal debug2 is undriven @N:CD630 : instructions.vhd(31) | Synthesizing coreabc_lib.top_waveform_coreabc_0_instructions.rtl Post processing for coreabc_lib.top_waveform_coreabc_0_instructions.rtl @N:CD630 : ramblocks.vhd(14) | Synthesizing coreabc_lib.top_waveform_coreabc_0_ramblocks.rtl @N:CD630 : ram256x16_pa3.vhd(11) | Synthesizing coreabc_lib.top_waveform_coreabc_0_ram256x16.rtl @N:CD630 : proasic3.vhd(2967) | Synthesizing proasic3.ram512x18.syn_black_box Post processing for proasic3.ram512x18.syn_black_box @N:CD630 : proasic3.vhd(1929) | Synthesizing proasic3.inv.syn_black_box Post processing for proasic3.inv.syn_black_box @N:CD630 : Top_Waveform.vhd(144) | Synthesizing work.gnd.syn_black_box Post processing for work.gnd.syn_black_box @N:CD630 : Top_Waveform.vhd(121) | Synthesizing work.vcc.syn_black_box Post processing for work.vcc.syn_black_box Post processing for coreabc_lib.top_waveform_coreabc_0_ram256x16.rtl Post processing for coreabc_lib.top_waveform_coreabc_0_ramblocks.rtl Post processing for coreabc_lib.top_waveform_coreabc_0_coreabc.rtl @W:CL252 : coreabc.vhd(140) | Bit 0 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 1 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 2 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 3 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 4 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 5 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 6 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 7 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 8 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 9 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 10 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 11 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 12 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 13 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 14 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 15 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 16 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 17 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 18 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 19 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 20 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 21 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 22 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 23 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 24 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 25 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 26 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 27 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 28 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 29 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 30 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL252 : coreabc.vhd(140) | Bit 31 of signal ABCiio1 is floating - a simulation mismatch is possible @W:CL169 : coreabc.vhd(766) | Pruning Register ABColi1 @W:CL111 : coreabc.vhd(766) | All reachable assignments to zregISTER(8) assign '0', register removed by optimization @W:CL111 : coreabc.vhd(766) | All reachable assignments to sTKPTR(4) assign '1', register removed by optimization @W:CL111 : coreabc.vhd(766) | All reachable assignments to sTKPTR(5) assign '1', register removed by optimization @W:CL111 : coreabc.vhd(766) | All reachable assignments to sTKPTR(6) assign '1', register removed by optimization @W:CL111 : coreabc.vhd(766) | All reachable assignments to sTKPTR(7) assign '1', register removed by optimization @W:CL111 : coreabc.vhd(766) | All reachable assignments to isr assign '0', register removed by optimization @W:CL111 : coreabc.vhd(766) | All reachable assignments to ABCill1 assign '0', register removed by optimization @W:CL111 : coreabc.vhd(616) | All reachable assignments to ABCoLL1 assign '0', register removed by optimization @W:CL111 : coreabc.vhd(616) | All reachable assignments to ABCiol1 assign '0', register removed by optimization @W:CL189 : coreabc.vhd(387) | Register bit Instr_SLOT(2) is always 0, optimizing ... @W:CL260 : coreabc.vhd(387) | Pruning Register bit 2 of Instr_SLOT(2 downto 0) @N:CD630 : MSS_Waveform.vhd(8) | Synthesizing work.mss_waveform.def_arch @W:CD280 : MSS_Waveform.vhd(38) | Unbound component OUTBUF_A mapped to black box @W:CD280 : MSS_Waveform.vhd(308) | Unbound component INBUF_A mapped to black box @N:CD630 : MSS_Waveform.vhd(308) | Synthesizing work.inbuf_a.syn_black_box Post processing for work.inbuf_a.syn_black_box @N:CD630 : mss_comps.vhd(422) | Synthesizing work.mss_apb.def_arch Post processing for work.mss_apb.def_arch @N:CD630 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.vhd(8) | Synthesizing work.mss_waveform_tmp_mss_ccc_0_mss_ccc.def_arch @N:CD630 : mss_comps.vhd(907) | Synthesizing work.mss_xtlosc.def_arch Post processing for work.mss_xtlosc.def_arch @N:CD630 : mss_comps.vhd(947) | Synthesizing work.mss_ccc.def_arch Post processing for work.mss_ccc.def_arch Post processing for work.mss_waveform_tmp_mss_ccc_0_mss_ccc.def_arch @W:CL240 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.vhd(38) | LPXIN_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible @W:CL240 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.vhd(37) | MAINXIN_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible @W:CL240 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.vhd(36) | RCOSC_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible @N:CD630 : MSS_Waveform.vhd(38) | Synthesizing work.outbuf_a.syn_black_box Post processing for work.outbuf_a.syn_black_box @N:CD630 : mss_comps.vhd(4) | Synthesizing work.inbuf_mss.def_arch Post processing for work.inbuf_mss.def_arch Post processing for work.mss_waveform.def_arch @N:CD630 : APB_sine_LUT.vhd(9) | Synthesizing work.apb_sine_lut.apb_sine_lut_arch @N:CD630 : sine_LUT.vhd(10) | Synthesizing work.sine_lut.sine_lut_arch Post processing for work.sine_lut.sine_lut_arch Post processing for work.apb_sine_lut.apb_sine_lut_arch @N:CD630 : coreapb3.vhd(14) | Synthesizing coreapb3_lib.coreapb3.capb3i0l @W:CD604 : coreapb3.vhd(439) | OTHERS clause is not synthesized @N:CD630 : coreapb3_muxptob3.vhd(14) | Synthesizing coreapb3_lib.capb3o.capb3ll @W:CD604 : coreapb3_muxptob3.vhd(152) | OTHERS clause is not synthesized @W:CD604 : coreapb3_muxptob3.vhd(195) | OTHERS clause is not synthesized @W:CD604 : coreapb3_muxptob3.vhd(238) | OTHERS clause is not synthesized Post processing for coreapb3_lib.capb3o.capb3ll Post processing for coreapb3_lib.coreapb3.capb3i0l @W:CL111 : coreapb3.vhd(384) | All reachable assignments to CAPB3L0OL(0) assign '0', register removed by optimization @W:CL111 : coreapb3.vhd(384) | All reachable assignments to CAPB3L0OL(1) assign '0', register removed by optimization @W:CL111 : coreapb3.vhd(384) | All reachable assignments to CAPB3L0OL(2) assign '0', register removed by optimization @W:CL111 : coreapb3.vhd(384) | All reachable assignments to CAPB3L0OL(3) assign '0', register removed by optimization @W:CL111 : coreapb3.vhd(384) | All reachable assignments to CAPB3L0OL(4) assign '0', register removed by optimization @W:CL111 : coreapb3.vhd(384) | All reachable assignments to CAPB3L0OL(5) assign '0', register removed by optimization @W:CL111 : coreapb3.vhd(384) | All reachable assignments to CAPB3L0OL(6) assign '0', register removed by optimization @W:CL111 : coreapb3.vhd(384) | All reachable assignments to CAPB3L0OL(7) assign '0', register removed by optimization @W:CL111 : coreapb3.vhd(384) | All reachable assignments to CAPB3L0OL(8) assign '0', register removed by optimization @W:CL111 : coreapb3.vhd(384) | All reachable assignments to CAPB3L0OL(9) assign '0', register removed by optimization @W:CL111 : coreapb3.vhd(384) | All reachable assignments to CAPB3L0OL(10) assign '0', register removed by optimization @W:CL111 : coreapb3.vhd(384) | All reachable assignments to CAPB3L0OL(11) assign '0', register removed by optimization @W:CL111 : coreapb3.vhd(384) | All reachable assignments to CAPB3L0OL(12) assign '0', register removed by optimization @W:CL111 : coreapb3.vhd(384) | All reachable assignments to CAPB3L0OL(13) assign '0', register removed by optimization @W:CL111 : coreapb3.vhd(384) | All reachable assignments to CAPB3L0OL(14) assign '0', register removed by optimization @W:CL111 : coreapb3.vhd(384) | All reachable assignments to CAPB3L0OL(15) assign '0', register removed by optimization Post processing for work.top_waveform.def_arch @W:CL246 : coreapb3.vhd(35) | Input port bits 23 to 20 of paddr(23 downto 0) are unused @W:CL159 : coreapb3.vhd(65) | Input PRDATAS1 is unused @W:CL159 : coreapb3.vhd(67) | Input PRDATAS3 is unused @W:CL159 : coreapb3.vhd(68) | Input PRDATAS4 is unused @W:CL159 : coreapb3.vhd(69) | Input PRDATAS5 is unused @W:CL159 : coreapb3.vhd(70) | Input PRDATAS6 is unused @W:CL159 : coreapb3.vhd(71) | Input PRDATAS7 is unused @W:CL159 : coreapb3.vhd(72) | Input PRDATAS8 is unused @W:CL159 : coreapb3.vhd(73) | Input PRDATAS9 is unused @W:CL159 : coreapb3.vhd(74) | Input PRDATAS10 is unused @W:CL159 : coreapb3.vhd(75) | Input PRDATAS11 is unused @W:CL159 : coreapb3.vhd(76) | Input PRDATAS12 is unused @W:CL159 : coreapb3.vhd(77) | Input PRDATAS13 is unused @W:CL159 : coreapb3.vhd(78) | Input PRDATAS14 is unused @W:CL159 : coreapb3.vhd(79) | Input PRDATAS15 is unused @W:CL159 : coreapb3.vhd(81) | Input preadys1 is unused @W:CL159 : coreapb3.vhd(83) | Input preADYS3 is unused @W:CL159 : coreapb3.vhd(84) | Input preadys4 is unused @W:CL159 : coreapb3.vhd(85) | Input PREADYs5 is unused @W:CL159 : coreapb3.vhd(86) | Input preadyS6 is unused @W:CL159 : coreapb3.vhd(87) | Input PREadys7 is unused @W:CL159 : coreapb3.vhd(88) | Input pREADYS8 is unused @W:CL159 : coreapb3.vhd(89) | Input preADYS9 is unused @W:CL159 : coreapb3.vhd(90) | Input preadys10 is unused @W:CL159 : coreapb3.vhd(91) | Input preaDYS11 is unused @W:CL159 : coreapb3.vhd(92) | Input PREADYS12 is unused @W:CL159 : coreapb3.vhd(93) | Input PREadys13 is unused @W:CL159 : coreapb3.vhd(94) | Input preADYS14 is unused @W:CL159 : coreapb3.vhd(95) | Input PREAdys15 is unused @W:CL159 : coreapb3.vhd(97) | Input PSLVERrs1 is unused @W:CL159 : coreapb3.vhd(99) | Input pslverrS3 is unused @W:CL159 : coreapb3.vhd(100) | Input pSLVERRS4 is unused @W:CL159 : coreapb3.vhd(101) | Input PSLVERRS5 is unused @W:CL159 : coreapb3.vhd(102) | Input PSLVERRS6 is unused @W:CL159 : coreapb3.vhd(103) | Input pslvERRS7 is unused @W:CL159 : coreapb3.vhd(104) | Input pslverrs8 is unused @W:CL159 : coreapb3.vhd(105) | Input PSLVERRS9 is unused @W:CL159 : coreapb3.vhd(106) | Input PSLVERRS10 is unused @W:CL159 : coreapb3.vhd(107) | Input pslverRS11 is unused @W:CL159 : coreapb3.vhd(108) | Input PSLverrs12 is unused @W:CL159 : coreapb3.vhd(109) | Input PSLVERRS13 is unused @W:CL159 : coreapb3.vhd(110) | Input pslverrs14 is unused @W:CL159 : coreapb3.vhd(111) | Input pSLVERRS15 is unused @W:CL159 : APB_sine_LUT.vhd(13) | Input PENABLE is unused @W:CL159 : APB_sine_LUT.vhd(17) | Input PWDATA is unused @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.vhd(10) | Input CLKA is unused @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.vhd(11) | Input CLKA_PAD is unused @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.vhd(12) | Input CLKA_PADP is unused @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.vhd(13) | Input CLKA_PADN is unused @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.vhd(14) | Input CLKB is unused @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.vhd(15) | Input CLKB_PAD is unused @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.vhd(16) | Input CLKB_PADP is unused @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.vhd(17) | Input CLKB_PADN is unused @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.vhd(18) | Input CLKC is unused @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.vhd(19) | Input CLKC_PAD is unused @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.vhd(20) | Input CLKC_PADP is unused @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.vhd(21) | Input CLKC_PADN is unused @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.vhd(23) | Input LPXIN is unused @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.vhd(24) | Input MAC_CLK is unused @N:CL177 : coreabc.vhd(387) | Sharing sequential element ABCo110. @N:CL201 : coreabc.vhd(766) | Trying to extract state machine for register ABCl0i1 Extracted state machine for register ABCl0i1 State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL159 : coreabc.vhd(60) | Input PSLVERr_m is unused @W:CL159 : coreabc.vhd(63) | Input intreq is unused @W:CL159 : coreabc.vhd(65) | Input INItdatval is unused @W:CL159 : coreabc.vhd(66) | Input INITdone is unused @W:CL159 : coreabc.vhd(67) | Input INITADDR is unused @W:CL159 : coreabc.vhd(68) | Input INITDATA is unused @W:CL159 : coreabc.vhd(69) | Input Psel_s is unused @W:CL159 : coreabc.vhd(70) | Input pENABLE_s is unused @W:CL159 : coreabc.vhd(71) | Input pwritE_S is unused @W:CL159 : coreabc.vhd(72) | Input PADDR_S is unused @W:CL159 : coreabc.vhd(73) | Input PWDATA_S is unused @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Aug 31 18:54:33 2010 ###########################################################] Synopsys Actel Technology Mapper, Version map500act, Build 058R, Built Jan 18 2010 09:16:23 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved Product Version D-2009.12A @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled Automatic dissolve at startup in view:coreapb3_lib.CoreAPB3(capb3i0l) of CAPB3O1II(CAPB3o) Automatic dissolve at startup in view:work.MSS_Waveform(def_arch) of MSS_CCC_0(MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC) Automatic dissolve at startup in view:coreabc_lib.Top_Waveform_COREABC_0_raMBLOcks(rtl) of ABCl1I0\.ABCI1i0\.ABCOO00(Top_Waveform_COREABC_0_RAM256x16) Automatic dissolve at startup in view:coreabc_lib.Top_Waveform_COREABC_0_raMBLOcks(rtl) of ABCl1I0\.ABCII1(Top_Waveform_COREABC_0_RAM256x16) Automatic dissolve at startup in view:coreabc_lib.Top_Waveform_COREABC_0_cOREABc(rtl) of ABCO01\.ABCiI1(Top_Waveform_COREABC_0_raMBLOcks) Automatic dissolve at startup in view:work.Top_Waveform(def_arch) of MSS_Waveform_0(MSS_Waveform) Automatic dissolve at startup in view:work.Top_Waveform(def_arch) of CoreAPB3_0(CoreAPB3) Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 58MB) @N:MO106 : sine_lut.vhd(26) | Found ROM, 'table_value_195[7:0]', 256 words by 8 bits Encoding state machine coreabc_lib.Top_Waveform_COREABC_0_cOREABc(rtl)-ABCl0i1[0:3] original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MF176 : | Default generator successful @N:MF176 : | Default generator successful @N:MF176 : | Default generator successful @N:MF238 : coreabc.vhd(318) | Found 4 bit incrementor, 'un5_abcloi1[3:0]' @N:MF238 : coreabc.vhd(758) | Found 4 bit incrementor, 'un1_abcoli[3:0]' @W:MO129 : coreabc.vhd(387) | Sequential instance COREABC_0.INStr_addr[3] has been reduced to a combinational gate by constant propagation @W:MO129 : coreabc.vhd(387) | Sequential instance COREABC_0.INStr_addr[4] has been reduced to a combinational gate by constant propagation @W:MO129 : coreabc.vhd(387) | Sequential instance COREABC_0.INStr_addr[7] has been reduced to a combinational gate by constant propagation @W:MO129 : coreabc.vhd(387) | Sequential instance COREABC_0.INStr_addr[8] has been reduced to a combinational gate by constant propagation @W:MO129 : coreabc.vhd(387) | Sequential instance COREABC_0.INStr_addr[9] has been reduced to a combinational gate by constant propagation @W:MO129 : coreabc.vhd(387) | Sequential instance COREABC_0.INStr_addr[10] has been reduced to a combinational gate by constant propagation @W:MO129 : coreabc.vhd(387) | Sequential instance COREABC_0.INStr_addr[11] has been reduced to a combinational gate by constant propagation @W:MO129 : coreabc.vhd(387) | Sequential instance COREABC_0.INStr_addr[12] has been reduced to a combinational gate by constant propagation @W:MO129 : coreabc.vhd(387) | Sequential instance COREABC_0.INStr_addr[13] has been reduced to a combinational gate by constant propagation @W:MO129 : coreabc.vhd(387) | Sequential instance COREABC_0.INStr_addr[14] has been reduced to a combinational gate by constant propagation @W:MO129 : coreabc.vhd(387) | Sequential instance COREABC_0.INStr_addr[15] has been reduced to a combinational gate by constant propagation Finished factoring (Time elapsed 0h:00m:02s; Memory used current: 64MB peak: 65MB) @N:BN116 : coreabc.vhd(766) | Removing sequential instance COREABC_0.IO_OUT[0] of view:PrimLib.dffr(prim) because there are no references to its outputs @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.INStr_addr[2], because it is equivalent to instance COREABC_0.insTR_data[1] @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.INStr_addr[5], because it is equivalent to instance COREABC_0.INStr_addr[6] @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.insTR_data[29], because it is equivalent to instance COREABC_0.insTR_data[31] @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.insTR_data[28], because it is equivalent to instance COREABC_0.insTR_data[31] @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.insTR_data[27], because it is equivalent to instance COREABC_0.insTR_data[31] @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.insTR_data[26], because it is equivalent to instance COREABC_0.insTR_data[31] @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.insTR_data[25], because it is equivalent to instance COREABC_0.insTR_data[31] @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.insTR_data[24], because it is equivalent to instance COREABC_0.insTR_data[31] @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.insTR_data[23], because it is equivalent to instance COREABC_0.insTR_data[31] @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.insTR_data[22], because it is equivalent to instance COREABC_0.insTR_data[31] @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.insTR_data[21], because it is equivalent to instance COREABC_0.insTR_data[31] @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.insTR_data[20], because it is equivalent to instance COREABC_0.insTR_data[31] @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.insTR_data[19], because it is equivalent to instance COREABC_0.insTR_data[31] @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.insTR_data[18], because it is equivalent to instance COREABC_0.insTR_data[31] @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.insTR_data[16], because it is equivalent to instance COREABC_0.insTR_data[31] @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.insTR_data[15], because it is equivalent to instance COREABC_0.insTR_data[31] @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.insTR_data[14], because it is equivalent to instance COREABC_0.insTR_data[31] @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.insTR_data[13], because it is equivalent to instance COREABC_0.insTR_data[31] @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.insTR_data[12], because it is equivalent to instance COREABC_0.insTR_data[31] @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.insTR_data[11], because it is equivalent to instance COREABC_0.insTR_data[31] @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.insTR_data[10], because it is equivalent to instance COREABC_0.insTR_data[31] @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.insTR_data[9], because it is equivalent to instance COREABC_0.insTR_data[31] @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.insTR_data[8], because it is equivalent to instance COREABC_0.insTR_data[31] @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.insTR_data[6], because it is equivalent to instance COREABC_0.insTR_data[31] @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.insTR_data[5], because it is equivalent to instance COREABC_0.insTR_data[31] @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.insTR_data[3], because it is equivalent to instance COREABC_0.insTR_data[31] @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.insTR_data[4], because it is equivalent to instance COREABC_0.insTR_data[7] @W:BN132 : coreabc.vhd(387) | Removing sequential instance COREABC_0.insTR_data[17], because it is equivalent to instance COREABC_0.insTR_data[30] Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:02s; Memory used current: 63MB peak: 65MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:02s; Memory used current: 66MB peak: 66MB) Starting Early Timing Optimization (Time elapsed 0h:00m:02s; Memory used current: 66MB peak: 67MB) Finished Early Timing Optimization (Time elapsed 0h:00m:05s; Memory used current: 64MB peak: 67MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:05s; Memory used current: 63MB peak: 67MB) Finished preparing to map (Time elapsed 0h:00m:06s; Memory used current: 69MB peak: 70MB) High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes ------------------------------------------------------------------- COREABC_0.ABCo1i1 / Q 84 : 82 asynchronous set/reset COREABC_0.PADDR_M_1[0] / Y 47 COREABC_0.PADDR_M_1[1] / Y 45 COREABC_0.PADDR_M_1[2] / Y 56 COREABC_0.PADDR_M_1[3] / Y 42 COREABC_0.PADDR_M_1[4] / Y 28 COREABC_0.PADDR_M_1[7] / Y 62 CoreAPB3_0.CAPB3iool_i_o2[0] / Y 40 COREABC_0.insTR_data[31] / Q 51 COREABC_0.un3_abco1l1 / Y 34 COREABC_0.ABCI110_6_sqmuxa / Y 32 COREABC_0.un1_abcl1109 / Y 32 COREABC_0.ABCI110_2_sqmuxa / Y 32 COREABC_0.ABCI110_3_sqmuxa / Y 32 COREABC_0.ABCI110_5_sqmuxa / Y 32 COREABC_0.ABCI110_7_sqmuxa / Y 32 COREABC_0.abcll11_1[2] / Y 65 COREABC_0.ABCI110_1_sqmuxa / Y 32 COREABC_0.ABCO0l1_5_0_a3_1 / Y 33 COREABC_0.un1_abco1o1 / Y 32 COREABC_0.ABCl0o1_1 / Y 32 =================================================================== @N:FP130 : | Promoting Net COREABC_0_PRESETN on CLKINT I_133 @N:FP130 : | Promoting Net COREABC_0.abcll11_1[2] on CLKINT I_134 @N:FP130 : | Promoting Net \\COREABC_0_APB3master_PADDR_\[7\]\\ on CLKINT I_135 Replicating Combinational Instance COREABC_0.ABCl0o1_1, fanout 32 segments 2 Replicating Combinational Instance COREABC_0.un1_abco1o1, fanout 32 segments 2 Replicating Combinational Instance COREABC_0.ABCO0l1_5_0_a3_1, fanout 33 segments 2 Replicating Combinational Instance COREABC_0.ABCI110_1_sqmuxa, fanout 32 segments 2 Replicating Combinational Instance COREABC_0.ABCI110_7_sqmuxa, fanout 32 segments 2 Replicating Combinational Instance COREABC_0.ABCI110_5_sqmuxa, fanout 32 segments 2 Replicating Combinational Instance COREABC_0.ABCI110_3_sqmuxa, fanout 32 segments 2 Replicating Combinational Instance COREABC_0.ABCI110_2_sqmuxa, fanout 32 segments 2 Replicating Combinational Instance COREABC_0.un1_abcl1109, fanout 32 segments 2 Replicating Combinational Instance COREABC_0.ABCI110_6_sqmuxa, fanout 32 segments 2 Replicating Combinational Instance COREABC_0.un3_abco1l1, fanout 34 segments 2 Replicating Sequential Instance COREABC_0.insTR_data[31], fanout 51 segments 3 Replicating Combinational Instance CoreAPB3_0.CAPB3iool_i_o2[0], fanout 40 segments 2 Replicating Combinational Instance COREABC_0.PADDR_M_1[4], fanout 28 segments 2 Replicating Combinational Instance COREABC_0.PADDR_M_1[3], fanout 42 segments 2 Replicating Combinational Instance COREABC_0.PADDR_M_1[2], fanout 56 segments 3 Replicating Combinational Instance COREABC_0.PADDR_M_1[1], fanout 45 segments 2 Replicating Combinational Instance COREABC_0.PADDR_M_1[0], fanout 47 segments 2 Buffering MSS_Waveform_0_FAB_CLK, fanout 108 segments 5 Replicating Sequential Instance COREABC_0.instr_SCmd[2], fanout 25 segments 2 Finished technology mapping (Time elapsed 0h:00m:07s; Memory used current: 64MB peak: 73MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:07s; Memory used current: 64MB peak: 73MB) Added 4 Buffers Added 21 Cells via replication Added 3 Sequential Cells via replication Added 18 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:07s; Memory used current: 64MB peak: 73MB) Writing Analyst data base D:\DATA\PROJECTS\Waveform_Gen\Fabric_Logic_as_Master\Hardware\A2F200\VHDL\Waveform_Gen\synthesis\Top_Waveform.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:07s; Memory used current: 64MB peak: 73MB) Writing EDIF Netlist and constraint files D-2009.12A Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:07s; Memory used current: 65MB peak: 73MB) @W:MT420 : | Found inferred clock Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:MSS_Waveform_0_FAB_CLK" @W:MT246 : mss_waveform.vhd(376) | Blackbox MSS_APB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : mss_waveform_tmp_mss_ccc_0_mss_ccc.vhd(156) | Blackbox MSS_XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) ##### START OF TIMING REPORT #####[ # Timing Report written on Tue Aug 31 18:54:43 2010 # Top view: Top_Waveform Library name: smartfusion Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree ) Requested Frequency: 100.0 MHz Wire load mode: top Wire load model: smartfusion Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: -15.695 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock 100.0 MHz 38.9 MHz 10.000 25.695 -15.695 inferred Inferred_clkgroup_0 System 100.0 MHz 171.5 MHz 10.000 5.831 4.169 system default_clkgroup ==================================================================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock | 10.000 -15.695 | No paths - | No paths - | No paths - ================================================================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- COREABC_0.instR_Cmd[1] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1 Q instR_Cmd[1] 0.737 -15.695 COREABC_0.instR_Cmd[0] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1 Q instR_Cmd[0] 0.737 -15.367 COREABC_0.instr_SCmd[1] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1 Q instr_SCmd[1] 0.737 -15.106 COREABC_0.instr_SCmd_0[2] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1 Q instr_SCmd_0[2] 0.737 -15.040 COREABC_0.instR_Cmd[2] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1 Q instR_Cmd[2] 0.737 -14.393 COREABC_0.instr_SCmd[2] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1 Q instr_SCmd[2] 0.737 -11.899 COREABC_0.ABCO01\.ABCiI1.ABCl1I0\.ABCII1.ABCL0l0 Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock RAM512X18 RD7 ABCOoi1[7] 2.963 -11.682 COREABC_0.ABCO01\.ABCiI1.ABCl1I0\.ABCI1i0\.ABCOO00.ABCL0l0 Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock RAM512X18 RD2 ABCOoi1[18] 2.963 -11.529 COREABC_0.ABCO01\.ABCiI1.ABCl1I0\.ABCII1.ABCL0l0 Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock RAM512X18 RD1 ABCOoi1[1] 2.963 -11.470 COREABC_0.ABCO01\.ABCiI1.ABCl1I0\.ABCI1i0\.ABCOO00.ABCL0l0 Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock RAM512X18 RD4 ABCOoi1[20] 2.963 -11.468 ========================================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- COREABC_0.ABCool1 Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1E1C0 D abcool1 9.461 -15.695 COREABC_0.ABClol1 Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1E1C0 D ABCL110[31] 9.461 -13.657 COREABC_0.accumULATOr[31] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1E1C0 D ABCL110[31] 9.461 -13.657 COREABC_0.accumULATOr[16] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1E1C0 D ABCL110[16] 9.496 -12.301 COREABC_0.accumULATOr[24] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1E1C0 D ABCL110[24] 9.461 -12.275 COREABC_0.accumULATOr[28] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1E1C0 D ABCL110[28] 9.461 -12.068 COREABC_0.accumULATOr[20] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1E1C0 D ABCL110[20] 9.461 -11.816 COREABC_0.accumULATOr[18] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1E1C0 D ABCL110[18] 9.496 -11.747 COREABC_0.accumULATOr[29] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1E1C0 D ABCL110[29] 9.461 -11.554 COREABC_0.accumULATOr[15] Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock DFN1E1C0 D ABCL110[15] 9.461 -11.437 ======================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 25.157 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -15.695 Number of logic level(s): 17 Starting point: COREABC_0.instR_Cmd[1] / Q Ending point: COREABC_0.ABCool1 / D The start point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------- COREABC_0.instR_Cmd[1] DFN1 Q Out 0.737 0.737 - instR_Cmd[1] Net - - 2.218 - 17 COREABC_0.instR_Cmd_RNIFL27[0] OR2B A In - 2.955 - COREABC_0.instR_Cmd_RNIFL27[0] OR2B Y Out 0.514 3.469 - N_362 Net - - 1.279 - 5 COREABC_0.instR_Cmd_RNIG4CJ_0[2] OR2A B In - 4.748 - COREABC_0.instR_Cmd_RNIG4CJ_0[2] OR2A Y Out 0.514 5.263 - un3_abco1l1_0_0 Net - - 2.218 - 17 COREABC_0.ABCO01\.ABCiI1.ABCl1I0\.ABCII1.ABCL0l0_RNIGS7O MX2 S In - 7.480 - COREABC_0.ABCO01\.ABCiI1.ABCl1I0\.ABCII1.ABCL0l0_RNIGS7O MX2 Y Out 0.396 7.877 - ABCi1i1[7] Net - - 1.279 - 5 COREABC_0.ABCO01\.ABCiI1.ABCl1I0\.ABCII1.ABCL0l0_RNIUH181 NOR2B B In - 9.156 - COREABC_0.ABCO01\.ABCiI1.ABCl1I0\.ABCII1.ABCL0l0_RNIUH181 NOR2B Y Out 0.627 9.783 - un3[24] Net - - 1.184 - 4 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I7_P0N OR2 A In - 10.967 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I7_P0N OR2 Y Out 0.507 11.474 - N402 Net - - 0.806 - 3 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I135_Y_0 OA1 C In - 12.281 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I135_Y_0 OA1 Y Out 0.666 12.946 - ADD_32x32_fast_I135_Y_0 Net - - 0.322 - 1 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I135_Y NOR2B A In - 13.268 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I135_Y NOR2B Y Out 0.514 13.782 - N581 Net - - 1.184 - 4 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I192_Y AO1 B In - 14.966 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I192_Y AO1 Y Out 0.598 15.563 - N644 Net - - 0.386 - 2 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I230_un1_Y NOR3C C In - 15.949 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I230_un1_Y NOR3C Y Out 0.641 16.590 - I230_un1_Y Net - - 0.322 - 1 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I263_Y OR3 C In - 16.912 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I263_Y OR3 Y Out 0.751 17.663 - N764 Net - - 0.386 - 2 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I298_Y_0 XNOR3 C In - 18.049 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I298_Y_0 XNOR3 Y Out 0.985 19.034 - un1_accumULATOr[18] Net - - 0.322 - 1 COREABC_0.instr_SCmd_RNIG5R713[1] OR2B A In - 19.355 - COREABC_0.instr_SCmd_RNIG5R713[1] OR2B Y Out 0.514 19.870 - un1_accumULATOr_m_i[18] Net - - 0.322 - 1 COREABC_0.accumULATOr_RNIVRDOM3[17] OR3C C In - 20.191 - COREABC_0.accumULATOr_RNIVRDOM3[17] OR3C Y Out 0.666 20.857 - ABCL110[18] Net - - 0.386 - 2 COREABC_0.ABCool1_RNO_9 NOR3A C In - 21.243 - COREABC_0.ABCool1_RNO_9 NOR3A Y Out 0.716 21.959 - abcool1_18 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_5 NOR3B B In - 22.280 - COREABC_0.ABCool1_RNO_5 NOR3B Y Out 0.624 22.904 - abcool1_23 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_1 NOR3A A In - 23.226 - COREABC_0.ABCool1_RNO_1 NOR3A Y Out 0.664 23.890 - abcool1_28 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO NOR3B B In - 24.211 - COREABC_0.ABCool1_RNO NOR3B Y Out 0.624 24.835 - abcool1 Net - - 0.322 - 1 COREABC_0.ABCool1 DFN1E1C0 D In - 25.157 - ========================================================================================================================== Total path delay (propagation time + setup) of 25.695 is 11.798(45.9%) logic and 13.897(54.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 25.004 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -15.542 Number of logic level(s): 17 Starting point: COREABC_0.instR_Cmd[1] / Q Ending point: COREABC_0.ABCool1 / D The start point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------ COREABC_0.instR_Cmd[1] DFN1 Q Out 0.737 0.737 - instR_Cmd[1] Net - - 2.218 - 17 COREABC_0.instR_Cmd_RNIFL27[0] OR2B A In - 2.955 - COREABC_0.instR_Cmd_RNIFL27[0] OR2B Y Out 0.514 3.469 - N_362 Net - - 1.279 - 5 COREABC_0.instR_Cmd_RNIG4CJ[2] OR2A B In - 4.748 - COREABC_0.instR_Cmd_RNIG4CJ[2] OR2A Y Out 0.514 5.263 - un3_abco1l1 Net - - 2.218 - 17 COREABC_0.ABCO01\.ABCiI1.ABCl1I0\.ABCI1i0\.ABCOO00.ABCL0l0_RNIRVMQ_0 MX2 S In - 7.480 - COREABC_0.ABCO01\.ABCiI1.ABCl1I0\.ABCI1i0\.ABCOO00.ABCL0l0_RNIRVMQ_0 MX2 Y Out 0.396 7.877 - ABCi1i1[18] Net - - 1.279 - 5 COREABC_0.ABCO01\.ABCiI1.ABCl1I0\.ABCI1i0\.ABCOO00.ABCL0l0_RNI9LGA1 OR2B B In - 9.156 - COREABC_0.ABCO01\.ABCiI1.ABCl1I0\.ABCI1i0\.ABCOO00.ABCL0l0_RNI9LGA1 OR2B Y Out 0.627 9.783 - un3[13] Net - - 1.279 - 5 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I18_P0N OR2A A In - 11.062 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I18_P0N OR2A Y Out 0.537 11.599 - N435 Net - - 0.322 - 1 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I57_Y AND2 B In - 11.921 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I57_Y AND2 Y Out 0.627 12.548 - N500 Net - - 0.806 - 3 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I113_Y NOR2B A In - 13.355 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I113_Y NOR2B Y Out 0.514 13.869 - N559 Net - - 0.806 - 3 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I171_Y NOR2B B In - 14.675 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I171_Y NOR2B Y Out 0.627 15.303 - N623 Net - - 0.806 - 3 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I260_un1_Y_0 NOR2B B In - 16.109 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I260_un1_Y_0 NOR2B Y Out 0.627 16.737 - ADD_32x32_fast_I260_un1_Y_0 Net - - 0.322 - 1 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I260_un1_Y NOR2B A In - 17.058 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I260_un1_Y NOR2B Y Out 0.514 17.573 - I260_un1_Y Net - - 0.322 - 1 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I301_Y_0 AX1D A In - 17.894 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I301_Y_0 AX1D Y Out 1.001 18.895 - un1_accumULATOr[21] Net - - 0.322 - 1 COREABC_0.instr_SCmd_RNIT1SRT3[1] AO1B A In - 19.217 - COREABC_0.instr_SCmd_RNIT1SRT3[1] AO1B Y Out 0.502 19.719 - ABCL110[21] Net - - 0.386 - 2 COREABC_0.ABCool1_RNO_12 NOR3A C In - 20.105 - COREABC_0.ABCool1_RNO_12 NOR3A Y Out 0.716 20.820 - abcool1_12 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_9 NOR3A A In - 21.142 - COREABC_0.ABCool1_RNO_9 NOR3A Y Out 0.664 21.806 - abcool1_18 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_5 NOR3B B In - 22.127 - COREABC_0.ABCool1_RNO_5 NOR3B Y Out 0.624 22.751 - abcool1_23 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_1 NOR3A A In - 23.073 - COREABC_0.ABCool1_RNO_1 NOR3A Y Out 0.664 23.737 - abcool1_28 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO NOR3B B In - 24.058 - COREABC_0.ABCool1_RNO NOR3B Y Out 0.624 24.682 - abcool1 Net - - 0.322 - 1 COREABC_0.ABCool1 DFN1E1C0 D In - 25.004 - ==================================================================================================================================== Total path delay (propagation time + setup) of 25.542 is 11.571(45.3%) logic and 13.972(54.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 0.504 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.496 - Propagation time: 25.009 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -15.513 Number of logic level(s): 16 Starting point: COREABC_0.instR_Cmd[1] / Q Ending point: COREABC_0.ABCool1 / D The start point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------- COREABC_0.instR_Cmd[1] DFN1 Q Out 0.737 0.737 - instR_Cmd[1] Net - - 2.218 - 17 COREABC_0.instR_Cmd_RNIFL27[0] OR2B A In - 2.955 - COREABC_0.instR_Cmd_RNIFL27[0] OR2B Y Out 0.514 3.469 - N_362 Net - - 1.279 - 5 COREABC_0.instR_Cmd_RNIG4CJ_0[2] OR2A B In - 4.748 - COREABC_0.instR_Cmd_RNIG4CJ_0[2] OR2A Y Out 0.514 5.263 - un3_abco1l1_0_0 Net - - 2.218 - 17 COREABC_0.ABCO01\.ABCiI1.ABCl1I0\.ABCII1.ABCL0l0_RNIAS7O MX2 S In - 7.480 - COREABC_0.ABCO01\.ABCiI1.ABCl1I0\.ABCII1.ABCL0l0_RNIAS7O MX2 Y Out 0.480 7.960 - ABCi1i1[1] Net - - 1.279 - 5 COREABC_0.ABCO01\.ABCiI1.ABCl1I0\.ABCII1.ABCL0l0_RNIOH181 OR2B B In - 9.239 - COREABC_0.ABCO01\.ABCiI1.ABCl1I0\.ABCII1.ABCL0l0_RNIOH181 OR2B Y Out 0.516 9.755 - un3[30] Net - - 1.184 - 4 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I88_un1_Y_0_0 OR2A B In - 10.939 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I88_un1_Y_0_0 OR2A Y Out 0.646 11.585 - ADD_32x32_fast_I88_un1_Y_0_0 Net - - 0.322 - 1 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I88_Y AO13 C In - 11.907 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I88_Y AO13 Y Out 0.407 12.313 - N531 Net - - 0.386 - 2 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I147_Y AO1 C In - 12.699 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I147_Y AO1 Y Out 0.655 13.354 - N594 Net - - 1.184 - 4 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I197_un1_Y OR2B A In - 14.538 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I197_un1_Y OR2B Y Out 0.488 15.026 - I197_un1_Y Net - - 1.184 - 4 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I235_un1_Y OA1A A In - 16.210 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I235_un1_Y OA1A Y Out 0.933 17.143 - I235_un1_Y Net - - 0.322 - 1 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I235_Y OR2 B In - 17.465 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I235_Y OR2 Y Out 0.514 17.979 - N771 Net - - 0.806 - 3 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I250_un1_Y OR3C C In - 18.785 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I250_un1_Y OR3C Y Out 0.666 19.451 - I250_un1_Y Net - - 0.322 - 1 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I250_Y OR3C C In - 19.773 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I250_Y OR3C Y Out 0.641 20.414 - N738 Net - - 0.322 - 1 COREABC_0.instr_SCmd_RNI163GM4[1] XAI1A A In - 20.735 - COREABC_0.instr_SCmd_RNI163GM4[1] XAI1A Y Out 0.627 21.363 - un1_accumULATOr_m_i[31] Net - - 0.322 - 1 COREABC_0.accumULATOr_RNIPIA8C5[30] OR2B B In - 21.684 - COREABC_0.accumULATOr_RNIPIA8C5[30] OR2B Y Out 0.627 22.312 - ABCL110[31] Net - - 0.806 - 3 COREABC_0.ABCool1_RNO_1 NOR3A C In - 23.118 - COREABC_0.ABCool1_RNO_1 NOR3A Y Out 0.641 23.759 - abcool1_28 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO NOR3B B In - 24.081 - COREABC_0.ABCool1_RNO NOR3B Y Out 0.607 24.687 - abcool1 Net - - 0.322 - 1 COREABC_0.ABCool1 DFN1E1C0 D In - 25.009 - ========================================================================================================================== Total path delay (propagation time + setup) of 25.513 is 10.719(42.0%) logic and 14.794(58.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 24.943 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -15.481 Number of logic level(s): 17 Starting point: COREABC_0.instR_Cmd[1] / Q Ending point: COREABC_0.ABCool1 / D The start point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------- COREABC_0.instR_Cmd[1] DFN1 Q Out 0.737 0.737 - instR_Cmd[1] Net - - 2.218 - 17 COREABC_0.instR_Cmd_RNIFL27[0] OR2B A In - 2.955 - COREABC_0.instR_Cmd_RNIFL27[0] OR2B Y Out 0.514 3.469 - N_362 Net - - 1.279 - 5 COREABC_0.instR_Cmd_RNIG4CJ[2] OR2A B In - 4.748 - COREABC_0.instR_Cmd_RNIG4CJ[2] OR2A Y Out 0.514 5.263 - un3_abco1l1 Net - - 2.218 - 17 COREABC_0.ABCO01\.ABCiI1.ABCl1I0\.ABCI1i0\.ABCOO00.ABCL0l0_RNIRVMQ_2 MX2 S In - 7.480 - COREABC_0.ABCO01\.ABCiI1.ABCl1I0\.ABCI1i0\.ABCOO00.ABCL0l0_RNIRVMQ_2 MX2 Y Out 0.396 7.877 - ABCi1i1[20] Net - - 1.279 - 5 COREABC_0.ABCO01\.ABCiI1.ABCl1I0\.ABCI1i0\.ABCOO00.ABCL0l0_RNI9LGA1_0 NOR2B B In - 9.156 - COREABC_0.ABCO01\.ABCiI1.ABCl1I0\.ABCI1i0\.ABCOO00.ABCL0l0_RNI9LGA1_0 NOR2B Y Out 0.627 9.783 - un3[11] Net - - 1.184 - 4 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I20_P0N OR2 A In - 10.967 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I20_P0N OR2 Y Out 0.507 11.474 - N441 Net - - 0.386 - 2 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I53_Y NOR2B A In - 11.860 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I53_Y NOR2B Y Out 0.514 12.374 - N496 Net - - 0.806 - 3 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I113_Y NOR2B B In - 13.181 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I113_Y NOR2B Y Out 0.627 13.808 - N559 Net - - 0.806 - 3 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I171_Y NOR2B B In - 14.615 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I171_Y NOR2B Y Out 0.627 15.242 - N623 Net - - 0.806 - 3 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I260_un1_Y_0 NOR2B B In - 16.048 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I260_un1_Y_0 NOR2B Y Out 0.627 16.676 - ADD_32x32_fast_I260_un1_Y_0 Net - - 0.322 - 1 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I260_un1_Y NOR2B A In - 16.997 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I260_un1_Y NOR2B Y Out 0.514 17.512 - I260_un1_Y Net - - 0.322 - 1 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I301_Y_0 AX1D A In - 17.833 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I301_Y_0 AX1D Y Out 1.001 18.834 - un1_accumULATOr[21] Net - - 0.322 - 1 COREABC_0.instr_SCmd_RNIT1SRT3[1] AO1B A In - 19.156 - COREABC_0.instr_SCmd_RNIT1SRT3[1] AO1B Y Out 0.502 19.658 - ABCL110[21] Net - - 0.386 - 2 COREABC_0.ABCool1_RNO_12 NOR3A C In - 20.044 - COREABC_0.ABCool1_RNO_12 NOR3A Y Out 0.716 20.760 - abcool1_12 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_9 NOR3A A In - 21.081 - COREABC_0.ABCool1_RNO_9 NOR3A Y Out 0.664 21.745 - abcool1_18 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_5 NOR3B B In - 22.067 - COREABC_0.ABCool1_RNO_5 NOR3B Y Out 0.624 22.690 - abcool1_23 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_1 NOR3A A In - 23.012 - COREABC_0.ABCool1_RNO_1 NOR3A Y Out 0.664 23.676 - abcool1_28 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO NOR3B B In - 23.997 - COREABC_0.ABCool1_RNO NOR3B Y Out 0.624 24.621 - abcool1 Net - - 0.322 - 1 COREABC_0.ABCool1 DFN1E1C0 D In - 24.943 - ===================================================================================================================================== Total path delay (propagation time + setup) of 25.481 is 11.541(45.3%) logic and 13.940(54.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 24.922 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -15.461 Number of logic level(s): 17 Starting point: COREABC_0.instR_Cmd[1] / Q Ending point: COREABC_0.ABCool1 / D The start point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------- COREABC_0.instR_Cmd[1] DFN1 Q Out 0.737 0.737 - instR_Cmd[1] Net - - 2.218 - 17 COREABC_0.instR_Cmd_RNIFL27[0] OR2B A In - 2.955 - COREABC_0.instR_Cmd_RNIFL27[0] OR2B Y Out 0.514 3.469 - N_362 Net - - 1.279 - 5 COREABC_0.instR_Cmd_RNIG4CJ_0[2] OR2A B In - 4.748 - COREABC_0.instR_Cmd_RNIG4CJ_0[2] OR2A Y Out 0.514 5.263 - un3_abco1l1_0_0 Net - - 2.218 - 17 COREABC_0.ABCO01\.ABCiI1.ABCl1I0\.ABCII1.ABCL0l0_RNIGS7O MX2 S In - 7.480 - COREABC_0.ABCO01\.ABCiI1.ABCl1I0\.ABCII1.ABCL0l0_RNIGS7O MX2 Y Out 0.396 7.877 - ABCi1i1[7] Net - - 1.279 - 5 COREABC_0.ABCO01\.ABCiI1.ABCl1I0\.ABCII1.ABCL0l0_RNIUH181 NOR2B B In - 9.156 - COREABC_0.ABCO01\.ABCiI1.ABCl1I0\.ABCII1.ABCL0l0_RNIUH181 NOR2B Y Out 0.627 9.783 - un3[24] Net - - 1.184 - 4 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I7_P0N OR2 A In - 10.967 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I7_P0N OR2 Y Out 0.507 11.474 - N402 Net - - 0.806 - 3 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I135_Y_0 OA1 C In - 12.281 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I135_Y_0 OA1 Y Out 0.666 12.946 - ADD_32x32_fast_I135_Y_0 Net - - 0.322 - 1 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I135_Y NOR2B A In - 13.268 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I135_Y NOR2B Y Out 0.514 13.782 - N581 Net - - 1.184 - 4 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I263_un1_Y_0 NOR3C A In - 14.966 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I263_un1_Y_0 NOR3C Y Out 0.464 15.430 - ADD_32x32_fast_I263_un1_Y_0 Net - - 0.322 - 1 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I263_un1_Y NOR3C C In - 15.751 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I263_un1_Y NOR3C Y Out 0.641 16.392 - I263_un1_Y Net - - 0.322 - 1 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I263_Y OR3 B In - 16.714 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I263_Y OR3 Y Out 0.714 17.428 - N764 Net - - 0.386 - 2 COREABC_0.un1_accumULATOr.ADD_32x32_fast_I298_Y_0 XNOR3 C In - 17.814 - COREABC_0.un1_accumULATOr.ADD_32x32_fast_I298_Y_0 XNOR3 Y Out 0.985 18.799 - un1_accumULATOr[18] Net - - 0.322 - 1 COREABC_0.instr_SCmd_RNIG5R713[1] OR2B A In - 19.121 - COREABC_0.instr_SCmd_RNIG5R713[1] OR2B Y Out 0.514 19.635 - un1_accumULATOr_m_i[18] Net - - 0.322 - 1 COREABC_0.accumULATOr_RNIVRDOM3[17] OR3C C In - 19.957 - COREABC_0.accumULATOr_RNIVRDOM3[17] OR3C Y Out 0.666 20.622 - ABCL110[18] Net - - 0.386 - 2 COREABC_0.ABCool1_RNO_9 NOR3A C In - 21.008 - COREABC_0.ABCool1_RNO_9 NOR3A Y Out 0.716 21.724 - abcool1_18 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_5 NOR3B B In - 22.046 - COREABC_0.ABCool1_RNO_5 NOR3B Y Out 0.624 22.670 - abcool1_23 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_1 NOR3A A In - 22.991 - COREABC_0.ABCool1_RNO_1 NOR3A Y Out 0.664 23.655 - abcool1_28 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO NOR3B B In - 23.977 - COREABC_0.ABCool1_RNO NOR3B Y Out 0.624 24.600 - abcool1 Net - - 0.322 - 1 COREABC_0.ABCool1 DFN1E1C0 D In - 24.922 - ========================================================================================================================== Total path delay (propagation time + setup) of 25.461 is 11.628(45.7%) logic and 13.833(54.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------- MSS_Waveform_0.MSS_ADLIB_INST System MSS_APB FABPRDATA[1] Z\\CoreAPB3_0_APBmslave0_PRDATA_\[1\]\\ 0.000 -2.063 MSS_Waveform_0.MSS_ADLIB_INST System MSS_APB FABPRDATA[4] Z\\CoreAPB3_0_APBmslave0_PRDATA_\[4\]\\ 0.000 -1.981 MSS_Waveform_0.MSS_ADLIB_INST System MSS_APB FABPRDATA[0] Z\\CoreAPB3_0_APBmslave0_PRDATA_\[0\]\\ 0.000 -1.951 MSS_Waveform_0.MSS_ADLIB_INST System MSS_APB FABPRDATA[3] Z\\CoreAPB3_0_APBmslave0_PRDATA_\[3\]\\ 0.000 -1.767 MSS_Waveform_0.MSS_ADLIB_INST System MSS_APB FABPRDATA[2] Z\\CoreAPB3_0_APBmslave0_PRDATA_\[2\]\\ 0.000 -1.539 MSS_Waveform_0.MSS_ADLIB_INST System MSS_APB FABPRDATA[5] Z\\CoreAPB3_0_APBmslave0_PRDATA_\[5\]\\ 0.000 -1.498 MSS_Waveform_0.MSS_ADLIB_INST System MSS_APB FABPRDATA[7] Z\\CoreAPB3_0_APBmslave0_PRDATA_\[7\]\\ 0.000 -0.830 MSS_Waveform_0.MSS_ADLIB_INST System MSS_APB FABPRDATA[6] Z\\CoreAPB3_0_APBmslave0_PRDATA_\[6\]\\ 0.000 -0.811 MSS_Waveform_0.MSS_ADLIB_INST System MSS_APB FABPRDATA[11] Z\\CoreAPB3_0_APBmslave0_PRDATA_\[11\]\\ 0.000 -0.655 MSS_Waveform_0.MSS_ADLIB_INST System MSS_APB FABPRDATA[21] Z\\CoreAPB3_0_APBmslave0_PRDATA_\[21\]\\ 0.000 -0.624 ========================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------- COREABC_0.ABCool1 System DFN1E1C0 D abcool1 9.461 -2.063 COREABC_0.accumULATOr[4] System DFN1E1C0 D ABCL110[4] 9.496 3.937 COREABC_0.accumULATOr[6] System DFN1E1C0 D ABCL110[6] 9.496 3.937 COREABC_0.accumULATOr[7] System DFN1E1C0 D ABCL110[7] 9.496 3.937 COREABC_0.accumULATOr[17] System DFN1E1C0 D ABCL110[17] 9.496 4.030 COREABC_0.accumULATOr[22] System DFN1E1C0 D ABCL110[22] 9.496 4.030 COREABC_0.accumULATOr[30] System DFN1E1C0 D ABCL110[30] 9.496 4.030 COREABC_0.accumULATOr[14] System DFN1E1C0 D ABCL110[14] 9.461 4.102 COREABC_0.accumULATOr[18] System DFN1E1C0 D ABCL110[18] 9.496 4.119 MSS_Waveform_0.MSS_ADLIB_INST System MSS_APB PLLLOCK MSS_ADLIB_INST_PLLLOCK 10.000 4.169 ======================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 11.524 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -2.063 Number of logic level(s): 12 Starting point: MSS_Waveform_0.MSS_ADLIB_INST / FABPRDATA[1] Ending point: COREABC_0.ABCool1 / D The start point is clocked by System [rising] The end point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------- MSS_Waveform_0.MSS_ADLIB_INST MSS_APB FABPRDATA[1] Out 0.000 0.000 - Z\\CoreAPB3_0_APBmslave0_PRDATA_\[1\]\\ Net - - 0.322 - 1 COREABC_0.Instr_SLOT_RNI620C[1] MX2 A In - 0.322 - COREABC_0.Instr_SLOT_RNI620C[1] MX2 Y Out 0.579 0.900 - PRDATA_M_m_0[1] Net - - 0.322 - 1 COREABC_0.Instr_SLOT_RNI6S8V[1] OR3B A In - 1.222 - COREABC_0.Instr_SLOT_RNI6S8V[1] OR3B Y Out 0.464 1.686 - PRDATA_M_m[1] Net - - 0.322 - 1 COREABC_0.accumULATOr_RNIA4E72[2] AOI1B C In - 2.007 - COREABC_0.accumULATOr_RNIA4E72[2] AOI1B Y Out 0.398 2.405 - ABCL110_iv_0[1] Net - - 0.322 - 1 COREABC_0.accumULATOr_RNIFQ28A[1] NOR3C B In - 2.727 - COREABC_0.accumULATOr_RNIFQ28A[1] NOR3C Y Out 0.624 3.351 - ABCL110_iv_2[1] Net - - 0.322 - 1 COREABC_0.accumULATOr_RNILQ2NM[0] OR3C B In - 3.672 - COREABC_0.accumULATOr_RNILQ2NM[0] OR3C Y Out 0.624 4.296 - ABCL110[1] Net - - 0.386 - 2 COREABC_0.ABCool1_RNO_15 NOR2 B In - 4.682 - COREABC_0.ABCool1_RNO_15 NOR2 Y Out 0.646 5.328 - abcool1_0 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_13 NOR3A A In - 5.650 - COREABC_0.ABCool1_RNO_13 NOR3A Y Out 0.664 6.314 - abcool1_2 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_11 NOR3A A In - 6.635 - COREABC_0.ABCool1_RNO_11 NOR3A Y Out 0.664 7.299 - abcool1_6 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_8 NOR3A A In - 7.621 - COREABC_0.ABCool1_RNO_8 NOR3A Y Out 0.664 8.284 - abcool1_13 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_5 NOR3B A In - 8.606 - COREABC_0.ABCool1_RNO_5 NOR3B Y Out 0.666 9.272 - abcool1_23 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_1 NOR3A A In - 9.593 - COREABC_0.ABCool1_RNO_1 NOR3A Y Out 0.664 10.257 - abcool1_28 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO NOR3B B In - 10.579 - COREABC_0.ABCool1_RNO NOR3B Y Out 0.624 11.202 - abcool1 Net - - 0.322 - 1 COREABC_0.ABCool1 DFN1E1C0 D In - 11.524 - ============================================================================================================== Total path delay (propagation time + setup) of 12.063 is 7.819(64.8%) logic and 4.244(35.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 11.442 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -1.981 Number of logic level(s): 12 Starting point: MSS_Waveform_0.MSS_ADLIB_INST / FABPRDATA[4] Ending point: COREABC_0.ABCool1 / D The start point is clocked by System [rising] The end point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------- MSS_Waveform_0.MSS_ADLIB_INST MSS_APB FABPRDATA[4] Out 0.000 0.000 - Z\\CoreAPB3_0_APBmslave0_PRDATA_\[4\]\\ Net - - 0.322 - 1 COREABC_0.Instr_SLOT_RNI9E0C[1] MX2 A In - 0.322 - COREABC_0.Instr_SLOT_RNI9E0C[1] MX2 Y Out 0.579 0.900 - PRDATA_M_m_0[4] Net - - 0.322 - 1 COREABC_0.Instr_SLOT_RNI989V[1] OR3B A In - 1.222 - COREABC_0.Instr_SLOT_RNI989V[1] OR3B Y Out 0.464 1.686 - PRDATA_M_m[4] Net - - 0.322 - 1 COREABC_0.accumULATOr_RNIGSE72[5] AOI1B C In - 2.007 - COREABC_0.accumULATOr_RNIGSE72[5] AOI1B Y Out 0.398 2.405 - ABCL110_iv_0[4] Net - - 0.322 - 1 COREABC_0.accumULATOr_RNI2OOS8[4] NOR3C B In - 2.727 - COREABC_0.accumULATOr_RNI2OOS8[4] NOR3C Y Out 0.624 3.351 - ABCL110_iv_2[4] Net - - 0.322 - 1 COREABC_0.accumULATOr_RNIAV41I[3] NOR3C A In - 3.672 - COREABC_0.accumULATOr_RNIAV41I[3] NOR3C Y Out 0.525 4.197 - ABCL110_iv_5[4] Net - - 0.322 - 1 COREABC_0.accumULATOr_RNID3G6V[3] AO1B C In - 4.518 - COREABC_0.accumULATOr_RNID3G6V[3] AO1B Y Out 0.655 5.174 - ABCL110[4] Net - - 0.386 - 2 COREABC_0.ABCool1_RNO_14 NOR3 B In - 5.559 - COREABC_0.ABCool1_RNO_14 NOR3 Y Out 0.714 6.274 - abcool1_5 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_12 NOR3A A In - 6.595 - COREABC_0.ABCool1_RNO_12 NOR3A Y Out 0.664 7.259 - abcool1_12 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_9 NOR3A A In - 7.581 - COREABC_0.ABCool1_RNO_9 NOR3A Y Out 0.664 8.245 - abcool1_18 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_5 NOR3B B In - 8.566 - COREABC_0.ABCool1_RNO_5 NOR3B Y Out 0.624 9.190 - abcool1_23 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_1 NOR3A A In - 9.511 - COREABC_0.ABCool1_RNO_1 NOR3A Y Out 0.664 10.175 - abcool1_28 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO NOR3B B In - 10.497 - COREABC_0.ABCool1_RNO NOR3B Y Out 0.624 11.121 - abcool1 Net - - 0.322 - 1 COREABC_0.ABCool1 DFN1E1C0 D In - 11.442 - ============================================================================================================== Total path delay (propagation time + setup) of 11.981 is 7.737(64.6%) logic and 4.244(35.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 11.413 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -1.951 Number of logic level(s): 12 Starting point: MSS_Waveform_0.MSS_ADLIB_INST / FABPRDATA[0] Ending point: COREABC_0.ABCool1 / D The start point is clocked by System [rising] The end point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------- MSS_Waveform_0.MSS_ADLIB_INST MSS_APB FABPRDATA[0] Out 0.000 0.000 - Z\\CoreAPB3_0_APBmslave0_PRDATA_\[0\]\\ Net - - 0.322 - 1 COREABC_0.Instr_SLOT_RNI5UVB[1] MX2 A In - 0.322 - COREABC_0.Instr_SLOT_RNI5UVB[1] MX2 Y Out 0.579 0.900 - PRDATA_M_m_0[0] Net - - 0.322 - 1 COREABC_0.Instr_SLOT_RNI5O8V[1] OR3B A In - 1.222 - COREABC_0.Instr_SLOT_RNI5O8V[1] OR3B Y Out 0.464 1.686 - PRDATA_M_m[0] Net - - 0.322 - 1 COREABC_0.accumULATOr_RNIM92I5[0] NOR3C B In - 2.007 - COREABC_0.accumULATOr_RNIM92I5[0] NOR3C Y Out 0.624 2.631 - ABCL110_iv_1[0] Net - - 0.322 - 1 COREABC_0.accumULATOr_RNII4B7C[0] NOR3C A In - 2.953 - COREABC_0.accumULATOr_RNII4B7C[0] NOR3C Y Out 0.525 3.477 - ABCL110_iv_3[0] Net - - 0.322 - 1 COREABC_0.insTR_data_RNIVK4LL[0] OR3C A In - 3.799 - COREABC_0.insTR_data_RNIVK4LL[0] OR3C Y Out 0.525 4.324 - ABCL110[0] Net - - 0.386 - 2 COREABC_0.ABCool1_RNO_15 NOR2 A In - 4.710 - COREABC_0.ABCool1_RNO_15 NOR2 Y Out 0.507 5.217 - abcool1_0 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_13 NOR3A A In - 5.538 - COREABC_0.ABCool1_RNO_13 NOR3A Y Out 0.664 6.202 - abcool1_2 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_11 NOR3A A In - 6.524 - COREABC_0.ABCool1_RNO_11 NOR3A Y Out 0.664 7.188 - abcool1_6 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_8 NOR3A A In - 7.509 - COREABC_0.ABCool1_RNO_8 NOR3A Y Out 0.664 8.173 - abcool1_13 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_5 NOR3B A In - 8.495 - COREABC_0.ABCool1_RNO_5 NOR3B Y Out 0.666 9.160 - abcool1_23 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_1 NOR3A A In - 9.482 - COREABC_0.ABCool1_RNO_1 NOR3A Y Out 0.664 10.146 - abcool1_28 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO NOR3B B In - 10.467 - COREABC_0.ABCool1_RNO NOR3B Y Out 0.624 11.091 - abcool1 Net - - 0.322 - 1 COREABC_0.ABCool1 DFN1E1C0 D In - 11.413 - ============================================================================================================== Total path delay (propagation time + setup) of 11.951 is 7.707(64.5%) logic and 4.244(35.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 11.228 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -1.767 Number of logic level(s): 12 Starting point: MSS_Waveform_0.MSS_ADLIB_INST / FABPRDATA[3] Ending point: COREABC_0.ABCool1 / D The start point is clocked by System [rising] The end point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------- MSS_Waveform_0.MSS_ADLIB_INST MSS_APB FABPRDATA[3] Out 0.000 0.000 - Z\\CoreAPB3_0_APBmslave0_PRDATA_\[3\]\\ Net - - 0.322 - 1 COREABC_0.Instr_SLOT_RNI8A0C[1] MX2 A In - 0.322 - COREABC_0.Instr_SLOT_RNI8A0C[1] MX2 Y Out 0.579 0.900 - PRDATA_M_m_0[3] Net - - 0.322 - 1 COREABC_0.Instr_SLOT_RNI849V[1] OR3B A In - 1.222 - COREABC_0.Instr_SLOT_RNI849V[1] OR3B Y Out 0.464 1.686 - PRDATA_M_m[3] Net - - 0.322 - 1 COREABC_0.accumULATOr_RNIEKE72[4] AOI1B C In - 2.007 - COREABC_0.accumULATOr_RNIEKE72[4] AOI1B Y Out 0.398 2.405 - ABCL110_iv_0[3] Net - - 0.322 - 1 COREABC_0.accumULATOr_RNI4M2K5[3] AOI1B C In - 2.727 - COREABC_0.accumULATOr_RNI4M2K5[3] AOI1B Y Out 0.398 3.125 - ABCL110_iv_1[3] Net - - 0.322 - 1 COREABC_0.accumULATOr_RNI1H3JB[2] NOR3C B In - 3.446 - COREABC_0.accumULATOr_RNI1H3JB[2] NOR3C Y Out 0.624 4.070 - ABCL110_iv_4[3] Net - - 0.322 - 1 COREABC_0.accumULATOr_RNIN0GES[2] OR3C A In - 4.392 - COREABC_0.accumULATOr_RNIN0GES[2] OR3C Y Out 0.525 4.916 - ABCL110[3] Net - - 0.386 - 2 COREABC_0.ABCool1_RNO_13 NOR3A C In - 5.302 - COREABC_0.ABCool1_RNO_13 NOR3A Y Out 0.716 6.018 - abcool1_2 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_11 NOR3A A In - 6.340 - COREABC_0.ABCool1_RNO_11 NOR3A Y Out 0.664 7.004 - abcool1_6 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_8 NOR3A A In - 7.325 - COREABC_0.ABCool1_RNO_8 NOR3A Y Out 0.664 7.989 - abcool1_13 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_5 NOR3B A In - 8.310 - COREABC_0.ABCool1_RNO_5 NOR3B Y Out 0.666 8.976 - abcool1_23 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_1 NOR3A A In - 9.298 - COREABC_0.ABCool1_RNO_1 NOR3A Y Out 0.664 9.961 - abcool1_28 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO NOR3B B In - 10.283 - COREABC_0.ABCool1_RNO NOR3B Y Out 0.624 10.907 - abcool1 Net - - 0.322 - 1 COREABC_0.ABCool1 DFN1E1C0 D In - 11.228 - ============================================================================================================== Total path delay (propagation time + setup) of 11.767 is 7.523(63.9%) logic and 4.244(36.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 11.001 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -1.539 Number of logic level(s): 12 Starting point: MSS_Waveform_0.MSS_ADLIB_INST / FABPRDATA[2] Ending point: COREABC_0.ABCool1 / D The start point is clocked by System [rising] The end point is clocked by Top_Waveform|MSS_Waveform_0.MSS_CCC_0.MSS_Waveform_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------- MSS_Waveform_0.MSS_ADLIB_INST MSS_APB FABPRDATA[2] Out 0.000 0.000 - Z\\CoreAPB3_0_APBmslave0_PRDATA_\[2\]\\ Net - - 0.322 - 1 COREABC_0.Instr_SLOT_RNI760C[1] MX2 A In - 0.322 - COREABC_0.Instr_SLOT_RNI760C[1] MX2 Y Out 0.579 0.900 - PRDATA_M_m_0[2] Net - - 0.322 - 1 COREABC_0.Instr_SLOT_RNI709V[1] OR3B A In - 1.222 - COREABC_0.Instr_SLOT_RNI709V[1] OR3B Y Out 0.464 1.686 - PRDATA_M_m[2] Net - - 0.322 - 1 COREABC_0.accumULATOr_RNICCE72[3] AOI1B C In - 2.007 - COREABC_0.accumULATOr_RNICCE72[3] AOI1B Y Out 0.398 2.405 - ABCL110_iv_0[2] Net - - 0.322 - 1 COREABC_0.accumULATOr_RNIU13I5[2] AOI1B C In - 2.727 - COREABC_0.accumULATOr_RNIU13I5[2] AOI1B Y Out 0.398 3.125 - ABCL110_iv_1[2] Net - - 0.322 - 1 COREABC_0.accumULATOr_RNIMC4FB[1] NOR3C B In - 3.446 - COREABC_0.accumULATOr_RNIMC4FB[1] NOR3C Y Out 0.624 4.070 - ABCL110_iv_4[2] Net - - 0.322 - 1 COREABC_0.accumULATOr_RNI8EF2O[1] OR3C A In - 4.392 - COREABC_0.accumULATOr_RNI8EF2O[1] OR3C Y Out 0.525 4.916 - ABCL110[2] Net - - 0.386 - 2 COREABC_0.ABCool1_RNO_13 NOR3A B In - 5.302 - COREABC_0.ABCool1_RNO_13 NOR3A Y Out 0.488 5.790 - abcool1_2 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_11 NOR3A A In - 6.112 - COREABC_0.ABCool1_RNO_11 NOR3A Y Out 0.664 6.776 - abcool1_6 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_8 NOR3A A In - 7.097 - COREABC_0.ABCool1_RNO_8 NOR3A Y Out 0.664 7.761 - abcool1_13 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_5 NOR3B A In - 8.083 - COREABC_0.ABCool1_RNO_5 NOR3B Y Out 0.666 8.748 - abcool1_23 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO_1 NOR3A A In - 9.070 - COREABC_0.ABCool1_RNO_1 NOR3A Y Out 0.664 9.734 - abcool1_28 Net - - 0.322 - 1 COREABC_0.ABCool1_RNO NOR3B B In - 10.055 - COREABC_0.ABCool1_RNO NOR3B Y Out 0.624 10.679 - abcool1 Net - - 0.322 - 1 COREABC_0.ABCool1 DFN1E1C0 D In - 11.001 - ============================================================================================================== Total path delay (propagation time + setup) of 11.539 is 7.296(63.2%) logic and 4.244(36.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Target Part: A2F200M3F_FBGA256_Std Report for cell Top_Waveform.def_arch Core Cell usage: cell count area count*area AND2 1 1.0 1.0 AND3 2 1.0 2.0 AO1 55 1.0 55.0 AO12 1 1.0 1.0 AO13 8 1.0 8.0 AO14 1 1.0 1.0 AO15 1 1.0 1.0 AO16 2 1.0 2.0 AO17 1 1.0 1.0 AO18 3 1.0 3.0 AO1A 8 1.0 8.0 AO1B 48 1.0 48.0 AO1C 6 1.0 6.0 AO1D 5 1.0 5.0 AOI1 13 1.0 13.0 AOI1B 92 1.0 92.0 AOI5 1 1.0 1.0 AX1 5 1.0 5.0 AX1A 6 1.0 6.0 AX1B 5 1.0 5.0 AX1C 15 1.0 15.0 AX1D 7 1.0 7.0 AX1E 12 1.0 12.0 AXO1 1 1.0 1.0 AXO6 2 1.0 2.0 AXO7 2 1.0 2.0 AXOI1 1 1.0 1.0 AXOI2 3 1.0 3.0 AXOI3 1 1.0 1.0 AXOI4 2 1.0 2.0 AXOI5 1 1.0 1.0 AXOI7 1 1.0 1.0 BUFF 4 1.0 4.0 CLKINT 3 0.0 0.0 GND 12 0.0 0.0 INV 4 1.0 4.0 MAJ3 9 1.0 9.0 MAJ3X 1 1.0 1.0 MAJ3XI 2 1.0 2.0 MIN3 4 1.0 4.0 MIN3X 1 1.0 1.0 MSS_APB 1 0.0 0.0 MSS_CCC 1 0.0 0.0 MX2 126 1.0 126.0 MX2A 20 1.0 20.0 MX2B 21 1.0 21.0 MX2C 54 1.0 54.0 NAND2 6 1.0 6.0 NOR2 27 1.0 27.0 NOR2A 29 1.0 29.0 NOR2B 115 1.0 115.0 NOR3 4 1.0 4.0 NOR3A 16 1.0 16.0 NOR3B 24 1.0 24.0 NOR3C 80 1.0 80.0 OA1 12 1.0 12.0 OA1A 9 1.0 9.0 OA1B 1 1.0 1.0 OA1C 5 1.0 5.0 OAI1 9 1.0 9.0 OR2 43 1.0 43.0 OR2A 26 1.0 26.0 OR2B 133 1.0 133.0 OR3 2 1.0 2.0 OR3A 7 1.0 7.0 OR3B 22 1.0 22.0 OR3C 44 1.0 44.0 VCC 12 0.0 0.0 XA1 1 1.0 1.0 XA1B 1 1.0 1.0 XAI1 38 1.0 38.0 XAI1A 5 1.0 5.0 XNOR2 10 1.0 10.0 XNOR3 3 1.0 3.0 XOR2 36 1.0 36.0 XOR3 2 1.0 2.0 ZOR3 1 1.0 1.0 DFN1 20 1.0 20.0 DFN1C0 6 1.0 6.0 DFN1E0C0 9 1.0 9.0 DFN1E1C0 58 1.0 58.0 DFN1P0 11 1.0 11.0 RAM512X18 2 0.0 0.0 ----- ---------- TOTAL 1404 1373.0 IO Cell usage: cell count INBUF_A 1 INBUF_MSS 1 MSS_XTLOSC 1 OUTBUF_A 1 ----- TOTAL 4 Core Cells : 1373 of 4608 (30%) IO Cells : 4 of 66 (6%) RAM/ROM Usage Summary Block Rams : 2 of 8 (25%) Mapper successful! Process took 0h:00m:08s realtime, 0h:00m:07s cputime # Tue Aug 31 18:54:43 2010 ###########################################################]