#-- Synopsys, Inc.
#-- Version E-2010.09A-1
#-- Project file C:\A2F_AC350_DF\A2F500\Fabric_Logic_as_Master\Verilog\Waveform_Gen\synthesis\run_options.txt
#-- Written on Thu Dec 08 14:57:58 2011


#project files
add_file -include "C:/A2F_AC350_DF/A2F500/Fabric_Logic_as_Master/Verilog/Waveform_Gen/hdl/sine_LUT.v"
add_file -include "C:/A2F_AC350_DF/A2F500/Fabric_Logic_as_Master/Verilog/Waveform_Gen/component/work/Top_Waveform/COREABC_0/rtl/vlog/core_obfuscated/support.v"
add_file -verilog "C:/A2F_AC350_DF/A2F500/Fabric_Logic_as_Master/Verilog/Waveform_Gen/hdl/APB_sine_LUT.v"
add_file -verilog "C:/A2F_AC350_DF/A2F500/Fabric_Logic_as_Master/Verilog/Waveform_Gen/component/Actel/SmartFusionMSS/MSS/2.5.106/mss_comps.v"
add_file -verilog "C:/A2F_AC350_DF/A2F500/Fabric_Logic_as_Master/Verilog/Waveform_Gen/component/work/MSS_Waveform/MSS_CCC_0/MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v"
add_file -verilog "C:/A2F_AC350_DF/A2F500/Fabric_Logic_as_Master/Verilog/Waveform_Gen/component/work/MSS_Waveform/mss_tshell.v"
add_file -verilog "C:/A2F_AC350_DF/A2F500/Fabric_Logic_as_Master/Verilog/Waveform_Gen/component/work/MSS_Waveform/MSS_Waveform.v"
add_file -verilog "C:/A2F_AC350_DF/A2F500/Fabric_Logic_as_Master/Verilog/Waveform_Gen/component/work/Top_Waveform/COREABC_0/rtl/vlog/core_obfuscated/ram256x16_smartfusion.v"
add_file -verilog "C:/A2F_AC350_DF/A2F500/Fabric_Logic_as_Master/Verilog/Waveform_Gen/component/work/Top_Waveform/COREABC_0/rtl/vlog/core_obfuscated/ram256x8_rtl.v"
add_file -verilog "C:/A2F_AC350_DF/A2F500/Fabric_Logic_as_Master/Verilog/Waveform_Gen/component/work/Top_Waveform/COREABC_0/rtl/vlog/core_obfuscated/ramblocks.v"
add_file -verilog "C:/A2F_AC350_DF/A2F500/Fabric_Logic_as_Master/Verilog/Waveform_Gen/component/work/Top_Waveform/COREABC_0/rtl/vlog/core_obfuscated/acmtable.v"
add_file -verilog "C:/A2F_AC350_DF/A2F500/Fabric_Logic_as_Master/Verilog/Waveform_Gen/component/work/Top_Waveform/COREABC_0/rtl/vlog/core_obfuscated/instructions.v"
add_file -verilog "C:/A2F_AC350_DF/A2F500/Fabric_Logic_as_Master/Verilog/Waveform_Gen/component/work/Top_Waveform/COREABC_0/rtl/vlog/core_obfuscated/iram512x9_smartfusion.v"
add_file -verilog "C:/A2F_AC350_DF/A2F500/Fabric_Logic_as_Master/Verilog/Waveform_Gen/component/work/Top_Waveform/COREABC_0/rtl/vlog/core_obfuscated/instructram.v"
add_file -verilog "C:/A2F_AC350_DF/A2F500/Fabric_Logic_as_Master/Verilog/Waveform_Gen/component/work/Top_Waveform/COREABC_0/rtl/vlog/core_obfuscated/instructnvm_bb.v"
add_file -verilog "C:/A2F_AC350_DF/A2F500/Fabric_Logic_as_Master/Verilog/Waveform_Gen/component/work/Top_Waveform/COREABC_0/rtl/vlog/core_obfuscated/debugblk.v"
add_file -verilog "C:/A2F_AC350_DF/A2F500/Fabric_Logic_as_Master/Verilog/Waveform_Gen/component/work/Top_Waveform/COREABC_0/rtl/vlog/core_obfuscated/coreabc.v"
add_file -verilog -lib COREAPB3_LIB "C:/A2F_AC350_DF/A2F500/Fabric_Logic_as_Master/Verilog/Waveform_Gen/component/Actel/DirectCore/CoreAPB3/3.0.103/rtl/vlog/core_obfuscated/coreapb3_muxptob3.v"
add_file -verilog -lib COREAPB3_LIB "C:/A2F_AC350_DF/A2F500/Fabric_Logic_as_Master/Verilog/Waveform_Gen/component/Actel/DirectCore/CoreAPB3/3.0.103/rtl/vlog/core_obfuscated/coreapb3.v"
add_file -verilog "C:/A2F_AC350_DF/A2F500/Fabric_Logic_as_Master/Verilog/Waveform_Gen/component/work/Top_Waveform/Top_Waveform.v"
add_file -constraint "C:/A2F_AC350_DF/A2F500/Fabric_Logic_as_Master/Verilog/Waveform_Gen/component/work/MSS_Waveform/mss_tshell_syn.sdc"


#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std v2001

#device options
set_option -technology SmartFusion
set_option -part A2F500M3G
set_option -package FBGA484
set_option -speed_grade STD
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "Top_Waveform"

# mapper_options
set_option -frequency 100.000
set_option -write_verilog 0
set_option -write_vhdl 0

# Actel 500K
set_option -run_prop_extract 1
set_option -maxfan 24
set_option -maxfan_hard3 0
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -report_path 0
set_option -opcond COMWC
set_option -update_models_cp 0
set_option -preserve_registers 0

# Actel 500K
set_option -globalthreshold 50

# NFilter
set_option -popfeed 0
set_option -constprop 0
set_option -createhierarchy 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./Top_Waveform.edn"
impl -active "synthesis"
