----------------------------------------------------------------------
-- Created by Actel SmartDesign Thu Dec 08 14:57:18 2011
-- Testbench Template
-- This is a basic testbench that instantiates your design with basic 
-- clock and reset pins connected.  If your design has special
-- clock/reset or testbench driver requirements then you should 
-- copy this file and modify it. 
----------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench;

architecture behavioral of testbench is

    constant SYSCLK_PERIOD : time := 100 ns;

    signal SYSCLK : std_logic := '0';
    signal NSYSRESET : std_logic := '0';

    component MSS_Waveform
        -- ports
        port( 
            -- Inputs
            MAINXIN : in std_logic;
            FABPSEL : in std_logic;
            FABPENABLE : in std_logic;
            FABPWRITE : in std_logic;
            FABPADDR : in std_logic_vector(31 downto 0);
            FABPWDATA : in std_logic_vector(31 downto 0);
            VAREF0 : in std_logic;
            MSS_RESET_N : in std_logic;

            -- Outputs
            FAB_CLK : out std_logic;
            FABPREADY : out std_logic;
            FABPSLVERR : out std_logic;
            M2F_RESET_N : out std_logic;
            FABPRDATA : out std_logic_vector(31 downto 0);
            SDD_0 : out std_logic

            -- Inouts

        );
    end component;

begin

    process
        variable vhdl_initial : BOOLEAN := TRUE;

    begin
        if ( vhdl_initial ) then
            -- Assert Reset
            NSYSRESET <= '0';
            wait for ( SYSCLK_PERIOD * 10 );
            
            NSYSRESET <= '1';
            wait;
        end if;
    end process;

    -- 10MHz Clock Driver
    SYSCLK <= not SYSCLK after (SYSCLK_PERIOD / 2.0 );

    -- Instantiate Unit Under Test:  MSS_Waveform
    MSS_Waveform_0 : MSS_Waveform
        -- port map
        port map( 
            -- Inputs
            MAINXIN => '0',
            FABPSEL => '0',
            FABPENABLE => '0',
            FABPWRITE => '0',
            FABPADDR => (others=> '0'),
            FABPWDATA => (others=> '0'),
            VAREF0 => '0',
            MSS_RESET_N => NSYSRESET,

            -- Outputs
            FAB_CLK =>  open,
            FABPREADY =>  open,
            FABPSLVERR =>  open,
            M2F_RESET_N =>  open,
            FABPRDATA => open,
            SDD_0 =>  open

            -- Inouts

        );

end behavioral;

