Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Thu Dec 08 11:51:46 2011


Design: Top_Waveform
Family: SmartFusion
Die: A2F200M3F
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.574
External Hold (ns):         1.448
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_glb
Period (ns):                30.358
Frequency (MHz):            32.940
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               MSS_Waveform_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.781
  Slack (ns):
  Arrival (ns):                0.781
  Required (ns):
  Setup (ns):                  -1.830
  External Setup (ns):         -1.574


Expanded Path 1
  From: MSS_RESET_N
  To: MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.781
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        MSS_Waveform_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.781          cell: ADLIB:IOPAD_IN
  0.781                        MSS_Waveform_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: MSS_Waveform_0/MSS_RESET_0_MSS_RESET_N_Y
  0.781                        MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.781                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.525          net: MSS_Waveform_0/GLA0
  N/C                          MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -1.830          Library setup time: ADLIB:MSS_APB_IP
  N/C                          MSS_Waveform_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glb

SET Register to Register

Path 1
  From:                        COREABC_0/ABCO01.ABCii1/ABCII00.ABCII1/ABCI0L0:RCLK
  To:                          COREABC_0/ABClil1:D
  Delay (ns):                  29.740
  Slack (ns):
  Arrival (ns):                30.433
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         30.358

Path 2
  From:                        COREABC_0/iNSTR_SCMd[2]:CLK
  To:                          COREABC_0/ABClil1:D
  Delay (ns):                  29.574
  Slack (ns):
  Arrival (ns):                30.097
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         30.022

Path 3
  From:                        COREABC_0/INstr_cmd[2]:CLK
  To:                          COREABC_0/ABClil1:D
  Delay (ns):                  29.220
  Slack (ns):
  Arrival (ns):                29.743
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         29.668

Path 4
  From:                        COREABC_0/ABCO01.ABCii1/ABCII00.ABCII1/ABCI0L0:RCLK
  To:                          COREABC_0/ACCUMULAtor[31]:D
  Delay (ns):                  29.012
  Slack (ns):
  Arrival (ns):                29.705
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         29.615

Path 5
  From:                        COREABC_0/ABCO01.ABCii1/ABCII00.ABCII1/ABCI0L0:RCLK
  To:                          COREABC_0/ABCIIL1:D
  Delay (ns):                  29.012
  Slack (ns):
  Arrival (ns):                29.705
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         29.615


Expanded Path 1
  From: COREABC_0/ABCO01.ABCii1/ABCII00.ABCII1/ABCI0L0:RCLK
  To: COREABC_0/ABClil1:D
  data required time                             N/C
  data arrival time                          -   30.433
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.693          net: FAB_CLK
  0.693                        COREABC_0/ABCO01.ABCii1/ABCII00.ABCII1/ABCI0L0:RCLK (r)
               +     2.159          cell: ADLIB:RAM512X18
  2.852                        COREABC_0/ABCO01.ABCii1/ABCII00.ABCII1/ABCI0L0:RD0 (f)
               +     1.053          net: COREABC_0/ABCLII1[0]
  3.905                        COREABC_0/ABCO01.ABCii1/ABCII00.ABCII1/ABCI0L0_RNISCF7:B (f)
               +     0.493          cell: ADLIB:OR2
  4.398                        COREABC_0/ABCO01.ABCii1/ABCII00.ABCII1/ABCI0L0_RNISCF7:Y (f)
               +     0.245          net: COREABC_0/ABCO01_ABCii1/ABCII00_ABCII1/ABCOI01_a0_0[0]
  4.643                        COREABC_0/ABCO01.ABCii1/ABCII00.ABCII1/ABCI0L0_RNIM2RG:A (f)
               +     0.398          cell: ADLIB:OR3
  5.041                        COREABC_0/ABCO01.ABCii1/ABCII00.ABCII1/ABCI0L0_RNIM2RG:Y (f)
               +     0.255          net: COREABC_0/ABCI0L0_RNIM2RG
  5.296                        COREABC_0/instr_dATA_RNIIIA41[0]:B (f)
               +     0.479          cell: ADLIB:OR2B
  5.775                        COREABC_0/instr_dATA_RNIIIA41[0]:Y (r)
               +     0.765          net: COREABC_0/ABCOI01[0]
  6.540                        COREABC_0/ACCUMULAtor_RNI0VVA1[0]:B (r)
               +     0.293          cell: ADLIB:NOR2A
  6.833                        COREABC_0/ACCUMULAtor_RNI0VVA1[0]:Y (f)
               +     0.332          net: COREABC_0/ABCoio1_3_m_0[0]
  7.165                        COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I2_un1_CO1_m14_i_a5_2_0:B (f)
               +     0.479          cell: ADLIB:NOR2B
  7.644                        COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I2_un1_CO1_m14_i_a5_2_0:Y (f)
               +     0.276          net: COREABC_0/ADD_32x32_slow_I2_un1_CO1_m14_i_a5_2_0
  7.920                        COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I2_un1_CO1_m14_i_a5_2:B (f)
               +     0.486          cell: ADLIB:OR3C
  8.406                        COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I2_un1_CO1_m14_i_a5_2:Y (r)
               +     0.268          net: COREABC_0/ADD_32x32_slow_I2_un1_CO1_N_26
  8.674                        COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I2_un1_CO1_m14_i:B (r)
               +     0.543          cell: ADLIB:NOR3C
  9.217                        COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I2_un1_CO1_m14_i:Y (r)
               +     0.567          net: COREABC_0/I2_un1_CO1_i_0
  9.784                        COREABC_0/ACCUMULAtor_RNI6NA7B[4]:A (r)
               +     0.301          cell: ADLIB:AO18
  10.085                       COREABC_0/ACCUMULAtor_RNI6NA7B[4]:Y (f)
               +     0.255          net: COREABC_0/d_N_4_2
  10.340                       COREABC_0/ACCUMULAtor_RNIL4TLC[5]:B (f)
               +     0.469          cell: ADLIB:MX2C
  10.809                       COREABC_0/ACCUMULAtor_RNIL4TLC[5]:Y (r)
               +     0.247          net: COREABC_0/ACCUMULAtor_RNIL4TLC[5]
  11.056                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I5_CO1_1:A (r)
               +     0.505          cell: ADLIB:MX2
  11.561                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I5_CO1_1:Y (r)
               +     0.308          net: COREABC_0/N392
  11.869                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I6_un1_CO1:C (r)
               +     0.465          cell: ADLIB:AO18
  12.334                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I6_un1_CO1:Y (f)
               +     0.255          net: COREABC_0/I6_un1_CO1
  12.589                       COREABC_0/ACCUMULAtor_RNIFCNVS[8]:C (f)
               +     0.351          cell: ADLIB:AO18
  12.940                       COREABC_0/ACCUMULAtor_RNIFCNVS[8]:Y (r)
               +     0.268          net: COREABC_0/d_N_4_1
  13.208                       COREABC_0/ACCUMULAtor_RNINKPFU[9]:B (r)
               +     0.498          cell: ADLIB:MX2B
  13.706                       COREABC_0/ACCUMULAtor_RNINKPFU[9]:Y (f)
               +     0.268          net: COREABC_0/ACCUMULAtor_RNINKPFU[9]
  13.974                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I9_CO1_1:A (f)
               +     0.439          cell: ADLIB:MX2A
  14.413                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I9_CO1_1:Y (r)
               +     0.715          net: COREABC_0/N400
  15.128                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I10_un1_CO1:C (r)
               +     0.453          cell: ADLIB:AO18
  15.581                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I10_un1_CO1:Y (f)
               +     0.334          net: COREABC_0/I10_un1_CO1
  15.915                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I11_CO1:B (f)
               +     0.461          cell: ADLIB:AO1C
  16.376                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I11_CO1:Y (f)
               +     0.900          net: COREABC_0/N404
  17.276                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I15_CO1_m3:B (f)
               +     0.625          cell: ADLIB:XAI1
  17.901                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I15_CO1_m3:Y (f)
               +     0.336          net: COREABC_0/ADD_32x32_slow_I15_CO1_m3
  18.237                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I15_CO1_m6:B (f)
               +     0.479          cell: ADLIB:NOR2B
  18.716                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I15_CO1_m6:Y (f)
               +     0.262          net: COREABC_0/ADD_32x32_slow_I15_CO1_m6
  18.978                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I15_CO1_1:S (f)
               +     0.394          cell: ADLIB:MX2C
  19.372                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I15_CO1_1:Y (f)
               +     0.934          net: COREABC_0/N412
  20.306                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I18_un1_CO1_m7:B (f)
               +     0.600          cell: ADLIB:XAI1A
  20.906                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I18_un1_CO1_m7:Y (f)
               +     0.308          net: COREABC_0/ADD_32x32_slow_I18_un1_CO1_m7
  21.214                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I26_un1_CO1_1_m6_i:C (f)
               +     0.517          cell: ADLIB:OR3C
  21.731                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I26_un1_CO1_1_m6_i:Y (r)
               +     0.235          net: COREABC_0/ADD_32x32_slow_I26_un1_CO1_1_m6_i
  21.966                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I26_un1_CO1:S (r)
               +     0.385          cell: ADLIB:MX2C
  22.351                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I26_un1_CO1:Y (r)
               +     0.292          net: COREABC_0/I26_un1_CO1
  22.643                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I27_CO1_i_a3:B (r)
               +     0.505          cell: ADLIB:AO1
  23.148                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I27_CO1_i_a3:Y (r)
               +     0.245          net: COREABC_0/N_18
  23.393                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I27_CO1_i:C (r)
               +     0.302          cell: ADLIB:AOI1D
  23.695                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I27_CO1_i:Y (r)
               +     0.351          net: COREABC_0/N_11_i_0
  24.046                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I28_un1_CO1_i_o3_0_tz:A (r)
               +     0.276          cell: ADLIB:OR2
  24.322                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I28_un1_CO1_i_o3_0_tz:Y (r)
               +     0.247          net: COREABC_0/ADD_32x32_slow_I28_un1_CO1_i_o3_0_tz
  24.569                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I28_un1_CO1_i_o3_0:C (r)
               +     0.570          cell: ADLIB:OR3C
  25.139                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I28_un1_CO1_i_o3_0:Y (f)
               +     0.255          net: COREABC_0/ADD_32x32_slow_I28_un1_CO1_i_o3_0
  25.394                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I28_un1_CO1_i_o3:C (f)
               +     0.535          cell: ADLIB:AO1B
  25.929                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I28_un1_CO1_i_o3:Y (r)
               +     0.292          net: COREABC_0/N_12
  26.221                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I29_CO1_i_o3:B (r)
               +     0.708          cell: ADLIB:MAJ3
  26.929                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I29_CO1_i_o3:Y (r)
               +     0.308          net: COREABC_0/N_13
  27.237                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I30_un1_CO1_i:C (r)
               +     0.548          cell: ADLIB:MIN3
  27.785                       COREABC_0/un1_ACCUMULAtor_ADD_32x32_slow_I30_un1_CO1_i:Y (f)
               +     0.255          net: COREABC_0/N_9
  28.040                       COREABC_0/INstr_cmd_RNIM3I83R1[1]:A (f)
               +     0.484          cell: ADLIB:XAI1
  28.524                       COREABC_0/INstr_cmd_RNIM3I83R1[1]:Y (r)
               +     0.247          net: COREABC_0/un1_ACCUMULAtor_m_i[31]
  28.771                       COREABC_0/ACCUMULAtor_RNII2FAJR1[30]:C (r)
               +     0.570          cell: ADLIB:OR3C
  29.341                       COREABC_0/ACCUMULAtor_RNII2FAJR1[30]:Y (f)
               +     0.364          net: COREABC_0/ABCILO1[31]
  29.705                       COREABC_0/ABClil1_RNO:C (f)
               +     0.473          cell: ADLIB:NOR3A
  30.178                       COREABC_0/ABClil1_RNO:Y (r)
               +     0.255          net: COREABC_0/abclil1_net_1
  30.433                       COREABC_0/ABClil1:D (r)
                                    
  30.433                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.484          net: FAB_CLK
  N/C                          COREABC_0/ABClil1:CLK (r)
               -     0.409          Library setup time: ADLIB:DFN1E1C0
  N/C                          COREABC_0/ABClil1:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        COREABC_0/ABCLL01:CLK
  To:                          COREABC_0/ABCO01.ABCii1/ABCII00.ABCO000.ABCl000/ABCI0L0:RESET
  Delay (ns):                  3.848
  Slack (ns):
  Arrival (ns):                4.392
  Required (ns):
  Recovery (ns):               1.483
  Minimum Period (ns):         5.182
  Skew (ns):                   -0.149

Path 2
  From:                        COREABC_0/ABCLL01:CLK
  To:                          COREABC_0/ABCO01.ABCii1/ABCII00.ABCII1/ABCI0L0:RESET
  Delay (ns):                  3.847
  Slack (ns):
  Arrival (ns):                4.391
  Required (ns):
  Recovery (ns):               1.483
  Minimum Period (ns):         5.181
  Skew (ns):                   -0.149

Path 3
  From:                        COREABC_0/ABCLL01:CLK
  To:                          COREABC_0/STKPTR[0]:PRE
  Delay (ns):                  3.626
  Slack (ns):
  Arrival (ns):                4.170
  Required (ns):
  Recovery (ns):               0.225
  Minimum Period (ns):         3.918
  Skew (ns):                   0.067

Path 4
  From:                        COREABC_0/ABCLL01:CLK
  To:                          COREABC_0/ABColi1:CLR
  Delay (ns):                  3.626
  Slack (ns):
  Arrival (ns):                4.170
  Required (ns):
  Recovery (ns):               0.225
  Minimum Period (ns):         3.914
  Skew (ns):                   0.063

Path 5
  From:                        COREABC_0/ABCLL01:CLK
  To:                          COREABC_0/STKPTR[1]:PRE
  Delay (ns):                  3.626
  Slack (ns):
  Arrival (ns):                4.170
  Required (ns):
  Recovery (ns):               0.225
  Minimum Period (ns):         3.914
  Skew (ns):                   0.063


Expanded Path 1
  From: COREABC_0/ABCLL01:CLK
  To: COREABC_0/ABCO01.ABCii1/ABCII00.ABCO000.ABCl000/ABCI0L0:RESET
  data required time                             N/C
  data arrival time                          -   4.392
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.544          net: FAB_CLK
  0.544                        COREABC_0/ABCLL01:CLK (r)
               +     0.440          cell: ADLIB:DFN1C0
  0.984                        COREABC_0/ABCLL01:Q (r)
               +     2.117          net: COREABC_0/ABCLL01
  3.101                        COREABC_0/ABCLL01_RNIN7Q5/U_CLKSRC:A (r)
               +     0.583          cell: ADLIB:CLKSRC
  3.684                        COREABC_0/ABCLL01_RNIN7Q5/U_CLKSRC:Y (r)
               +     0.708          net: COREABC_0_PRESETN
  4.392                        COREABC_0/ABCO01.ABCii1/ABCII00.ABCO000.ABCl000/ABCI0L0:RESET (r)
                                    
  4.392                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.693          net: FAB_CLK
  N/C                          COREABC_0/ABCO01.ABCii1/ABCII00.ABCO000.ABCl000/ABCI0L0:RCLK (r)
               -     1.483          Library recovery time: ADLIB:RAM512X18
  N/C                          COREABC_0/ABCO01.ABCii1/ABCII00.ABCO000.ABCl000/ABCI0L0:RESET


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MSS_Waveform_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

