`timescale 1ns/100ps
//Copyright 2008 Actel Corporation.  All rights reserved.
//ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
//ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
//IN ADVANCE IN WRITING.
// Rev: 2.4   24Jan08 IPB  : Production Release
// SVN Revision Information:
// SVN $Revision: 11436 $
module
Top_Waveform_COREABC_0_DEBUGBLK
(
PCLK
,
RESETN
,
ISR
,
SMADDR
,
INSTR_CMD
,
INSTR_SCMD
,
INSTR_DATA
,
INSTR_ADDR
,
INSTR_SLOT
,
PRDATA
,
PWDATA
,
ACCUM_OLD
,
ACCUM_NEW
,
ACCUM_ZERO
,
ACCUM_NEG
,
FLAGS
,
RAMDOUT
,
STKPTR
,
ZREGISTER
,
ACMDO
,
DEBUG1
,
DEBUG2
)
;
parameter
DEBUG
=
0
;
parameter
AWIDTH
=
0
;
parameter
DWIDTH
=
0
;
parameter
SWIDTH
=
0
;
parameter
ABCl
=
0
;
parameter
ICWIDTH
=
0
;
parameter
ABCOI
=
0
;
parameter
ZRWIDTH
=
0
;
parameter
IIWIDTH
=
0
;
parameter
IOWIDTH
=
0
;
parameter
ABCII
=
0
;
parameter
EN_MULT
=
0
;
// Copyright 2008 Actel Corporation.  All rights reserved.
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
// Rev: 2.4   24Jan08 IPB  : Production Release
// SVN Revision Information:
// SVN $Revision: 12260 $
localparam
BLANK
=
-
1
;
localparam
iNOP
=
256
*
1
;
localparam
iLOAD
=
256
*
2
;
localparam
iINCB
=
256
*
3
;
localparam
iAND
=
256
*
4
;
localparam
iOR
=
256
*
5
;
localparam
iXOR
=
256
*
6
;
localparam
iADD
=
256
*
7
;
localparam
iSUB
=
256
*
8
;
localparam
iSHL0
=
256
*
9
;
localparam
iSHL1
=
256
*
10
;
localparam
iSHLE
=
256
*
11
;
localparam
iROL
=
256
*
12
;
localparam
iSHR0
=
256
*
13
;
localparam
iSHR1
=
256
*
14
;
localparam
iSHRE
=
256
*
15
;
localparam
iROR
=
256
*
16
;
localparam
iCMP
=
256
*
17
;
localparam
iCMPLEQ
=
256
*
18
;
localparam
iBITCLR
=
256
*
19
;
localparam
iBITSET
=
256
*
20
;
localparam
iBITTST
=
256
*
21
;
localparam
iAPBREAD
=
256
*
22
;
localparam
iAPBWRT
=
256
*
23
;
localparam
iLOADZ
=
256
*
24
;
localparam
iDECZ
=
256
*
25
;
localparam
iINCZ
=
256
*
26
;
localparam
iIOWRT
=
256
*
27
;
localparam
iRAMREAD
=
256
*
28
;
localparam
iRAMWRT
=
256
*
29
;
localparam
iPUSH
=
256
*
30
;
localparam
iPOP
=
256
*
31
;
localparam
iIOREAD
=
256
*
32
;
localparam
iUSER
=
256
*
33
;
localparam
iJUMPB
=
256
*
34
;
localparam
iCALLB
=
256
*
35
;
localparam
iRETURNB
=
256
*
36
;
localparam
iRETISRB
=
256
*
37
;
localparam
iWAITB
=
256
*
38
;
localparam
iHALTB
=
256
*
38
;
localparam
iMULT
=
256
*
39
;
localparam
iDEC
=
256
*
40
;
localparam
iAPBREADZ
=
256
*
41
;
localparam
iAPBWRTZ
=
256
*
42
;
localparam
iADDZ
=
256
*
43
;
localparam
iSUBZ
=
256
*
44
;
localparam
iDAT
=
10
;
localparam
iDAT8
=
11
;
localparam
iDAT16
=
12
;
localparam
iDAT32
=
13
;
localparam
iACM
=
14
;
localparam
iACC
=
15
;
localparam
iRAM
=
16
;
localparam
ABClI
=
10
;
localparam
DAT8
=
11
;
localparam
DAT16
=
12
;
localparam
DAT32
=
13
;
localparam
ACM
=
14
;
localparam
ACC
=
15
;
localparam
RAM
=
16
;
localparam
iIFNOT
=
0
;
localparam
iNOTIF
=
0
;
localparam
iIF
=
1
;
localparam
iUNTIL
=
0
;
localparam
iNOTUNTIL
=
1
;
localparam
iUNTILNOT
=
1
;
localparam
iWHILE
=
1
;
localparam
iZZERO
=
8
'h
08
;
localparam
iNEGATIVE
=
8
'h
04
;
localparam
iZERO
=
8
'h
02
;
localparam
iLTE_ZERO
=
8
'h
06
;
localparam
iALWAYS
=
8
'h
01
;
localparam
iINPUT0
=
12
'h
010
;
localparam
iINPUT1
=
12
'h
020
;
localparam
iINPUT2
=
12
'h
040
;
localparam
iINPUT3
=
12
'h
080
;
localparam
iINPUT4
=
12
'h
100
;
localparam
iINPUT5
=
12
'h
200
;
localparam
iINPUT6
=
12
'h
400
;
localparam
iINPUT7
=
12
'h
800
;
localparam
iINPUT8
=
16
'h
1000
;
localparam
iINPUT9
=
16
'h
2000
;
localparam
iINPUT10
=
16
'h
4000
;
localparam
iINPUT11
=
16
'h
8000
;
localparam
iINPUT12
=
20
'h
10000
;
localparam
iINPUT13
=
20
'h
20000
;
localparam
iINPUT14
=
20
'h
40000
;
localparam
iINPUT15
=
20
'h
80000
;
localparam
iINPUT16
=
24
'h
100000
;
localparam
iINPUT17
=
24
'h
200000
;
localparam
iINPUT18
=
24
'h
400000
;
localparam
iINPUT19
=
24
'h
800000
;
localparam
iINPUT20
=
28
'h
1000000
;
localparam
iINPUT21
=
28
'h
2000000
;
localparam
iINPUT22
=
28
'h
4000000
;
localparam
iINPUT23
=
28
'h
8000000
;
localparam
iINPUT24
=
32
'h
10000000
;
localparam
iINPUT25
=
32
'h
20000000
;
localparam
iINPUT26
=
32
'h
40000000
;
localparam
iINPUT27
=
32
'h
80000000
;
localparam
iANYINPUT
=
32
'h
7FFFFFF0
;
localparam
ALWAYS
=
8
'h
01
;
localparam
ZZERO
=
8
'h
08
;
localparam
NEGATIVE
=
8
'h
04
;
localparam
ZERO
=
8
'h
02
;
localparam
LTE_ZERO
=
8
'h
06
;
localparam
INPUT0
=
12
'h
010
;
localparam
INPUT1
=
12
'h
020
;
localparam
INPUT2
=
12
'h
040
;
localparam
INPUT3
=
12
'h
080
;
localparam
INPUT4
=
12
'h
100
;
localparam
INPUT5
=
12
'h
200
;
localparam
INPUT6
=
12
'h
400
;
localparam
INPUT7
=
12
'h
800
;
localparam
INPUT8
=
16
'h
1000
;
localparam
INPUT9
=
16
'h
2000
;
localparam
INPUT10
=
16
'h
3000
;
localparam
INPUT11
=
16
'h
8000
;
localparam
INPUT12
=
20
'h
10000
;
localparam
INPUT13
=
20
'h
20000
;
localparam
INPUT14
=
20
'h
40000
;
localparam
INPUT15
=
20
'h
80000
;
localparam
INPUT16
=
24
'h
100000
;
localparam
INPUT17
=
24
'h
200000
;
localparam
INPUT18
=
24
'h
300000
;
localparam
INPUT19
=
24
'h
800000
;
localparam
INPUT20
=
28
'h
1000000
;
localparam
INPUT21
=
28
'h
2000000
;
localparam
INPUT22
=
28
'h
4000000
;
localparam
INPUT23
=
28
'h
8000000
;
localparam
INPUT24
=
32
'h
10000000
;
localparam
INPUT25
=
32
'h
20000000
;
localparam
INPUT26
=
32
'h
40000000
;
localparam
INPUT27
=
32
'h
40000000
;
localparam
ANYINPUT
=
32
'h
7FFFFFF0
;
localparam
iLOADLOOP
=
256
*
24
;
localparam
iDECLOOP
=
256
*
25
;
localparam
iINCLOOP
=
256
*
26
;
localparam
iLOOPZ
=
8
;
localparam
LOOPZ
=
8
;
localparam
EN_USER
=
0
;
function
[
57
:
0
]
ABCOl
;
input
[
2
:
0
]
ABCIl
;
input
[
2
:
0
]
ABCll
;
input
[
3
:
0
]
ABCO0
;
input
[
15
:
0
]
ABCI0
;
input
[
31
:
0
]
ABCl0
;
reg
[
32
+
16
+
4
+
6
-
1
:
0
]
ABCO1
;
begin
ABCO1
=
{
ABCl0
,
ABCI0
,
ABCO0
,
ABCll
,
ABCIl
}
;
ABCOl
=
ABCO1
;
end
endfunction
function
[
57
:
0
]
doins
;
input
ABCI1
;
integer
ABCI1
;
input
ABCl1
;
integer
ABCl1
;
input
ABCOOI
;
integer
ABCOOI
;
input
ABCIOI
;
integer
ABCIOI
;
input
ABClOI
;
integer
ABClOI
;
input
ABCOII
;
integer
ABCOII
;
reg
[
2
:
0
]
ABCIl
;
reg
[
2
:
0
]
ABCll
;
reg
[
3
:
0
]
ABCO0
;
reg
[
15
:
0
]
ABCI0
;
reg
[
31
:
0
]
ABCl0
;
localparam
[
31
:
0
]
ABCIII
=
{
32
{
1
'b
1
}
}
;
localparam
[
31
:
0
]
ZERO
=
{
32
{
1
'b
0
}
}
;
integer
ABClII
;
integer
FFW
;
integer
ABCOlI
;
begin
ABCIl
=
3
'b
xxx
;
ABCll
=
3
'b
xxx
;
ABCO0
=
4
'b
xxx0
;
ABCI0
=
{
16
{
1
'b
x
}
}
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
ABClII
=
ABCl1
/
256
;
FFW
=
ABCl1
-
ABClII
*
256
;
ABClII
=
ABClII
*
256
;
case
(
ABClII
)
iLOAD
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
111
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
ABCOOI
;
if
(
ABCI1
>=
3
)
begin
case
(
ABCOOI
)
iDAT
:
begin
ABCl0
=
ABCIOI
;
end
iDAT8
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCl0
=
ABCIOI
;
end
iRAM
:
begin
ABCI0
[
7
:
0
]
=
ABCIOI
;
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
default
:
begin
end
endcase
end
end
iINCB
:
begin
if
(
FFW
>
0
)
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
100
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
1
;
end
else
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
000
;
ABCO0
[
0
]
=
1
'b
0
;
end
end
iDEC
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
100
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
{
32
{
1
'b
1
}
}
;
end
iAND
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
001
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
ABCOOI
;
if
(
ABCI1
>=
3
)
begin
case
(
ABCOOI
)
iDAT
:
begin
ABCl0
=
ABCIOI
;
end
iDAT8
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCl0
=
ABCIOI
;
end
iRAM
:
begin
ABCI0
[
7
:
0
]
=
ABCIOI
;
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
default
:
begin
end
endcase
end
end
iOR
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
010
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
ABCOOI
;
if
(
ABCI1
>=
3
)
begin
case
(
ABCOOI
)
iDAT
:
begin
ABCl0
=
ABCIOI
;
end
iDAT8
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCl0
=
ABCIOI
;
end
iRAM
:
begin
ABCI0
[
7
:
0
]
=
ABCIOI
;
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
default
:
begin
end
endcase
end
end
iXOR
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
011
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
ABCOOI
;
if
(
ABCI1
>=
3
)
begin
case
(
ABCOOI
)
iDAT
:
begin
ABCl0
=
ABCIOI
;
end
iDAT8
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCl0
=
ABCIOI
;
end
iRAM
:
begin
ABCI0
[
7
:
0
]
=
ABCIOI
;
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
default
:
begin
end
endcase
end
end
iADD
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
100
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
ABCOOI
;
if
(
ABCI1
>=
3
)
begin
case
(
ABCOOI
)
iDAT
:
begin
ABCl0
=
ABCIOI
;
end
iDAT8
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCl0
=
ABCIOI
;
end
iRAM
:
begin
ABCI0
[
7
:
0
]
=
ABCIOI
;
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
default
:
begin
end
endcase
end
end
iMULT
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
000
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
ABCOOI
;
if
(
ABCI1
>=
3
)
begin
case
(
ABCOOI
)
iDAT
:
begin
ABCl0
=
ABCIOI
;
end
iDAT8
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCl0
=
ABCIOI
;
end
iRAM
:
begin
ABCI0
[
7
:
0
]
=
ABCIOI
;
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
default
:
begin
end
endcase
end
end
iSUB
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
100
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
~
(
ABCOOI
-
1
)
;
if
(
ABCI1
>=
3
)
begin
ABCl0
=
~
(
ABCIOI
-
1
)
;
case
(
ABCOOI
)
iDAT
:
begin
end
iDAT8
:
begin
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
1
}
}
;
end
iDAT16
:
begin
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
1
}
}
;
end
iDAT32
:
begin
end
iRAM
:
begin
ABCI0
[
7
:
0
]
=
ABCIOI
;
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
default
:
begin
end
endcase
end
end
iSHL0
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
101
;
ABCl0
[
1
:
0
]
=
2
'b
00
;
ABCO0
[
0
]
=
1
'b
0
;
end
iSHL1
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
101
;
ABCl0
[
1
:
0
]
=
2
'b
01
;
ABCO0
[
0
]
=
1
'b
0
;
end
iSHLE
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
101
;
ABCl0
[
1
:
0
]
=
2
'b
10
;
ABCO0
[
0
]
=
1
'b
0
;
end
iROL
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
101
;
ABCl0
[
1
:
0
]
=
2
'b
11
;
ABCO0
[
0
]
=
1
'b
0
;
end
iSHR0
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
110
;
ABCl0
[
1
:
0
]
=
2
'b
00
;
ABCO0
[
0
]
=
1
'b
0
;
end
iSHR1
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
110
;
ABCl0
[
1
:
0
]
=
2
'b
01
;
ABCO0
[
0
]
=
1
'b
0
;
end
iSHRE
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
110
;
ABCl0
[
1
:
0
]
=
2
'b
10
;
ABCO0
[
0
]
=
1
'b
0
;
end
iROR
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
110
;
ABCl0
[
1
:
0
]
=
2
'b
11
;
ABCO0
[
0
]
=
1
'b
0
;
end
iCMP
:
begin
ABCIl
=
3
'b
001
;
ABCll
=
3
'b
011
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
ABCOOI
;
if
(
ABCI1
>=
3
)
begin
case
(
ABCOOI
)
iDAT
:
begin
ABCl0
=
ABCIOI
;
end
iDAT8
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCl0
=
ABCIOI
;
end
iRAM
:
begin
ABCI0
[
7
:
0
]
=
ABCIOI
;
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
default
:
begin
end
endcase
end
end
iCMPLEQ
:
begin
ABCIl
=
3
'b
001
;
ABCll
=
3
'b
100
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
~
(
ABCOOI
-
1
)
;
if
(
ABCI1
>=
3
)
begin
ABCl0
=
~
(
ABCIOI
-
1
)
;
case
(
ABCOOI
)
iDAT
:
begin
end
iDAT8
:
begin
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
end
iRAM
:
begin
ABCI0
[
7
:
0
]
=
ABCIOI
;
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
default
:
begin
end
endcase
end
end
iBITCLR
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
001
;
ABCl0
=
ABCIII
;
ABCl0
[
ABCOOI
]
=
1
'b
0
;
ABCO0
[
0
]
=
1
'b
0
;
end
iBITSET
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
010
;
ABCl0
=
ZERO
;
ABCl0
[
ABCOOI
]
=
1
'b
1
;
ABCO0
[
0
]
=
1
'b
0
;
end
iBITTST
:
begin
ABCIl
=
3
'b
001
;
ABCll
=
3
'b
001
;
ABCl0
=
ZERO
;
ABCl0
[
ABCOOI
]
=
1
'b
1
;
ABCO0
[
0
]
=
1
'b
0
;
end
iAPBREAD
:
begin
ABCIl
=
3
'b
010
;
ABCll
=
3
'b
011
;
ABCO0
=
ABCOOI
;
ABCI0
=
ABCIOI
;
end
iAPBWRT
:
begin
ABCIl
=
3
'b
010
;
ABCll
=
3
'b
xxx
;
ABCO0
=
ABCIOI
;
ABCI0
=
ABClOI
;
case
(
ABCOOI
)
iACM
:
ABCll
=
3
'b
010
;
iACC
:
ABCll
=
3
'b
000
;
iDAT
:
begin
ABCll
=
3
'b
001
;
ABCl0
=
ABCOII
;
end
iDAT8
:
begin
ABCll
=
3
'b
001
;
ABCl0
=
ABCOII
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCll
=
3
'b
001
;
ABCl0
=
ABCOII
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCll
=
3
'b
001
;
ABCl0
=
ABCOII
;
end
default
:
begin
end
endcase
end
iAPBREADZ
:
begin
ABCIl
=
3
'b
010
;
ABCll
=
3
'b
111
;
ABCO0
=
ABCOOI
;
end
iAPBWRTZ
:
begin
ABCIl
=
3
'b
010
;
ABCll
=
3
'b
xxx
;
ABCO0
=
ABCIOI
;
case
(
ABCOOI
)
iACM
:
ABCll
=
3
'b
110
;
iACC
:
ABCll
=
3
'b
100
;
iDAT
:
begin
ABCll
=
3
'b
101
;
ABCl0
=
ABClOI
;
end
iDAT8
:
begin
ABCll
=
3
'b
101
;
ABCl0
=
ABClOI
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCll
=
3
'b
101
;
ABCl0
=
ABClOI
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCll
=
3
'b
101
;
ABCl0
=
ABClOI
;
end
default
:
begin
end
endcase
end
iLOADZ
:
begin
ABCIl
=
3
'b
011
;
ABCll
=
3
'b
000
;
ABCO0
[
0
]
=
1
'b
0
;
case
(
ABCOOI
)
iACC
:
begin
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
iDAT
:
begin
ABCl0
=
ABCIOI
;
end
iDAT8
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCl0
=
ABCIOI
;
end
default
:
begin
end
endcase
end
iDECZ
:
begin
ABCIl
=
3
'b
011
;
ABCll
=
3
'b
001
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
{
32
{
1
'b
1
}
}
;
end
iINCZ
:
begin
ABCIl
=
3
'b
011
;
ABCll
=
3
'b
001
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
1
;
end
iADDZ
:
begin
ABCIl
=
3
'b
011
;
ABCll
=
3
'b
001
;
ABCO0
[
0
]
=
1
'b
0
;
case
(
ABCOOI
)
iACC
:
begin
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
iDAT
:
begin
ABCl0
=
ABCIOI
;
end
iDAT8
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCl0
=
ABCIOI
;
end
default
:
begin
end
endcase
end
iSUBZ
:
begin
ABCIl
=
3
'b
011
;
ABCll
=
3
'b
001
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
~
(
ABCIOI
-
1
)
;
case
(
ABCOOI
)
iACC
:
begin
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
iDAT
:
begin
end
iDAT8
:
begin
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
1
}
}
;
end
iDAT16
:
begin
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
1
}
}
;
end
iDAT32
:
begin
end
default
:
begin
end
endcase
end
iIOWRT
:
begin
ABCIl
=
3
'b
011
;
ABCll
=
3
'b
111
;
ABCO0
[
0
]
=
1
'b
0
;
case
(
ABCOOI
)
iACC
:
begin
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
iDAT
:
begin
ABCl0
=
ABCIOI
;
end
iDAT8
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCl0
=
ABCIOI
;
end
default
:
begin
end
endcase
end
iIOREAD
:
begin
ABCIl
=
3
'b
011
;
ABCll
=
3
'b
110
;
end
iRAMREAD
:
begin
ABCIl
=
3
'b
011
;
ABCll
=
3
'b
011
;
ABCI0
=
ABCOOI
;
end
iRAMWRT
:
begin
ABCIl
=
3
'b
011
;
ABCll
=
3
'b
010
;
ABCI0
=
ABCOOI
;
ABCO0
[
0
]
=
1
'b
1
;
if
(
ABCI1
>=
3
)
begin
ABCO0
[
0
]
=
1
'b
0
;
ABCI0
=
ABCOOI
;
case
(
ABCIOI
)
iACC
:
begin
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
iDAT
:
begin
ABCl0
=
ABClOI
;
end
iDAT8
:
begin
ABCl0
=
ABClOI
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCl0
=
ABClOI
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCl0
=
ABClOI
;
end
default
:
begin
end
endcase
end
end
iPUSH
:
begin
ABCIl
=
3
'b
011
;
ABCll
=
3
'b
100
;
ABCO0
[
0
]
=
1
'b
0
;
case
(
ABCOOI
)
BLANK
:
begin
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
iACC
:
begin
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
iDAT
:
begin
ABCl0
=
ABCIOI
;
end
iDAT8
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCl0
=
ABCIOI
;
end
default
:
begin
end
endcase
end
iPOP
:
begin
ABCIl
=
3
'b
011
;
ABCll
=
3
'b
101
;
end
iJUMPB
:
begin
ABCIl
=
3
'b
100
;
ABCll
=
3
'b
x01
;
if
(
ABCI1
>=
4
)
begin
ABCll
[
0
]
=
ABCIlI
(
ABCOOI
)
;
ABCl0
=
ABCIOI
;
ABCI0
=
ABClOI
;
end
else
begin
ABCl0
[
0
]
=
1
'b
1
;
ABCI0
=
ABCOOI
;
end
for
(
ABCOlI
=
31
;
ABCOlI
>=
FFW
+
4
;
ABCOlI
=
ABCOlI
-
1
)
ABCl0
[
ABCOlI
]
=
1
'b
x
;
end
iWAITB
:
begin
ABCIl
=
3
'b
100
;
ABCll
=
3
'b
x11
;
if
(
ABCI1
>=
3
)
begin
ABCll
[
0
]
=
ABCIlI
(
ABCOOI
)
;
ABCl0
=
ABCIOI
;
end
else
begin
ABCl0
[
0
]
=
1
'b
1
;
end
for
(
ABCOlI
=
31
;
ABCOlI
>=
FFW
+
4
;
ABCOlI
=
ABCOlI
-
1
)
ABCl0
[
ABCOlI
]
=
1
'b
x
;
end
iCALLB
:
begin
ABCIl
=
3
'b
101
;
ABCll
=
3
'b
x01
;
if
(
ABCI1
>=
4
)
begin
ABCll
[
0
]
=
ABCIlI
(
ABCOOI
)
;
ABCl0
=
ABCIOI
;
ABCI0
=
ABClOI
;
end
else
begin
ABCl0
[
0
]
=
1
'b
1
;
ABCI0
=
ABCOOI
;
end
for
(
ABCOlI
=
31
;
ABCOlI
>=
FFW
+
4
;
ABCOlI
=
ABCOlI
-
1
)
ABCl0
[
ABCOlI
]
=
1
'b
x
;
end
iRETURNB
:
begin
ABCIl
=
3
'b
110
;
ABCll
=
3
'b
x01
;
if
(
ABCI1
>=
3
)
begin
ABCll
[
0
]
=
ABCIlI
(
ABCOOI
)
;
ABCl0
=
ABCIOI
;
end
else
begin
ABCl0
[
0
]
=
1
'b
1
;
end
for
(
ABCOlI
=
31
;
ABCOlI
>=
FFW
+
4
;
ABCOlI
=
ABCOlI
-
1
)
ABCl0
[
ABCOlI
]
=
1
'b
x
;
end
iRETISRB
:
begin
ABCIl
=
3
'b
110
;
ABCll
=
3
'b
x11
;
if
(
ABCI1
>=
3
)
begin
ABCll
[
0
]
=
ABCIlI
(
ABCOOI
)
;
ABCl0
=
ABCIOI
;
end
else
begin
ABCl0
[
0
]
=
1
'b
1
;
end
for
(
ABCOlI
=
31
;
ABCOlI
>=
FFW
+
4
;
ABCOlI
=
ABCOlI
-
1
)
ABCl0
[
ABCOlI
]
=
1
'b
x
;
end
iNOP
:
begin
ABCIl
=
3
'b
111
;
if
(
EN_USER
==
1
)
begin
ABCll
=
3
'b
000
;
end
end
iUSER
:
begin
ABCIl
=
3
'b
111
;
ABCll
[
0
]
=
1
'b
1
;
ABCll
=
ABCOOI
;
ABCl0
=
ABCIOI
;
ABCI0
=
ABClOI
;
ABCO0
=
ABCOII
;
end
default
:
begin
end
endcase
doins
=
ABCOl
(
ABCIl
,
ABCll
,
ABCO0
,
ABCI0
,
ABCl0
)
;
end
endfunction
function
[
57
:
0
]
doins5
;
input
ABCl1
;
input
ABCOOI
;
input
ABCIOI
;
input
ABClOI
;
input
ABCOII
;
integer
ABCl1
;
integer
ABCOOI
;
integer
ABCIOI
;
integer
ABClOI
;
integer
ABCOII
;
integer
ABCllI
;
begin
ABCllI
=
-
1
;
doins5
=
doins
(
5
,
ABCl1
,
ABCOOI
,
ABCIOI
,
ABClOI
,
ABCOII
)
;
end
endfunction
function
[
57
:
0
]
doins4
;
input
ABCl1
;
input
ABCOOI
;
input
ABCIOI
;
input
ABClOI
;
integer
ABCl1
;
integer
ABCOOI
;
integer
ABCIOI
;
integer
ABClOI
;
integer
ABCllI
;
begin
ABCllI
=
-
1
;
doins4
=
doins
(
4
,
ABCl1
,
ABCOOI
,
ABCIOI
,
ABClOI
,
ABCllI
)
;
end
endfunction
function
[
57
:
0
]
doins3
;
input
ABCl1
;
input
ABCOOI
;
input
ABCIOI
;
integer
ABCl1
;
integer
ABCOOI
;
integer
ABCIOI
;
integer
ABCllI
;
begin
ABCllI
=
-
1
;
doins3
=
doins
(
3
,
ABCl1
,
ABCOOI
,
ABCIOI
,
ABCllI
,
ABCllI
)
;
end
endfunction
function
[
57
:
0
]
doins2
;
input
ABCl1
;
input
ABCOOI
;
integer
ABCl1
;
integer
ABCOOI
;
integer
ABCllI
;
begin
ABCllI
=
-
1
;
doins2
=
doins
(
2
,
ABCl1
,
ABCOOI
,
ABCllI
,
ABCllI
,
ABCllI
)
;
end
endfunction
function
[
57
:
0
]
doins1
;
input
ABCl1
;
integer
ABCl1
;
integer
ABCllI
;
begin
ABCllI
=
-
1
;
doins1
=
doins
(
1
,
ABCl1
,
ABCllI
,
ABCllI
,
ABCllI
,
ABCllI
)
;
end
endfunction
function
[
57
:
0
]
ABCIlI
;
input
ABCO0I
;
integer
ABCO0I
;
begin
if
(
ABCO0I
!=
0
)
begin
ABCIlI
=
1
'b
1
;
end
else
begin
ABCIlI
=
1
'b
0
;
end
end
endfunction
function
[
57
:
0
]
ABCI0I
;
input
ABCO0I
;
begin
if
(
ABCO0I
)
begin
ABCI0I
=
1
'b
1
;
end
else
begin
ABCI0I
=
1
'b
0
;
end
end
endfunction
function
integer
ABCl0I
;
input
ABCO1I
;
integer
ABCO1I
;
input
ABCI1I
;
integer
ABCI1I
;
input
ABCl1I
;
integer
ABCl1I
;
input
ABCOOl
;
integer
ABCOOl
;
integer
ABCIOl
;
integer
ABClOl
;
begin
ABCIOl
=
0
;
ABClOl
=
0
;
if
(
ABCI1I
==
1
)
begin
ABClOl
=
8
;
if
(
ABCOOl
>
8
)
begin
ABClOl
=
16
;
end
end
if
(
ABCO1I
==
1
)
begin
ABCIOl
=
ABCl1I
;
end
if
(
ABCIOl
>
ABClOl
)
begin
ABCl0I
=
ABCIOl
;
end
else
if
(
ABClOl
>
0
)
begin
ABCl0I
=
ABClOl
;
end
else
begin
ABCl0I
=
1
;
end
end
endfunction
function
integer
calc_swidth
;
input
ABCOIl
;
integer
ABCOIl
;
begin
if
(
ABCOIl
>=
9
)
begin
calc_swidth
=
4
;
end
else
if
(
ABCOIl
>=
5
)
begin
calc_swidth
=
3
;
end
else
if
(
ABCOIl
>=
3
)
begin
calc_swidth
=
2
;
end
else
if
(
ABCOIl
>=
2
)
begin
calc_swidth
=
1
;
end
else
begin
calc_swidth
=
0
;
end
end
endfunction
function
integer
log2r
;
input
ABCOIl
;
integer
ABCOIl
;
begin
if
(
ABCOIl
>=
65536
)
begin
log2r
=
17
;
end
else
if
(
ABCOIl
>=
32768
)
begin
log2r
=
16
;
end
else
if
(
ABCOIl
>=
16384
)
begin
log2r
=
15
;
end
else
if
(
ABCOIl
>=
8192
)
begin
log2r
=
14
;
end
else
if
(
ABCOIl
>=
4096
)
begin
log2r
=
13
;
end
else
if
(
ABCOIl
>=
2048
)
begin
log2r
=
12
;
end
else
if
(
ABCOIl
>=
1024
)
begin
log2r
=
11
;
end
else
if
(
ABCOIl
>=
512
)
begin
log2r
=
10
;
end
else
if
(
ABCOIl
>=
256
)
begin
log2r
=
9
;
end
else
if
(
ABCOIl
>=
128
)
begin
log2r
=
8
;
end
else
if
(
ABCOIl
>=
64
)
begin
log2r
=
7
;
end
else
if
(
ABCOIl
>=
32
)
begin
log2r
=
6
;
end
else
if
(
ABCOIl
>=
16
)
begin
log2r
=
5
;
end
else
if
(
ABCOIl
>=
8
)
begin
log2r
=
4
;
end
else
if
(
ABCOIl
>=
4
)
begin
log2r
=
3
;
end
else
if
(
ABCOIl
>=
2
)
begin
log2r
=
2
;
end
else
if
(
ABCOIl
>=
1
)
begin
log2r
=
1
;
end
else
begin
log2r
=
1
;
end
end
endfunction
function
integer
calc_initwidth
;
input
AWIDTH
;
integer
AWIDTH
;
input
DWIDTH
;
integer
DWIDTH
;
input
ABCl
;
integer
ABCl
;
input
ICWIDTH
;
integer
ICWIDTH
;
integer
SWIDTH
;
integer
ABCIIl
;
integer
ABClIl
;
integer
ABCOll
;
integer
ABCIll
;
integer
ABClll
;
integer
ABCO0l
;
integer
ABCI0l
;
begin
SWIDTH
=
calc_swidth
(
ABCl
)
;
if
(
ABCl
==
0
)
SWIDTH
=
1
;
ABCIIl
=
2
**
ICWIDTH
;
ABClIl
=
AWIDTH
+
DWIDTH
+
SWIDTH
+
6
;
ABCOll
=
1
+
(
ABCIIl
-
1
)
/
512
;
ABCIll
=
1
+
(
ABClIl
-
1
)
/
9
;
ABClll
=
ABCIll
*
ABCOll
;
ABCO0l
=
ABClll
*
512
;
ABCI0l
=
log2r
(
ABCO0l
)
;
if
(
ABCI0l
>
16
)
ABCI0l
=
16
;
calc_initwidth
=
ABCI0l
;
end
endfunction
function
integer
max
;
input
ABCl0l
,
ABCO1l
;
integer
ABCl0l
,
ABCO1l
;
begin
if
(
ABCl0l
>
ABCO1l
)
max
=
ABCl0l
;
else
max
=
ABCO1l
;
end
endfunction
function
integer
min
;
input
ABCl0l
,
ABCO1l
;
integer
ABCl0l
,
ABCO1l
;
begin
if
(
ABCl0l
<
ABCO1l
)
min
=
ABCl0l
;
else
min
=
ABCO1l
;
end
endfunction
input
PCLK
;
input
RESETN
;
input
ISR
;
input
[
ICWIDTH
-
1
:
0
]
SMADDR
;
input
[
2
:
0
]
INSTR_CMD
;
input
[
2
:
0
]
INSTR_SCMD
;
input
[
DWIDTH
-
1
:
0
]
INSTR_DATA
;
input
[
AWIDTH
-
1
:
0
]
INSTR_ADDR
;
input
[
SWIDTH
:
0
]
INSTR_SLOT
;
input
[
DWIDTH
-
1
:
0
]
PRDATA
;
input
[
DWIDTH
-
1
:
0
]
PWDATA
;
input
[
DWIDTH
-
1
:
0
]
ACCUM_OLD
;
input
[
DWIDTH
-
1
:
0
]
ACCUM_NEW
;
input
ACCUM_ZERO
;
input
ACCUM_NEG
;
input
FLAGS
;
input
[
DWIDTH
-
1
:
0
]
RAMDOUT
;
input
[
7
:
0
]
STKPTR
;
input
[
ZRWIDTH
:
0
]
ZREGISTER
;
input
ACMDO
;
input
DEBUG1
;
input
DEBUG2
;
// synthesis translate_off
function
integer
ABCI1l
;
input
[
DWIDTH
-
1
:
0
]
ABCOIl
;
input
ABCO1l
;
integer
ABCl1l
;
begin
begin
:
ABCOO0
integer
ABCOlI
;
for
(
ABCOlI
=
0
;
ABCOlI
<=
DWIDTH
-
1
;
ABCOlI
=
ABCOlI
+
1
)
begin
if
(
ABCOIl
[
ABCOlI
]
==
ABCO1l
)
begin
ABCl1l
=
ABCOlI
;
end
end
end
ABCI1l
=
ABCl1l
;
end
endfunction
function
[
1
:
40
*
8
]
ABCIO0
;
input
[
DWIDTH
-
1
:
0
]
ABClO0
;
input
[
DWIDTH
-
1
:
0
]
ABCOI0
;
input
[
2
:
0
]
ABCII0
;
input
[
DWIDTH
-
1
:
0
]
ABClI0
;
input
ABCOl0
;
input
[
AWIDTH
-
1
:
0
]
ABCIl0
;
reg
[
2
:
0
]
ABCll0
;
reg
[
1
:
(
80
)
*
8
]
ABCO00
;
integer
ABCI00
;
begin
case
(
ABClI0
[
1
:
0
]
)
2
'b
00
:
begin
ABCI00
=
0
;
end
2
'b
01
:
begin
ABCI00
=
1
;
end
2
'b
10
:
begin
ABCI00
=
14
;
end
default
:
begin
ABCI00
=
15
;
end
endcase
if
(
ABCOl0
!=
1
'b
1
)
begin
case
(
ABCII0
)
0
:
begin
if
(
EN_MULT
==
0
)
$swrite
(
ABCO00
,
"ACCUM %02x <= %02x INC"
,
ABClO0
,
ABCOI0
)
;
else
$swrite
(
ABCO00
,
"ACCUM %02x <= %02x MULT %02x"
,
ABClO0
,
ABCOI0
,
ABClI0
)
;
end
1
:
begin
$swrite
(
ABCO00
,
"ACCUM %02x <= %02x AND %02x"
,
ABClO0
,
ABCOI0
,
ABClI0
)
;
end
2
:
begin
$swrite
(
ABCO00
,
"ACCUM %02x <= %02x OR  %02x"
,
ABClO0
,
ABCOI0
,
ABClI0
)
;
end
3
:
begin
$swrite
(
ABCO00
,
"ACCUM %02x <= %02x XOR %02x"
,
ABClO0
,
ABCOI0
,
ABClI0
)
;
end
4
:
begin
$swrite
(
ABCO00
,
"ACCUM %02x <= %02x ADD %02x"
,
ABClO0
,
ABCOI0
,
ABClI0
)
;
end
5
:
begin
if
(
ABCI00
==
15
)
begin
$swrite
(
ABCO00
,
"ACCUM %02x <= %02x ROL"
,
ABClO0
,
ABCOI0
)
;
end
else
begin
$swrite
(
ABCO00
,
"ACCUM %02x <= %02x SHL%01x"
,
ABClO0
,
ABCOI0
,
ABCI00
)
;
end
end
6
:
begin
if
(
ABCI00
==
15
)
begin
$swrite
(
ABCO00
,
"ACCUM %02x <= %02x ROR"
,
ABClO0
,
ABCOI0
)
;
end
else
begin
$swrite
(
ABCO00
,
"ACCUM %02x <= %02x SHR%01x"
,
ABClO0
,
ABCOI0
,
ABCI00
)
;
end
end
7
:
begin
$swrite
(
ABCO00
,
"LOAD %02x"
,
ABClI0
)
;
end
endcase
end
else
begin
case
(
ABCII0
)
0
:
begin
if
(
EN_MULT
>
0
)
$swrite
(
ABCO00
,
"ACCUM %02x <= %02x MULT RAM(%0d) %02x"
,
ABClO0
,
ABCOI0
,
ABCIl0
,
ABClI0
)
;
end
1
:
begin
$swrite
(
ABCO00
,
"ACCUM %02x <= %02x AND RAM(%0d) %02x"
,
ABClO0
,
ABCOI0
,
ABCIl0
,
ABClI0
)
;
end
2
:
begin
$swrite
(
ABCO00
,
"ACCUM %02x <= %02x OR  RAM(%0d) %02x"
,
ABClO0
,
ABCOI0
,
ABCIl0
,
ABClI0
)
;
end
3
:
begin
$swrite
(
ABCO00
,
"ACCUM %02x <= %02x XOR RAM(%0d) %02x"
,
ABClO0
,
ABCOI0
,
ABCIl0
,
ABClI0
)
;
end
4
:
begin
$swrite
(
ABCO00
,
"ACCUM %02x <= %02x ADD RAM(%0d) %02x"
,
ABClO0
,
ABCOI0
,
ABCIl0
,
ABClI0
)
;
end
7
:
begin
$swrite
(
ABCO00
,
"LOAD RAM(%0d) %02x"
,
ABCIl0
,
ABClI0
)
;
end
default
:
begin
$swrite
(
ABCO00
,
"UNEXPECTED INSTRUCTION"
)
;
end
endcase
end
ABCIO0
=
ABCO00
;
end
endfunction
function
[
1
:
40
*
8
]
ABCl00
;
input
[
DWIDTH
-
1
:
0
]
ABClO0
;
input
[
DWIDTH
-
1
:
0
]
ABCOI0
;
input
[
2
:
0
]
ABCII0
;
input
[
DWIDTH
-
1
:
0
]
ABClI0
;
reg
[
2
:
0
]
ABCll0
;
reg
[
1
:
(
40
)
*
8
]
ABCO00
;
integer
ABCI00
;
input
ABCOl0
;
input
[
AWIDTH
-
1
:
0
]
ABCIl0
;
begin
if
(
ABCOl0
!=
1
'b
1
)
begin
case
(
ABCII0
)
1
:
begin
$swrite
(
ABCO00
,
"BITTST(%02x) %0d"
,
ABCOI0
,
ABCI1l
(
ABClI0
,
1
'b
1
)
)
;
end
3
:
begin
$swrite
(
ABCO00
,
"CMP (%02x) %02x"
,
ABCOI0
,
ABClI0
)
;
end
4
:
begin
$swrite
(
ABCO00
,
"CMPLEQ (%02x) %02x"
,
ABCOI0
,
ABClI0
)
;
end
default
:
begin
$swrite
(
ABCO00
,
"UNEXPECTED INSTRUCTION"
)
;
end
endcase
end
else
begin
case
(
ABCII0
)
3
:
begin
$swrite
(
ABCO00
,
"CMP (%02x)RAM(%0d) %02x"
,
ABCOI0
,
ABCIl0
,
ABClI0
)
;
end
default
:
begin
$swrite
(
ABCO00
,
"UNEXPECTED INSTRUCTION"
)
;
end
endcase
end
ABCl00
=
ABCO00
;
end
endfunction
function
[
1
:
16
*
8
]
ABCO10
;
input
[
DWIDTH
-
1
:
0
]
ABCI10
;
input
[
2
:
0
]
ABCl10
;
input
IIWIDTH
;
integer
IIWIDTH
;
reg
[
1
:
(
16
)
*
8
]
ABCO00
;
reg
[
1
:
(
16
)
*
8
]
ABCOO1
;
begin
if
(
(
ABCI10
[
0
]
)
==
1
'b
1
)
begin
if
(
(
ABCl10
[
0
]
)
==
1
'b
1
)
begin
$swrite
(
ABCO00
,
"ALWAYS"
)
;
end
else
begin
$swrite
(
ABCO00
,
"NEVER"
)
;
end
end
else
begin
$swrite
(
ABCO00
,
""
)
;
if
(
(
ABCl10
[
0
]
)
==
1
'b
0
)
begin
$swrite
(
ABCO00
,
"NOTIF"
)
;
end
else
begin
$swrite
(
ABCO00
,
"IF"
)
;
end
if
(
(
ABCI10
[
1
]
)
==
1
'b
1
)
begin
ABCOO1
=
ABCO00
;
$swrite
(
ABCO00
,
"%0s ZERO"
,
ABCOO1
)
;
end
if
(
(
ABCI10
[
2
]
)
==
1
'b
1
)
begin
ABCOO1
=
ABCO00
;
$swrite
(
ABCO00
,
"%0s NEG"
,
ABCOO1
)
;
end
if
(
(
ABCI10
[
3
]
)
==
1
'b
1
)
begin
ABCOO1
=
ABCO00
;
$swrite
(
ABCO00
,
"%0s LCZERO"
,
ABCOO1
)
;
end
begin
:
ABCO
integer
ABCOlI
;
for
(
ABCOlI
=
0
;
ABCOlI
<=
IIWIDTH
-
1
;
ABCOlI
=
ABCOlI
+
1
)
begin
if
(
(
ABCI10
[
4
+
ABCOlI
]
)
==
1
'b
1
)
begin
ABCOO1
=
ABCO00
;
$swrite
(
ABCO00
,
"%0s INPUT%0d"
,
ABCOO1
,
ABCOlI
)
;
end
end
end
end
ABCO10
=
ABCO00
;
end
endfunction
function
[
1
:
8
*
8
]
ABCIO1
;
input
[
DWIDTH
-
1
:
0
]
ABClO1
;
reg
[
1
:
(
8
)
*
8
]
ABCO00
;
begin
if
(
ABClO1
==
0
)
begin
$swrite
(
ABCO00
,
"ZERO"
)
;
end
else
if
(
(
ABClO1
[
DWIDTH
-
1
]
)
==
1
'b
1
)
begin
$swrite
(
ABCO00
,
"NEG"
)
;
end
else
begin
$swrite
(
ABCO00
,
"POS"
)
;
end
ABCIO1
=
ABCO00
;
end
endfunction
function
[
1
:
16
*
8
]
ABCOI1
;
input
FLAGS
;
input
[
DWIDTH
-
1
:
0
]
ABClI0
;
reg
[
1
:
(
16
)
*
8
]
ABCO00
;
begin
if
(
ABClI0
[
0
]
==
1
'b
1
)
begin
$swrite
(
ABCO00
,
"   "
)
;
end
else
if
(
FLAGS
==
1
'b
1
)
begin
$swrite
(
ABCO00
,
" (taken)"
)
;
end
else
begin
$swrite
(
ABCO00
,
" (not taken)"
)
;
end
ABCOI1
=
ABCO00
;
end
endfunction
function
[
1
:
80
*
8
]
ABCII1
;
input
[
DWIDTH
-
1
:
0
]
ABClO0
;
input
[
DWIDTH
-
1
:
0
]
ABCOI0
;
input
[
2
:
0
]
ABClI1
;
input
[
2
:
0
]
ABCOl1
;
input
[
SWIDTH
:
0
]
ABCIl1
;
input
[
AWIDTH
-
1
:
0
]
ABCIl0
;
input
[
DWIDTH
-
1
:
0
]
ABClI0
;
input
[
7
:
0
]
STKPTR
;
input
[
ZRWIDTH
:
0
]
ZREGISTER
;
input
ABCll1
;
input
ACMDO
;
input
FLAGS
;
integer
ABCll1
;
reg
[
2
:
0
]
ABCO01
;
reg
[
2
:
0
]
ABCII0
;
reg
[
1
:
(
80
)
*
8
]
ABCO00
;
reg
[
1
:
(
16
)
*
8
]
ABCI01
;
reg
[
DWIDTH
-
1
:
0
]
ABCl01
;
reg
[
1
:
(
16
)
*
8
]
ABCO11
;
reg
ABCOl0
;
begin
ABCO01
=
0
;
ABCII0
=
0
;
ABCOl0
=
ABCIl1
[
0
]
;
ABCl01
=
0
-
ABClI0
;
begin
:
ABCI11
integer
ABCOlI
;
for
(
ABCOlI
=
0
;
ABCOlI
<=
2
;
ABCOlI
=
ABCOlI
+
1
)
begin
if
(
(
ABClI1
[
ABCOlI
]
)
==
1
'b
1
)
begin
ABCO01
=
ABCO01
+
2
**
ABCOlI
;
end
if
(
(
ABCOl1
[
ABCOlI
]
)
==
1
'b
1
)
begin
ABCII0
=
ABCII0
+
2
**
ABCOlI
;
end
end
end
case
(
ABCO01
)
0
:
begin
$swrite
(
ABCO00
,
"%0s"
,
ABCIO0
(
ABClO0
,
ABCOI0
,
ABCII0
,
ABClI0
,
ABCOl0
,
ABCIl0
)
)
;
end
1
:
begin
$swrite
(
ABCO00
,
"%0s"
,
ABCl00
(
ABClO0
,
ABCOI0
,
ABCII0
,
ABClI0
,
ABCOl0
,
ABCIl0
)
)
;
end
2
:
begin
case
(
ABCII0
)
0
:
$swrite
(
ABCO00
,
"APBWRT ACC %0d:%02x = %02x"
,
ABCIl1
,
ABCIl0
,
ABCOI0
)
;
1
:
$swrite
(
ABCO00
,
"APBWRT DAT %0d:%02x = %02x"
,
ABCIl1
,
ABCIl0
,
ABClI0
)
;
2
:
begin
if
(
ACMDO
==
1
'b
1
)
$swrite
(
ABCO00
,
"APBWRT ACM %0d:%02x = %02x"
,
ABCIl1
,
ABCIl0
,
ABClI0
[
7
:
0
]
)
;
else
$swrite
(
ABCO00
,
"APBWRT ACM %0d:%02x (No Write)"
,
ABCIl1
,
ABCIl0
)
;
end
3
:
$swrite
(
ABCO00
,
"APBREAD %0d:%02x = %02x"
,
ABCIl1
,
ABCIl0
,
ABClI0
)
;
4
:
$swrite
(
ABCO00
,
"APBWRTZ ACC %0d:Z(%02x) = %02x"
,
ABCIl1
,
ZREGISTER
,
ABCOI0
)
;
5
:
$swrite
(
ABCO00
,
"APBWRTZ DAT %0d:Z(%02x) = %02x"
,
ABCIl1
,
ZREGISTER
,
ABClI0
)
;
6
:
begin
if
(
ACMDO
==
1
'b
1
)
$swrite
(
ABCO00
,
"APBWRTZ ACM %0d:Z(%02x) = %02x"
,
ABCIl1
,
ZREGISTER
,
ABClI0
[
7
:
0
]
)
;
else
$swrite
(
ABCO00
,
"APBWRTZ ACM %0d:Z(%02x) (No Write)"
,
ZREGISTER
,
ABCIl0
)
;
end
7
:
$swrite
(
ABCO00
,
"APBREADZ %0d:Z(%02x) = %02x"
,
ZREGISTER
,
ABCIl0
,
ABClI0
)
;
default
:
begin
$swrite
(
ABCO00
,
"UNEXPECTED INSTRUCTION"
)
;
end
endcase
end
3
:
begin
case
(
ABCII0
)
0
:
begin
if
(
ABCOl0
!=
1
'b
1
)
begin
$swrite
(
ABCO00
,
"LOADZ DAT %02x"
,
ABClI0
)
;
end
else
begin
$swrite
(
ABCO00
,
"LOADZ ACC %02x"
,
ABCOI0
)
;
end
end
1
:
begin
if
(
ABCOl0
!=
1
'b
1
)
begin
if
(
ABClI0
==
1
)
$swrite
(
ABCO00
,
"INCZ <= %02x +1 "
,
ZREGISTER
)
;
else
if
(
ABClI0
==
-
1
)
$swrite
(
ABCO00
,
"DECZ <= %02x -1"
,
ZREGISTER
)
;
else
if
(
ABClI0
[
DWIDTH
-
1
]
==
1
'b
0
)
$swrite
(
ABCO00
,
"ADDZ <= %02x + %02x"
,
ZREGISTER
,
ABClI0
)
;
else
$swrite
(
ABCO00
,
"SUBZ <= %02x - %02x"
,
ZREGISTER
,
ABCl01
)
;
end
else
$swrite
(
ABCO00
,
"ADDZ <= %02x + ACC(%02x)"
,
ZREGISTER
,
ABCOI0
)
;
end
6
:
begin
$swrite
(
ABCO00
,
"IOREAD %02x"
,
ABClO0
)
;
end
7
:
begin
if
(
ABCOl0
!=
1
'b
1
)
begin
$swrite
(
ABCO00
,
"IOWRT DAT %02x "
,
ABClI0
)
;
end
else
begin
$swrite
(
ABCO00
,
"IOWRT ACC %02x "
,
ABCOI0
)
;
end
end
3
:
begin
$swrite
(
ABCO00
,
"RAMREAD %02x = %02x"
,
ABCIl0
,
ABClO0
)
;
end
2
:
begin
if
(
ABCOl0
!=
1
'b
1
)
begin
$swrite
(
ABCO00
,
"RAMWRITE DAT %02x = %02x"
,
ABCIl0
,
ABClI0
)
;
end
else
begin
$swrite
(
ABCO00
,
"RAMWRITE ACC %02x = %02x"
,
ABCIl0
,
ABClI0
)
;
end
end
4
:
begin
if
(
ABCOl0
!=
1
'b
1
)
begin
$swrite
(
ABCO00
,
"PUSH %02x (SP=%02x)"
,
ABClI0
,
STKPTR
)
;
end
else
begin
$swrite
(
ABCO00
,
"PUSH ACC %02x (SP=%02x)"
,
ABCOI0
,
STKPTR
)
;
end
end
5
:
begin
$swrite
(
ABCO00
,
"POP %02x (SP=%02x)"
,
ABClO0
,
STKPTR
)
;
end
default
:
begin
$swrite
(
ABCO00
,
"UNEXPECTED INSTRUCTION"
)
;
end
endcase
end
4
:
begin
ABCI01
=
ABCO10
(
ABClI0
,
ABCOl1
,
IIWIDTH
)
;
ABCO11
=
ABCOI1
(
FLAGS
,
ABClI0
)
;
if
(
(
ABCOl1
[
1
]
)
==
1
'b
0
)
begin
$swrite
(
ABCO00
,
"JUMP %0s %0d %0s"
,
ABCI01
,
ABCIl0
,
ABCO11
)
;
end
else
begin
$swrite
(
ABCO00
,
"WAIT %0s %0s"
,
ABCI01
,
ABCO11
)
;
end
end
5
:
begin
ABCI01
=
ABCO10
(
ABClI0
,
ABCOl1
,
IIWIDTH
)
;
ABCO11
=
ABCOI1
(
FLAGS
,
ABClI0
)
;
$swrite
(
ABCO00
,
"CALL %0s %0d %0s (SP=%02x)"
,
ABCI01
,
ABCIl0
,
ABCO11
,
STKPTR
)
;
end
6
:
begin
ABCI01
=
ABCO10
(
ABClI0
,
ABCOl1
,
IIWIDTH
)
;
ABCO11
=
ABCOI1
(
FLAGS
,
ABClI0
)
;
if
(
(
ABCOl1
[
1
]
)
==
1
'b
0
)
begin
$swrite
(
ABCO00
,
"RETURN %0s  %0s (SP=%02x)"
,
ABCI01
,
ABCO11
,
STKPTR
)
;
end
else
begin
$swrite
(
ABCO00
,
"RETISR %0s  %0s (SP=%02x)"
,
ABCI01
,
ABCO11
,
STKPTR
)
;
end
end
7
:
begin
$swrite
(
ABCO00
,
"NOP"
)
;
end
default
:
begin
$swrite
(
ABCO00
,
"NOT DONE"
)
;
end
endcase
ABCII1
=
ABCO00
;
end
endfunction
function
integer
ABCl11
;
input
[
2
:
0
]
ABClI1
;
input
[
2
:
0
]
ABCOl1
;
input
ABCOOOI
;
reg
[
2
:
0
]
ABCO01
;
reg
[
2
:
0
]
ABCII0
;
integer
ABCIOOI
;
begin
ABCO01
=
0
;
ABCII0
=
0
;
begin
:
ABClOOI
integer
ABCOlI
;
for
(
ABCOlI
=
0
;
ABCOlI
<=
2
;
ABCOlI
=
ABCOlI
+
1
)
begin
if
(
(
ABClI1
[
ABCOlI
]
)
==
1
'b
1
)
begin
ABCO01
=
ABCO01
+
2
**
ABCOlI
;
end
if
(
(
ABCOl1
[
ABCOlI
]
)
==
1
'b
1
)
begin
ABCII0
=
ABCII0
+
2
**
ABCOlI
;
end
end
end
ABCIOOI
=
1
;
case
(
ABCO01
)
0
:
begin
if
(
ABCOOOI
==
1
'b
1
)
ABCIOOI
=
3
;
end
1
:
begin
if
(
ABCOOOI
==
1
'b
1
)
ABCIOOI
=
3
;
end
2
:
begin
if
(
ABCII0
==
2
|
ABCII0
==
6
)
ABCIOOI
=
4
;
else
if
(
ABCII0
==
3
|
ABCII0
==
7
)
ABCIOOI
=
2
;
end
3
:
begin
if
(
ABCII0
==
3
|
ABCII0
==
5
)
ABCIOOI
=
3
;
end
default
:
begin
end
endcase
ABCl11
=
ABCIOOI
;
end
endfunction
function
[
DWIDTH
-
1
:
0
]
ABCOIOI
;
input
[
DWIDTH
-
1
:
0
]
ABCIIOI
;
reg
[
DWIDTH
-
1
:
0
]
ABClIOI
;
begin
ABClIOI
=
0
;
begin
:
ABCOlOI
integer
ABCOlI
;
for
(
ABCOlI
=
0
;
ABCOlI
<=
DWIDTH
-
1
;
ABCOlI
=
ABCOlI
+
1
)
begin
if
(
(
ABCIIOI
[
ABCOlI
]
)
==
1
'b
1
)
begin
ABClIOI
[
ABCOlI
]
=
1
'b
1
;
end
end
end
ABCOIOI
=
ABClIOI
;
end
endfunction
function
[
AWIDTH
-
1
:
0
]
ABCIlOI
;
input
[
AWIDTH
-
1
:
0
]
ABCIIOI
;
reg
[
AWIDTH
-
1
:
0
]
ABClIOI
;
begin
ABClIOI
=
0
;
begin
:
ABCOlOI
integer
ABCOlI
;
for
(
ABCOlI
=
0
;
ABCOlI
<=
AWIDTH
-
1
;
ABCOlI
=
ABCOlI
+
1
)
begin
if
(
(
ABCIIOI
[
ABCOlI
]
)
==
1
'b
1
)
begin
ABClIOI
[
ABCOlI
]
=
1
'b
1
;
end
end
end
ABCIlOI
=
ABClIOI
;
end
endfunction
wire
[
7
:
0
]
ABCllOI
;
wire
[
7
:
0
]
ABCO0OI
;
reg
ABCI0OI
;
assign
ABCllOI
=
STKPTR
-
1
;
assign
ABCO0OI
=
STKPTR
+
1
;
wire
ABCl0OI
=
PCLK
&
DEBUG
&
RESETN
;
initial
begin
#
1
;
$display
(
"# INFO CoreABC Verilog Disassembler"
)
;
end
always
@
(
posedge
ABCl0OI
)
begin
:
ABCO1OI
reg
[
DWIDTH
-
1
:
0
]
ABCI1OI
;
reg
[
DWIDTH
-
1
:
0
]
ABCl1OI
;
reg
ABCOOII
;
reg
ABCIOII
;
reg
[
AWIDTH
-
1
:
0
]
ADDR
;
reg
[
DWIDTH
-
1
:
0
]
ABCIIOI
;
integer
ABCIOOI
;
ABCI0OI
<=
DEBUG1
;
ABCI1OI
=
ACCUM_NEW
;
ABCl1OI
=
ACCUM_OLD
;
ABCOOII
=
ABCIOII
;
ABCIOII
=
ISR
;
if
(
INSTR_CMD
[
2
:
1
]
==
2
'b
00
&
INSTR_SLOT
[
0
]
==
1
'b
1
)
ABCIIOI
=
ABCOIOI
(
RAMDOUT
)
;
else
ABCIIOI
=
ABCOIOI
(
INSTR_DATA
)
;
ADDR
=
ABCIlOI
(
INSTR_ADDR
)
;
if
(
ABCIOII
==
1
'b
1
&
ABCOOII
==
1
'b
0
)
begin
$display
(
"Entering ISR: (SP=%02x)"
,
STKPTR
)
;
end
if
(
ABCIOII
==
1
'b
0
&
ABCOOII
==
1
'b
1
)
begin
$display
(
"Exiting ISR: (SP=%02x)"
,
STKPTR
)
;
end
ABCIOOI
=
ABCl11
(
INSTR_CMD
,
INSTR_SCMD
,
INSTR_SLOT
[
0
]
)
;
if
(
DEBUG1
==
1
'b
1
)
begin
if
(
ABCIOOI
==
1
)
begin
$display
(
"INS:%0d: %0s"
,
SMADDR
,
ABCII1
(
ABCI1OI
,
ABCl1OI
,
INSTR_CMD
,
INSTR_SCMD
,
INSTR_SLOT
,
ADDR
,
ABCIIOI
,
STKPTR
,
ZREGISTER
,
IIWIDTH
,
ACMDO
,
FLAGS
)
)
;
end
end
if
(
ABCI0OI
==
1
'b
1
)
begin
if
(
ABCIOOI
==
3
)
begin
$display
(
"INS:%0d: %0s"
,
SMADDR
,
ABCII1
(
ABCI1OI
,
ABCl1OI
,
INSTR_CMD
,
INSTR_SCMD
,
INSTR_SLOT
,
ADDR
,
ABCIIOI
,
STKPTR
,
ZREGISTER
,
IIWIDTH
,
ACMDO
,
FLAGS
)
)
;
end
if
(
ABCIOOI
==
4
)
begin
$display
(
"INS:%0d: %0s"
,
SMADDR
,
ABCII1
(
ABCI1OI
,
ABCl1OI
,
INSTR_CMD
,
INSTR_SCMD
,
INSTR_SLOT
,
ADDR
,
PWDATA
,
STKPTR
,
ZREGISTER
,
IIWIDTH
,
ACMDO
,
FLAGS
)
)
;
end
end
if
(
DEBUG2
==
1
'b
1
)
begin
if
(
ABCIOOI
==
2
)
begin
$display
(
"INS:%0d: %0s"
,
SMADDR
,
ABCII1
(
ABCI1OI
,
ABCl1OI
,
INSTR_CMD
,
INSTR_SCMD
,
INSTR_SLOT
,
ADDR
,
PRDATA
,
STKPTR
,
ZREGISTER
,
IIWIDTH
,
ACMDO
,
FLAGS
)
)
;
end
end
end
// synthesis translate_on
endmodule
