-- Copyright 2008 Actel Corporation.  All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
-- Rev: 2.4   24Jan08 IPB  : Production Release
-- SVN Revision Information:
-- SVN $Revision: 10605 $
library ieee;
use ieee.Std_logic_1164.all;
library proasic3;
entity Top_Waveform_COREABC_0_RAM256x16 is
port (RWCLK: in std_LOGIC;
reset: in STD_LOGic;
WEN: in STd_logic;
ren: in Std_logiC;
waddr: in Std_loGIC_vectoR(7 downto 0);
Raddr: in STD_LOgic_vector(7 downto 0);
wd: in std_logic_VECTOR(15 downto 0);
rd: out STD_LOGIc_vector(15 downto 0));
end Top_Waveform_COREABC_0_raM256X16;

architecture RTL of Top_Waveform_COREABC_0_RAM256x16 is

component ram512x18
generic (memoryfILE: strinG := "");
port (RADDR8,raddr7,raddr6,raddr5,raddr4,Raddr3,RADDR2,rADDR1,raddr0,WADDR8,Waddr7,waddr6,WADDR5,Waddr4,waddr3,wADDR2,WADDR1,WADdr0,WD17,WD16,wD15,wd14,WD13,wd12,wd11,wD10,Wd9,wd8,WD7,WD6,wD5,WD4,WD3,WD2,WD1,wD0,rW0,rw1,Ww0,WW1,pIPE,ren,WEN,rclk,WCLK,reset: in STd_logic := 'U';
rd17,Rd16,rd15,rd14,rd13,RD12,RD11,rd10,rd9,RD8,RD7,rd6,RD5,rd4,rD3,RD2,rd1,rd0: out Std_logic);
end component;

component INV
port (a: in Std_logic := 'U';
Y: out STD_Logic);
end component;

component Vcc
port (y: out Std_logic);
end component;

component gnd
port (y: out Std_logic);
end component;

signal ABColl0,ABClll0,ABCLloi,ABCiloi: STd_logic;

begin
ABClioi: VCc
port map (Y => ABClloi);
ABCiioI: GND
port map (Y => ABCiloi);
ABCI0L0: rAM512X18
port map (RADDR8 => ABCiloi,
rADDR7 => radDR(7),
raDDR6 => Raddr(6),
RADDR5 => rADDR(5),
rADDR4 => RADDR(4),
raddr3 => RAddr(3),
RAddr2 => raDDR(2),
raDDR1 => RADDR(1),
Raddr0 => RADDR(0),
waddr8 => ABCiloi,
waddr7 => waddR(7),
waddr6 => WADDR(6),
waddr5 => waddr(5),
waddr4 => WADdr(4),
Waddr3 => wADDR(3),
waddr2 => waddr(2),
WADDR1 => waddr(1),
waddR0 => WADDr(0),
wD17 => ABCIloi,
wD16 => ABCiloi,
wd15 => wd(15),
WD14 => WD(14),
WD13 => wd(13),
WD12 => wd(12),
wd11 => wd(11),
wd10 => wd(10),
wd9 => WD(9),
wd8 => wd(8),
wd7 => wd(7),
wd6 => Wd(6),
WD5 => wd(5),
wD4 => wd(4),
WD3 => wd(3),
wd2 => WD(2),
wD1 => Wd(1),
WD0 => Wd(0),
RW0 => ABCIloi,
rw1 => ABClloi,
WW0 => ABCILOI,
Ww1 => ABCLLoi,
pIPE => ABCiloi,
rEN => ABClll0,
wEN => ABColl0,
rCLK => RWCLK,
WClk => rwCLK,
reseT => rESET,
RD17 => open ,
rd16 => open ,
rd15 => RD(15),
RD14 => RD(14),
RD13 => Rd(13),
RD12 => RD(12),
RD11 => RD(11),
rd10 => RD(10),
RD9 => RD(9),
rd8 => RD(8),
rd7 => rd(7),
rd6 => Rd(6),
RD5 => RD(5),
rD4 => rD(4),
rd3 => Rd(3),
RD2 => RD(2),
rd1 => rD(1),
RD0 => Rd(0));
ABCo1L0: INV
port map (a => ren,
y => ABClLL0);
ABCl1l0: INV
port map (a => WEN,
y => ABColl0);
end rtl;
