# (OPEN DESIGN)

open_design "F:/old_designfiles/Waveform_Gen/Fabric_Logic_as_Master/Hardware/A2F200/Verilog/Waveform_Gen/designer/impl1/Top_Waveform.adb"
export -format "FDB" {F:/old_designfiles/Waveform_Gen/Fabric_Logic_as_Master/Hardware/A2F200/Verilog/Waveform_Gen/designer/impl1/Top_Waveform.fdb}

save_design "F:/old_designfiles/Waveform_Gen/Fabric_Logic_as_Master/Hardware/A2F200/Verilog/Waveform_Gen/designer/impl1/Top_Waveform.adb"

