`timescale 1ns/100ps
// Copyright 2008 Actel Corporation.  All rights reserved.
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
// Rev: 2.4   24Jan08 IPB  : Production Release
// SVN Revision Information:
// SVN $Revision: 11279 $
module
Top_Waveform_COREABC_0_INSTRUCTRAM
(
CLK
,
RSTN
,
INITDATVAL
,
INITDONE
,
INITADDR
,
INITDATA
,
ADDRESS
,
INSTRUCTION
,
PSEL
,
PENABLE
,
PWRITE
,
PADDR
,
PWDATA
,
PRDATA
,
PSLVERR
,
PREADY
)
;
parameter
AWIDTH
=
7
;
parameter
DWIDTH
=
16
;
parameter
SWIDTH
=
1
;
parameter
ICWIDTH
=
7
;
parameter
ABCOI
=
128
;
parameter
IWWIDTH
=
30
;
parameter
INITWIDTH
=
7
;
parameter
TESTMODE
=
0
;
parameter
IMEM_APB_ACCESS
=
2
;
parameter
UNIQ_STRING_LENGTH
=
10
;
input
CLK
;
input
RSTN
;
input
INITDATVAL
;
input
INITDONE
;
input
[
INITWIDTH
-
1
:
0
]
INITADDR
;
input
[
8
:
0
]
INITDATA
;
input
[
ICWIDTH
-
1
:
0
]
ADDRESS
;
output
[
IWWIDTH
-
1
:
0
]
INSTRUCTION
;
reg
[
IWWIDTH
-
1
:
0
]
INSTRUCTION
;
input
PSEL
;
input
PENABLE
;
input
PWRITE
;
input
[
AWIDTH
-
1
:
0
]
PADDR
;
input
[
DWIDTH
-
1
:
0
]
PWDATA
;
output
[
DWIDTH
-
1
:
0
]
PRDATA
;
reg
[
DWIDTH
-
1
:
0
]
PRDATA
;
output
PSLVERR
;
wire
PSLVERR
;
output
PREADY
;
wire
PREADY
;
function
integer
max
;
input
ABCl0l
,
ABCO1l
;
integer
ABCl0l
,
ABCO1l
;
begin
if
(
ABCl0l
>
ABCO1l
)
max
=
ABCl0l
;
else
max
=
ABCO1l
;
end
endfunction
localparam
ABClOII
=
AWIDTH
;
localparam
ABCOIII
=
DWIDTH
;
localparam
ABCIIII
=
max
(
SWIDTH
,
1
)
;
localparam
ABClIII
=
ICWIDTH
;
localparam
ABCIIl
=
2
**
ICWIDTH
;
localparam
ABClIl
=
ABClOII
+
ABCOIII
+
ABCIIII
+
6
;
localparam
ABCOll
=
1
+
(
ABCIIl
-
1
)
/
512
;
localparam
ABCIll
=
1
+
(
ABClIl
-
1
)
/
9
;
reg
[
15
:
0
]
ABCI1II
;
reg
[
9
*
ABCIll
-
1
:
0
]
ABCl1II
;
wire
[
9
*
ABCIll
-
1
:
0
]
RDATAX
[
0
:
7
]
;
wire
RENABLE
;
wire
[
ABCOll
*
ABCIll
-
1
:
0
]
WENABLE
;
reg
[
63
:
0
]
ABCOOlI
;
reg
[
63
:
0
]
ABCIOlI
;
reg
[
62
:
0
]
ABClOlI
;
reg
[
31
:
0
]
ABCOIlI
;
reg
[
7
:
0
]
ABCIIlI
;
reg
ABClIlI
;
reg
[
8
:
0
]
ABCOllI
;
wire
[
8
:
0
]
WADDR
;
wire
[
8
:
0
]
ABCIllI
;
wire
ABClllI
;
wire
ABCO0lI
;
assign
ABClllI
=
1
'b
0
;
assign
ABCO0lI
=
1
'b
1
;
assign
PSLVERR
=
1
'b
0
;
assign
PREADY
=
1
'b
1
;
always
@
(
INITADDR
)
begin
ABCOOlI
<=
{
64
{
1
'b
0
}
}
;
begin
:
ABClOOI
integer
ABCI0lI
;
for
(
ABCI0lI
=
0
;
ABCI0lI
<=
ABCIll
-
1
;
ABCI0lI
=
ABCI0lI
+
1
)
begin
begin
:
ABCOlOI
integer
ABCl0lI
;
for
(
ABCl0lI
=
0
;
ABCl0lI
<=
ABCOll
-
1
;
ABCl0lI
=
ABCl0lI
+
1
)
begin
ABCOOlI
[
ABCl0lI
*
ABCIll
+
ABCI0lI
]
<=
(
INITADDR
[
INITWIDTH
-
1
:
9
]
==
ABCl0lI
*
ABCIll
+
ABCI0lI
)
;
end
end
end
end
end
always
@
(
PADDR
or
ABCIIlI
)
begin
ABCIOlI
<=
{
64
{
1
'b
0
}
}
;
begin
:
ABCO1lI
integer
ABCI0lI
;
for
(
ABCI0lI
=
0
;
ABCI0lI
<=
ABCIll
-
1
;
ABCI0lI
=
ABCI0lI
+
1
)
begin
begin
:
ABCI1lI
integer
ABCl0lI
;
for
(
ABCl0lI
=
0
;
ABCl0lI
<=
ABCOll
-
1
;
ABCl0lI
=
ABCl0lI
+
1
)
begin
ABCIOlI
[
ABCl0lI
*
ABCIll
+
ABCI0lI
]
<=
(
ABCIIlI
[
7
:
2
]
==
ABCl0lI
*
ABCIll
+
ABCI0lI
)
;
end
end
end
end
end
assign
RENABLE
=
(
PSEL
&
!
PADDR
[
7
]
)
?
!
PWRITE
:
INITDONE
;
always
@
(
ADDRESS
or
PADDR
or
PSEL
or
ABCIIlI
)
begin
ABCI1II
=
{
16
{
1
'b
0
}
}
;
if
(
PSEL
)
begin
ABCI1II
[
14
:
0
]
=
{
ABCIIlI
[
7
:
0
]
,
PADDR
[
6
:
0
]
}
;
end
else
begin
ABCI1II
[
ICWIDTH
-
1
:
0
]
=
ADDRESS
;
end
end
genvar
ABCI0lI
;
generate
for
(
ABCI0lI
=
0
;
ABCI0lI
<=
ABCIll
-
1
;
ABCI0lI
=
ABCI0lI
+
1
)
begin
:
ABCl1lI
genvar
ABCl0lI
;
for
(
ABCl0lI
=
0
;
ABCl0lI
<=
ABCOll
-
1
;
ABCl0lI
=
ABCl0lI
+
1
)
begin
:
ABCOO0I
assign
WENABLE
[
ABCl0lI
*
ABCIll
+
ABCI0lI
]
=
(
PSEL
&
!
PADDR
[
7
]
&
PWRITE
&
(
IMEM_APB_ACCESS
==
2
)
)
?
ABCIOlI
[
ABCl0lI
*
ABCIll
+
ABCI0lI
]
:
~
INITDONE
&
ABCOOlI
[
ABCl0lI
*
ABCIll
+
ABCI0lI
]
&
INITDATVAL
;
assign
WADDR
[
8
:
0
]
=
(
PSEL
&
!
PADDR
[
7
]
&
(
IMEM_APB_ACCESS
==
2
)
)
?
{
ABCIIlI
[
1
:
0
]
,
PADDR
[
6
:
0
]
}
:
INITADDR
[
8
:
0
]
;
assign
ABCIllI
[
8
:
0
]
=
(
PSEL
&
!
PADDR
[
7
]
&
(
IMEM_APB_ACCESS
==
2
)
)
?
ABCOllI
[
8
:
0
]
:
INITDATA
[
8
:
0
]
;
Top_Waveform_COREABC_0_IRAM512X9
#
(
.CID
(
ABCI0lI
)
,
.RID
(
ABCl0lI
)
,
.UNIQ_STRING_LENGTH
(
UNIQ_STRING_LENGTH
)
)
ABCIO0I
(
.RD
(
RDATAX
[
ABCl0lI
]
[
ABCI0lI
*
9
+
8
:
ABCI0lI
*
9
]
)
,
.RADDR
(
ABCI1II
[
8
:
0
]
)
,
.RWCLK
(
CLK
)
,
.RESET
(
RSTN
)
,
.WENABLE
(
WENABLE
[
ABCl0lI
*
ABCIll
+
ABCI0lI
]
)
,
.RENABLE
(
RENABLE
)
,
.INITADDR
(
WADDR
[
8
:
0
]
)
,
.INITDATA
(
ABCIllI
)
)
;
end
end
endgenerate
generate
if
(
ABCOll
==
1
)
begin
:
ABClO0I
wire
[
9
*
ABCIll
-
1
:
0
]
ABCOI0I
=
RDATAX
[
0
]
;
always
@
(
ABCOI0I
)
begin
ABCl1II
<=
ABCOI0I
;
end
end
endgenerate
generate
if
(
ABCOll
>
1
)
begin
:
ABCII0I
always
@
(
RDATAX
[
0
]
or
RDATAX
[
1
]
or
RDATAX
[
2
]
or
RDATAX
[
3
]
or
RDATAX
[
4
]
or
RDATAX
[
5
]
or
RDATAX
[
6
]
or
RDATAX
[
7
]
or
ABCI1II
)
begin
:
ABClI0I
integer
ABCOl0I
;
ABCOl0I
=
ABCI1II
[
11
:
9
]
;
ABCl1II
<=
RDATAX
[
ABCOl0I
]
;
end
end
endgenerate
always
@
(
ABCl1II
or
PSEL
)
begin
if
(
PSEL
==
1
'b
0
)
begin
INSTRUCTION
<=
{
IWWIDTH
{
1
'b
x
}
}
;
INSTRUCTION
[
5
:
0
]
<=
ABCl1II
[
5
:
0
]
;
if
(
ABCIIII
>
0
)
begin
INSTRUCTION
[
1
+
ABCIIII
-
1
+
6
:
6
]
<=
ABCl1II
[
1
+
ABCIIII
-
1
+
6
:
6
]
;
end
INSTRUCTION
[
ABClOII
-
1
+
4
+
6
:
4
+
6
]
<=
ABCl1II
[
ABClOII
-
1
+
ABCIIII
+
6
:
ABCIIII
+
6
]
;
INSTRUCTION
[
ABCOIII
-
1
+
16
+
4
+
6
:
16
+
4
+
6
]
<=
ABCl1II
[
ABCOIII
-
1
+
ABClOII
+
ABCIIII
+
6
:
ABClOII
+
ABCIIII
+
6
]
;
end
end
always
@
(
negedge
RSTN
or
posedge
CLK
)
begin
if
(
!
RSTN
)
begin
ABClOlI
<=
{
63
{
1
'b
0
}
}
;
end
else
begin
if
(
(
PSEL
==
1
'b
1
)
&&
(
PADDR
[
7
]
==
1
'b
0
)
&&
(
PWRITE
==
1
'b
0
)
)
begin
ABClOlI
[
9
*
ABCIll
-
1
:
0
]
<=
ABCl1II
;
end
end
end
always
@
(
negedge
RSTN
or
posedge
CLK
)
begin
if
(
!
RSTN
)
begin
ABCIIlI
<=
8
'b
0
;
ABClIlI
<=
1
'b
0
;
end
else
begin
if
(
(
PSEL
==
1
'b
1
)
&&
(
PADDR
[
7
]
==
1
'b
1
)
&&
(
PWRITE
==
1
'b
1
)
)
begin
case
(
PADDR
[
5
:
2
]
)
4
'b
0000
:
ABCIIlI
<=
PWDATA
[
7
:
0
]
;
4
'b
0001
:
ABClIlI
<=
PWDATA
[
0
]
;
endcase
end
end
end
generate
if
(
DWIDTH
==
8
)
always
@(*)
begin
ABCOllI
=
{
ABClIlI
,
PWDATA
[
7
:
0
]
}
;
end
endgenerate
generate
if
(
DWIDTH
!=
8
)
always
@(*)
begin
ABCOllI
=
PWDATA
[
8
:
0
]
;
end
endgenerate
always
@(*)
begin
if
(
IMEM_APB_ACCESS
!=
2
)
begin
PRDATA
[
DWIDTH
-
1
:
0
]
=
ABCl1II
[
DWIDTH
-
1
:
0
]
;
end
else
begin
if
(
PADDR
[
7
]
==
1
'b
0
)
begin
PRDATA
[
DWIDTH
-
1
:
0
]
=
ABCl1II
[
DWIDTH
-
1
:
0
]
;
end
else
begin
ABCOIlI
=
32
'b
0
;
if
(
DWIDTH
==
8
)
begin
case
(
PADDR
[
5
:
2
]
)
4
'b
0010
:
ABCOIlI
[
7
:
0
]
=
ABClOlI
[
15
:
8
]
;
4
'b
0011
:
ABCOIlI
[
7
:
0
]
=
ABClOlI
[
23
:
16
]
;
4
'b
0100
:
ABCOIlI
[
7
:
0
]
=
ABClOlI
[
31
:
24
]
;
4
'b
0101
:
ABCOIlI
[
7
:
0
]
=
ABClOlI
[
39
:
32
]
;
default
:
ABCOIlI
[
DWIDTH
-
1
:
0
]
=
{
DWIDTH
{
1
'b
0
}
}
;
endcase
end
else
if
(
DWIDTH
==
16
)
begin
case
(
PADDR
[
5
:
2
]
)
4
'b
0010
:
ABCOIlI
[
15
:
0
]
=
ABClOlI
[
31
:
16
]
;
4
'b
0011
:
ABCOIlI
[
15
:
0
]
=
ABClOlI
[
47
:
32
]
;
default
:
ABCOIlI
[
DWIDTH
-
1
:
0
]
=
{
DWIDTH
{
1
'b
0
}
}
;
endcase
end
else
begin
case
(
PADDR
[
5
:
2
]
)
4
'b
0010
:
ABCOIlI
[
30
:
0
]
=
ABClOlI
[
62
:
32
]
;
default
:
ABCOIlI
[
DWIDTH
-
1
:
0
]
=
{
DWIDTH
{
1
'b
0
}
}
;
endcase
end
PRDATA
[
DWIDTH
-
1
:
0
]
=
ABCOIlI
[
DWIDTH
-
1
:
0
]
;
end
end
end
endmodule
