----------------------------------------------------------------------
-- Created by Actel SmartDesign Thu Dec 08 14:57:30 2011
-- Parameters for COREABC
----------------------------------------------------------------------


package coreparameters is
    constant ABCCODE : string( 1 to 822 ) := "// Program to read the sine sample value from 
// sine LUT through slot 2 and writing to 
// DAC0_BYTE0 register.

DEF DAC0_BYTE0_OFFSET 0x0064

// Delay to change the output frequency
// Vary this delay to change the output freq

DEF DELAY 150

// Setting the Base Address of SmartFusion ACE
// for APB3 indirect addressing

APBWRT DAT 1 0x0000 0x40020000

// Initialize the CoreABC Z register with ZERO

LOADZ DAT 0
JUMP $MAIN

// Main loop

$MAIN
$LOOP
    // Read the sample value from sine LUT to 
    // CoreABC Accumulator over slot 2

    APBREADZ 2

    // Write the Accumulator data to DAC0_BYTE0
    // register over slot 0

    APBWRT ACC 0 DAC0_BYTE0_OFFSET

    // Delay Loop

    LOAD DAT DELAY
    $WAIT 
    DEC
    JUMP IFNOT ZERO $WAIT

    // Increment the value in the Z register

    INCZ

JUMP $LOOP";
    constant ACT_CALIBRATIONDATA : integer := 1;
    constant APB_AWIDTH : integer := 16;
    constant APB_DWIDTH : integer := 32;
    constant APB_SDEPTH : integer := 3;
    constant CODEHEXDUMP : string( 1 to 0 ) := "";
    constant CODEHEXDUMP2 : string( 1 to 0 ) := "";
    constant DEBUG : integer := 1;
    constant EN_ACM : integer := 0;
    constant EN_ADD : integer := 1;
    constant EN_ALURAM : integer := 0;
    constant EN_AND : integer := 1;
    constant EN_CALL : integer := 1;
    constant EN_DATAM : integer := 2;
    constant EN_INC : integer := 1;
    constant EN_INDIRECT : integer := 1;
    constant EN_INT : integer := 0;
    constant EN_IOREAD : integer := 1;
    constant EN_IOWRT : integer := 1;
    constant EN_MULT : integer := 0;
    constant EN_OR : integer := 1;
    constant EN_PUSH : integer := 1;
    constant EN_RAM : integer := 1;
    constant EN_SHL : integer := 1;
    constant EN_SHR : integer := 1;
    constant EN_XOR : integer := 1;
    constant FAMILY : integer := 18;
    constant HDL_license : string( 1 to 1 ) := "O";
    constant ICWIDTH : integer := 4;
    constant IFWIDTH : integer := 0;
    constant IIWIDTH : integer := 1;
    constant IMEM_APB_ACCESS : integer := 0;
    constant INITWIDTH : integer := 11;
    constant INSMODE : integer := 0;
    constant IOWIDTH : integer := 1;
    constant ISRADDR : integer := 1;
    constant MAX_NVMDWIDTH : integer := 32;
    constant STWIDTH : integer := 4;
    constant TESTBENCH : string( 1 to 4 ) := "User";
    constant TESTMODE : integer := 0;
    constant UNIQ_STRING : string( 1 to 22 ) := "Top_Waveform_COREABC_0";
    constant UNIQ_STRING_LENGTH : integer := 22;
    constant VERILOGCODE : string( 1 to 0 ) := "";
    constant VERILOGVARS : string( 1 to 0 ) := "";
    constant VHDLCODE : string( 1 to 0 ) := "";
    constant VHDLVARS : string( 1 to 0 ) := "";
    constant ZRWIDTH : integer := 8;
end coreparameters;
