-- Copyright 2008 Actel Corporation.  All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
-- Rev: 2.4   24Jan08 IPB  : Production Release
-- SVN Revision Information:
-- SVN $Revision: 14825 $
library ieee;
use Ieee.STD_logiC_1164.all;
library smartfuSION;
entity Top_Waveform_COREABC_0_rAM256X16 is
port (RWCLK: in std_logiC;
Reset: in std_logiC;
WEN: in std_logic;
REN: in STD_LOGIc;
waddR: in STD_Logic_vectoR(7 downto 0);
radDR: in std_loGIC_VECTor(7 downto 0);
wd: in std_LOGIC_vector(15 downto 0);
RD: out STD_Logic_vectoR(15 downto 0));
end Top_Waveform_COREABC_0_Ram256x16;

architecture rtl of Top_Waveform_COREABC_0_ram256x16 is

component RAm512x18
generic (MEMORyfile: STring := "");
port (RADDR8,raddr7,radDR6,raddr5,RAddr4,RADDR3,raddR2,Raddr1,raDDR0,WAddr8,waddr7,WADDR6,waddr5,waddR4,waddr3,waddr2,wADDR1,wadDR0,wd17,wD16,wd15,wd14,wd13,wd12,Wd11,WD10,wd9,WD8,wd7,wd6,WD5,WD4,WD3,WD2,WD1,WD0,rW0,rw1,WW0,wW1,pipe,REN,wen,Rclk,wcLK,reset: in Std_logic := 'U';
RD17,Rd16,rd15,rd14,rd13,rd12,Rd11,RD10,RD9,rd8,RD7,rd6,rD5,Rd4,rD3,RD2,rd1,rd0: out STD_LOGIc);
end component;

component Inv
port (a: in STd_logic := 'U';
Y: out std_lOGIC);
end component;

component VCc
port (y: out std_logic);
end component;

component gnd
port (y: out STd_logic);
end component;

signal ABColl0,ABClll0,ABClloi,ABCiloi: STd_logic;

begin
ABClioI: Vcc
port map (Y => ABCLLOi);
ABCiioi: gnD
port map (y => ABCiloi);
ABCI0l0: RAM512x18
port map (RADDR8 => ABCIloi,
RADdr7 => Raddr(7),
RADdr6 => rADDR(6),
RADDR5 => RAddr(5),
Raddr4 => RADDR(4),
RADDR3 => Raddr(3),
RADdr2 => raddr(2),
rADDR1 => raddr(1),
raddr0 => rADDR(0),
WADDr8 => ABCIloi,
WADDr7 => WADDR(7),
waDDR6 => waddr(6),
waddR5 => wADDR(5),
WAddr4 => waddr(4),
wadDR3 => waDDR(3),
WADDr2 => wadDR(2),
Waddr1 => waddr(1),
WAddr0 => Waddr(0),
WD17 => ABCiloi,
wd16 => ABCiloi,
WD15 => Wd(15),
wd14 => wd(14),
WD13 => WD(13),
Wd12 => wd(12),
WD11 => wD(11),
WD10 => wd(10),
Wd9 => Wd(9),
wd8 => wd(8),
wd7 => wd(7),
wd6 => WD(6),
wd5 => wd(5),
wd4 => wd(4),
wD3 => wd(3),
WD2 => wd(2),
wd1 => WD(1),
wd0 => wd(0),
Rw0 => ABCiLOI,
rw1 => ABCLLOI,
ww0 => ABCILOI,
WW1 => ABCLLoi,
pipe => ABCiloI,
ren => ABClll0,
wen => ABColl0,
rclk => rwclk,
Wclk => RWClk,
RESET => RESET,
RD17 => open ,
RD16 => open ,
RD15 => RD(15),
RD14 => RD(14),
rd13 => rd(13),
RD12 => Rd(12),
RD11 => rD(11),
RD10 => rd(10),
rd9 => rd(9),
RD8 => rd(8),
rd7 => RD(7),
rd6 => RD(6),
rd5 => RD(5),
RD4 => rD(4),
RD3 => rd(3),
RD2 => RD(2),
RD1 => rd(1),
RD0 => RD(0));
ABCO1l0: inv
port map (A => ren,
y => ABCLLL0);
ABCl1l0: inv
port map (A => Wen,
Y => ABColl0);
end RTL;
