// APB_sine_LUT.v

// This code creates a sine wave LUT with APB slave wrapper interface

`timescale 1ns/1ns
`include "sine_LUT.v"

module APB_sine_LUT(
                    input PCLK,
                    input PRESETn,
                    input PENABLE,
                    input PSEL,
                    input [7:0] PADDR,
                    input PWRITE,
                    input [31:0] PWDATA,
                    output [7:0] PRDATA,
                    output PREADY ,
                    output PSLVERR    
                   ); 
wire rd_enable_i; 

assign PREADY      = 1'b1;  
assign PSLVERR     = 1'b0; 
assign rd_enable_i = ((~PWRITE) && PSEL);

sine_lut I1 (.clock(PCLK),
             .reset_n(PRESETn),
             .rd_enable(rd_enable_i),
             .table_index(PADDR),
             .table_value(PRDATA)
            );  

endmodule
