-- Copyright 2008 Actel Corporation.  All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
-- Rev: 2.4   24Jan08 IPB  : Production Release
-- SVN Revision Information:
-- SVN $Revision: 14578 $
library ieee;
use ieee.stD_logic_1164.all;
use ieee.STD_LOGIc_arith.all;
use IEEE.STD_logic_unsigNED.all;
library COREABC_LIB;
use COREABC_LIB.Top_Waveform_COREABC_0_SUPPOrt.all;
entity Top_Waveform_COREABC_0_instructNVM is
generic (MAX_NVMDwidth: INTeger range 16 to 32;
AWIDTH: INTEGer range 1 to 16;
dwidTH: inTEGER range 8 to 32;
Swidth: integer range 0 to 4;
Icwidth: Integer range 1 to 16;
icdePTH: iNTEGER range 1 to 65536;
iwwidth: integER range 1 to 64;
act_caliBRATIONData: integer range 0 to 1;
imem_apb_ACCESS: INTEGer range 0 to 2;
uniq_strinG_LENGTH: INTEGer range 1 to 256 := 10); port (cLK: in STD_logic;
rSTN: in std_logic;
starT: in Std_logic;
Stall: out STD_logic;
ADDRESs: in STD_Logic_vectoR(ICWIDTH-1 downto 0);
InstructioN: out STD_LOgic_vector(Iwwidth-1 downto 0);
pSEL: in STD_logic;
PENAble: in STD_logic;
pwrITE: in std_loGIC;
PAddr: in std_loGIC_VECTor(awidth-1 downto 0);
Pwdata: in Std_logic_vECTOR(DWIDth-1 downto 0);
PRDATA: out STD_logic_vectOR(dwidtH-1 downto 0);
pslverr: out STD_LOGic;
PREady: out STD_LOGIc);
end Top_Waveform_COREABC_0_instructnVM;

architecture ABColoI of Top_Waveform_COREABC_0_INSTRUctnvm is

begin
end ABCOLOI;
