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    #Build: Synplify Pro D-2009.12A, Build 040R, Jan 20 2010
    #install: D:\Actel\Libero_v9.0\Synopsys\synplify_D200912A
    #OS: Windows XP 5.1
    #Hostname: WXPL-ODIGAS

    #Implementation: synthesis

    #Tue Aug 31 16:23:11 2010

    $ Start of Compile
    #Tue Aug 31 16:23:11 2010

    Synopsys Verilog Compiler, version comp475rc, Build 060R, built Jan 15 2010
    Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved

    @I::"D:\Actel\Libero_v9.0\Synopsys\synplify_D200912A\lib\proasic\smartfusion.v"
    @I::"D:\DATA\PROJECTS\Waveform_Gen\Hardware\A2F200\Verilog\Waveform_Gen\component\Actel\SmartFusionMSS\MSS\2.2.101\mss_comps.v"
    @I::"D:\DATA\PROJECTS\Waveform_Gen\Hardware\A2F200\Verilog\Waveform_Gen\component\work\MSS_Waveform\MSS_CCC_0\MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v"
    @I::"D:\DATA\PROJECTS\Waveform_Gen\Hardware\A2F200\Verilog\Waveform_Gen\component\work\MSS_Waveform\MSS_Waveform.v"
    @I::"D:\DATA\PROJECTS\Waveform_Gen\Hardware\A2F200\Verilog\Waveform_Gen\component\work\Top_Waveform\Top_Waveform.v"
    Verilog syntax check successful!
    Options changed - recompiling
    Selecting top level module Top_Waveform
    @N:CG364 : smartfusion.v(1814) | Synthesizing module VCC

    @N:CG364 : mss_comps.v(23) | Synthesizing module INBUF_MSS

    @N:CG364 : smartfusion.v(2614) | Synthesizing module OUTBUF_A

    @N:CG364 : mss_comps.v(37) | Synthesizing module OUTBUF_MSS

    @N:CG364 : mss_comps.v(151) | Synthesizing module MSS_CCC

    @N:CG364 : mss_comps.v(1) | Synthesizing module MSS_XTLOSC

    @N:CG364 : smartfusion.v(1133) | Synthesizing module GND

    @N:CG364 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(5) | Synthesizing module MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC

    @N:CG364 : mss_comps.v(680) | Synthesizing module MSS_APB

    @N:CG364 : smartfusion.v(2609) | Synthesizing module INBUF_A

    @N:CG364 : MSS_Waveform.v(5) | Synthesizing module MSS_Waveform

    @N:CG364 : Top_Waveform.v(5) | Synthesizing module Top_Waveform

    @W:CL168 : Top_Waveform.v(26) | Pruning instance GND - not in use ...

    @W:CL168 : Top_Waveform.v(22) | Pruning instance VCC - not in use ...

    @W:CL157 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(62) | *Output RCOSC_CLKOUT has undriven bits - a simulation mismatch is possible
    @W:CL157 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(63) | *Output MAINXIN_CLKOUT has undriven bits - a simulation mismatch is possible
    @W:CL157 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(64) | *Output LPXIN_CLKOUT has undriven bits - a simulation mismatch is possible
    @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(36) | Input CLKA is unused
    @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(37) | Input CLKA_PAD is unused
    @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(38) | Input CLKA_PADP is unused
    @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(39) | Input CLKA_PADN is unused
    @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(40) | Input CLKB is unused
    @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(41) | Input CLKB_PAD is unused
    @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(42) | Input CLKB_PADP is unused
    @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(43) | Input CLKB_PADN is unused
    @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(44) | Input CLKC is unused
    @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(45) | Input CLKC_PAD is unused
    @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(46) | Input CLKC_PADP is unused
    @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(47) | Input CLKC_PADN is unused
    @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(49) | Input LPXIN is unused
    @W:CL159 : MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC.v(50) | Input MAC_CLK is unused
    @END
    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Tue Aug 31 16:23:12 2010

    ###########################################################]
    Synopsys Actel Technology Mapper, Version map500act, Build 058R, Built Jan 18 2010 09:16:23
    Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved
    Product Version D-2009.12A
    @N:MF249 :  | Running in 32-bit mode.
    @N:MF258 :  | Gated clock conversion disabled

    @W:MO111 : mss_waveform_tmp_mss_ccc_0_mss_ccc.v(62) | tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC)
    @W:MO111 : mss_waveform_tmp_mss_ccc_0_mss_ccc.v(63) | tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC)
    @W:MO111 : mss_waveform_tmp_mss_ccc_0_mss_ccc.v(64) | tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC)
    Automatic dissolve at startup in view:work.MSS_Waveform(verilog) of MSS_CCC_0(MSS_Waveform_tmp_MSS_CCC_0_MSS_CCC)
    Automatic dissolve at startup in view:work.Top_Waveform(verilog) of MSS_Waveform_0(MSS_Waveform)

    Available hyper_sources - for debug and ip models
    	None Found

    Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB)

    Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB)

    Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB)

    Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB)

    Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB)

    Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB)

    Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB)

    Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB)

    Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB)

    Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB)

    Added 0 Buffers
    Added 0 Cells via replication
    	Added 0 Sequential Cells via replication
    	Added 0 Combinational Cells via replication
    Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 57MB)

    Writing Analyst data base D:\DATA\PROJECTS\Waveform_Gen\Hardware\A2F200\Verilog\Waveform_Gen\synthesis\Top_Waveform.srm
    Finished Writing Netlist Databases (Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB)

    Writing EDIF Netlist and constraint files
    D-2009.12A
    Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB)

    @W:MT246 : mss_waveform.v(44) | Blackbox MSS_APB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT246 : mss_waveform_tmp_mss_ccc_0_mss_ccc.v(98) | Blackbox MSS_XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Tue Aug 31 16:23:14 2010
    #

    Top view:               Top_Waveform
    Library name:           smartfusion
    Operating conditions:   COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree )
    Requested Frequency:    100.0 MHz
    Wire load mode:         top
    Wire load model:        smartfusion
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report estimates place and route data. Please look at the place and route timing report for final timing..

    @N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock..

    Performance Summary
    *******************

    Worst slack in design: 4.169

                       Requested     Estimated     Requested     Estimated               Clock      Clock
    Starting Clock     Frequency     Frequency     Period        Period        Slack     Type       Group
    ----------------------------------------------------------------------------------------------------------------
    System             100.0 MHz     171.5 MHz     10.000        5.831         4.169     system     default_clkgroup
    ================================================================================================================

    Interface Information
    *********************

    		No IO constraint found

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                          Starting                                                          Arrival
    Instance                              Reference     Type           Pin        Net                       Time        Slack
                                          Clock
    -------------------------------------------------------------------------------------------------------------------------
    MSS_Waveform_0.MSS_CCC_0.I_XTLOSC     System        MSS_XTLOSC     CLKOUT     N_CLKA_XTLOSC             0.000       4.169
    MSS_Waveform_0.MSS_ACE_0_VAREF0       System        INBUF_A        Y          MSS_ACE_0_VAREF0_Y        0.000       9.678
    MSS_Waveform_0.MSS_ADLIB_INST         System        MSS_APB        EMCCLK     MSS_ADLIB_INST_EMCCLK     0.000       9.678
    MSS_Waveform_0.MSS_ADLIB_INST         System        MSS_APB        SDD0       MSS_ACE_0_SDD0_D          0.000       9.678
    =========================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                      Starting                                                            Required
    Instance                          Reference     Type         Pin           Net                        Time         Slack
                                      Clock
    ------------------------------------------------------------------------------------------------------------------------
    MSS_Waveform_0.MSS_ADLIB_INST     System        MSS_APB      PLLLOCK       MSS_ADLIB_INST_PLLLOCK     10.000       4.169
    MSS_Waveform_0.MSS_ADLIB_INST     System        MSS_APB      FCLK          MSS_ADLIB_INST_FCLK        10.000       4.491
    MSS_Waveform_0.MSS_ACE_0_SDD0     System        OUTBUF_A     D             MSS_ACE_0_SDD0_D           10.000       9.678
    MSS_Waveform_0.MSS_ADLIB_INST     System        MSS_APB      EMCCLKRTN     MSS_ADLIB_INST_EMCCLK      10.000       9.678
    MSS_Waveform_0.MSS_ADLIB_INST     System        MSS_APB      VAREF0        MSS_ACE_0_VAREF0_Y         10.000       9.678
    ========================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            0.000
        + Clock delay at ending point:           0.000 (ideal)
        + Estimated clock delay at ending point: 0.000
        = Required time:                         10.000

        - Propagation time:                      5.831
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (critical) :                     4.169

        Number of logic level(s):                1
        Starting point:                          MSS_Waveform_0.MSS_CCC_0.I_XTLOSC / CLKOUT
        Ending point:                            MSS_Waveform_0.MSS_ADLIB_INST / PLLLOCK
        The start point is clocked by            System [rising]
        The end   point is clocked by            System [rising]

    Instance / Net                                       Pin         Pin               Arrival     No. of
    Name                                  Type           Name        Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------------------------------
    MSS_Waveform_0.MSS_CCC_0.I_XTLOSC     MSS_XTLOSC     CLKOUT      Out     0.000     0.000       -
    N_CLKA_XTLOSC                         Net            -           -       0.322     -           1
    MSS_Waveform_0.MSS_CCC_0.I_MSSCCC     MSS_CCC        CLKA        In      -         0.322       -
    MSS_Waveform_0.MSS_CCC_0.I_MSSCCC     MSS_CCC        LOCKMSS     Out     5.188     5.509       -
    MSS_ADLIB_INST_PLLLOCK                Net            -           -       0.322     -           1
    MSS_Waveform_0.MSS_ADLIB_INST         MSS_APB        PLLLOCK     In      -         5.831       -
    =========================================================================================================
    Total path delay (propagation time + setup) of 5.831 is 5.188(89.0%) logic and 0.643(11.0%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    --------------------------------------------------------------------------------
    Target Part: A2F200M3F_FBGA256_Std
    Report for cell Top_Waveform.verilog
      Core Cell usage:
                  cell count     area count*area
                   GND     3      0.0        0.0
               MSS_APB     1      0.0        0.0
               MSS_CCC     1      0.0        0.0
                   VCC     3      0.0        0.0

                       -----          ----------
                 TOTAL     8                 0.0

      IO Cell usage:
                  cell count
               INBUF_A     1
             INBUF_MSS     2
            MSS_XTLOSC     1
              OUTBUF_A     1
            OUTBUF_MSS     1
                       -----
                 TOTAL     6

    Core Cells         : 0 of 4608 (0%)
    IO Cells           : 6 of 66 (9%)

      RAM/ROM Usage Summary
    Block Rams : 0 of 8 (0%)

    Mapper successful!
    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Tue Aug 31 16:23:14 2010

    ###########################################################]

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