`timescale 1ns/100ps
// Copyright 2008 Actel Corporation.  All rights reserved.
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
// Rev: 2.4   24Jan08 IPB  : Production Release
// SVN Revision Information:
// SVN $Revision: 11083 $
module
Top_Waveform_COREABC_0_IRAM512X9
(
RWCLK
,
RESET
,
RENABLE
,
RADDR
,
RD
,
INITADDR
,
WENABLE
,
INITDATA
)
;
parameter
CID
=
0
;
parameter
RID
=
0
;
parameter
UNIQ_STRING_LENGTH
=
10
;
input
RWCLK
;
input
RESET
;
input
RENABLE
;
input
[
8
:
0
]
RADDR
;
output
[
8
:
0
]
RD
;
wire
[
8
:
0
]
RD
;
input
[
8
:
0
]
INITADDR
;
input
WENABLE
;
input
[
8
:
0
]
INITDATA
;
wire
ABCOI10
;
wire
ABCII10
;
wire
ABCOI0l
;
wire
ABCII0l
;
localparam
[
1
:
(
10
)
*
8
]
ABCOO0l
=
"0123456789"
;
localparam
[
1
:
(
UNIQ_STRING_LENGTH
+
11
)
*
8
]
ABClI0l
=
{
"Top_Waveform_COREABC_0_RAM_"
,
ABCOO0l
[
RID
*
8
+
1
:
RID
*
8
+
8
]
,
ABCOO0l
[
CID
*
8
+
1
:
CID
*
8
+
8
]
,
".mem"
}
;
assign
ABCOI0l
=
1
'b
1
;
assign
ABCII0l
=
1
'b
0
;
assign
ABCII10
=
~
RENABLE
;
assign
ABCOI10
=
~
WENABLE
;
// synthesis translate_off
// synthesis translate_on
RAM4K9
#
(
.MEMORYFILE
(
ABClI0l
)
)
ABCll0l
(
.ADDRA11
(
ABCII0l
)
,
.ADDRA10
(
ABCII0l
)
,
.ADDRA9
(
ABCII0l
)
,
.ADDRA8
(
INITADDR
[
8
]
)
,
.ADDRA7
(
INITADDR
[
7
]
)
,
.ADDRA6
(
INITADDR
[
6
]
)
,
.ADDRA5
(
INITADDR
[
5
]
)
,
.ADDRA4
(
INITADDR
[
4
]
)
,
.ADDRA3
(
INITADDR
[
3
]
)
,
.ADDRA2
(
INITADDR
[
2
]
)
,
.ADDRA1
(
INITADDR
[
1
]
)
,
.ADDRA0
(
INITADDR
[
0
]
)
,
.ADDRB11
(
ABCII0l
)
,
.ADDRB10
(
ABCII0l
)
,
.ADDRB9
(
ABCII0l
)
,
.ADDRB8
(
RADDR
[
8
]
)
,
.ADDRB7
(
RADDR
[
7
]
)
,
.ADDRB6
(
RADDR
[
6
]
)
,
.ADDRB5
(
RADDR
[
5
]
)
,
.ADDRB4
(
RADDR
[
4
]
)
,
.ADDRB3
(
RADDR
[
3
]
)
,
.ADDRB2
(
RADDR
[
2
]
)
,
.ADDRB1
(
RADDR
[
1
]
)
,
.ADDRB0
(
RADDR
[
0
]
)
,
.DINA8
(
INITDATA
[
8
]
)
,
.DINA7
(
INITDATA
[
7
]
)
,
.DINA6
(
INITDATA
[
6
]
)
,
.DINA5
(
INITDATA
[
5
]
)
,
.DINA4
(
INITDATA
[
4
]
)
,
.DINA3
(
INITDATA
[
3
]
)
,
.DINA2
(
INITDATA
[
2
]
)
,
.DINA1
(
INITDATA
[
1
]
)
,
.DINA0
(
INITDATA
[
0
]
)
,
.DINB8
(
ABCII0l
)
,
.DINB7
(
ABCII0l
)
,
.DINB6
(
ABCII0l
)
,
.DINB5
(
ABCII0l
)
,
.DINB4
(
ABCII0l
)
,
.DINB3
(
ABCII0l
)
,
.DINB2
(
ABCII0l
)
,
.DINB1
(
ABCII0l
)
,
.DINB0
(
ABCII0l
)
,
.WIDTHA0
(
ABCOI0l
)
,
.WIDTHA1
(
ABCOI0l
)
,
.WIDTHB0
(
ABCOI0l
)
,
.WIDTHB1
(
ABCOI0l
)
,
.PIPEA
(
ABCII0l
)
,
.PIPEB
(
ABCII0l
)
,
.WMODEA
(
ABCII0l
)
,
.WMODEB
(
ABCII0l
)
,
.BLKA
(
ABCOI10
)
,
.BLKB
(
ABCII10
)
,
.WENA
(
ABCII0l
)
,
.WENB
(
ABCOI0l
)
,
.CLKA
(
RWCLK
)
,
.CLKB
(
RWCLK
)
,
.RESET
(
RESET
)
,
.DOUTA8
(
)
,
.DOUTA7
(
)
,
.DOUTA6
(
)
,
.DOUTA5
(
)
,
.DOUTA4
(
)
,
.DOUTA3
(
)
,
.DOUTA2
(
)
,
.DOUTA1
(
)
,
.DOUTA0
(
)
,
.DOUTB8
(
RD
[
8
]
)
,
.DOUTB7
(
RD
[
7
]
)
,
.DOUTB6
(
RD
[
6
]
)
,
.DOUTB5
(
RD
[
5
]
)
,
.DOUTB4
(
RD
[
4
]
)
,
.DOUTB3
(
RD
[
3
]
)
,
.DOUTB2
(
RD
[
2
]
)
,
.DOUTB1
(
RD
[
1
]
)
,
.DOUTB0
(
RD
[
0
]
)
)
;
endmodule
