-- Copyright 2008 Actel Corporation.  All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
-- Rev: 2.4   24Jan08 IPB  : Production Release
-- SVN Revision Information:
-- SVN $Revision: 14578 $
library Ieee;
use Ieee.std_LOgic_1164.all;
use IEEE.STD_logic_aritH.all;
use iEEE.std_logic_UNSIGNEd.all;
library COREABC_LIB;
use COREABC_LIB.Top_Waveform_COREABC_0_sUPPORT.all;
-- synthesis translate_off
use COREABC_LIB.Top_Waveform_COREABC_0_tEXTIO.all;
-- synthesis translate_on
entity Top_Waveform_COREABC_0_DEBUGBLK is
generic (debug: integer range 0 to 1;
awidtH: INTEGER range 1 to 16;
DWIDth: INTEGEr range 8 to 32;
SWIDTH: INTEGER range 0 to 4;
sdepth: Integer range 1 to 16;
iCWIDTH: INTEGER range 1 to 16;
ICDEPTH: INTEGER range 1 to 65536;
ZRWidth: INTEGER range 0 to 16;
iiwIDTH: Integer range 1 to 32;
IOWIDth: INTEGER range 1 to 32;
irwidtH: INTEger range 1 to 32;
en_mULT: Integer range 0 to 3); port (pclk: in std_LOGIC;
RESETN: in std_LOGIC;
isr: in stD_LOGIC;
SMaddr: in STD_logic_vectOR(ICWIDTH-1 downto 0);
inSTR_CMD: in std_lOGIC_VECtor(2 downto 0);
Instr_scmd: in STD_Logic_vectoR(2 downto 0);
instr_DATA: in STD_logic_vectOR(dWIDTH-1 downto 0);
INSTR_ADdr: in std_LOGIC_Vector(awidth-1 downto 0);
iNSTR_slot: in stD_LOGIC_vector(SWIdth downto 0);
PRDATa: in sTD_LOGIC_vector(DWIDth-1 downto 0);
pwdata: in std_logIC_VECTOr(DWIDTh-1 downto 0);
ACCUM_Old: in sTD_LOGIC_vector(DWIDTH-1 downto 0);
accum_nEW: in std_loGIC_Vector(DWIDTh-1 downto 0);
ACcum_zerO: in sTD_Logic;
ACCUM_neg: in STD_Logic;
FLAGS: in std_loGIC;
rAMDOUt: in std_logIC_VEctor(dWIDTH-1 downto 0);
stKPTR: in stD_LOGic_vectOR(7 downto 0);
ZREGister: in STD_logic_VECTor(ZRWIDTH downto 0);
ACmdo: in STD_logic;
debug1: in std_LOGIC;
deBUG2: in sTD_LOGic);
end Top_Waveform_COREABC_0_dEBUGBlk;

architecture RTL of Top_Waveform_COREABC_0_DEBUgblk is

-- synthesis translate_off
function ABCL(X: stD_LOGIc_vectOR;
b: STD_logic)
return integer is
variable ABCi: integeR;
begin
for ABCOL in x'range
loop
if x(ABCol) = B then
ABCI := ABCOl;
end if;
end loop;
return (ABCI);
end ABCl;

function ABCLl(ABCiL,ABCoI: Std_logiC_VECTor;
ABCli: inTEGER range 0 to 7;
ABCii: std_LOGIC_vector;
ABCo0: std_lOGIC;
ADDR: std_lOGIC_vector)
return stRING is
variable ABCl0: STD_logic_vECTOR(2 downto 0);
variable ABCi0: sTRINg(1 to 80);
variable ABCO1: Integer;
begin
case ABCii(1 downto 0) is
when "00" =>
ABCo1 := 0;
when "01" =>
ABCo1 := 1;
when "10" =>
ABCo1 := 14;
when others =>
ABCo1 := 15;
end case;
if ABCo0 /= '1' then
case ABCli is
when 0 =>
if EN_MULT = 0 then
SPrintf(ABCi0,
"ACCUM %02x <= %02x INC",
FMT(ABCil)&Fmt(ABCOI));
else
SPRINtf(ABCi0,
"ACCUM %02x <= %02x MULT %02x",
FMT(ABCil)&FMT(ABCoi)&FMT(ABCii));
end if;
when 1 =>
sPRINTF(ABCI0,
"ACCUM %02x <= %02x AND %02x",
fmt(ABCil)&fmt(ABCOi)&fmt(ABCII));
when 2 =>
sprintf(ABCI0,
"ACCUM %02x <= %02x OR  %02x",
fMT(ABCil)&fmt(ABCoi)&FMT(ABCII));
when 3 =>
Sprintf(ABCI0,
"ACCUM %02x <= %02x XOR %02x",
FMT(ABCIL)&Fmt(ABCoi)&FMT(ABCii));
when 4 =>
sprINTF(ABCi0,
"ACCUM %02x <= %02x ADD %02x",
fmt(ABCil)&Fmt(ABCOi)&fMT(ABCii));
when 5 =>
if ABCo1 = 15 then
sprintf(ABCI0,
"ACCUM %02x <= %02x ROL",
FMT(ABCIl)&FMT(ABCOI));
else
Sprintf(ABCI0,
"ACCUM %02x <= %02x SHL%x",
FMT(ABCIL)&fmT(ABCoi)&FMT(ABCO1));
end if;
when 6 =>
if ABCO1 = 15 then
Sprintf(ABCI0,
"ACCUM %02x <= %02x ROR",
fmt(ABCIl)&FMt(ABCOI));
else
SPrintf(ABCI0,
"ACCUM %02x <= %02x SHR%x",
fmt(ABCil)&FMT(ABCOI)&fmt(ABCO1));
end if;
when 7 =>
sprINTF(ABCI0,
"LOAD %02x",
fmt(ABCii));
when others =>
SPRIntf(ABCI0,
"UNEXPECTED INSTRUCTION");
end case;
else
case ABCli is
when 0 =>
if EN_MULT > 0 then
SPRINTF(ABCi0,
"ACCUM %02x <= %02x MULT RAM(%d) %02x",
FMT(ABCIL)&fmt(ABCoi)&Fmt(aDDR)&fmt(ABCii));
end if;
when 1 =>
SPRINTF(ABCI0,
"ACCUM %02x <= %02x AND RAM(%d) %02x",
fmt(ABCiL)&FMT(ABCOi)&fmt(addr)&Fmt(ABCII));
when 2 =>
sprintF(ABCi0,
"ACCUM %02x <= %02x OR  RAM(%d) %02x",
fmt(ABCIL)&FMT(ABCOI)&FMT(addr)&FMT(ABCII));
when 3 =>
sprintf(ABCI0,
"ACCUM %02x <= %02x XOR RAM(%d) %02x",
fmt(ABCil)&FMt(ABCoi)&fmt(addr)&FMT(ABCII));
when 4 =>
sPRINTF(ABCi0,
"ACCUM %02x <= %02x ADD RAM(%d) %02x",
FMT(ABCil)&fmt(ABCoi)&fmt(ADDr)&fmt(ABCiI));
when 7 =>
spRINTF(ABCi0,
"LOAD RAM(%d) %02x",
Fmt(ADdr)&fMT(ABCii));
when others =>
SPrintf(ABCi0,
"UNEXPECTED INSTRUCTION");
end case;
end if;
return (ABCI0);
end ABCLL;

function ABCL1(ABCil,ABCoi: STD_logic_vectOR;
ABCli: INTEGer range 0 to 7;
ABCII: Std_logic_VECTOR;
ABCO0: STD_logic;
ADdr: Std_logic_veCTOR)
return sTRING is
variable ABCL0: std_logIC_VECTOr(2 downto 0);
variable ABCI0: strING(1 to 16);
variable ABCo1: INTEGER;
begin
if ABCo0 /= '1' then
case ABCLI is
when 1 =>
sprintF(ABCI0,
"BITTST (%02x) %d",
fMT(ABCOI)&FMT(ABCl(ABCii,
'1')));
when 3 =>
sprintf(ABCI0,
"CMP (%02x) to %02x",
Fmt(ABCoi)&Fmt(ABCii));
when 4 =>
SPRINTF(ABCi0,
"CMPLEQ (%02x) %02x",
Fmt(ABCOI)&FMT(ABCii));
when others =>
sprintf(ABCI0,
"UNEXPECTED INSTRUCTION");
end case;
else
case ABCLI is
when 3 =>
sprintf(ABCi0,
"CMP (%02x) RAM(%d) %02x",
FMT(ABCoi)&FMT(ADDR)&fmt(ABCii));
when others =>
SPRIntf(ABCi0,
"UNEXPECTED INSTRUCTION");
end case;
end if;
return (ABCI0);
end ABCl1;

function ABCI1(ABCool,ABCLi: std_logic_VECTOR;
IIWIDTH: INTEGER)
return striNG is
variable ABCi0: STRINg(1 to 80);
begin
if ABCOOL(0) = '1' then
if ABCLI(0) = '1' then
spriNTF(ABCI0,
"ALWAYS");
else
SPRIntf(ABCI0,
"NEVER");
end if;
else
sPRINTF(ABCi0,
"");
if ABCLI(0) = '0' then
sprintf(ABCI0,
"NOTIF");
else
SPRINtf(ABCI0,
"IF");
end if;
if ABCooL(1) = '1' then
SPRIntf(ABCI0,
"%s ZERO",
FMT(ABCi0));
end if;
if ABCool(2) = '1' then
sprintf(ABCI0,
"%s NEG",
fmt(ABCi0));
end if;
if ABCool(3) = '1' then
SPRINTF(ABCi0,
"%s LCZERO",
fmt(ABCi0));
end if;
for ABCol in 0 to min(IIWIDTH,
ABCool'left+1-4)-1
loop
if ABCool(4+ABCol) = '1' then
sprintf(ABCi0,
"%s INPUT%d",
fMT(ABCi0)&fmT(ABCOL));
end if;
end loop;
end if;
return (ABCi0);
end ABCI1;

function ABCLOL(ACC: sTD_LOGIc_vector)
return striNG is
variable ABCi0: striNG(1 to 4);
begin
if ACC = 0 then
ABCI0 := "ZERO";
elsif ACC(dwidTH-1) = '1' then
ABCi0 := "NEG ";
else
ABCi0 := "POS ";
end if;
return (ABCi0);
end ABCLol;

function ABCIOL(flaGS: std_logic;
ABCII: STD_LOgic_vector)
return STRIng is
variable ABCi0: string(1 to 4);
begin
if ABCii(0) = '1' then
return (" ");
elsif FLAgs = '1' then
return (" (taken)");
else
return (" (not taken)");
end if;
end ABCiOL;

function ABColl(ABCil,ABCOI: STD_LOGIc_vector;
ABCLLL,ABCILL,ABCOIL,Addr,ABCii,stkptr,zregisTER: std_lOGIC_VECtor;
ABCLIL: Integer;
Acmdo: std_LOGIC;
flagS: STd_logic)
return stRING is
variable ABCiil,ABClI: INTEGER range 0 to 7;
variable ABCI0: STRing(1 to 40);
variable ABCo0: std_logic;
variable ABCo0l: STD_logic_vectOR(ABCii'range );
variable ABCL0L,ABCI0L: STD_LOgic_vector(ABCii'range );
begin
ABCl0l := ( others => '0');
ABCl0l(0) := '1';
ABCi0l := ( others => '1');
ABCO0l := 0-CLEAn(ABCii);
ABCIil := 0;
ABCli := 0;
ABCo0 := ABCOil(0);
for ABCol in 0 to 2
loop
if ABClLL(ABCoL) = '1' then
ABCiil := ABCiiL+2**ABCol;
end if;
if ABCILl(ABCol) = '1' then
ABCli := ABCLI+2**ABCol;
end if;
end loop;
case ABCiil is
when 0 =>
SPRintf(ABCi0,
"%s",
FMT(ABCll(ABCIL,
ABCoi,
ABCli,
ABCii,
ABCo0,
Addr)));
when 1 =>
Sprintf(ABCi0,
"%s",
Fmt(ABCl1(ABCil,
ABCOI,
ABCLi,
ABCii,
ABCo0,
ADDR)));
when 2 =>
case ABCli is
when 0 =>
sprINTF(ABCI0,
"APBWRT ACC %d:%02x = %02x",
fMT(ABCOIL)&fmt(ADDR)&fmt(ABCII));
when 1 =>
sprintf(ABCI0,
"APBWRT DAT %d:%02x = %02x",
fMT(ABCOil)&Fmt(ADdr)&fmt(ABCII));
when 2 =>
if ACMDO = '1' then
SPRINTF(ABCI0,
"APBWRT ACM %d:%02x = %02x",
FMT(ABCoil)&fmt(Addr)&FMt(ABCii(7 downto 0)));
else
SPrintf(ABCi0,
"APBWRT ACM %d:%02x (No Write)",
Fmt(ABCoIL)&fmt(ADDR));
end if;
when 3 =>
Sprintf(ABCi0,
"APBREAD %d:%02x = %02x",
fmt(ABCoil)&FMT(Addr)&FMT(ABCii));
when 4 =>
Sprintf(ABCI0,
"APBWRTZ ACC %d:Z(%02x) = %02x",
FMT(ABCoil)&fmt(zregisTER)&FMT(ABCII));
when 5 =>
SPRINtf(ABCI0,
"APBWRTZ DAT %d:Z(%02x) = %02x",
FMT(ABCoil)&fmt(ZRegister)&fmt(ABCII));
when 6 =>
if Acmdo = '1' then
SPRINTF(ABCI0,
"APBWRTZ ACM %d:Z(%02x) = %02x",
FMT(ABCOIL)&fmt(Zregister)&FMT(ABCII(7 downto 0)));
else
sprintF(ABCi0,
"APBWRTZ ACM %d:Z(%02x) (No Write)",
FMT(ABCoil)&FMT(Zregister));
end if;
when 7 =>
Sprintf(ABCi0,
"APBREADZ %d:Z(%02x) = %02x",
FMt(ABCOil)&fmt(Zregister)&Fmt(ABCII));
when others =>
sprintf(ABCI0,
"UNEXPECTED INSTRUCTION");
end case;
when 3 =>
case ABCLI is
when 0 =>
if ABCo0 /= '1' then
sprINTF(ABCI0,
"LOADZ DAT %02x",
fmt(ABCII));
else
sPRINTF(ABCi0,
"LOADZ ACC %02x",
FMT(ABCoi));
end if;
when 1 =>
if ABCO0 = '0' then
if ABCii = ABCl0l then
Sprintf(ABCi0,
"INCZ <= %02x +1 ",
fMT(ZREgister));
elsif ABCii = ABCi0L then
SPRintf(ABCi0,
"DECZ <= %02x -1",
FMT(zregisteR));
elsif ABCII(ABCII'LEFT) = '0' then
sprintf(ABCI0,
"ADDZ <= %02x + %02x",
FMT(ZREGIster)&fmt(ABCii));
else
sprintf(ABCi0,
"SUBZ <= %02x - %02x",
FMT(zregister)&fmt(ABCo0l));
end if;
else
sprINTF(ABCi0,
"ADDZ <= %02x + ACC(%02x)",
Fmt(zreGISTER)&fmT(ABCOI));
end if;
when 6 =>
SPRINTF(ABCI0,
"IOREAD %02x ",
fmt(ABCil));
when 7 =>
if ABCO0 /= '1' then
Sprintf(ABCi0,
"IOWRT DAT %02x ",
FMT(ABCii));
else
SPRINTF(ABCI0,
"IOWRT ACC %02x ",
fmt(ABCoi));
end if;
when 3 =>
sprintf(ABCi0,
"RAMREAD %02x = %02x",
fmt(addR)&Fmt(ABCil));
when 2 =>
if ABCO0 /= '1' then
Sprintf(ABCI0,
"RAMWRITE DAT %02x = %02x",
fmt(ADdr)&fmt(ABCII));
else
sprINTF(ABCi0,
"RAMWRITE ACC %02x = %02x",
FMT(adDR)&FMT(ABCii));
end if;
when 4 =>
if ABCO0 /= '1' then
SPRINTF(ABCI0,
"PUSH DAT %02x (SP=%02x)",
FMT(ABCII)&FMT(Stkptr));
else
sprintf(ABCI0,
"PUSH ACC %02x (SP=%02x)",
fmt(ABCoi)&FMT(STKPtr));
end if;
when 5 =>
spriNTF(ABCi0,
"POP  %02x (SP=%02x)",
fmt(ABCil)&fmt(stkPTR));
when others =>
sprintf(ABCi0,
"UNEXPECTED INSTRUCTION");
end case;
when 4 =>
if ABCILL(1) = '0' then
SPRintf(ABCi0,
"JUMP %s %d %s",
fmt(ABCI1(ABCii,
ABCILL,
IIWIDTH))&fMT(addr)&FMT(ABCIOl(FLAGS,
ABCii)));
else
SPRINtf(ABCi0,
"WAIT %s %s",
FMT(ABCi1(ABCii,
ABCill,
IIWIDTH))&fmt(ABCIOL(flags,
ABCII)));
end if;
when 5 =>
SPRINTf(ABCI0,
"CALL %s %d %s (SP=%02x)",
FMT(ABCI1(ABCii,
ABCill,
IIWIDTH))&Fmt(addR)&fMT(ABCiol(flAGS,
ABCii))&FMT(sTKPTR));
when 6 =>
if ABCILL(1) = '0' then
sprintf(ABCi0,
"RETURN %s  %s (SP=%02x)",
fmt(ABCi1(ABCii,
ABCIll,
IIWIDTH))&FMT(ABCiol(FLAGS,
ABCii))&fmt(stkptr));
else
sPRINTF(ABCi0,
"RETISR %s  %s (SP=%02x)",
fmt(ABCi1(ABCii,
ABCill,
IIWIDTH))&FMT(ABCIOl(flags,
ABCiI))&Fmt(sTKPTR));
end if;
when 7 =>
SPRINTF(ABCi0,
"NOP");
when others =>
SPRINtf(ABCI0,
"NOT DONE");
end case;
return (ABCi0);
end ABColl;

function ABCo1l(ABClll,ABCill,ABCl1l: std_LOGIC_VEctor)
return INTEGEr is
variable ABCIIL,ABCli: Integer range 0 to 7;
variable ABCI1l: inTEGER;
begin
ABCiil := 0;
ABCli := 0;
for ABCol in 0 to 2
loop
if ABCLLl(ABCOL) = '1' then
ABCIil := ABCiil+2**ABCOL;
end if;
if ABCILL(ABCol) = '1' then
ABCli := ABCli+2**ABCol;
end if;
end loop;
ABCI1l := 1;
case ABCiiL is
when 0 =>
if ABCl1l(0) = '1' then
ABCI1L := 3;
end if;
when 1 =>
if ABCL1L(0) = '1' then
ABCI1L := 3;
end if;
when 2 =>
if ABCli = 2 or ABCli = 6 then
ABCi1l := 4;
elsif ABCLI = 3 or ABCli = 7 then
ABCi1l := 2;
end if;
when 3 =>
if ABCLI = 3 or ABCli = 5 then
ABCi1l := 3;
end if;
when others =>
end case;
return (ABCi1l);
end ABCo1l;

function ABCOOI(ABCii: Std_logic_VECTOR)
return STD_logic_veCTOR is
variable ABCloi: std_logiC_VECTOR(ABCiI'range );
begin
ABClOI := ( others => '0');
for ABCOl in ABCLOI'range
loop
if ABCIi(ABCol) = '1' then
ABCloi(ABCOL) := '1';
end if;
end loop;
return (ABCloi);
end ABCooi;

signal ABCioi: Std_logic_vECTOR(7 downto 0);

signal ABCOli: STD_logic_vectOR(7 downto 0);

signal ABClli: Std_logic;

-- synthesis translate_on
begin
-- synthesis translate_off
ABCioi <= clean(STKPTR)-1;
ABColi <= CLean(STKPTR)+1;
process
begin
wait for 1 Ns;
printf("# INFO COREABC VHDL Disassembler");
wait;
end process;
process (PCLK)
variable ABCil: std_logIC_VECTor(DWIDTH-1 downto 0);
variable ABCoi: STD_LOGic_vector(Dwidth-1 downto 0);
variable ABCili: STd_logic := '0';
variable ABCOIi: STD_LOGic := '0';
variable ADdr: std_loGIC_VECTor(AWIDTH-1 downto 0);
variable ABCII: STD_Logic_vectoR(DWIDTH-1 downto 0);
variable ABCLII: STD_Logic;
variable ABCi1l: integer;
begin
if PCLK'event and PCLK = '1'
and DEBUG = 1
and RESETN = '1' then
ABCLLi <= debug1;
ABCIL := accum_neW;
ABCOI := Accum_old;
ABCilI := ABCoii;
ABCoii := ISr;
ABCLII := iNSTR_SLot(0);
if INSTR_cmd(2 downto 1) = "00" and ABClii = '1' then
ABCII := ABCOOI(Ramdout);
else
ABCii := ABCOOI(inSTR_DATA);
end if;
ADDR := ABCooi(INSTR_addr);
if ABCOII = '1' and ABCili = '0' then
printf("Entering ISR: (SP=%02x)",
FMT(STKPTR));
end if;
if ABCOII = '0' and ABCILI = '1' then
printf("Exiting ISR: (SP=%02x)",
fmt(stkptr));
end if;
ABCI1l := ABCo1l(instr_cMD,
instr_SCMD,
instR_SLOT);
if debUG1 = '1' then
if ABCi1l = 1 then
printF("INS:%d: %s",
FMT(smaddR)&FMT(ABColl(ABCil,
ABCoi,
Instr_cmd,
INSTR_scmd,
instr_SLOT,
Addr,
ABCII,
STKPtr,
ZREGIster,
IIWIDTH,
acmdo,
flags)));
end if;
end if;
if ABClli = '1' then
if ABCi1l = 3 then
PRINTF("INS:%d: %s",
Fmt(smaddR)&fmt(ABColl(ABCil,
ABCoi,
instr_cMD,
iNSTR_SCmd,
Instr_slot,
addr,
ABCII,
stkptr,
Zregister,
IIWIDTH,
acmDO,
flagS)));
end if;
if ABCi1l = 4 then
Printf("INS:%d: %s",
FMT(smaddr)&fmt(ABColl(ABCil,
ABCoi,
INSTR_cmd,
INStr_scmd,
instr_sLOT,
addr,
Pwdata,
STkptr,
zregisTER,
IIWIDTH,
acmdo,
flags)));
end if;
end if;
if debug2 = '1' then
if ABCI1l = 2 then
Printf("INS:%d: %s",
fmt(SMADDr)&fmt(ABColl(ABCIL,
ABCoi,
instr_cmd,
instr_scmD,
Instr_slot,
ADDR,
prdata,
stkptr,
ZREGISTEr,
IIWIDTH,
acmdo,
FLAGS)));
end if;
end if;
end if;
end process;
-- synthesis translate_on
end RTL;
