-- APB_sine_LUT.vhd

--This code creates a sine wave LUT with APB slave wrapper interface

library IEEE;
use     IEEE.std_logic_1164.all;
use     IEEE.std_logic_unsigned.all;

entity APB_sine_LUT is
    port(
        PCLK            : in  std_logic;                        
        PRESETn         : in  std_logic;                        
        PENABLE         : in  std_logic;                        
        PSEL            : in  std_logic;                        
        PADDR           : in  std_logic_vector(7 downto 0);     
        PWRITE          : in  std_logic;                        
        PWDATA          : in  std_logic_vector(31 downto 0);    
        PRDATA          : out std_logic_vector(7 downto 0);    
        PREADY          : out std_logic;                       
        PSLVERR         : out std_logic                       
    );
end APB_sine_LUT;

Architecture APB_sine_LUT_arch of APB_sine_LUT is 

component sine_LUT is
  port( clock, reset_n, rd_enable : in std_logic;
        table_index : in std_logic_vector (7 downto 0);
        table_value : out std_logic_vector (7 downto 0));
end component;
signal rd_enable_i : std_logic;

begin
  PREADY <= '1';
  PSLVERR <= '0'; 
  rd_enable_i <= (not PWRITE) and PSEL;
  I1: sine_LUT port map( PCLK, PRESETn, rd_enable_i, PADDR, PRDATA);
end APB_sine_LUT_arch;

