-- Copyright 2008 Actel Corporation.  All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
-- Rev: 2.4   24Jan08 IPB  : Production Release
-- SVN Revision Information:
-- SVN $Revision: 14690 $
library Ieee;
use IEee.STD_logic_1164.all;
use IEEE.STD_logic_ariTH.all;
use iEEE.stD_Logic_unsignED.all;
library COREABC_LIB;
use COREABC_LIB.Top_Waveform_COREABC_0_support.all;
entity Top_Waveform_COREABC_0_ramBLOCKS is
generic (dwiDTH: INTEGER range 8 to 32;
FAMily: INTEGer range 0 to 23); port (clk: in STD_logic;
reseTN: in std_lOGIC;
wen: in STd_logic;
addr: in STD_LOGic_vector(7 downto 0);
wd: in std_logic_VECTOR(DWIDTH-1 downto 0);
RD: out sTD_LOGIC_vector(dwidTH-1 downto 0));
end Top_Waveform_COREABC_0_rAMBLOCKS;

architecture RTL of Top_Waveform_COREABC_0_RAMBLOcks is

subtype ABCL00 is STd_logic_vecTOR(dwidTH-1 downto 0);

type ABCiLL0 is array (integer range <> ) of ABCl00;

signal ABCLII0: std_LOGIC_Vector(15 downto 0);

signal ABCIII0: sTD_LOGic_vector(15 downto 0);

signal ABCo0I0: std_loGIC_VEctor(15 downto 0);

signal ABCL0I0: std_logic_VECTOR(15 downto 0);

signal ABCi0i0: STD_LOgic_vector(8 downto 0);

signal RD32: STD_LOgic_vector(31 downto 0);

signal WD32: STD_logic_vecTOR(31 downto 0);

signal ABCo1I0: STd_logic;

signal ABCll1: sTD_LOGIC;

signal ABCil1: std_logic;

begin
ABCll1 <= '0';
ABCIl1 <= '1';
ABCo1i0 <= not WEN;
ABCI0i0 <= '0'&addr;
ABCl1i0:
if FAMILY = 0
generate
process (CLK)
variable RAM: ABCill0(0 to 255);
variable ABCI1I0: std_logic_VECTOR(7 downto 0);
variable ABCOIL0: integer range 0 to 255 := 0;
begin
if Clk'EVENT and CLK = '1' then
ABCI1i0 := ( others => '0');
for ABCol in 0 to 7
loop
if addr(ABCol) = '1' then
ABCI1I0(ABCOL) := '1';
end if;
end loop;
ABCoil0 := CONV_integer(ABCi1i0);
if WEN = '1' then
RAM(ABCOIl0) := wd;
end if;
rd <= RAM(ABCOIL0);
end if;
end process;
end generate;
ABCOO00:
if FAMILY = 11 or FAMILY = 12
generate
ABCLo00:
if dwidth = 8 or DWIDTH = 16
generate
ABCII1: Top_Waveform_COREABC_0_ram256x16
port map (rwcLK => cLK,
RESET => RESETN,
WEN => WEN,
ren => ABCO1i0,
waddr => addR,
raddr => ADDR,
wd => ABClii0,
rd => ABCiii0);
end generate;
ABCIO00:
if dwidth = 8
generate
ABCLII0 <= "00000000"&wd;
rd <= ABCiii0(7 downto 0);
end generate;
ABCol00:
if dwidTH = 16
generate
ABCLII0 <= Wd;
rd <= ABCiii0;
end generate;
ABCLL00:
if DWIDTH = 32
generate
ABCil00: Top_Waveform_COREABC_0_ram256X16
port map (RWCLK => cLK,
RESEt => RESETN,
WEN => WEN,
rEN => ABCo1i0,
waddr => addr,
RADDr => ADDr,
WD => WD(15 downto 0),
RD => rd(15 downto 0));
ABCOI00: Top_Waveform_COREABC_0_RAM256x16
port map (rwCLK => clk,
reset => RESETN,
wen => wen,
REN => ABCo1i0,
wADDR => addR,
raddr => ADDR,
Wd => WD(31 downto 16),
rD => RD(31 downto 16));
end generate;
end generate;
ABCLI00:
if FAMILY = 14
generate
ABCIi1:
for ABCol in 0 to dwidth/8-1
generate
ABCii1: Top_Waveform_COREABC_0_ram256x8
port map (RWCLK => clk,
reset => clk,
WEN => Wen,
REN => ABCil1,
waddr => Addr,
RADDR => ADDR,
wd => WD(ABCol*8+7 downto ABCol*8),
RD => rd(ABCol*8+7 downto ABCOL*8));
end generate;
end generate;
ABCII00:
if FAMILY = 15 or FAMILY = 16
or FAMILY = 17
or FAMILY = 18
or FAMILY = 20
or FAMILY = 21
or FAMILY = 22
or FAMILY = 23
generate
ABCII1: Top_Waveform_COREABC_0_ram256X16
port map (Rwclk => CLK,
Reset => RESETN,
WEN => WEN,
reN => ABCO1i0,
WADDR => adDR,
rADDR => ADDr,
WD => ABCLii0,
Rd => ABCiii0);
ABCIO00:
if dwidth = 8
generate
ABClii0 <= "00000000"&WD;
rd <= ABCiii0(7 downto 0);
end generate;
ABCol00:
if dwIDTH = 16
generate
ABClii0 <= wd;
RD <= ABCiII0;
end generate;
ABCO000:
if dwidth = 32
generate
ABCl000: Top_Waveform_COREABC_0_ram256x16
port map (rwclk => clk,
reseT => RESETN,
wen => wen,
ren => ABCo1i0,
waddr => addr,
Raddr => ADDr,
WD => ABCo0i0,
RD => ABCL0I0);
ABCLII0 <= WD(15 downto 0);
ABCO0i0 <= WD(31 downto 16);
RD <= ABCl0i0&ABCIII0;
end generate;
end generate;
end rtl;
