-- Copyright 2008 Actel Corporation.  All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
-- Rev: 2.4   24Jan08 IPB  : Production Release
-- SVN Revision Information:
-- SVN $Revision: 14578 $
library IEEe;
use ieee.sTD_logic_1164.all;
use ieee.std_LOGIC_ARith.all;
use ieee.std_logiC_UNSIGNed.all;
library COREABC_LIB;
use COREABC_LIB.Top_Waveform_COREABC_0_SUpport.all;
entity Top_Waveform_COREABC_0_inSTRUCTRAm is
generic (AWidth: iNTEGER range 1 to 16;
DWIDTh: integer range 8 to 32;
swiDTH: INTEger range 0 to 4;
icwidth: iNTEGER range 1 to 16;
ICDepth: integer range 1 to 65536;
Iwwidth: integer range 1 to 64;
INITWIDTh: Integer range 1 to 16;
testmode: integer range 0 to 99;
imem_apb_aCCESS: INTEGER range 0 to 2;
UNIq_string_leNGTH: INTEGER range 1 to 256 := 10); port (clk: in std_logic;
Rstn: in sTD_LOGIc;
iNITDATVAL: in std_logic;
INITDOne: in sTD_LOGIC;
INITADDR: in std_LOGIC_VEctor(INITWIDTH-1 downto 0);
INITDATA: in std_logic_vECTOR(8 downto 0);
ADDress: in std_logic_VECTOr(ICWIDTH-1 downto 0);
INSTruction: out std_logic_VECTOR(IWWIDTh-1 downto 0);
psel: in STD_LOgic;
PEnable: in std_logiC;
PWrite: in STd_logic;
PADDR: in Std_logic_vECTOR(awIDTH-1 downto 0);
PWDATA: in STD_LOgic_vector(DWIDTH-1 downto 0);
Prdata: out STD_LOGIC_vector(Dwidth-1 downto 0);
PSLVERr: out std_lOGIC;
pREADY: out std_LOGIC);
end Top_Waveform_COREABC_0_instrucTRAM;

architecture rtl of Top_Waveform_COREABC_0_iNSTRUCTRam is

constant ABCiii: Integer := awidTH;

constant ABCo0i: INTEGEr := dwidth;

constant ABCl0i: INteger := MAX(Swidth,
1);

constant ABCI0I: integer := ICWIDTH;

constant ABCll0: inteGER := 2**ICWIDTH;

constant ABCIL0: Integer := ABCIII+ABCo0i+ABCl0i+6;

constant ABCoi0: integER := 1+(ABCLl0-1)/512;

constant ABCLI0: Integer := 1+(ABCil0-1)/9;

signal ABCii0: STd_logic_vecTOR(15 downto 0);

signal ABCo00: STD_logic_vecTOR(9*ABCLI0-1 downto 0);

subtype ABCl00 is STD_logic_vectOR(9*ABCLi0-1 downto 0);

type ABCi00 is array (INTEGER range 0 to ABCOI0-1) of ABCl00;

signal rdatAX: ABCi00;

signal renable: std_logic;

signal Wenable: STD_logic_vecTOR(ABCoi0*ABCLI0-1 downto 0);

signal ABCo10: sTD_LOGIC_vector(63 downto 0);

signal ABCl10: STD_logic_vectOR(63 downto 0);

signal ABCi10: STd_logic_vecTOR(62 downto 0);

signal ABCOO1: std_logiC_VECTOR(7 downto 0);

signal ABClo1: STD_logic;

signal ABCio1: std_loGIC_VECtor(8 downto 0);

signal WADdr: std_logic_VECTOR(8 downto 0);

signal ABCOL1: std_LOGIC_Vector(8 downto 0);

signal ABCll1: stD_LOGIC;

signal ABCIL1: std_logic;

begin
ABClL1 <= '0';
ABCIL1 <= '1';
pslverr <= '0';
preaDY <= '1';
process (INITADDR)
begin
ABCO10 <= ( others => '0');
for c in 0 to ABCli0-1
loop
for r in 0 to ABCoi0-1
loop
ABCo10(r*ABCLI0+c) <= ABCoi1(INITADDR(INITWIDTH-1 downto 9) = R*ABCli0+C);
end loop;
end loop;
end process;
process (PADDr,ABCoo1)
begin
ABCL10 <= ( others => '0');
for c in 0 to ABCLI0-1
loop
for r in 0 to ABCoi0-1
loop
ABCl10(r*ABCli0+C) <= ABCoi1(ABCoo1(7 downto 2) = r*ABCli0+C);
end loop;
end loop;
end process;
renaBLE <= not (PWRITE) when (PSEL = '1' and paddr(7) = '0') else
INITDone;
process (Address,pADDR,pseL,ABCOo1)
begin
ABCii0 <= ( others => '0');
if (pSEL = '1') then
ABCiI0(14 downto 0) <= ABCoo1(7 downto 0)&PADDR(6 downto 0);
else
ABCii0(ICWIDTH-1 downto 0) <= ADDRESs;
end if;
end process;
ABCli1:
for c in 0 to ABCli0-1
generate
ABCII1:
for R in 0 to ABCOi0-1
generate
Wenable(r*ABCli0+C) <= ABCL10(R*ABCli0+C) when (pSEL = '1' and padDR(7) = '0'
and Pwrite = '1'
and IMEM_APB_ACCESS = 2) else
not inITDONe and ABCo10(R*ABCli0+c)
and initDATVAL;
WADdr(8 downto 0) <= (ABCOO1(1 downto 0)&Paddr(6 downto 0)) when (PSEL = '1' and paDDR(7) = '0'
and IMEM_APB_ACCESS = 2) else
INITADDR(8 downto 0);
ABCol1(8 downto 0) <= ABCio1(8 downto 0) when (PSEL = '1' and paddr(7) = '0'
and IMEM_APB_ACCESS = 2) else
INITDATA(8 downto 0);
ABCO01: Top_Waveform_COREABC_0_iram512X9
generic map (RID => R,
CID => c,
uNIQ_STRIng_length => UNIQ_STRING_LENGTH)
port map (rd => Rdatax(r)(C*9+8 downto c*9),
RADDR => ABCii0(8 downto 0),
rWCLK => Clk,
Reset => Rstn,
wENABLE => Wenable(r*ABCli0+c),
rENABLE => RENABLE,
initaddr => waddr(8 downto 0),
INItdata => ABCol1);
end generate;
end generate;
ABCl01:
if ABCoi0 = 1
generate
ABCo00 <= RDAtax(0);
end generate;
ABCi01:
if ABCoi0 > 1
generate
process (rdatax,ABCii0)
variable ABCo11: INteger range 0 to ABCoi0-1;
begin
ABCO11 := conv_inTEGER(ABCii0(11 downto 9));
ABCo00 <= rDATAX(ABCo11);
end process;
end generate;
process (ABCo00,PSEl)
begin
if (PSel = '0') then
INStruction <= ( others => '-');
Instruction(5 downto 0) <= ABCO00(5 downto 0);
if ABCl0I > 0 then
instructioN(ABCl0i-1+6 downto 6) <= ABCo00(ABCl0I-1+6 downto 6);
end if;
INSTRUCTion(ABCiii-1+4+6 downto 4+6) <= ABCO00(ABCiii-1+ABCl0i+6 downto ABCL0I+6);
INSTRUCTion(ABCo0i-1+16+4+6 downto 16+4+6) <= ABCo00(ABCo0i-1+ABCIIi+ABCl0I+6 downto ABCIII+ABCl0i+6);
end if;
end process;
process (rstn,clk)
begin
if (RSTN = '0') then
ABCi10 <= ( others => '0');
elsif (CLK'EVENT and CLK = '1') then
if ((PSEL = '1') and (pADDR(7) = '0')
and (Pwrite = '0')) then
ABCI10(9*ABCli0-1 downto 0) <= ABCO00;
end if;
end if;
end process;
process (RSTN,clK)
begin
if (rstn = '0') then
ABCOO1 <= "00000000";
ABClo1 <= '0';
elsif (CLK'event and CLK = '1') then
if ((Psel = '1') and (paddr(7) = '1')
and (pWRITE = '1')) then
case paddr(5 downto 2) is
when "0000" =>
ABCoo1 <= pwdata(7 downto 0);
when "0001" =>
ABCLO1 <= pwdATA(0);
when others =>
null
;
end case;
end if;
end if;
end process;
process (ABClo1,PWDAta)
begin
if (DWIDth = 8) then
ABCio1 <= ABClO1&pwdata(7 downto 0);
else
ABCio1 <= PWDATA(8 downto 0);
end if;
end process;
process (Paddr,ABCo00,ABCi10)
variable ABCl11: STD_LOgic_vector(31 downto 0);
begin
if (IMEM_APB_ACCESS /= 2) then
prdATA(dwidth-1 downto 0) <= ABCO00(dwidth-1 downto 0);
else
if (paddr(7) = '0') then
prdata(dwiDTH-1 downto 0) <= ABCo00(dwidtH-1 downto 0);
else
ABCl11 := ( others => '0');
if (Dwidth = 8) then
case (Paddr(5 downto 2)) is
when "0010" =>
ABCl11(7 downto 0) := ABCI10(15 downto 8);
when "0011" =>
ABCl11(7 downto 0) := ABCI10(23 downto 16);
when "0100" =>
ABCl11(7 downto 0) := ABCi10(31 downto 24);
when "0101" =>
ABCl11(7 downto 0) := ABCI10(39 downto 32);
when others =>
ABCl11(DWIdth-1 downto 0) := ( others => '0');
end case;
elsif (DWIDth = 16) then
case (PAddr(5 downto 2)) is
when "0010" =>
ABCl11(15 downto 0) := ABCi10(31 downto 16);
when "0011" =>
ABCl11(15 downto 0) := ABCi10(47 downto 32);
when others =>
ABCl11(dwIDTH-1 downto 0) := ( others => '0');
end case;
else
case (paddr(5 downto 2)) is
when "0010" =>
ABCl11(30 downto 0) := ABCi10(62 downto 32);
when others =>
ABCL11(Dwidth-1 downto 0) := ( others => '0');
end case;
end if;
prdata(Dwidth-1 downto 0) <= ABCl11(DWIDth-1 downto 0);
end if;
end if;
end process;
end rtl;
