`timescale 1ns/100ps
// Copyright 2008 Actel Corporation.  All rights reserved.
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
// Rev: 2.4   24Jan08 IPB  : Production Release
// SVN Revision Information:
// SVN $Revision: 12755 $
module
Top_Waveform_COREABC_0_COREABC
(
PCLK
,
NSYSRESET
,
PRESETN
,
PENABLE_M
,
PWRITE_M
,
PSEL_M
,
PADDR_M
,
PWDATA_M
,
PRDATA_M
,
PREADY_M
,
PSLVERR_M
,
IO_IN
,
IO_OUT
,
INTREQ
,
INTACT
,
INITDATVAL
,
INITDONE
,
INITADDR
,
INITDATA
,
PSEL_S
,
PENABLE_S
,
PWRITE_S
,
PADDR_S
,
PWDATA_S
,
PRDATA_S
,
PSLVERR_S
,
PREADY_S
)
;
parameter
FAMILY
=
0
;
parameter
APB_AWIDTH
=
10
;
parameter
APB_DWIDTH
=
8
;
parameter
APB_SDEPTH
=
4
;
parameter
ICWIDTH
=
8
;
parameter
ZRWIDTH
=
8
;
parameter
IFWIDTH
=
4
;
parameter
IIWIDTH
=
4
;
parameter
IOWIDTH
=
8
;
parameter
STWIDTH
=
4
;
parameter
EN_RAM
=
1
;
parameter
EN_AND
=
1
;
parameter
EN_XOR
=
1
;
parameter
EN_OR
=
1
;
parameter
EN_ADD
=
1
;
parameter
EN_INC
=
1
;
parameter
EN_SHL
=
1
;
parameter
EN_SHR
=
1
;
parameter
EN_CALL
=
1
;
parameter
EN_PUSH
=
1
;
parameter
EN_MULT
=
0
;
parameter
EN_ACM
=
1
;
parameter
EN_DATAM
=
1
;
parameter
EN_INT
=
1
;
parameter
EN_IOREAD
=
1
;
parameter
EN_IOWRT
=
1
;
parameter
EN_ALURAM
=
1
;
parameter
EN_INDIRECT
=
1
;
parameter
ISRADDR
=
1
;
parameter
DEBUG
=
1
;
parameter
INSMODE
=
0
;
parameter
INITWIDTH
=
8
;
parameter
TESTMODE
=
0
;
parameter
ACT_CALIBRATIONDATA
=
1
;
parameter
IMEM_APB_ACCESS
=
2
;
parameter
UNIQ_STRING_LENGTH
=
10
;
parameter
MAX_NVMDWIDTH
=
32
;
input
PCLK
;
input
NSYSRESET
;
output
PRESETN
;
wire
PRESETN
;
output
PENABLE_M
;
wire
PENABLE_M
;
output
PWRITE_M
;
wire
PWRITE_M
;
output
PSEL_M
;
reg
PSEL_M
;
output
[
19
:
0
]
PADDR_M
;
reg
[
19
:
0
]
PADDR_M
;
output
[
APB_DWIDTH
-
1
:
0
]
PWDATA_M
;
reg
[
APB_DWIDTH
-
1
:
0
]
PWDATA_M
;
input
[
APB_DWIDTH
-
1
:
0
]
PRDATA_M
;
input
PREADY_M
;
input
PSLVERR_M
;
input
[
IIWIDTH
-
1
:
0
]
IO_IN
;
output
[
IOWIDTH
-
1
:
0
]
IO_OUT
;
reg
[
IOWIDTH
-
1
:
0
]
IO_OUT
;
input
INTREQ
;
output
INTACT
;
wire
INTACT
;
input
INITDATVAL
;
input
INITDONE
;
input
[
INITWIDTH
-
1
:
0
]
INITADDR
;
input
[
8
:
0
]
INITDATA
;
input
PSEL_S
;
input
PENABLE_S
;
input
PWRITE_S
;
input
[
APB_AWIDTH
-
1
:
0
]
PADDR_S
;
input
[
APB_DWIDTH
-
1
:
0
]
PWDATA_S
;
output
[
APB_DWIDTH
-
1
:
0
]
PRDATA_S
;
wire
[
APB_DWIDTH
-
1
:
0
]
PRDATA_S
;
output
PSLVERR_S
;
output
PREADY_S
;
// Copyright 2008 Actel Corporation.  All rights reserved.
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
// Rev: 2.4   24Jan08 IPB  : Production Release
// SVN Revision Information:
// SVN $Revision: 12260 $
localparam
BLANK
=
-
1
;
localparam
iNOP
=
256
*
1
;
localparam
iLOAD
=
256
*
2
;
localparam
iINCB
=
256
*
3
;
localparam
iAND
=
256
*
4
;
localparam
iOR
=
256
*
5
;
localparam
iXOR
=
256
*
6
;
localparam
iADD
=
256
*
7
;
localparam
iSUB
=
256
*
8
;
localparam
iSHL0
=
256
*
9
;
localparam
iSHL1
=
256
*
10
;
localparam
iSHLE
=
256
*
11
;
localparam
iROL
=
256
*
12
;
localparam
iSHR0
=
256
*
13
;
localparam
iSHR1
=
256
*
14
;
localparam
iSHRE
=
256
*
15
;
localparam
iROR
=
256
*
16
;
localparam
iCMP
=
256
*
17
;
localparam
iCMPLEQ
=
256
*
18
;
localparam
iBITCLR
=
256
*
19
;
localparam
iBITSET
=
256
*
20
;
localparam
iBITTST
=
256
*
21
;
localparam
iAPBREAD
=
256
*
22
;
localparam
iAPBWRT
=
256
*
23
;
localparam
iLOADZ
=
256
*
24
;
localparam
iDECZ
=
256
*
25
;
localparam
iINCZ
=
256
*
26
;
localparam
iIOWRT
=
256
*
27
;
localparam
iRAMREAD
=
256
*
28
;
localparam
iRAMWRT
=
256
*
29
;
localparam
iPUSH
=
256
*
30
;
localparam
iPOP
=
256
*
31
;
localparam
iIOREAD
=
256
*
32
;
localparam
iUSER
=
256
*
33
;
localparam
iJUMPB
=
256
*
34
;
localparam
iCALLB
=
256
*
35
;
localparam
iRETURNB
=
256
*
36
;
localparam
iRETISRB
=
256
*
37
;
localparam
iWAITB
=
256
*
38
;
localparam
iHALTB
=
256
*
38
;
localparam
iMULT
=
256
*
39
;
localparam
iDEC
=
256
*
40
;
localparam
iAPBREADZ
=
256
*
41
;
localparam
iAPBWRTZ
=
256
*
42
;
localparam
iADDZ
=
256
*
43
;
localparam
iSUBZ
=
256
*
44
;
localparam
iDAT
=
10
;
localparam
iDAT8
=
11
;
localparam
iDAT16
=
12
;
localparam
iDAT32
=
13
;
localparam
iACM
=
14
;
localparam
iACC
=
15
;
localparam
iRAM
=
16
;
localparam
ABClI
=
10
;
localparam
DAT8
=
11
;
localparam
DAT16
=
12
;
localparam
DAT32
=
13
;
localparam
ACM
=
14
;
localparam
ACC
=
15
;
localparam
RAM
=
16
;
localparam
iIFNOT
=
0
;
localparam
iNOTIF
=
0
;
localparam
iIF
=
1
;
localparam
iUNTIL
=
0
;
localparam
iNOTUNTIL
=
1
;
localparam
iUNTILNOT
=
1
;
localparam
iWHILE
=
1
;
localparam
iZZERO
=
8
'h
08
;
localparam
iNEGATIVE
=
8
'h
04
;
localparam
iZERO
=
8
'h
02
;
localparam
iLTE_ZERO
=
8
'h
06
;
localparam
iALWAYS
=
8
'h
01
;
localparam
iINPUT0
=
12
'h
010
;
localparam
iINPUT1
=
12
'h
020
;
localparam
iINPUT2
=
12
'h
040
;
localparam
iINPUT3
=
12
'h
080
;
localparam
iINPUT4
=
12
'h
100
;
localparam
iINPUT5
=
12
'h
200
;
localparam
iINPUT6
=
12
'h
400
;
localparam
iINPUT7
=
12
'h
800
;
localparam
iINPUT8
=
16
'h
1000
;
localparam
iINPUT9
=
16
'h
2000
;
localparam
iINPUT10
=
16
'h
4000
;
localparam
iINPUT11
=
16
'h
8000
;
localparam
iINPUT12
=
20
'h
10000
;
localparam
iINPUT13
=
20
'h
20000
;
localparam
iINPUT14
=
20
'h
40000
;
localparam
iINPUT15
=
20
'h
80000
;
localparam
iINPUT16
=
24
'h
100000
;
localparam
iINPUT17
=
24
'h
200000
;
localparam
iINPUT18
=
24
'h
400000
;
localparam
iINPUT19
=
24
'h
800000
;
localparam
iINPUT20
=
28
'h
1000000
;
localparam
iINPUT21
=
28
'h
2000000
;
localparam
iINPUT22
=
28
'h
4000000
;
localparam
iINPUT23
=
28
'h
8000000
;
localparam
iINPUT24
=
32
'h
10000000
;
localparam
iINPUT25
=
32
'h
20000000
;
localparam
iINPUT26
=
32
'h
40000000
;
localparam
iINPUT27
=
32
'h
80000000
;
localparam
iANYINPUT
=
32
'h
7FFFFFF0
;
localparam
ALWAYS
=
8
'h
01
;
localparam
ZZERO
=
8
'h
08
;
localparam
NEGATIVE
=
8
'h
04
;
localparam
ZERO
=
8
'h
02
;
localparam
LTE_ZERO
=
8
'h
06
;
localparam
INPUT0
=
12
'h
010
;
localparam
INPUT1
=
12
'h
020
;
localparam
INPUT2
=
12
'h
040
;
localparam
INPUT3
=
12
'h
080
;
localparam
INPUT4
=
12
'h
100
;
localparam
INPUT5
=
12
'h
200
;
localparam
INPUT6
=
12
'h
400
;
localparam
INPUT7
=
12
'h
800
;
localparam
INPUT8
=
16
'h
1000
;
localparam
INPUT9
=
16
'h
2000
;
localparam
INPUT10
=
16
'h
3000
;
localparam
INPUT11
=
16
'h
8000
;
localparam
INPUT12
=
20
'h
10000
;
localparam
INPUT13
=
20
'h
20000
;
localparam
INPUT14
=
20
'h
40000
;
localparam
INPUT15
=
20
'h
80000
;
localparam
INPUT16
=
24
'h
100000
;
localparam
INPUT17
=
24
'h
200000
;
localparam
INPUT18
=
24
'h
300000
;
localparam
INPUT19
=
24
'h
800000
;
localparam
INPUT20
=
28
'h
1000000
;
localparam
INPUT21
=
28
'h
2000000
;
localparam
INPUT22
=
28
'h
4000000
;
localparam
INPUT23
=
28
'h
8000000
;
localparam
INPUT24
=
32
'h
10000000
;
localparam
INPUT25
=
32
'h
20000000
;
localparam
INPUT26
=
32
'h
40000000
;
localparam
INPUT27
=
32
'h
40000000
;
localparam
ANYINPUT
=
32
'h
7FFFFFF0
;
localparam
iLOADLOOP
=
256
*
24
;
localparam
iDECLOOP
=
256
*
25
;
localparam
iINCLOOP
=
256
*
26
;
localparam
iLOOPZ
=
8
;
localparam
LOOPZ
=
8
;
localparam
EN_USER
=
0
;
function
[
57
:
0
]
ABCOl
;
input
[
2
:
0
]
ABCIl
;
input
[
2
:
0
]
ABCll
;
input
[
3
:
0
]
ABCO0
;
input
[
15
:
0
]
ABCI0
;
input
[
31
:
0
]
ABCl0
;
reg
[
32
+
16
+
4
+
6
-
1
:
0
]
ABCO1
;
begin
ABCO1
=
{
ABCl0
,
ABCI0
,
ABCO0
,
ABCll
,
ABCIl
}
;
ABCOl
=
ABCO1
;
end
endfunction
function
[
57
:
0
]
doins
;
input
ABCI1
;
integer
ABCI1
;
input
ABCl1
;
integer
ABCl1
;
input
ABCOOI
;
integer
ABCOOI
;
input
ABCIOI
;
integer
ABCIOI
;
input
ABClOI
;
integer
ABClOI
;
input
ABCOII
;
integer
ABCOII
;
reg
[
2
:
0
]
ABCIl
;
reg
[
2
:
0
]
ABCll
;
reg
[
3
:
0
]
ABCO0
;
reg
[
15
:
0
]
ABCI0
;
reg
[
31
:
0
]
ABCl0
;
localparam
[
31
:
0
]
ABCIII
=
{
32
{
1
'b
1
}
}
;
localparam
[
31
:
0
]
ZERO
=
{
32
{
1
'b
0
}
}
;
integer
ABClII
;
integer
FFW
;
integer
ABCOlI
;
begin
ABCIl
=
3
'b
xxx
;
ABCll
=
3
'b
xxx
;
ABCO0
=
4
'b
xxx0
;
ABCI0
=
{
16
{
1
'b
x
}
}
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
ABClII
=
ABCl1
/
256
;
FFW
=
ABCl1
-
ABClII
*
256
;
ABClII
=
ABClII
*
256
;
case
(
ABClII
)
iLOAD
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
111
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
ABCOOI
;
if
(
ABCI1
>=
3
)
begin
case
(
ABCOOI
)
iDAT
:
begin
ABCl0
=
ABCIOI
;
end
iDAT8
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCl0
=
ABCIOI
;
end
iRAM
:
begin
ABCI0
[
7
:
0
]
=
ABCIOI
;
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
default
:
begin
end
endcase
end
end
iINCB
:
begin
if
(
FFW
>
0
)
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
100
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
1
;
end
else
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
000
;
ABCO0
[
0
]
=
1
'b
0
;
end
end
iDEC
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
100
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
{
32
{
1
'b
1
}
}
;
end
iAND
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
001
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
ABCOOI
;
if
(
ABCI1
>=
3
)
begin
case
(
ABCOOI
)
iDAT
:
begin
ABCl0
=
ABCIOI
;
end
iDAT8
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCl0
=
ABCIOI
;
end
iRAM
:
begin
ABCI0
[
7
:
0
]
=
ABCIOI
;
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
default
:
begin
end
endcase
end
end
iOR
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
010
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
ABCOOI
;
if
(
ABCI1
>=
3
)
begin
case
(
ABCOOI
)
iDAT
:
begin
ABCl0
=
ABCIOI
;
end
iDAT8
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCl0
=
ABCIOI
;
end
iRAM
:
begin
ABCI0
[
7
:
0
]
=
ABCIOI
;
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
default
:
begin
end
endcase
end
end
iXOR
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
011
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
ABCOOI
;
if
(
ABCI1
>=
3
)
begin
case
(
ABCOOI
)
iDAT
:
begin
ABCl0
=
ABCIOI
;
end
iDAT8
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCl0
=
ABCIOI
;
end
iRAM
:
begin
ABCI0
[
7
:
0
]
=
ABCIOI
;
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
default
:
begin
end
endcase
end
end
iADD
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
100
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
ABCOOI
;
if
(
ABCI1
>=
3
)
begin
case
(
ABCOOI
)
iDAT
:
begin
ABCl0
=
ABCIOI
;
end
iDAT8
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCl0
=
ABCIOI
;
end
iRAM
:
begin
ABCI0
[
7
:
0
]
=
ABCIOI
;
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
default
:
begin
end
endcase
end
end
iMULT
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
000
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
ABCOOI
;
if
(
ABCI1
>=
3
)
begin
case
(
ABCOOI
)
iDAT
:
begin
ABCl0
=
ABCIOI
;
end
iDAT8
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCl0
=
ABCIOI
;
end
iRAM
:
begin
ABCI0
[
7
:
0
]
=
ABCIOI
;
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
default
:
begin
end
endcase
end
end
iSUB
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
100
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
~
(
ABCOOI
-
1
)
;
if
(
ABCI1
>=
3
)
begin
ABCl0
=
~
(
ABCIOI
-
1
)
;
case
(
ABCOOI
)
iDAT
:
begin
end
iDAT8
:
begin
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
1
}
}
;
end
iDAT16
:
begin
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
1
}
}
;
end
iDAT32
:
begin
end
iRAM
:
begin
ABCI0
[
7
:
0
]
=
ABCIOI
;
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
default
:
begin
end
endcase
end
end
iSHL0
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
101
;
ABCl0
[
1
:
0
]
=
2
'b
00
;
ABCO0
[
0
]
=
1
'b
0
;
end
iSHL1
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
101
;
ABCl0
[
1
:
0
]
=
2
'b
01
;
ABCO0
[
0
]
=
1
'b
0
;
end
iSHLE
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
101
;
ABCl0
[
1
:
0
]
=
2
'b
10
;
ABCO0
[
0
]
=
1
'b
0
;
end
iROL
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
101
;
ABCl0
[
1
:
0
]
=
2
'b
11
;
ABCO0
[
0
]
=
1
'b
0
;
end
iSHR0
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
110
;
ABCl0
[
1
:
0
]
=
2
'b
00
;
ABCO0
[
0
]
=
1
'b
0
;
end
iSHR1
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
110
;
ABCl0
[
1
:
0
]
=
2
'b
01
;
ABCO0
[
0
]
=
1
'b
0
;
end
iSHRE
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
110
;
ABCl0
[
1
:
0
]
=
2
'b
10
;
ABCO0
[
0
]
=
1
'b
0
;
end
iROR
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
110
;
ABCl0
[
1
:
0
]
=
2
'b
11
;
ABCO0
[
0
]
=
1
'b
0
;
end
iCMP
:
begin
ABCIl
=
3
'b
001
;
ABCll
=
3
'b
011
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
ABCOOI
;
if
(
ABCI1
>=
3
)
begin
case
(
ABCOOI
)
iDAT
:
begin
ABCl0
=
ABCIOI
;
end
iDAT8
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCl0
=
ABCIOI
;
end
iRAM
:
begin
ABCI0
[
7
:
0
]
=
ABCIOI
;
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
default
:
begin
end
endcase
end
end
iCMPLEQ
:
begin
ABCIl
=
3
'b
001
;
ABCll
=
3
'b
100
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
~
(
ABCOOI
-
1
)
;
if
(
ABCI1
>=
3
)
begin
ABCl0
=
~
(
ABCIOI
-
1
)
;
case
(
ABCOOI
)
iDAT
:
begin
end
iDAT8
:
begin
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
end
iRAM
:
begin
ABCI0
[
7
:
0
]
=
ABCIOI
;
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
default
:
begin
end
endcase
end
end
iBITCLR
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
001
;
ABCl0
=
ABCIII
;
ABCl0
[
ABCOOI
]
=
1
'b
0
;
ABCO0
[
0
]
=
1
'b
0
;
end
iBITSET
:
begin
ABCIl
=
3
'b
000
;
ABCll
=
3
'b
010
;
ABCl0
=
ZERO
;
ABCl0
[
ABCOOI
]
=
1
'b
1
;
ABCO0
[
0
]
=
1
'b
0
;
end
iBITTST
:
begin
ABCIl
=
3
'b
001
;
ABCll
=
3
'b
001
;
ABCl0
=
ZERO
;
ABCl0
[
ABCOOI
]
=
1
'b
1
;
ABCO0
[
0
]
=
1
'b
0
;
end
iAPBREAD
:
begin
ABCIl
=
3
'b
010
;
ABCll
=
3
'b
011
;
ABCO0
=
ABCOOI
;
ABCI0
=
ABCIOI
;
end
iAPBWRT
:
begin
ABCIl
=
3
'b
010
;
ABCll
=
3
'b
xxx
;
ABCO0
=
ABCIOI
;
ABCI0
=
ABClOI
;
case
(
ABCOOI
)
iACM
:
ABCll
=
3
'b
010
;
iACC
:
ABCll
=
3
'b
000
;
iDAT
:
begin
ABCll
=
3
'b
001
;
ABCl0
=
ABCOII
;
end
iDAT8
:
begin
ABCll
=
3
'b
001
;
ABCl0
=
ABCOII
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCll
=
3
'b
001
;
ABCl0
=
ABCOII
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCll
=
3
'b
001
;
ABCl0
=
ABCOII
;
end
default
:
begin
end
endcase
end
iAPBREADZ
:
begin
ABCIl
=
3
'b
010
;
ABCll
=
3
'b
111
;
ABCO0
=
ABCOOI
;
end
iAPBWRTZ
:
begin
ABCIl
=
3
'b
010
;
ABCll
=
3
'b
xxx
;
ABCO0
=
ABCIOI
;
case
(
ABCOOI
)
iACM
:
ABCll
=
3
'b
110
;
iACC
:
ABCll
=
3
'b
100
;
iDAT
:
begin
ABCll
=
3
'b
101
;
ABCl0
=
ABClOI
;
end
iDAT8
:
begin
ABCll
=
3
'b
101
;
ABCl0
=
ABClOI
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCll
=
3
'b
101
;
ABCl0
=
ABClOI
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCll
=
3
'b
101
;
ABCl0
=
ABClOI
;
end
default
:
begin
end
endcase
end
iLOADZ
:
begin
ABCIl
=
3
'b
011
;
ABCll
=
3
'b
000
;
ABCO0
[
0
]
=
1
'b
0
;
case
(
ABCOOI
)
iACC
:
begin
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
iDAT
:
begin
ABCl0
=
ABCIOI
;
end
iDAT8
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCl0
=
ABCIOI
;
end
default
:
begin
end
endcase
end
iDECZ
:
begin
ABCIl
=
3
'b
011
;
ABCll
=
3
'b
001
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
{
32
{
1
'b
1
}
}
;
end
iINCZ
:
begin
ABCIl
=
3
'b
011
;
ABCll
=
3
'b
001
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
1
;
end
iADDZ
:
begin
ABCIl
=
3
'b
011
;
ABCll
=
3
'b
001
;
ABCO0
[
0
]
=
1
'b
0
;
case
(
ABCOOI
)
iACC
:
begin
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
iDAT
:
begin
ABCl0
=
ABCIOI
;
end
iDAT8
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCl0
=
ABCIOI
;
end
default
:
begin
end
endcase
end
iSUBZ
:
begin
ABCIl
=
3
'b
011
;
ABCll
=
3
'b
001
;
ABCO0
[
0
]
=
1
'b
0
;
ABCl0
=
~
(
ABCIOI
-
1
)
;
case
(
ABCOOI
)
iACC
:
begin
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
iDAT
:
begin
end
iDAT8
:
begin
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
1
}
}
;
end
iDAT16
:
begin
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
1
}
}
;
end
iDAT32
:
begin
end
default
:
begin
end
endcase
end
iIOWRT
:
begin
ABCIl
=
3
'b
011
;
ABCll
=
3
'b
111
;
ABCO0
[
0
]
=
1
'b
0
;
case
(
ABCOOI
)
iACC
:
begin
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
iDAT
:
begin
ABCl0
=
ABCIOI
;
end
iDAT8
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCl0
=
ABCIOI
;
end
default
:
begin
end
endcase
end
iIOREAD
:
begin
ABCIl
=
3
'b
011
;
ABCll
=
3
'b
110
;
end
iRAMREAD
:
begin
ABCIl
=
3
'b
011
;
ABCll
=
3
'b
011
;
ABCI0
=
ABCOOI
;
end
iRAMWRT
:
begin
ABCIl
=
3
'b
011
;
ABCll
=
3
'b
010
;
ABCI0
=
ABCOOI
;
ABCO0
[
0
]
=
1
'b
1
;
if
(
ABCI1
>=
3
)
begin
ABCO0
[
0
]
=
1
'b
0
;
ABCI0
=
ABCOOI
;
case
(
ABCIOI
)
iACC
:
begin
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
iDAT
:
begin
ABCl0
=
ABClOI
;
end
iDAT8
:
begin
ABCl0
=
ABClOI
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCl0
=
ABClOI
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCl0
=
ABClOI
;
end
default
:
begin
end
endcase
end
end
iPUSH
:
begin
ABCIl
=
3
'b
011
;
ABCll
=
3
'b
100
;
ABCO0
[
0
]
=
1
'b
0
;
case
(
ABCOOI
)
BLANK
:
begin
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
iACC
:
begin
ABCO0
[
0
]
=
1
'b
1
;
ABCl0
=
{
32
{
1
'b
x
}
}
;
end
iDAT
:
begin
ABCl0
=
ABCIOI
;
end
iDAT8
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
8
]
=
{
24
{
1
'b
x
}
}
;
end
iDAT16
:
begin
ABCl0
=
ABCIOI
;
ABCl0
[
31
:
16
]
=
{
16
{
1
'b
x
}
}
;
end
iDAT32
:
begin
ABCl0
=
ABCIOI
;
end
default
:
begin
end
endcase
end
iPOP
:
begin
ABCIl
=
3
'b
011
;
ABCll
=
3
'b
101
;
end
iJUMPB
:
begin
ABCIl
=
3
'b
100
;
ABCll
=
3
'b
x01
;
if
(
ABCI1
>=
4
)
begin
ABCll
[
0
]
=
ABCIlI
(
ABCOOI
)
;
ABCl0
=
ABCIOI
;
ABCI0
=
ABClOI
;
end
else
begin
ABCl0
[
0
]
=
1
'b
1
;
ABCI0
=
ABCOOI
;
end
for
(
ABCOlI
=
31
;
ABCOlI
>=
FFW
+
4
;
ABCOlI
=
ABCOlI
-
1
)
ABCl0
[
ABCOlI
]
=
1
'b
x
;
end
iWAITB
:
begin
ABCIl
=
3
'b
100
;
ABCll
=
3
'b
x11
;
if
(
ABCI1
>=
3
)
begin
ABCll
[
0
]
=
ABCIlI
(
ABCOOI
)
;
ABCl0
=
ABCIOI
;
end
else
begin
ABCl0
[
0
]
=
1
'b
1
;
end
for
(
ABCOlI
=
31
;
ABCOlI
>=
FFW
+
4
;
ABCOlI
=
ABCOlI
-
1
)
ABCl0
[
ABCOlI
]
=
1
'b
x
;
end
iCALLB
:
begin
ABCIl
=
3
'b
101
;
ABCll
=
3
'b
x01
;
if
(
ABCI1
>=
4
)
begin
ABCll
[
0
]
=
ABCIlI
(
ABCOOI
)
;
ABCl0
=
ABCIOI
;
ABCI0
=
ABClOI
;
end
else
begin
ABCl0
[
0
]
=
1
'b
1
;
ABCI0
=
ABCOOI
;
end
for
(
ABCOlI
=
31
;
ABCOlI
>=
FFW
+
4
;
ABCOlI
=
ABCOlI
-
1
)
ABCl0
[
ABCOlI
]
=
1
'b
x
;
end
iRETURNB
:
begin
ABCIl
=
3
'b
110
;
ABCll
=
3
'b
x01
;
if
(
ABCI1
>=
3
)
begin
ABCll
[
0
]
=
ABCIlI
(
ABCOOI
)
;
ABCl0
=
ABCIOI
;
end
else
begin
ABCl0
[
0
]
=
1
'b
1
;
end
for
(
ABCOlI
=
31
;
ABCOlI
>=
FFW
+
4
;
ABCOlI
=
ABCOlI
-
1
)
ABCl0
[
ABCOlI
]
=
1
'b
x
;
end
iRETISRB
:
begin
ABCIl
=
3
'b
110
;
ABCll
=
3
'b
x11
;
if
(
ABCI1
>=
3
)
begin
ABCll
[
0
]
=
ABCIlI
(
ABCOOI
)
;
ABCl0
=
ABCIOI
;
end
else
begin
ABCl0
[
0
]
=
1
'b
1
;
end
for
(
ABCOlI
=
31
;
ABCOlI
>=
FFW
+
4
;
ABCOlI
=
ABCOlI
-
1
)
ABCl0
[
ABCOlI
]
=
1
'b
x
;
end
iNOP
:
begin
ABCIl
=
3
'b
111
;
if
(
EN_USER
==
1
)
begin
ABCll
=
3
'b
000
;
end
end
iUSER
:
begin
ABCIl
=
3
'b
111
;
ABCll
[
0
]
=
1
'b
1
;
ABCll
=
ABCOOI
;
ABCl0
=
ABCIOI
;
ABCI0
=
ABClOI
;
ABCO0
=
ABCOII
;
end
default
:
begin
end
endcase
doins
=
ABCOl
(
ABCIl
,
ABCll
,
ABCO0
,
ABCI0
,
ABCl0
)
;
end
endfunction
function
[
57
:
0
]
doins5
;
input
ABCl1
;
input
ABCOOI
;
input
ABCIOI
;
input
ABClOI
;
input
ABCOII
;
integer
ABCl1
;
integer
ABCOOI
;
integer
ABCIOI
;
integer
ABClOI
;
integer
ABCOII
;
integer
ABCllI
;
begin
ABCllI
=
-
1
;
doins5
=
doins
(
5
,
ABCl1
,
ABCOOI
,
ABCIOI
,
ABClOI
,
ABCOII
)
;
end
endfunction
function
[
57
:
0
]
doins4
;
input
ABCl1
;
input
ABCOOI
;
input
ABCIOI
;
input
ABClOI
;
integer
ABCl1
;
integer
ABCOOI
;
integer
ABCIOI
;
integer
ABClOI
;
integer
ABCllI
;
begin
ABCllI
=
-
1
;
doins4
=
doins
(
4
,
ABCl1
,
ABCOOI
,
ABCIOI
,
ABClOI
,
ABCllI
)
;
end
endfunction
function
[
57
:
0
]
doins3
;
input
ABCl1
;
input
ABCOOI
;
input
ABCIOI
;
integer
ABCl1
;
integer
ABCOOI
;
integer
ABCIOI
;
integer
ABCllI
;
begin
ABCllI
=
-
1
;
doins3
=
doins
(
3
,
ABCl1
,
ABCOOI
,
ABCIOI
,
ABCllI
,
ABCllI
)
;
end
endfunction
function
[
57
:
0
]
doins2
;
input
ABCl1
;
input
ABCOOI
;
integer
ABCl1
;
integer
ABCOOI
;
integer
ABCllI
;
begin
ABCllI
=
-
1
;
doins2
=
doins
(
2
,
ABCl1
,
ABCOOI
,
ABCllI
,
ABCllI
,
ABCllI
)
;
end
endfunction
function
[
57
:
0
]
doins1
;
input
ABCl1
;
integer
ABCl1
;
integer
ABCllI
;
begin
ABCllI
=
-
1
;
doins1
=
doins
(
1
,
ABCl1
,
ABCllI
,
ABCllI
,
ABCllI
,
ABCllI
)
;
end
endfunction
function
[
57
:
0
]
ABCIlI
;
input
ABCO0I
;
integer
ABCO0I
;
begin
if
(
ABCO0I
!=
0
)
begin
ABCIlI
=
1
'b
1
;
end
else
begin
ABCIlI
=
1
'b
0
;
end
end
endfunction
function
[
57
:
0
]
ABCI0I
;
input
ABCO0I
;
begin
if
(
ABCO0I
)
begin
ABCI0I
=
1
'b
1
;
end
else
begin
ABCI0I
=
1
'b
0
;
end
end
endfunction
function
integer
ABCl0I
;
input
ABCO1I
;
integer
ABCO1I
;
input
ABCI1I
;
integer
ABCI1I
;
input
ABCl1I
;
integer
ABCl1I
;
input
ABCOOl
;
integer
ABCOOl
;
integer
ABCIOl
;
integer
ABClOl
;
begin
ABCIOl
=
0
;
ABClOl
=
0
;
if
(
ABCI1I
==
1
)
begin
ABClOl
=
8
;
if
(
ABCOOl
>
8
)
begin
ABClOl
=
16
;
end
end
if
(
ABCO1I
==
1
)
begin
ABCIOl
=
ABCl1I
;
end
if
(
ABCIOl
>
ABClOl
)
begin
ABCl0I
=
ABCIOl
;
end
else
if
(
ABClOl
>
0
)
begin
ABCl0I
=
ABClOl
;
end
else
begin
ABCl0I
=
1
;
end
end
endfunction
function
integer
calc_swidth
;
input
ABCOIl
;
integer
ABCOIl
;
begin
if
(
ABCOIl
>=
9
)
begin
calc_swidth
=
4
;
end
else
if
(
ABCOIl
>=
5
)
begin
calc_swidth
=
3
;
end
else
if
(
ABCOIl
>=
3
)
begin
calc_swidth
=
2
;
end
else
if
(
ABCOIl
>=
2
)
begin
calc_swidth
=
1
;
end
else
begin
calc_swidth
=
0
;
end
end
endfunction
function
integer
log2r
;
input
ABCOIl
;
integer
ABCOIl
;
begin
if
(
ABCOIl
>=
65536
)
begin
log2r
=
17
;
end
else
if
(
ABCOIl
>=
32768
)
begin
log2r
=
16
;
end
else
if
(
ABCOIl
>=
16384
)
begin
log2r
=
15
;
end
else
if
(
ABCOIl
>=
8192
)
begin
log2r
=
14
;
end
else
if
(
ABCOIl
>=
4096
)
begin
log2r
=
13
;
end
else
if
(
ABCOIl
>=
2048
)
begin
log2r
=
12
;
end
else
if
(
ABCOIl
>=
1024
)
begin
log2r
=
11
;
end
else
if
(
ABCOIl
>=
512
)
begin
log2r
=
10
;
end
else
if
(
ABCOIl
>=
256
)
begin
log2r
=
9
;
end
else
if
(
ABCOIl
>=
128
)
begin
log2r
=
8
;
end
else
if
(
ABCOIl
>=
64
)
begin
log2r
=
7
;
end
else
if
(
ABCOIl
>=
32
)
begin
log2r
=
6
;
end
else
if
(
ABCOIl
>=
16
)
begin
log2r
=
5
;
end
else
if
(
ABCOIl
>=
8
)
begin
log2r
=
4
;
end
else
if
(
ABCOIl
>=
4
)
begin
log2r
=
3
;
end
else
if
(
ABCOIl
>=
2
)
begin
log2r
=
2
;
end
else
if
(
ABCOIl
>=
1
)
begin
log2r
=
1
;
end
else
begin
log2r
=
1
;
end
end
endfunction
function
integer
calc_initwidth
;
input
AWIDTH
;
integer
AWIDTH
;
input
DWIDTH
;
integer
DWIDTH
;
input
ABCl
;
integer
ABCl
;
input
ICWIDTH
;
integer
ICWIDTH
;
integer
SWIDTH
;
integer
ABCIIl
;
integer
ABClIl
;
integer
ABCOll
;
integer
ABCIll
;
integer
ABClll
;
integer
ABCO0l
;
integer
ABCI0l
;
begin
SWIDTH
=
calc_swidth
(
ABCl
)
;
if
(
ABCl
==
0
)
SWIDTH
=
1
;
ABCIIl
=
2
**
ICWIDTH
;
ABClIl
=
AWIDTH
+
DWIDTH
+
SWIDTH
+
6
;
ABCOll
=
1
+
(
ABCIIl
-
1
)
/
512
;
ABCIll
=
1
+
(
ABClIl
-
1
)
/
9
;
ABClll
=
ABCIll
*
ABCOll
;
ABCO0l
=
ABClll
*
512
;
ABCI0l
=
log2r
(
ABCO0l
)
;
if
(
ABCI0l
>
16
)
ABCI0l
=
16
;
calc_initwidth
=
ABCI0l
;
end
endfunction
function
integer
max
;
input
ABCl0l
,
ABCO1l
;
integer
ABCl0l
,
ABCO1l
;
begin
if
(
ABCl0l
>
ABCO1l
)
max
=
ABCl0l
;
else
max
=
ABCO1l
;
end
endfunction
function
integer
min
;
input
ABCl0l
,
ABCO1l
;
integer
ABCl0l
,
ABCO1l
;
begin
if
(
ABCl0l
<
ABCO1l
)
min
=
ABCl0l
;
else
min
=
ABCO1l
;
end
endfunction
localparam
IWWIDTH
=
32
+
16
+
4
+
6
;
localparam
ABCII
=
ABCl0I
(
EN_RAM
,
EN_CALL
,
APB_DWIDTH
,
ICWIDTH
)
;
localparam
ABCOI
=
2
**
ICWIDTH
;
localparam
APB_SWIDTH
=
calc_swidth
(
APB_SDEPTH
)
;
localparam
ABClIl
=
APB_AWIDTH
+
APB_DWIDTH
+
APB_SWIDTH
+
6
;
reg
[
ICWIDTH
-
1
:
0
]
SMADDR
;
wire
[
IWWIDTH
-
1
:
0
]
INSTRUCTION
;
reg
[
7
:
0
]
STKPTR
;
reg
[
7
:
0
]
ABCllOI
;
reg
[
7
:
0
]
ABCO0OI
;
wire
[
7
:
0
]
ABCOIl1
;
reg
[
2
:
0
]
INSTR_CMD
;
reg
[
2
:
0
]
INSTR_SCMD
;
reg
[
APB_SWIDTH
:
0
]
INSTR_SLOT
;
reg
[
APB_AWIDTH
-
1
:
0
]
INSTR_ADDR
;
reg
[
APB_DWIDTH
-
1
:
0
]
INSTR_DATA
;
reg
ABCIIl1
;
reg
[
APB_DWIDTH
-
1
:
0
]
ACCUMULATOR
;
reg
[
APB_DWIDTH
-
1
:
0
]
ABClIl1
;
reg
[
APB_DWIDTH
-
1
:
0
]
ABCOll1
;
reg
[
APB_DWIDTH
-
1
:
0
]
ABCIll1
;
reg
[
APB_DWIDTH
-
1
:
0
]
ABClll1
;
reg
[
APB_DWIDTH
-
1
:
0
]
ABCO0l1
;
reg
[
APB_DWIDTH
-
1
:
0
]
ABCI0l1
;
reg
[
APB_DWIDTH
-
1
:
0
]
ABCl0l1
;
reg
[
ZRWIDTH
-
1
:
0
]
ABCO1l1
;
reg
[
APB_DWIDTH
-
1
:
0
]
ABCI1l1
;
reg
[
APB_DWIDTH
-
1
:
0
]
ABCl1l1
;
reg
[
APB_DWIDTH
-
1
:
0
]
ABCOO01
;
reg
ABCIO01
;
reg
ABClO01
;
reg
[
ZRWIDTH
:
0
]
ZREGISTER
;
wire
ABCOI01
;
reg
ABCII01
;
reg
ABClI01
;
wire
ABCOl01
;
wire
ACCUM_ZERO
;
wire
ACCUM_NEG
;
reg
ABCIl01
;
reg
ABCll01
;
reg
ABCO001
;
reg
ABCI001
;
reg
FLAGS
;
reg
ABCl001
;
reg
ABCO101
;
reg
ABCI101
;
reg
ABCl101
;
reg
ABCOO11
;
reg
ABCIO11
;
wire
ABClO11
;
reg
ABCOI11
;
wire
ABCII11
;
reg
[
7
:
0
]
ABClI11
;
reg
[
7
:
0
]
ABCOl11
;
wire
[
ABCII
-
1
:
0
]
ABCIl11
;
reg
[
ABCII
-
1
:
0
]
ABCll11
;
wire
[
APB_DWIDTH
-
1
:
0
]
RAMDOUT
;
reg
ISR
;
wire
ABCO011
;
wire
ACMDO
;
wire
[
7
:
0
]
ACMDATA
;
wire
DEBUG1
;
wire
DEBUG2
;
reg
ABCI011
;
wire
STALL
;
wire
ABCl011
;
reg
[
1
:
0
]
ABCO111
;
parameter
[
1
:
0
]
ABCI111
=
0
;
parameter
[
1
:
0
]
ABCl111
=
1
;
parameter
[
1
:
0
]
ABCOOOOI
=
2
;
parameter
[
1
:
0
]
ABCIOOOI
=
3
;
reg
ABClOOOI
;
reg
ABCOIOOI
;
wire
RESETN
;
wire
ABCIIOOI
;
wire
[
APB_DWIDTH
-
1
:
0
]
ABClIOOI
;
wire
[
31
:
0
]
ABCOlOOI
;
wire
ABClllI
;
wire
ABCO0lI
;
assign
ABCOlOOI
=
{
32
{
1
'b
0
}
}
;
assign
ABClllI
=
1
'b
0
;
assign
ABCO0lI
=
1
'b
1
;
integer
ABCIlOOI
;
integer
ABCllOOI
;
reg
[
APB_DWIDTH
-
1
:
0
]
ABCO0OOI
;
wire
[
ICWIDTH
-
1
:
0
]
ABCI0OOI
=
SMADDR
+
1
;
reg
[
7
:
0
]
ABCIIlI
;
reg
[
15
:
0
]
ABCl0OOI
;
reg
[
ICWIDTH
-
1
:
0
]
ADDRESS
;
wire
ABCO1OOI
;
wire
ABCI1OOI
;
wire
ABCl1OOI
;
wire
[
APB_AWIDTH
-
1
:
0
]
ABCOOIOI
;
wire
[
APB_DWIDTH
-
1
:
0
]
ABCIOIOI
;
wire
[
APB_DWIDTH
-
1
:
0
]
ABClOIOI
;
wire
ABCOIIOI
;
wire
ABCIIIOI
;
generate
if
(
IMEM_APB_ACCESS
==
0
)
begin
assign
ABCO1OOI
=
1
'b
0
;
assign
ABCI1OOI
=
1
'b
0
;
assign
ABCl1OOI
=
1
'b
0
;
assign
ABCOOIOI
=
{
APB_AWIDTH
{
1
'b
0
}
}
;
assign
ABCIOIOI
=
{
APB_DWIDTH
{
1
'b
0
}
}
;
assign
PRDATA_S
=
{
APB_DWIDTH
{
1
'b
0
}
}
;
assign
PSLVERR_S
=
1
'b
0
;
assign
PREADY_S
=
1
'b
1
;
end
else
begin
assign
ABCO1OOI
=
PSEL_S
;
assign
ABCI1OOI
=
PENABLE_S
;
assign
ABCl1OOI
=
PWRITE_S
;
assign
ABCOOIOI
=
PADDR_S
;
assign
ABCIOIOI
=
PWDATA_S
;
assign
PRDATA_S
=
ABClOIOI
;
assign
PSLVERR_S
=
ABCOIIOI
;
assign
PREADY_S
=
ABCIIIOI
;
end
endgenerate
always
@
(
posedge
PCLK
or
negedge
NSYSRESET
)
begin
if
(
NSYSRESET
==
1
'b
0
)
begin
ABClOOOI
<=
1
'b
0
;
ABCOIOOI
<=
1
'b
0
;
end
else
begin
ABClOOOI
<=
1
'b
1
;
ABCOIOOI
<=
ABClOOOI
;
end
end
assign
PRESETN
=
ABCOIOOI
;
assign
RESETN
=
ABCOIOOI
;
generate
if
(
EN_RAM
>
0
|
EN_CALL
>
0
|
EN_INT
>
0
|
EN_PUSH
>
0
)
begin
:
ABCIO0I
always
@
(
INSTR_ADDR
or
INSTR_CMD
or
INSTR_SCMD
or
ABCIIl1
or
ABCI0l1
or
ABCOIl1
or
SMADDR
or
ABCO101
or
ABCO111
or
ABCI0OOI
)
begin
ABClI11
<=
{
8
{
1
'b
x
}
}
;
ABCll11
<=
{
ABCII
{
1
'b
x
}
}
;
if
(
(
INSTR_CMD
==
3
'b
011
|
ABCIIl1
==
1
'b
1
)
&
EN_RAM
>
0
&
ABCO101
==
1
'b
0
)
begin
for
(
ABCIlOOI
=
0
;
(
ABCIlOOI
<
ABCII
&
ABCIlOOI
<
APB_DWIDTH
)
;
ABCIlOOI
=
ABCIlOOI
+
1
)
ABCll11
[
ABCIlOOI
]
<=
ABCI0l1
[
ABCIlOOI
]
;
ABClI11
<=
INSTR_ADDR
[
7
:
0
]
;
if
(
INSTR_CMD
==
3
'b
011
&
(
INSTR_SCMD
[
2
]
)
==
1
'b
1
&
EN_PUSH
==
1
)
begin
ABClI11
<=
ABCOIl1
;
end
end
else
if
(
EN_CALL
>
0
|
EN_INT
>
0
)
begin
ABClI11
<=
ABCOIl1
;
if
(
EN_INT
>
0
&
ABCO101
==
1
'b
1
)
begin
for
(
ABCIlOOI
=
0
;
(
ABCIlOOI
<
ABCII
&
ABCIlOOI
<
ICWIDTH
)
;
ABCIlOOI
=
ABCIlOOI
+
1
)
ABCll11
[
ABCIlOOI
]
<=
SMADDR
[
ABCIlOOI
]
;
end
else
begin
for
(
ABCIlOOI
=
0
;
(
ABCIlOOI
<
ABCII
&
ABCIlOOI
<
ICWIDTH
)
;
ABCIlOOI
=
ABCIlOOI
+
1
)
ABCll11
[
ABCIlOOI
]
<=
ABCI0OOI
[
ABCIlOOI
]
;
end
end
end
always
@
(
ABClI11
)
begin
ABCOl11
<=
{
8
{
1
'b
0
}
}
;
begin
:
ABCO1OI
integer
ABCOlI
;
for
(
ABCOlI
=
7
;
ABCOlI
>=
0
;
ABCOlI
=
ABCOlI
-
1
)
begin
if
(
(
ABClI11
[
ABCOlI
]
)
==
1
'b
1
)
begin
ABCOl11
[
ABCOlI
]
<=
1
'b
1
;
end
end
end
end
Top_Waveform_COREABC_0_RAMBLOCKS
#
(
.DWIDTH
(
ABCII
)
,
.FAMILY
(
FAMILY
)
)
ABCOO0I
(
.CLK
(
PCLK
)
,
.RESETN
(
RESETN
)
,
.WEN
(
ABCOI11
)
,
.ADDR
(
ABCOl11
)
,
.WD
(
ABCll11
)
,
.RD
(
ABCIl11
)
)
;
assign
RAMDOUT
=
ABCIl11
[
APB_DWIDTH
-
1
:
0
]
;
end
endgenerate
generate
if
(
EN_RAM
==
0
&
EN_CALL
==
0
&
EN_INT
==
0
&
EN_PUSH
==
0
)
begin
:
ABClIIOI
wire
[
7
:
0
]
ABCOlIOI
=
{
8
{
1
'b
0
}
}
;
always
@
(
ABCOlIOI
)
begin
ABClI11
<=
ABCOlIOI
;
end
wire
[
ABCII
-
1
:
0
]
ABCIlIOI
=
{
ABCII
-
1
-
(
0
)
+
1
{
1
'b
0
}
}
;
always
@
(
ABCIlIOI
)
begin
ABCll11
<=
ABCIlIOI
;
end
assign
RAMDOUT
=
{
APB_DWIDTH
-
1
-
(
0
)
+
1
{
1
'b
0
}
}
;
wire
[
7
:
0
]
ABCO1I1
=
{
8
{
1
'b
0
}
}
;
always
@
(
ABCO1I1
)
begin
ABCOl11
<=
ABCO1I1
;
end
assign
ABCIl11
=
{
ABCII
-
1
-
(
0
)
+
1
{
1
'b
0
}
}
;
end
endgenerate
generate
if
(
EN_ACM
==
1
)
begin
:
ABCllIOI
Top_Waveform_COREABC_0_ACMTABLE
#
(
.TESTMODE
(
TESTMODE
)
)
ABCO0IOI
(
.ACMADDR
(
ACCUMULATOR
[
7
:
0
]
)
,
.ACMDATA
(
ACMDATA
)
,
.ACMDO
(
ACMDO
)
)
;
end
endgenerate
generate
if
(
EN_ACM
==
0
)
begin
:
ABCI0IOI
assign
ACMDATA
=
{
8
{
1
'b
0
}
}
;
assign
ACMDO
=
1
'b
0
;
end
endgenerate
generate
if
(
INSMODE
==
0
|
(
INSMODE
==
2
&
FAMILY
!=
17
)
)
begin
:
UROM
Top_Waveform_COREABC_0_INSTRUCTIONS
#
(
.AWIDTH
(
APB_AWIDTH
)
,
.DWIDTH
(
APB_DWIDTH
)
,
.SWIDTH
(
APB_SWIDTH
)
,
.ICWIDTH
(
ICWIDTH
)
,
.IIWIDTH
(
IIWIDTH
)
,
.IFWIDTH
(
IFWIDTH
)
,
.IWWIDTH
(
IWWIDTH
)
,
.EN_MULT
(
EN_MULT
)
,
.EN_INC
(
EN_INC
)
,
.TESTMODE
(
TESTMODE
)
)
UROM
(
.ADDRESS
(
ADDRESS
)
,
.INSTRUCTION
(
INSTRUCTION
)
)
;
always
@
(
posedge
PCLK
)
begin
if
(
ABCO1OOI
==
1
'b
0
)
begin
INSTR_CMD
<=
INSTRUCTION
[
2
:
0
]
;
INSTR_SCMD
<=
INSTRUCTION
[
5
:
3
]
;
INSTR_SLOT
<=
INSTRUCTION
[
APB_SWIDTH
+
6
:
6
]
;
INSTR_SLOT
[
APB_SWIDTH
]
<=
1
'b
0
;
INSTR_ADDR
<=
INSTRUCTION
[
APB_AWIDTH
-
1
+
4
+
6
:
4
+
6
]
;
INSTR_DATA
<=
INSTRUCTION
[
APB_DWIDTH
-
1
+
16
+
4
+
6
:
16
+
4
+
6
]
;
ABCIIl1
<=
INSTRUCTION
[
6
]
;
end
end
assign
STALL
=
1
'b
0
;
always
@
(
negedge
RESETN
or
posedge
PCLK
)
begin
if
(
!
RESETN
)
begin
ABCIIlI
<=
8
'b
0
;
end
else
begin
if
(
(
ABCO1OOI
==
1
'b
1
)
&&
(
ABCl1OOI
==
1
'b
1
)
)
begin
ABCIIlI
<=
ABCIOIOI
[
7
:
0
]
;
end
end
end
always
@(*)
begin
ADDRESS
[
ICWIDTH
-
1
:
0
]
=
{
ICWIDTH
{
1
'b
0
}
}
;
if
(
ABCO1OOI
==
1
'b
1
)
begin
ABCl0OOI
=
{
ABCIIlI
[
7
:
0
]
,
ABCOOIOI
[
7
:
0
]
}
;
end
else
begin
ABCl0OOI
[
ICWIDTH
-
1
:
0
]
=
SMADDR
;
end
ADDRESS
[
ICWIDTH
-
1
:
0
]
=
ABCl0OOI
[
ICWIDTH
-
1
:
0
]
;
end
assign
ABClOIOI
[
APB_DWIDTH
-
1
:
0
]
=
INSTRUCTION
[
APB_DWIDTH
-
1
:
0
]
;
assign
ABCIIIOI
=
1
'b
1
;
assign
ABCOIIOI
=
1
'b
0
;
end
endgenerate
generate
if
(
INSMODE
==
1
)
begin
:
ABCl0IOI
Top_Waveform_COREABC_0_INSTRUCTRAM
#
(
.AWIDTH
(
APB_AWIDTH
)
,
.DWIDTH
(
APB_DWIDTH
)
,
.SWIDTH
(
APB_SWIDTH
)
,
.ICWIDTH
(
ICWIDTH
)
,
.ABCOI
(
ABCOI
)
,
.IWWIDTH
(
IWWIDTH
)
,
.INITWIDTH
(
INITWIDTH
)
,
.TESTMODE
(
TESTMODE
)
,
.IMEM_APB_ACCESS
(
IMEM_APB_ACCESS
)
,
.UNIQ_STRING_LENGTH
(
UNIQ_STRING_LENGTH
)
)
ABCl0IOI
(
.CLK
(
PCLK
)
,
.RSTN
(
RESETN
)
,
.INITDATVAL
(
INITDATVAL
)
,
.INITDONE
(
INITDONE
)
,
.INITADDR
(
INITADDR
)
,
.INITDATA
(
INITDATA
)
,
.ADDRESS
(
SMADDR
)
,
.INSTRUCTION
(
INSTRUCTION
)
,
.PSEL
(
ABCO1OOI
)
,
.PENABLE
(
ABCI1OOI
)
,
.PWRITE
(
ABCl1OOI
)
,
.PADDR
(
ABCOOIOI
)
,
.PWDATA
(
ABCIOIOI
)
,
.PRDATA
(
ABClOIOI
)
,
.PSLVERR
(
ABCOIIOI
)
,
.PREADY
(
ABCIIIOI
)
)
;
always
@
(
INSTRUCTION
)
begin
INSTR_CMD
<=
INSTRUCTION
[
2
:
0
]
;
INSTR_SCMD
<=
INSTRUCTION
[
5
:
3
]
;
INSTR_SLOT
<=
INSTRUCTION
[
APB_SWIDTH
+
6
:
6
]
;
INSTR_SLOT
[
APB_SWIDTH
]
<=
1
'b
0
;
INSTR_ADDR
<=
INSTRUCTION
[
APB_AWIDTH
-
1
+
4
+
6
:
4
+
6
]
;
INSTR_DATA
<=
INSTRUCTION
[
APB_DWIDTH
-
1
+
16
+
4
+
6
:
16
+
4
+
6
]
;
ABCIIl1
<=
INSTRUCTION
[
6
]
;
end
assign
STALL
=
1
'b
0
;
end
endgenerate
generate
if
(
INSMODE
==
2
&
FAMILY
==
17
)
begin
:
ABCO1IOI
Top_Waveform_COREABC_0_INSTRUCTNVM
#
(
.MAX_NVMDWIDTH
(
MAX_NVMDWIDTH
)
,
.AWIDTH
(
APB_AWIDTH
)
,
.DWIDTH
(
APB_DWIDTH
)
,
.SWIDTH
(
APB_SWIDTH
)
,
.ICWIDTH
(
ICWIDTH
)
,
.ABCOI
(
ABCOI
)
,
.IWWIDTH
(
IWWIDTH
)
,
.ACT_CALIBRATIONDATA
(
ACT_CALIBRATIONDATA
)
,
.IMEM_APB_ACCESS
(
IMEM_APB_ACCESS
)
,
.UNIQ_STRING_LENGTH
(
UNIQ_STRING_LENGTH
)
)
ABCI1IOI
(
.CLK
(
PCLK
)
,
.RSTN
(
RESETN
)
,
.START
(
ABCI011
)
,
.STALL
(
STALL
)
,
.ADDRESS
(
SMADDR
)
,
.INSTRUCTION
(
INSTRUCTION
)
,
.PSEL
(
ABCO1OOI
)
,
.PENABLE
(
ABCI1OOI
)
,
.PWRITE
(
ABCl1OOI
)
,
.PADDR
(
ABCOOIOI
)
,
.PWDATA
(
ABCIOIOI
)
,
.PRDATA
(
ABClOIOI
)
,
.PSLVERR
(
ABCOIIOI
)
,
.PREADY
(
ABCIIIOI
)
)
;
always
@
(
INSTRUCTION
)
begin
INSTR_CMD
<=
INSTRUCTION
[
2
:
0
]
;
INSTR_SCMD
<=
INSTRUCTION
[
5
:
3
]
;
INSTR_SLOT
<=
INSTRUCTION
[
APB_SWIDTH
+
6
:
6
]
;
INSTR_SLOT
[
APB_SWIDTH
]
<=
1
'b
0
;
INSTR_ADDR
<=
INSTRUCTION
[
APB_AWIDTH
-
1
+
4
+
6
:
4
+
6
]
;
INSTR_DATA
<=
INSTRUCTION
[
APB_DWIDTH
-
1
+
16
+
4
+
6
:
16
+
4
+
6
]
;
ABCIIl1
<=
INSTRUCTION
[
6
]
;
end
end
endgenerate
always
@
(
INSTR_DATA
or
ACCUMULATOR
)
begin
ABCI101
<=
1
'b
x
;
ABCl101
<=
1
'b
x
;
if
(
EN_SHL
==
1
|
EN_SHR
==
1
)
begin
case
(
INSTR_DATA
[
1
:
0
]
)
2
'b
00
:
begin
ABCI101
<=
1
'b
0
;
ABCl101
<=
1
'b
0
;
end
2
'b
01
:
begin
ABCI101
<=
1
'b
1
;
ABCl101
<=
1
'b
1
;
end
2
'b
10
:
begin
ABCI101
<=
ACCUMULATOR
[
APB_DWIDTH
-
1
]
;
ABCl101
<=
ACCUMULATOR
[
0
]
;
end
2
'b
11
:
begin
ABCI101
<=
ACCUMULATOR
[
0
]
;
ABCl101
<=
ACCUMULATOR
[
APB_DWIDTH
-
1
]
;
end
default
:
begin
end
endcase
end
end
assign
ABCIIOOI
=
ABCIlI
(
EN_RAM
==
1
)
&
(
ABCII11
|
(
ABCIlI
(
EN_ALURAM
==
1
)
&
ABCIIl1
)
)
;
assign
ABClIOOI
=
(
ABCIIOOI
==
1
'b
0
)
?
INSTR_DATA
:
RAMDOUT
;
always
@
(
ACCUMULATOR
or
ABClIOOI
)
begin
:
ABCl1IOI
reg
[
2
*
APB_DWIDTH
-
1
:
0
]
ABCOOlOI
;
reg
[
APB_DWIDTH
/
2
-
1
:
0
]
A
;
reg
[
APB_DWIDTH
/
2
-
1
:
0
]
B
;
case
(
EN_MULT
)
1
:
begin
A
=
ACCUMULATOR
[
APB_DWIDTH
/
2
-
1
:
0
]
;
B
=
ABClIOOI
[
APB_DWIDTH
/
2
-
1
:
0
]
;
ABCOO01
<=
A
*
B
;
end
2
:
begin
ABCOOlOI
=
ACCUMULATOR
*
ABClIOOI
;
ABCOO01
<=
ABCOOlOI
[
APB_DWIDTH
-
1
:
0
]
;
end
3
:
begin
ABCOOlOI
=
ACCUMULATOR
*
ABClIOOI
;
ABCOO01
<=
ABCOOlOI
[
2
*
APB_DWIDTH
-
1
:
APB_DWIDTH
]
;
end
default
:
begin
ABCOO01
<=
{
APB_DWIDTH
{
1
'b
x
}
}
;
end
endcase
end
always
@
(
ABCII11
or
INSTR_SCMD
or
ACCUMULATOR
or
INSTR_DATA
or
ABCI101
or
ABCl101
or
ABClIOOI
or
ABCOO01
)
begin
:
ABCIOlOI
reg
[
2
:
0
]
ABClOlOI
;
ABCOll1
<=
{
APB_DWIDTH
{
1
'b
x
}
}
;
ABClOlOI
=
INSTR_SCMD
;
if
(
ABCII11
==
1
'b
1
)
begin
ABClOlOI
=
3
'b
111
;
end
case
(
ABClOlOI
)
3
'b
000
:
begin
if
(
EN_INC
==
1
&
EN_MULT
==
0
&
(
INSMODE
==
0
|
(
INSMODE
==
2
&
FAMILY
!=
17
)
)
)
begin
ABCOll1
<=
ACCUMULATOR
+
1
;
end
if
(
EN_MULT
>=
1
)
begin
ABCOll1
<=
ABCOO01
;
end
end
3
'b
001
:
begin
if
(
EN_AND
==
1
)
begin
ABCOll1
<=
ACCUMULATOR
&
ABClIOOI
;
end
end
3
'b
010
:
begin
if
(
EN_OR
==
1
)
begin
ABCOll1
<=
ACCUMULATOR
|
ABClIOOI
;
end
end
3
'b
011
:
begin
if
(
EN_XOR
==
1
)
begin
ABCOll1
<=
ACCUMULATOR
^
ABClIOOI
;
end
end
3
'b
100
:
begin
if
(
EN_ADD
==
1
|
(
EN_INC
==
1
&
(
EN_MULT
>=
1
|
INSMODE
>
0
)
)
)
begin
ABCOll1
<=
ACCUMULATOR
+
ABClIOOI
;
end
end
3
'b
101
:
begin
if
(
EN_SHL
==
1
)
begin
ABCOll1
<=
{
ACCUMULATOR
[
APB_DWIDTH
-
2
:
0
]
,
ABCl101
}
;
end
end
3
'b
110
:
begin
if
(
EN_SHR
==
1
)
begin
ABCOll1
<=
{
ABCI101
,
ACCUMULATOR
[
APB_DWIDTH
-
1
:
1
]
}
;
end
end
3
'b
111
:
begin
ABCOll1
<=
ABClIOOI
;
end
default
:
begin
ABCOll1
<=
{
APB_DWIDTH
{
1
'b
x
}
}
;
end
endcase
end
always
@
(
ABCII11
or
INSTR_CMD
or
ABCOll1
or
PRDATA_M
or
IO_IN
)
begin
if
(
(
EN_RAM
>
0
&
ABCII11
==
1
'b
1
)
|
(
INSTR_CMD
[
1
]
)
==
1
'b
0
)
begin
ABClIl1
<=
ABCOll1
;
end
else
if
(
EN_IOREAD
==
1
&
(
INSTR_CMD
[
0
]
)
==
1
'b
1
)
begin
ABClIl1
<=
0
;
ABClIl1
[
IIWIDTH
-
1
:
0
]
<=
IO_IN
;
end
else
begin
ABClIl1
<=
PRDATA_M
[
APB_DWIDTH
-
1
:
0
]
;
end
end
always
@
(
posedge
PCLK
or
negedge
RESETN
)
begin
if
(
RESETN
==
1
'b
0
)
begin
ACCUMULATOR
<=
{
APB_DWIDTH
-
1
-
(
0
)
+
1
{
1
'b
0
}
}
;
ABCIl01
<=
1
'b
0
;
ABCll01
<=
1
'b
0
;
ABCO001
<=
1
'b
0
;
ABCI001
<=
1
'b
0
;
end
else
begin
if
(
ABCII01
==
1
'b
1
|
ABCOl01
==
1
'b
1
)
begin
ACCUMULATOR
<=
ABClIl1
;
end
if
(
ISR
==
1
'b
0
&
ABClI01
==
1
'b
1
)
begin
ABCIl01
<=
ABCIlI
(
ABClIl1
==
ABCOlOOI
[
APB_DWIDTH
-
1
:
0
]
)
;
ABCll01
<=
ABClIl1
[
APB_DWIDTH
-
1
]
;
end
if
(
ISR
==
1
'b
1
&
ABClI01
==
1
'b
1
&
EN_INT
>
0
)
begin
ABCO001
<=
ABCIlI
(
ABClIl1
==
ABCOlOOI
[
APB_DWIDTH
-
1
:
0
]
)
;
ABCI001
<=
ABClIl1
[
APB_DWIDTH
-
1
]
;
end
if
(
EN_INT
==
0
)
begin
ABCO001
<=
1
'b
0
;
ABCI001
<=
1
'b
0
;
end
end
end
assign
ACCUM_ZERO
=
(
ISR
==
1
'b
1
)
?
ABCO001
:
ABCIl01
;
assign
ACCUM_NEG
=
(
ISR
==
1
'b
1
)
?
ABCI001
:
ABCll01
;
assign
ABCOI01
=
(
ZREGISTER
==
ABCOlOOI
[
ZRWIDTH
:
0
]
&
ZRWIDTH
>
0
)
?
1
'b
1
:
1
'b
0
;
always
@
(
INSTR_DATA
or
INSTR_SCMD
or
IO_IN
or
ACCUM_NEG
or
ACCUM_ZERO
or
ABCOI01
)
begin
:
ABCOIlOI
reg
[
31
:
0
]
ABCIIlOI
;
reg
ABCIO1
;
ABCIIlOI
=
{
32
{
1
'b
0
}
}
;
ABCIIlOI
[
3
:
0
]
=
(
{
ABCOI01
,
ACCUM_NEG
,
ACCUM_ZERO
,
1
'b
1
}
)
;
begin
:
ABClIlOI
integer
ABCOlI
;
for
(
ABCOlI
=
0
;
ABCOlI
<=
IFWIDTH
-
1
;
ABCOlI
=
ABCOlI
+
1
)
begin
ABCIIlOI
[
ABCOlI
+
4
]
=
IO_IN
[
ABCOlI
]
;
end
end
ABCIO1
=
1
'b
0
;
begin
:
ABCOllOI
integer
ABCOlI
;
for
(
ABCOlI
=
0
;
ABCOlI
<=
IFWIDTH
+
4
-
1
;
ABCOlI
=
ABCOlI
+
1
)
begin
ABCIO1
=
ABCIO1
|
(
INSTR_DATA
[
ABCOlI
]
&
ABCIIlOI
[
ABCOlI
]
)
;
end
end
FLAGS
<=
~
(
ABCIO1
^
INSTR_SCMD
[
0
]
)
;
end
always
@
(
INSTR_CMD
or
INSTR_SCMD
or
ABCIIl1
)
begin
ABClO01
<=
1
'b
x
;
ABCIO01
<=
1
'b
x
;
case
(
INSTR_CMD
)
3
'b
010
:
begin
if
(
(
INSTR_SCMD
[
0
]
)
==
1
'b
1
)
begin
ABClO01
<=
1
'b
0
;
ABCIO01
<=
1
'b
x
;
end
else
if
(
EN_ACM
==
1
&
(
INSTR_SCMD
[
1
]
)
==
1
'b
1
)
begin
ABClO01
<=
1
'b
1
;
ABCIO01
<=
1
'b
1
;
end
else
begin
ABClO01
<=
1
'b
1
;
ABCIO01
<=
1
'b
0
;
end
end
3
'b
011
:
begin
if
(
ABCIIl1
==
1
'b
0
)
begin
ABClO01
<=
1
'b
0
;
ABCIO01
<=
1
'b
x
;
end
else
begin
ABClO01
<=
1
'b
1
;
ABCIO01
<=
1
'b
0
;
end
end
default
:
begin
ABClO01
<=
1
'b
x
;
ABCIO01
<=
1
'b
x
;
end
endcase
end
always
@
(
ABCIO01
or
ACCUMULATOR
or
ACMDATA
)
begin
ABCIll1
<=
ACCUMULATOR
;
if
(
EN_ACM
==
1
&
ABCIO01
==
1
'b
1
)
begin
ABCIll1
[
7
:
0
]
<=
ACMDATA
;
end
end
always
@
(
ABClO01
or
INSTR_DATA
or
ABCIll1
)
begin
if
(
ABClO01
==
1
'b
0
)
begin
ABClll1
<=
INSTR_DATA
;
end
else
begin
ABClll1
<=
ABCIll1
;
end
end
always
@
(
ABCIll1
or
ABClll1
or
ACCUMULATOR
or
INSTR_DATA
)
begin
case
(
EN_DATAM
)
0
:
begin
ABCO0l1
<=
ABCIll1
;
ABCI0l1
<=
ACCUMULATOR
;
ABCl0l1
<=
ACCUMULATOR
;
ABCI1l1
<=
ACCUMULATOR
;
end
1
:
begin
ABCO0l1
<=
INSTR_DATA
;
ABCI0l1
<=
INSTR_DATA
;
ABCl0l1
<=
INSTR_DATA
;
ABCI1l1
<=
INSTR_DATA
;
end
2
:
begin
ABCO0l1
<=
ABClll1
;
ABCI0l1
<=
ABClll1
;
ABCl0l1
<=
ABClll1
;
ABCI1l1
<=
ABClll1
;
end
3
:
begin
ABCO0l1
<=
ABCIll1
;
ABCI0l1
<=
ACCUMULATOR
;
ABCl0l1
<=
INSTR_DATA
;
ABCI1l1
<=
INSTR_DATA
;
end
endcase
ABCl1l1
<=
{
APB_DWIDTH
-
1
-
(
0
)
+
1
{
1
'b
0
}
}
;
// synthesis translate_off
ABCl1l1
<=
ABClll1
;
// synthesis translate_on
end
always
@
(
ABCl0l1
)
begin
:
ABCIllOI
integer
ABCOlI
;
ABCO1l1
<=
0
;
for
(
ABCOlI
=
0
;
ZRWIDTH
>
0
&
ABCOlI
<
ZRWIDTH
;
ABCOlI
=
ABCOlI
+
1
)
ABCO1l1
[
ABCOlI
]
<=
ABCl0l1
[
ZRWIDTH
-
1
]
;
for
(
ABCOlI
=
0
;
(
ABCOlI
<
APB_DWIDTH
&
ABCOlI
<
ZRWIDTH
)
;
ABCOlI
=
ABCOlI
+
1
)
ABCO1l1
[
ABCOlI
]
<=
ABCl0l1
[
ABCOlI
]
;
end
assign
ABCII11
=
ABCIlI
(
INSTR_CMD
==
3
'b
011
&
EN_RAM
>
0
&
INSTR_SCMD
[
2
:
1
]
!=
2
'b
11
)
;
always
@
(
STKPTR
)
begin
ABCllOI
<=
{
8
{
1
'b
1
}
}
;
ABCO0OI
<=
{
8
{
1
'b
1
}
}
;
ABCllOI
[
STWIDTH
-
1
:
0
]
<=
STKPTR
[
STWIDTH
-
1
:
0
]
-
1
;
ABCO0OI
[
STWIDTH
-
1
:
0
]
<=
STKPTR
[
STWIDTH
-
1
:
0
]
+
1
;
end
assign
ABCOIl1
=
ABCO0OI
;
assign
ABCO011
=
ABCIlI
(
(
INTREQ
==
1
'b
1
&
(
EN_INT
==
1
)
)
|
(
INTREQ
==
1
'b
0
&
(
EN_INT
==
2
)
)
)
;
assign
ABClO11
=
PREADY_M
;
assign
ABCl011
=
ABCIlI
(
INSMODE
<=
1
)
|
~
STALL
;
integer
ABCO1l
;
wire
[
ABCII
-
1
+
12
:
0
]
ABClllOI
=
{
"000000000000"
,
ABCIl11
}
;
always
@
(
posedge
PCLK
or
negedge
RESETN
)
begin
if
(
RESETN
==
1
'b
0
)
begin
ABCIO11
<=
1
'b
0
;
ABCOO11
<=
1
'b
0
;
ABClI01
<=
1
'b
0
;
ABCII01
<=
1
'b
0
;
ABCO111
<=
ABCIOOOI
;
ABCl001
<=
1
'b
0
;
ABCO101
<=
1
'b
0
;
ABCOI11
<=
1
'b
0
;
SMADDR
<=
{
ICWIDTH
-
1
-
(
0
)
+
1
{
1
'b
1
}
}
;
ZREGISTER
<=
{
ZRWIDTH
-
(
0
)
+
1
{
1
'b
0
}
}
;
IO_OUT
<=
{
IOWIDTH
-
1
-
(
0
)
+
1
{
1
'b
0
}
}
;
STKPTR
<=
{
8
{
1
'b
1
}
}
;
ISR
<=
1
'b
0
;
ABCI011
<=
1
'b
0
;
end
else
begin
ABCIO11
<=
1
'b
0
;
ABCOO11
<=
1
'b
0
;
ABClI01
<=
1
'b
0
;
ABCII01
<=
1
'b
0
;
ABCOI11
<=
1
'b
0
;
ABCI011
<=
1
'b
0
;
case
(
ABCO111
)
ABCI111
:
begin
if
(
INITDONE
==
1
'b
1
|
INSMODE
==
0
|
INSMODE
==
2
)
begin
if
(
EN_INT
>
0
&
ABCO011
==
1
'b
1
&
ISR
==
1
'b
0
)
begin
ISR
<=
1
'b
1
;
STKPTR
<=
ABCllOI
;
ABCO101
<=
1
'b
1
;
ABCO111
<=
ABCl111
;
ABCOI11
<=
1
'b
1
;
end
else
begin
ABCO111
<=
ABCl111
;
end
end
end
ABCl111
:
begin
if
(
ABCl011
==
1
'b
1
)
begin
if
(
ABCO101
==
1
'b
1
)
begin
ABCO111
<=
ABCIOOOI
;
end
else
begin
case
(
INSTR_CMD
)
3
'b
000
:
begin
ABCO111
<=
ABCIOOOI
;
ABClI01
<=
1
'b
1
;
ABCII01
<=
1
'b
1
;
end
3
'b
001
:
begin
ABCO111
<=
ABCIOOOI
;
ABClI01
<=
1
'b
1
;
end
3
'b
010
:
begin
if
(
EN_ACM
==
1
&
INSTR_SCMD
[
1
:
0
]
==
2
'b
10
)
begin
ABCIO11
<=
ACMDO
;
end
else
begin
ABCIO11
<=
1
'b
1
;
end
ABCO111
<=
ABCOOOOI
;
end
3
'b
011
:
begin
case
(
INSTR_SCMD
)
3
'b
000
:
begin
if
(
ZRWIDTH
>
0
)
begin
for
(
ABCO1l
=
0
;
ABCO1l
<
ZRWIDTH
;
ABCO1l
=
ABCO1l
+
1
)
ZREGISTER
[
ABCO1l
]
<=
ABCO1l1
[
ABCO1l
]
;
end
end
3
'b
001
:
begin
if
(
ZRWIDTH
>
0
)
begin
ZREGISTER
[
ZRWIDTH
-
1
:
0
]
<=
ZREGISTER
[
ZRWIDTH
-
1
:
0
]
+
ABCO1l1
[
ZRWIDTH
-
1
:
0
]
;
end
end
3
'b
010
:
begin
if
(
EN_RAM
>
0
)
begin
ABCOI11
<=
1
'b
1
;
end
end
3
'b
011
:
begin
if
(
EN_RAM
>
0
)
begin
ABClI01
<=
1
'b
1
;
ABCII01
<=
1
'b
1
;
end
end
3
'b
100
:
begin
if
(
EN_PUSH
==
1
)
begin
STKPTR
<=
ABCllOI
;
ABCOI11
<=
1
'b
1
;
end
end
3
'b
101
:
begin
if
(
EN_PUSH
==
1
)
begin
STKPTR
<=
ABCO0OI
;
ABClI01
<=
1
'b
1
;
ABCII01
<=
1
'b
1
;
end
end
3
'b
110
:
begin
if
(
EN_IOREAD
==
1
)
begin
ABClI01
<=
1
'b
1
;
ABCII01
<=
1
'b
1
;
end
end
3
'b
111
:
begin
if
(
EN_IOWRT
==
1
)
begin
IO_OUT
[
IOWIDTH
-
1
:
0
]
<=
ABCI1l1
[
IOWIDTH
-
1
:
0
]
;
end
end
default
:
begin
end
endcase
ABCO111
<=
ABCIOOOI
;
end
3
'b
100
:
begin
if
(
FLAGS
==
1
'b
1
)
begin
ABCl001
<=
1
'b
1
;
end
ABCO111
<=
ABCIOOOI
;
end
3
'b
101
:
begin
if
(
EN_CALL
==
1
&
FLAGS
==
1
'b
1
)
begin
STKPTR
<=
ABCllOI
;
ABCOI11
<=
1
'b
1
;
ABCl001
<=
1
'b
1
;
end
ABCO111
<=
ABCIOOOI
;
end
3
'b
110
:
begin
if
(
(
EN_CALL
==
1
|
EN_INT
>
0
)
&
FLAGS
==
1
'b
1
)
begin
ABCO111
<=
ABCIOOOI
;
STKPTR
<=
ABCO0OI
;
ABCl001
<=
1
'b
1
;
if
(
(
INSTR_SCMD
[
1
]
)
==
1
'b
1
&
EN_INT
>
0
)
begin
ISR
<=
1
'b
0
;
end
end
else
begin
ABCO111
<=
ABCIOOOI
;
end
end
3
'b
111
:
begin
ABCO111
<=
ABCIOOOI
;
end
default
:
begin
ABCO111
<=
ABCIOOOI
;
end
endcase
end
end
end
ABCOOOOI
:
begin
ABCOO11
<=
1
'b
1
;
ABCIO11
<=
1
'b
1
;
if
(
(
PREADY_M
==
1
'b
1
&
ABCOO11
==
1
'b
1
)
|
ABCIO11
==
1
'b
0
)
begin
ABCIO11
<=
1
'b
0
;
ABCOO11
<=
1
'b
0
;
ABCO111
<=
ABCIOOOI
;
end
end
ABCIOOOI
:
begin
if
(
ABCl011
==
1
'b
1
)
begin
ABCI011
<=
1
'b
1
;
ABCO101
<=
1
'b
0
;
ABCl001
<=
1
'b
0
;
if
(
ABCO101
==
1
'b
1
&
EN_INT
>
0
)
begin
SMADDR
<=
ISRADDR
;
end
else
if
(
ABCl001
==
1
'b
1
)
begin
SMADDR
<=
INSTR_ADDR
[
ICWIDTH
-
1
:
0
]
;
if
(
(
EN_CALL
==
1
|
EN_INT
>
0
)
&
INSTR_CMD
[
1
]
==
1
'b
1
)
for
(
ABCO1l
=
0
;
ABCO1l
<
ICWIDTH
&
(
EN_CALL
==
1
|
EN_INT
>
0
)
;
ABCO1l
=
ABCO1l
+
1
)
SMADDR
[
ABCO1l
]
<=
ABCIl11
[
ABCO1l
]
;
if
(
(
INSTR_CMD
[
1
]
==
1
'b
0
)
&
(
INSTR_SCMD
[
1
]
==
1
'b
1
)
)
SMADDR
<=
SMADDR
;
if
(
INSTR_CMD
==
3
'b
100
&
(
INSTR_SCMD
[
1
]
)
==
1
'b
1
)
ABCI011
<=
1
'b
0
;
end
else
begin
SMADDR
<=
SMADDR
+
1
;
end
ABCO111
<=
ABCI111
;
end
end
endcase
if
(
EN_CALL
==
0
&
EN_INT
==
0
)
begin
STKPTR
<=
{
8
{
1
'b
1
}
}
;
end
for
(
ABCO1l
=
7
;
ABCO1l
>=
STWIDTH
;
ABCO1l
=
ABCO1l
-
1
)
STKPTR
[
ABCO1l
]
<=
1
'b
1
;
if
(
ZRWIDTH
==
0
)
begin
ZREGISTER
<=
{
ZRWIDTH
-
(
0
)
+
1
{
1
'b
0
}
}
;
end
if
(
EN_RAM
==
0
&
EN_INT
==
0
&
EN_CALL
==
0
&
EN_PUSH
==
0
)
begin
ABCOI11
<=
1
'b
0
;
end
if
(
EN_INT
==
0
)
begin
ISR
<=
1
'b
0
;
ABCO101
<=
1
'b
0
;
end
if
(
EN_IOWRT
==
0
)
begin
IO_OUT
<=
{
IOWIDTH
-
1
-
(
0
)
+
1
{
1
'b
0
}
}
;
end
ZREGISTER
[
ZRWIDTH
]
<=
1
'b
0
;
if
(
INSMODE
!=
2
)
begin
ABCI011
<=
1
'b
0
;
end
end
end
assign
INTACT
=
ISR
;
always
@
(
INSTR_ADDR
or
INSTR_SCMD
or
ZREGISTER
or
INSTR_SLOT
)
begin
:
ABCO0lOI
localparam
ABCI0lOI
=
min
(
ZRWIDTH
,
APB_AWIDTH
)
;
integer
ABCO1l
;
PADDR_M
=
{
20
{
1
'b
0
}
}
;
PADDR_M
[
APB_SWIDTH
+
APB_AWIDTH
-
1
:
0
]
=
{
INSTR_SLOT
[
APB_SWIDTH
-
1
:
0
]
,
{
APB_AWIDTH
{
1
'b
0
}
}
}
;
if
(
EN_INDIRECT
==
1
&
INSTR_SCMD
[
2
]
==
1
'b
1
&
ZRWIDTH
>
0
)
begin
for
(
ABCO1l
=
0
;
ABCO1l
<
ABCI0lOI
;
ABCO1l
=
ABCO1l
+
1
)
PADDR_M
[
ABCO1l
]
=
ZREGISTER
[
ABCO1l
]
;
end
else
begin
PADDR_M
[
APB_AWIDTH
-
1
:
0
]
=
INSTR_ADDR
;
end
end
always
@
(
ABCO0l1
)
begin
PWDATA_M
<=
{
APB_DWIDTH
-
1
-
(
0
)
+
1
{
1
'b
0
}
}
;
PWDATA_M
[
APB_DWIDTH
-
1
:
0
]
<=
ABCO0l1
;
end
assign
PENABLE_M
=
ABCOO11
;
assign
PWRITE_M
=
~
(
INSTR_SCMD
[
0
]
&
INSTR_SCMD
[
1
]
)
;
assign
ABCOl01
=
ABCOO11
&
INSTR_SCMD
[
0
]
&
INSTR_SCMD
[
1
]
;
always
@
(
ABCIO11
)
begin
PSEL_M
=
ABCIO11
;
end
// synthesis translate_off
assign
DEBUG1
=
ABCIlI
(
(
ABCl011
==
1
'b
1
&
ABCO111
==
ABCl111
)
)
;
assign
DEBUG2
=
ABCIlI
(
ABCO111
==
ABCOOOOI
&
PREADY_M
==
1
'b
1
&
ABCOO11
==
1
'b
1
&
INSTR_SCMD
[
1
:
0
]
==
2
'b
11
)
;
Top_Waveform_COREABC_0_DEBUGBLK
#
(
.DEBUG
(
DEBUG
)
,
.AWIDTH
(
APB_AWIDTH
)
,
.DWIDTH
(
APB_DWIDTH
)
,
.SWIDTH
(
APB_SWIDTH
)
,
.ABCl
(
APB_SDEPTH
)
,
.ICWIDTH
(
ICWIDTH
)
,
.ABCOI
(
ABCOI
)
,
.ZRWIDTH
(
ZRWIDTH
)
,
.IIWIDTH
(
IIWIDTH
)
,
.IOWIDTH
(
IOWIDTH
)
,
.ABCII
(
ABCII
)
,
.EN_MULT
(
EN_MULT
)
)
ABCl0lOI
(
.PCLK
(
PCLK
)
,
.RESETN
(
RESETN
)
,
.SMADDR
(
SMADDR
)
,
.ISR
(
ISR
)
,
.INSTR_CMD
(
INSTR_CMD
)
,
.INSTR_SCMD
(
INSTR_SCMD
)
,
.INSTR_DATA
(
INSTR_DATA
)
,
.INSTR_ADDR
(
INSTR_ADDR
)
,
.INSTR_SLOT
(
INSTR_SLOT
)
,
.PRDATA
(
PRDATA_M
[
APB_DWIDTH
-
1
:
0
]
)
,
.PWDATA
(
ABCl1l1
)
,
.ACCUM_OLD
(
ACCUMULATOR
)
,
.ACCUM_NEW
(
ABClIl1
)
,
.ACCUM_ZERO
(
ACCUM_ZERO
)
,
.ACCUM_NEG
(
ACCUM_NEG
)
,
.FLAGS
(
FLAGS
)
,
.RAMDOUT
(
RAMDOUT
)
,
.STKPTR
(
STKPTR
)
,
.ZREGISTER
(
ZREGISTER
)
,
.ACMDO
(
ACMDO
)
,
.DEBUG1
(
DEBUG1
)
,
.DEBUG2
(
DEBUG2
)
)
;
// synthesis translate_on
endmodule
