-- Copyright 2008 Actel Corporation.  All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
-- Rev: 2.4   24Jan08 IPB  : Production Release
-- SVN Revision Information:
-- SVN $Revision: 14578 $
library IeeE;
use IEEE.STD_logic_1164.all;
use ieee.STD_LOgic_arith.all;
use ieee.STD_logic_unsiGNED.all;
library COREABC_LIB;
use COREABC_LIB.Top_Waveform_COREABC_0_suPPORT.all;
entity Top_Waveform_COREABC_0_COREABC is
generic (family: integER range 0 to 23 := 0;
apb_aWIDTH: Integer range 8 to 16 := 10;
apB_DWIDTh: INteger range 8 to 32 := 8;
apb_sdepth: Integer range 1 to 16 := 4;
Icwidth: INTEGEr range 1 to 16 := 8;
zrwIDTH: integer range 0 to 16 := 8;
IFwidth: iNTEGER range 0 to 28 := 4;
iiwidth: integer range 1 to 32 := 4;
IOWIDTH: integeR range 1 to 32 := 8;
STWIDTH: integeR range 1 to 8 := 4;
eN_RAM: Integer range 0 to 1 := 1;
EN_AND: INteger range 0 to 1 := 1;
EN_xor: integer range 0 to 1 := 1;
en_or: INTEGER range 0 to 1 := 1;
en_adD: inTEGER range 0 to 1 := 1;
EN_INC: INTEGEr range 0 to 1 := 1;
EN_shl: INteger range 0 to 1 := 1;
EN_SHR: INTEGer range 0 to 1 := 1;
en_call: integer range 0 to 1 := 1;
en_push: Integer range 0 to 1 := 1;
en_mulT: integer range 0 to 3 := 0;
en_acm: INTeger range 0 to 1 := 1;
en_dataM: Integer range 0 to 3 := 1;
en_int: INTEGEr range 0 to 2 := 1;
En_ioread: INTEGer range 0 to 1 := 1;
En_iowrt: integER range 0 to 1 := 1;
eN_ALuram: Integer range 0 to 1 := 1;
en_indirecT: integeR range 0 to 1 := 1;
ISRADDR: integer range 0 to 65536 := 1;
DEBUG: INTEGEr range 0 to 1 := 1;
INSmode: Integer range 0 to 2 := 0;
initwIDTH: inteGER range 1 to 16 := 8;
testmode: inteGER range 0 to 99 := 0;
act_calIBRATIONData: intEGER range 0 to 1 := 1;
imem_apb_ACCESS: INTEGEr range 0 to 2 := 2;
UNIQ_STRing_lengtH: iNTEGER range 1 to 256 := 10;
mAX_NVMDWidth: Integer range 16 to 32 := 32); port (PCLK: in std_logIC;
nsYSRESET: in std_lOGIC;
PResetn: out STD_LOGic;
PENABLE_m: out STD_Logic;
PWRITE_m: out std_lOGIC;
PSel_m: out STD_LOGic;
PADDR_M: out STD_logic_vectOR(19 downto 0);
PWDATA_M: out STD_logic_vectOR(APB_DWIDTH-1 downto 0);
PRDATA_M: in STd_logic_veCTOR(APB_DWIDTH-1 downto 0);
pREADY_M: in STD_logic;
PSlverr_m: in STD_logic;
IO_IN: in STD_LOGic_vector(IIWIDTH-1 downto 0);
IO_OUT: out STD_LOgic_vector(IOWIDTH-1 downto 0);
INTREQ: in std_logic;
inTACT: out STD_LOGIc;
INITdatval: in std_logic;
INItdone: in std_logic;
INITADDR: in std_logic_VECTOR(INITWIDTH-1 downto 0);
INITDATA: in std_loGIC_VECTor(8 downto 0);
psel_s: in STD_Logic;
PENABLE_s: in STD_logic;
pwrite_s: in std_lOGIC;
PADDR_S: in sTD_LOGIC_vector(APB_AWIDTH-1 downto 0);
PWDATA_S: in Std_logic_veCTOR(APB_DWIDTH-1 downto 0);
PRDATA_S: out sTD_LOGIC_vector(APB_DWIDTH-1 downto 0);
psLVERR_S: out stD_LOGIC;
preadY_S: out std_loGIC);
end Top_Waveform_COREABC_0_COREABC;

architecture Rtl of Top_Waveform_COREABC_0_COREABC is

constant iwwidth: Integer := 32+16+4+6;

constant ABCloo1: inteGER := ABCol10(EN_RAM,
EN_CALL,
APB_DWIDTH,
ICWIDTH);

constant ABCioo1: intEGER range 1 to 65536 := 2**ICWIDTH;

constant APB_SWIDTH: intEGER range 0 to 4 := CALc_swidtH(APB_SDEPTH);

constant ABCIl0: inTEGER := APB_AWIDTH+APB_DWIDTH+APB_SWIDTH+6;

signal SMADDR: std_logic_VECTOR(ICWIDTH-1 downto 0);

signal Instruction: std_logIC_VECTor(IWWIDTh-1 downto 0);

signal STKPTR: std_logic_VECTOR(7 downto 0);

signal ABCIOI: std_logic_VECTOR(7 downto 0);

signal ABCOLi: std_logIC_VECTOr(7 downto 0);

signal ABColo1: stD_LOGIC_vector(7 downto 0);

signal INstr_cmd: std_logic_VECTOR(2 downto 0);

signal iNSTR_SCMd: STd_logic_vecTOR(2 downto 0);

signal Instr_slot: std_logIC_VECTOr(APB_SWIDTH downto 0);

signal insTR_ADDR: stD_LOGIC_vector(APB_AWIDTH-1 downto 0);

signal instr_dATA: std_logIC_VECtor(APB_DWIDTH-1 downto 0);

signal ABCllo1: std_logIC;

signal ACCUMULAtor: std_logiC_VECTOr(APB_DWIDTH-1 downto 0);

signal ABCILO1: STD_LOGic_vector(APB_DWIDTH-1 downto 0);

signal ABCoio1: std_logiC_VECTOR(APB_DWIDTH-1 downto 0);

signal ABCLIO1: STD_logic_vecTOR(APB_DWIDTH-1 downto 0);

signal ABCiio1: STd_logic_vecTOR(APB_DWIDTH-1 downto 0);

signal ABCO0O1: std_LOGIC_Vector(APB_DWIDTH-1 downto 0);

signal ABCl0o1: Std_logic_VECTOR(APB_DWIDTH-1 downto 0);

signal ABCI0O1: std_logic_VECTOr(APB_DWIDTH-1 downto 0);

signal ABCO1O1: STd_logic_vecTOR(APB_DWIDTH-1 downto 0);

signal ABCl1o1: std_lOGIC_VECtor(APB_DWIDTH-1 downto 0);

signal ABCi1o1: sTD_LOGIc_vector(ZRWIDTH-1 downto 0);

signal ABCoOL1: STD_LOGIc_vector(APB_DWIDTH-1 downto 0);

signal ABClol1: sTD_LOGIc;

signal ABCIOL1: Std_logic;

signal Zregister: STD_logic_vectoR(ZRWIDTH downto 0);

signal ABColl1: std_logic;

signal ABClll1: std_loGIC;

signal ABCilL1: STD_LOGIc;

signal ABCOIL1: STD_logic;

signal accuM_ZERO: STD_logic;

signal Accum_neg: std_logic;

signal ABClil1: std_logic;

signal ABCIIL1: std_LOGIC;

signal ABCO0L1: std_LOGIC;

signal ABCL0L1: Std_logic;

signal flAGS: std_lOGIC;

signal ABCi0l1: stD_LOGIC;

signal ABCo1l1: std_logic;

signal ABCl1L1: Std_logic;

signal ABCi1l1: STD_LOGIc;

signal ABCooi1: std_LOGIC;

signal ABCLOI1: Std_logic;

signal ABCIOI1: std_logic;

signal ABColi1: std_loGIC;

signal ABClli1: std_logIC;

signal ABCILI1: STD_LOgic_vector(7 downto 0);

signal ABCoii1: sTD_LOGic_vector(7 downto 0);

signal ABCLII1: std_logic_VECTOR(ABCLOO1-1 downto 0);

signal ABCiii1: std_LOGIC_Vector(ABCloo1-1 downto 0);

signal Ramdout: STD_logic_vectOR(APB_DWIDTH-1 downto 0);

signal Isr: STD_LOgic;

signal ABCo0I1: std_lOGIC;

signal acmdO: Std_logic;

signal ACMDATa: std_logic_VECTOR(7 downto 0);

signal debug1: Std_logic;

signal Debug2: STD_LOGic;

signal ABCl0i1: std_lOGIC;

signal stall: stD_LOGIC;

signal ABCi0i1: Std_logic;

type ABCo1i1 is (ABCl1i1,ABCI1I1,ABCoo01,ABCLO01);

signal ABCio01: ABCO1I1;

signal ABCOL01: std_logic;

signal ABCLL01: std_lOGIC;

signal RESETN: Std_logic;

signal ABCil01: std_loGIC;

signal ABCOI01: STd_logic_vecTOR(APB_DWIDTH-1 downto 0);

signal ABCli01: std_LOGIC_vector(31 downto 0);

signal ABCll1: std_LOGIC;

signal ABCIL1: STD_LOGic;

signal ABCOo1: STD_LOgic_vector(7 downto 0);

signal ADDREss: STD_logic_vecTOR(ICWIDTH-1 downto 0);

signal ABCii01: Std_logic;

signal ABCO001: STD_LOgic;

signal ABCl001: STD_logic;

signal ABCI001: std_logic_VECTOR(APB_AWIDTH-1 downto 0);

signal ABCo101: std_logic_vECTOR(APB_DWIDTH-1 downto 0);

signal ABCl101: std_logic_vECTOR(APB_DWIDTH-1 downto 0);

signal ABCi101: STD_LOgic;

signal ABCOo11: std_loGIC;

begin
ABCli01 <= ( others => '0');
ABCLL1 <= '0';
ABCIL1 <= '1';
ABCLo11:
if (IMEM_APB_ACCESS = 0)
generate
ABCiI01 <= '0';
ABCo001 <= '0';
ABCl001 <= '0';
ABCi001 <= ( others => '0');
ABCo101 <= ( others => '0');
PRDATA_S <= ( others => '0');
PSLVERR_S <= '0';
PREADY_S <= '1';
end generate;
ABCIO11:
if (IMEM_APB_ACCESS /= 0)
generate
ABCii01 <= PSEL_S;
ABCo001 <= PENABLE_S;
ABCL001 <= PWRITE_S;
ABCi001 <= PADDR_S;
ABCo101 <= PWDATA_S;
PRDATA_S <= ABCl101;
PSLVERR_S <= ABCI101;
PREADY_S <= ABCoo11;
end generate;
process (PCLK,Nsysreset)
begin
if nsysrESET = '0' then
ABCol01 <= '0';
ABCLL01 <= '0';
elsif PCLK'eVENT and PCLK = '1' then
ABCol01 <= '1';
ABCLl01 <= ABCOL01;
end if;
end process;
PRESETN <= ABCll01;
RESETN <= ABCLl01;
ABCO01:
if EN_RAM > 0 or EN_CALL > 0
or EN_INT > 0
or EN_PUSH > 0
generate
process (INSTR_Addr,iNSTR_CMD,INSTr_scmd,ABClLO1,ABCL0O1,ABColo1,SMADdr,ABCo1L1,ABCio01)
begin
ABCili1 <= ( others => '-');
ABCIii1 <= ( others => '-');
if (INSTR_cmd = "011" or ABCllO1 = '1') and EN_RAM > 0
and ABCO1L1 = '0' then
ABCIII1(APB_DWIDTH-1 downto 0) <= ABCl0o1;
ABCili1 <= INSTr_addr(7 downto 0);
if INStr_cmd = "011" and iNSTR_SCmd(2) = '1'
and EN_PUSH = 1 then
ABCili1 <= ABColo1;
end if;
elsif EN_CALL > 0 or EN_INT > 0 then
ABCILI1 <= ABCOLo1;
if EN_INT > 0 and ABCO1l1 = '1' then
ABCiii1(ICWIDTH-1 downto 0) <= SMADDR;
else
ABCiii1(ICWIDTH-1 downto 0) <= smadDR+1;
end if;
end if;
end process;
process (ABCILI1)
begin
ABCoii1 <= ( others => '0');
for ABCol in ABCILI1'range
loop
if ABCilI1(ABCOL) = '1' then
ABCOII1(ABCol) <= '1';
end if;
end loop;
end process;
ABCii1: Top_Waveform_COREABC_0_raMBLOCKS
generic map (Dwidth => ABCloo1,
FAMILy => FAMILY)
port map (clk => PCLK,
resetn => RESETN,
WEN => ABColi1,
addr => ABCOII1,
WD => ABCiii1,
rd => ABClii1);
ramdout <= ABCLII1(APB_DWIDTH-1 downto 0);
end generate;
ABCol11:
if EN_RAM = 0 and EN_CALL = 0
and EN_INT = 0
and EN_PUSH = 0
generate
ABCILI1 <= ( others => '0');
ABCiII1 <= ( others => '0');
rAMDOUT <= ( others => '0');
ABCoii1 <= ( others => '0');
ABCLII1 <= ( others => '0');
end generate;
ABCll11:
if EN_ACM = 1
generate
ABCil11: Top_Waveform_COREABC_0_ACMTABLE
generic map (TEstmode => TESTMODE)
port map (acmaddr => accumulATOR(7 downto 0),
acmdaTA => acmdata,
ACMDO => ACMDO);
end generate;
ABCoi11:
if EN_ACM = 0
generate
acmdatA <= ( others => '0');
ACMdo <= '0';
end generate;
UROM:
if INSMODE = 0 or (INSMODE = 2 and FAMILY /= 17)
generate
urom: Top_Waveform_COREABC_0_InstructiONS
generic map (TESTmode => TESTMODE,
EN_mult => EN_MULT,
EN_inc => EN_INC,
AWIDTH => APB_AWIDTH,
DWIDTH => APB_DWIDTH,
Swidth => APB_SWIDTH,
iCWIDTH => ICWIDTH,
iiwidTH => IIWIDTH,
ifwidth => IFWIDTH,
iwwidth => iwwidTH)
port map (addRESS => ADDREss,
INSTruction => instructiON);
process (PCLK)
begin
if PCLK'Event and PCLK = '1' then
if ABCII01 = '0' then
INStr_cmd <= INSTRUction(2 downto 0);
iNSTR_SCMd <= INSTRUCTion(5 downto 3);
iNSTR_SLot <= INSTRUCtion(APB_SWIDTH+6 downto 6);
Instr_slot(APB_SWIDTH) <= '0';
INSTr_addr <= INSTRUCTion(APB_AWIDTH-1+4+6 downto 4+6);
Instr_data <= instrUCTION(APB_DWIDTH-1+16+4+6 downto 16+4+6);
ABCllO1 <= Instruction(6);
end if;
end if;
end process;
STALL <= '0';
process (RESETN,PCLK)
begin
if (RESETN = '0') then
ABCoo1 <= "00000000";
elsif PCLK'EVENT and PCLK = '1' then
if ((ABCii01 = '1') and (ABCL001 = '1')) then
ABCOO1 <= ABCo101(7 downto 0);
end if;
end if;
end process;
process (ABCii01,ABCoo1,ABCi001,smADDR)
variable ABCli11: std_logic_VECTOR(15 downto 0);
begin
ABCli11 := ( others => '0');
if (ABCII01 = '1') then
ABCli11 := ABCoo1(7 downto 0)&ABCi001(7 downto 0);
else
ABCli11(ICWIDTH-1 downto 0) := Smaddr;
end if;
ADDRess(ICWIDTH-1 downto 0) <= ABCli11(ICWIDTH-1 downto 0);
end process;
ABCl101(APB_DWIDTH-1 downto 0) <= INstruction(APB_DWIDTH-1 downto 0);
ABCoo11 <= '1';
ABCI101 <= '0';
end generate;
ABCII11:
if INSMODE = 1
generate
ABCII11: Top_Waveform_COREABC_0_instrucTRAM
generic map (Testmode => TESTMODE,
Awidth => APB_AWIDTH,
Dwidth => APB_DWIDTH,
SWIDth => APB_SWIDTH,
ICWIDTH => ICWIDTH,
ICDEPTH => ABCIOO1,
iwwidtH => iwwidth,
initwidth => INITWIDTH,
IMEM_apb_access => IMEM_APB_ACCESS,
Uniq_string_LENGTH => UNIQ_STRING_LENGTH)
port map (CLK => PCLK,
Rstn => RESETN,
initdatVAL => INITDAtval,
initdone => INITDONE,
iNITADDR => INITADDR,
Initdata => INITDATA,
Address => SMADdr,
INSTRUCTion => Instruction,
PSEL => ABCII01,
penable => ABCo001,
pWRITE => ABCl001,
PADDR => ABCi001,
PWDATA => ABCO101,
Prdata => ABCL101,
pslverr => ABCI101,
pready => ABCOO11);
process (INstruction)
begin
iNSTR_CMD <= instRUCTION(2 downto 0);
INSTR_scmd <= instructION(5 downto 3);
INSTR_Slot <= INstruction(APB_SWIDTH+6 downto 6);
instr_sloT(APB_SWIDTH) <= '0';
instR_ADDR <= instruction(APB_AWIDTH-1+4+6 downto 4+6);
INSTR_data <= INSTRuction(APB_DWIDTH-1+16+4+6 downto 16+4+6);
ABCllo1 <= iNSTRUCTIOn(6);
end process;
STALL <= '0';
end generate;
ABCO011:
if INSMODE = 2 and FAMILY = 17
generate
urom: Top_Waveform_COREABC_0_INstructnvm
generic map (max_NVMDWIDTh => MAX_NVMDWIDTH,
AWIDTH => APB_AWIDTH,
dWIDTH => APB_DWIDTH,
SWIDTH => APB_SWIDTH,
ICWIDTH => ICWIDTH,
iCDEPTH => ABCioo1,
iwwIDTH => IWWIDth,
ACT_calibratioNDATA => ACT_CALIBRATIONDATA,
IMEM_apb_access => IMEM_APB_ACCESS,
uniq_strinG_LENGTh => UNIQ_STRING_LENGTH)
port map (CLK => PCLK,
RStn => RESETN,
STARt => ABCL0I1,
staLL => STALl,
addRESS => smaddr,
instruCTION => INSTRUCTion,
PSEL => ABCii01,
PEnable => ABCO001,
pwriTE => ABCl001,
Paddr => ABCi001,
Pwdata => ABCO101,
PRDATA => ABCl101,
pSLVERR => ABCi101,
pready => ABCoo11);
process (instructiON)
begin
instr_CMD <= INSTRUCTion(2 downto 0);
instr_scmd <= instructiON(5 downto 3);
inSTR_SLOT <= INSTRUCTion(APB_SWIDTH+6 downto 6);
Instr_slot(APB_SWIDTH) <= '0';
instr_addR <= instRUCTION(APB_AWIDTH-1+4+6 downto 4+6);
INStr_data <= instructioN(APB_DWIDTH-1+16+4+6 downto 16+4+6);
ABCllo1 <= INSTRUCtion(6);
end process;
end generate;
process (Instr_data,ACCUMULATor)
begin
ABCl1l1 <= '-';
ABCi1l1 <= '-';
if EN_SHL = 1 or EN_SHR = 1 then
case insTR_DATA(1 downto 0) is
when "00" =>
ABCL1L1 <= '0';
ABCi1l1 <= '0';
when "01" =>
ABCl1L1 <= '1';
ABCI1l1 <= '1';
when "10" =>
ABCl1l1 <= ACCUmulator(APB_DWIDTH-1);
ABCi1l1 <= ACCUmulator(0);
when "11" =>
ABCl1L1 <= ACCumulator(0);
ABCi1l1 <= accumULATOR(APB_DWIDTH-1);
when others =>
end case;
end if;
end process;
ABCIL01 <= ABCOI1(EN_RAM = 1) and (ABCLLI1 or (ABCoi1(EN_ALURAM = 1) and ABCLLO1));
process (INSTR_data,ABCil01,Ramdout)
variable ABCIO10: STD_logic_vectOR(APB_DWIDTH-1 downto 0);
begin
if ABCil01 = '0' then
ABCOI01 <= clean(INSTR_Data);
else
ABCOI01 <= CLEAn(ramDOUT);
end if;
end process;
process (ACCUMULAtor,ABCoi01)
variable ABCl011: std_logic_VECTOR(2*APB_DWIDTH-1 downto 0);
variable a,b: stD_LOGIC_vector(APB_DWIDTH/2-1 downto 0);
begin
case EN_MULT is
when 1 =>
A := acCUMULATOR(APB_DWIDTH/2-1 downto 0);
B := ABCOI01(APB_DWIDTH/2-1 downto 0);
ABCool1 <= a*B;
when 2 =>
ABCL011 := Accumulator*ABCOI01;
ABCool1 <= ABCL011(APB_DWIDTH-1 downto 0);
when 3 =>
ABCl011 := ACCUMulator*ABCOI01;
ABCOOL1 <= ABCl011(2*APB_DWIDTH-1 downto APB_DWIDTH);
when others =>
ABCool1 <= ( others => '-');
end case;
end process;
process (ABClli1,insTR_SCMD,ACCUMulator,instr_data,ABCl1l1,ABCI1L1,ABCOI01,ABCooL1)
variable ABCI011: STD_logic_vectoR(2 downto 0);
begin
ABCoIO1 <= ( others => '-');
ABCI011 := inSTR_SCMD;
if ABCllI1 = '1' then
ABCI011 := "111";
end if;
case ABCi011 is
when "000" =>
if EN_INC = 1 and EN_MULT = 0
and (INSMODE = 0 or (INSMODE = 2 and FAMILY /= 17)) then
ABCoio1 <= ACCUMULAtor+1;
end if;
if EN_MULT >= 1 then
ABCoio1 <= ABCOOL1;
end if;
when "001" =>
if EN_AND = 1 then
ABCoio1 <= accumulATOR and ABCoi01;
end if;
when "010" =>
if EN_OR = 1 then
ABCOIO1 <= aCCUMULATOr or ABCoi01;
end if;
when "011" =>
if EN_XOR = 1 then
ABCoio1 <= accumulaTOR xor ABCOI01;
end if;
when "100" =>
if EN_ADD = 1 or (EN_INC = 1 and (EN_MULT >= 1 or INSMODE > 0)) then
ABCoio1 <= ACCUMULator+ABCOi01;
end if;
when "101" =>
if EN_SHL = 1 then
ABCoio1 <= accumuLATOR(APB_DWIDTH-2 downto 0)&ABCI1L1;
end if;
when "110" =>
if EN_SHR = 1 then
ABCOIO1 <= ABCL1L1&ACCUMulator(APB_DWIDTH-1 downto 1);
end if;
when "111" =>
ABCoio1 <= ABCoi01;
when others =>
ABCoio1 <= ( others => '-');
end case;
end process;
process (ABClli1,INSTR_cmd,ABCoIO1,PRDATA_M,IO_IN)
begin
if (EN_RAM > 0 and ABClli1 = '1') or Instr_cmd(1) = '0' then
ABCilo1 <= ABCoIO1;
elsif EN_IOREAD = 1 and INSTR_cmd(0) = '1' then
ABCilo1 <= ( others => '0');
ABCILO1(IIWIDTH-1 downto 0) <= IO_IN;
else
ABCILO1 <= PRDATA_M(APB_DWIDTH-1 downto 0);
end if;
end process;
process (PCLK,RESETN)
begin
if RESETN = '0' then
ACCumulator <= ( others => '0');
ABCLil1 <= '0';
ABCIIL1 <= '0';
ABCO0L1 <= '0';
ABCl0l1 <= '0';
elsif PCLK'EVENt and PCLK = '1' then
if ABClll1 = '1' or ABCoil1 = '1' then
aCCUMULATor <= ABCilo1;
end if;
if isr = '0' and ABCill1 = '1' then
ABClil1 <= ABCoi1(ABCilo1 = ABCLI01(APB_DWIDTH-1 downto 0));
ABCIIL1 <= ABCILO1(APB_DWIDTH-1);
end if;
if iSR = '1' and ABCill1 = '1'
and EN_INT > 0 then
ABCO0L1 <= ABCoi1(ABCilo1 = ABCli01(APB_DWIDTH-1 downto 0));
ABCl0l1 <= ABCilo1(APB_DWIDTH-1);
end if;
if EN_INT = 0 then
ABCo0l1 <= '0';
ABCl0l1 <= '0';
end if;
end if;
end process;
ACCUM_zero <= ABCo0l1 when ISr = '1' else
ABCliL1;
ACCUM_neg <= ABCL0L1 when isr = '1' else
ABCiil1;
ABColl1 <= '1' when (CLean(ZREGISTER) = CLEAN(ABCli01(ZRWIDTH downto 0)) and ZRWIDTH > 0) else
'0';
process (instr_DATA,INSTR_scmd,IO_IN,accum_NEG,ACCUM_zero,ABColl1)
variable ABCO111: std_logIC_VECTor(31 downto 0);
variable ABCloL: STD_logic;
begin
ABCo111 := ( others => '0');
ABCo111(3 downto 0) := (ABColl1&Accum_neg&ACCUm_zero&'1');
for ABCol in 0 to IFWIDTH-1
loop
ABCo111(ABCol+4) := IO_IN(ABCol);
end loop;
ABCLOL := '0';
for ABCoL in 0 to IFWIDTH+4-1
loop
ABClol := ABCLol or (instr_DATA(ABCol) and ABCO111(ABCOl));
end loop;
FLAGS <= ABCLOL xnor instr_SCMD(0);
end process;
process (INSTR_cmd,iNSTR_SCMd,ABCLLO1)
begin
ABCIOL1 <= '-';
ABClol1 <= '-';
case Instr_cmd is
when "010" =>
if INSTR_SCmd(0) = '1' then
ABCiol1 <= '0';
ABCLOL1 <= '-';
elsif EN_ACM = 1 and inSTR_SCMD(1) = '1' then
ABCIOL1 <= '1';
ABClol1 <= '1';
else
ABCIOL1 <= '1';
ABClol1 <= '0';
end if;
when "011" =>
if ABCllo1 = '0' then
ABCIOl1 <= '0';
ABCLOl1 <= '-';
else
ABCIOL1 <= '1';
ABClol1 <= '0';
end if;
when others =>
ABCioL1 <= '-';
ABCLOL1 <= '-';
end case;
end process;
process (ABCLOl1,aCCUMULATOr,acmdata)
begin
ABCLIO1 <= ACcumulator;
if EN_ACM = 1 and ABCLOL1 = '1' then
ABClio1(7 downto 0) <= acmdata;
end if;
end process;
process (ABCIOL1,instr_data,ABClio1)
begin
if ABCIOL1 = '0' then
ABCiiO1 <= INstr_data;
else
ABCiio1 <= ABClio1;
end if;
end process;
process (ABClio1,ABCiiO1,acCUMULATOR,INSTR_Data)
begin
case EN_DATAM is
when 0 =>
ABCO0O1 <= ABCliO1;
ABCL0o1 <= accumulatOR;
ABCL1o1 <= ACCUmulator;
ABCi0O1 <= ACCumulator;
when 1 =>
ABCo0O1 <= INSTR_data;
ABCl0o1 <= insTR_DATA;
ABCl1o1 <= Instr_data;
ABCi0o1 <= iNSTR_DATa;
when 2 =>
ABCo0o1 <= ABCiio1;
ABCl0o1 <= ABCiio1;
ABCl1o1 <= ABCIIO1;
ABCI0O1 <= ABCIIO1;
when 3 =>
ABCo0o1 <= ABClio1;
ABCl0o1 <= accumulaTOR;
ABCl1o1 <= Instr_data;
ABCi0o1 <= instr_daTA;
end case;
ABCo1o1 <= ( others => '0');
-- synthesis translate_off
ABCo1o1 <= ABCiio1;
-- synthesis translate_on
end process;
process (ABCL1O1)
constant ABCoI10: Integer := MIN(APB_DWIDTH,
ZRWIDTH);
constant M: integer := max(1,
ZRWIDTH-1);
begin
ABCi1O1 <= ( others => ABCl1O1(APB_DWIDTH-1));
for ABCol in 0 to ABCOI10-1
loop
ABCi1o1(ABCOL) <= ABCl1O1(ABCoL);
end loop;
end process;
ABClli1 <= ABCoi1(clean(Instr_cmd) = "011" and EN_RAM > 0
and cLEAN(instr_scMD(2 downto 1)) /= "11");
process (STKPTr)
variable ABCl111: stD_LOGIC_vector(STWIDTH-1 downto 0);
begin
ABCl111 := CLEAN(STKPTR(STWIDTH-1 downto 0));
ABCIOI <= ( others => '1');
ABColi <= ( others => '1');
ABCioI(STWIDTH-1 downto 0) <= ABCl111-1;
ABCOLI(STWIDTH-1 downto 0) <= ABCl111+1;
end process;
ABColo1 <= ABCOLi;
ABCO0I1 <= ABCOI1((INTREQ = '1' and (EN_INT = 1)) or (INTREQ = '0' and (EN_INT = 2)));
ABCIoi1 <= PREADY_M;
ABCI0I1 <= ABCoi1(INSMODE <= 1) or not stalL;
process (PCLK,RESETN)
begin
if RESETN = '0' then
ABClOI1 <= '0';
ABCooi1 <= '0';
ABCiLL1 <= '0';
ABCLll1 <= '0';
ABCio01 <= ABClo01;
ABCI0L1 <= '0';
ABCo1l1 <= '0';
ABCOLI1 <= '0';
sMADDR <= ( others => '1');
zregISTER <= ( others => '0');
IO_OUT <= ( others => '0');
STkptr <= ( others => '1');
ISR <= '0';
ABCL0I1 <= '0';
elsif PCLK'Event and PCLK = '1' then
ABCloi1 <= '0';
ABCOOI1 <= '0';
ABCILL1 <= '0';
ABClll1 <= '0';
ABColi1 <= '0';
ABCL0i1 <= '0';
case ABCio01 is
when ABCl1i1 =>
if INITDOne = '1' or INSMODE = 0
or INSMODE = 2 then
if EN_INT > 0 and ABCo0i1 = '1'
and isr = '0' then
ISR <= '1';
STKPTR <= ABCiOI;
ABCo1l1 <= '1';
ABCIO01 <= ABCI1i1;
ABCOLI1 <= '1';
else
ABCio01 <= ABCi1I1;
end if;
end if;
when ABCI1I1 =>
if ABCi0i1 = '1' then
if ABCo1l1 = '1' then
ABCio01 <= ABClo01;
else
case INSTR_Cmd is
when "000" =>
ABCio01 <= ABCLO01;
ABCill1 <= '1';
ABCLLL1 <= '1';
when "001" =>
ABCio01 <= ABClo01;
ABCill1 <= '1';
when "010" =>
if EN_ACM = 1 and INstr_scmd(1 downto 0) = "10" then
ABCLOI1 <= Acmdo;
else
ABCloi1 <= '1';
end if;
ABCIO01 <= ABCOO01;
when "011" =>
case instR_SCMD is
when "000" =>
if ZRWIDTH > 0 then
zREGISTER(ZRWIDTH-1 downto 0) <= ABCi1o1(ZRWIDTH-1 downto 0);
end if;
when "001" =>
if ZRWIDTH > 0 then
ZREGISTEr(ZRWIDTH-1 downto 0) <= zregister(ZRWIDTH-1 downto 0)+ABCi1o1(ZRWIDTH-1 downto 0);
end if;
when "010" =>
if EN_RAM > 0 then
ABCOLI1 <= '1';
end if;
when "011" =>
if EN_RAM > 0 then
ABCILL1 <= '1';
ABCLLL1 <= '1';
end if;
when "100" =>
if EN_PUSH = 1 then
STkptr <= ABCIOI;
ABCOLI1 <= '1';
end if;
when "101" =>
if EN_PUSH = 1 then
stkptr <= ABCOLI;
ABCILL1 <= '1';
ABCLLL1 <= '1';
end if;
when "110" =>
if EN_IOREAD = 1 then
ABCill1 <= '1';
ABClll1 <= '1';
end if;
when "111" =>
if EN_IOWRT = 1 then
IO_OUT(IOWIDTH-1 downto 0) <= ABCi0o1(IOWIDTH-1 downto 0);
end if;
when others =>
end case;
ABCIO01 <= ABClo01;
when "100" =>
if flags = '1' then
ABCi0L1 <= '1';
end if;
ABCio01 <= ABCLO01;
when "101" =>
if EN_CALL = 1 and FLags = '1' then
STKPTr <= ABCIOI;
ABColi1 <= '1';
ABCI0l1 <= '1';
end if;
ABCIO01 <= ABCLO01;
when "110" =>
if (EN_CALL = 1 or EN_INT > 0) and flags = '1' then
ABCio01 <= ABCLO01;
sTKPTR <= ABColi;
ABCi0l1 <= '1';
if INSTR_Scmd(1) = '1' and EN_INT > 0 then
ISR <= '0';
end if;
else
ABCIO01 <= ABClo01;
end if;
when "111" =>
ABCio01 <= ABClO01;
when others =>
ABCIO01 <= ABCLO01;
end case;
end if;
end if;
when ABCOO01 =>
ABCOOi1 <= '1';
ABCLOI1 <= '1';
if (PREADY_M = '1' and ABCooi1 = '1') or ABCloi1 = '0' then
ABCloi1 <= '0';
ABCOOI1 <= '0';
ABCio01 <= ABClo01;
end if;
when ABClo01 =>
if ABCI0I1 = '1' then
ABCl0i1 <= '1';
ABCo1l1 <= '0';
ABCI0L1 <= '0';
if ABCo1l1 = '1' and EN_INT > 0 then
Smaddr <= CONV_Std_logic_veCTOR(ISRADDR,
ICWIDTH);
elsif ABCi0l1 = '1' then
smaddr <= instr_addr(ICWIDTH-1 downto 0);
if (EN_CALL = 1 or EN_INT > 0) and iNSTR_CMd(1) = '1' then
sMADDR <= ABCLIi1(ICWIDTH-1 downto 0);
end if;
if (instr_cmd(1) = '0' and INstr_scmd(1) = '1') then
smaDDR <= smaddr;
end if;
if instr_cmd = "100" and instr_scmD(1) = '1' then
ABCL0I1 <= '0';
end if;
else
smadDR <= SMADDr+1;
end if;
ABCIO01 <= ABCL1I1;
end if;
end case;
if EN_CALL = 0 and EN_INT = 0 then
stkptr <= ( others => '1');
end if;
if STWIDTH < 8 then
Stkptr(7 downto STWIDTH) <= ( others => '1');
end if;
if ZRWIDTH = 0 then
zregISTER <= ( others => '0');
end if;
if EN_RAM = 0 and EN_INT = 0
and EN_CALL = 0
and EN_PUSH = 0 then
ABCOLI1 <= '0';
end if;
if EN_INT = 0 then
isr <= '0';
ABCo1L1 <= '0';
end if;
if EN_IOWRT = 0 then
IO_OUT <= ( others => '0');
end if;
zreGISTER(ZRWIDTH) <= '0';
if INSMODE /= 2 then
ABCl0i1 <= '0';
end if;
end if;
end process;
INTACT <= ISR;
process (instr_addR,instR_SCMD,ZRegister,INSTR_slot,ABCLI01)
constant ABCoi10: integer := min(ZRWIDTH,
APB_AWIDTH);
begin
PADDR_M <= ( others => '0');
PADDR_M(APB_SWIDTH+APB_AWIDTH-1 downto 0) <= instr_slot(APB_SWIDTH-1 downto 0)&ABCli01(APB_AWIDTH-1 downto 0);
if EN_INDIRECT = 1 and insTR_SCMD(2) = '1'
and ZRWIDTH > 0 then
PADDR_M(ABCOI10-1 downto 0) <= ZREGISter(ABCoi10-1 downto 0);
else
PADDR_M(APB_AWIDTH-1 downto 0) <= INSTR_addr;
end if;
end process;
process (ABCo0O1)
begin
PWDATA_M <= ( others => '0');
PWDATA_M(APB_DWIDTH-1 downto 0) <= ABCo0o1;
end process;
PENABLE_M <= ABCOoi1;
PWRITE_M <= not (instR_SCMD(0) and instR_SCMD(1));
ABCOil1 <= ABCooi1 and INSTR_scmd(0)
and instr_scMD(1);
process (ABCLoi1)
begin
PSEL_M <= ABCloi1;
end process;
-- synthesis translate_off
DEbug1 <= ABCoi1(ABCI0I1 = '1' and ABCIO01 = ABCi1i1);
debug2 <= ABCoi1(ABCio01 = ABCOO01 and PREADY_M = '1'
and ABCooi1 = '1'
and INSTR_scmd(1 downto 0) = "11");
ABCI111: Top_Waveform_COREABC_0_Debugblk
generic map (dEBUG => DEBUG,
AWIDTH => APB_AWIDTH,
DWIdth => APB_DWIDTH,
swIDTH => APB_SWIDTH,
sdePTH => APB_SDEPTH,
ICWidth => ICWIDTH,
Icdepth => ABCioO1,
Zrwidth => ZRWIDTH,
IIWIDTH => IIWIDTH,
iOWIDTH => IOWIDTH,
irwidtH => ABCloo1,
en_mult => EN_MULT)
port map (Pclk => PCLK,
RESetn => RESETN,
smaddr => SMADDR,
isr => ISr,
INStr_cmd => instr_CMD,
inSTR_SCMD => INStr_scmd,
INStr_data => instr_DATA,
INSTR_addr => Instr_addr,
instr_slot => instr_SLOT,
prdatA => PRDATA_M(APB_DWIDTH-1 downto 0),
pwdata => ABCo1o1,
ACCUM_old => ACCUMULator,
accUM_NEW => ABCilo1,
ACCUm_zero => accum_zERO,
ACCUM_neg => Accum_neg,
flags => FLAGS,
RAMDOUT => Ramdout,
STKptr => stkptr,
zregister => ZREGISTer,
aCMDO => ACmdo,
DEBUg1 => debug1,
debug2 => Debug2);
-- synthesis translate_on
end rtl;
