-- Copyright 2008 Actel Corporation.  All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
-- Rev: 2.4   24Jan08 IPB  : Production Release
-- SVN Revision Information:
-- SVN $Revision: 14690 $
library Ieee;
use ieeE.STD_logic_1164.all;
use IEEE.STD_LOgic_arith.all;
use ieee.STD_logic_unsiGNED.all;
package Top_Waveform_COREABC_0_SUPPort is

function clean(x: Std_logic_veCTOR)
return STD_logic_vectoR;

function ABCi000(ABCo100,ABCl100,ABCi100,ABCOO10,ABCLO10: STD_LOGic_vector)
return std_logiC_VECTOr;

function ABCoi1(ABCIO10: INTeger)
return std_loGIC;

function ABCoi1(ABCIo10: booleaN)
return std_logic;

function LOG2R(x: INTeger)
return iNTEGER;

function ABCOL10(EN_RAM,EN_CALL,DwidtH,ICWIDTH: INTEGer)
return Integer;

function Calc_swidth(x: Integer)
return INTEGER;

function Calc_initwiDTH(AWIdth,dwIDTH,ABCll10,ICWIDTH: INTEGER)
return integER;

function MAX(A,B: INTEGER)
return Integer;

function min(a,B: integER)
return INTEGER;

function ABCiL10(ABCOI10: inteGER;
s1: iNTEGER;
ABCOOol: integer;
ABClool: iNTEGER;
ABCioOL: inTEGER;
ABCli10: inteGER)
return sTD_LOGic_vector;

function Doins(S1: INTEGEr)
return Std_logic_veCTOR;

function doins(S1: iNTEGER;
ABCoool: iNTEGER)
return STd_logic_veCTOR;

function DOINS(s1: INTeger;
ABCoool: inteGER;
ABClool: Integer)
return STD_LOGIc_vector;

function Doins(s1: integer;
ABCoool: iNTEGER;
ABCLOol: Integer;
ABCiool: integer)
return STD_logic_vectOR;

function Doins(s1: INTEGEr;
ABCOOOL: INTEGER;
ABClool: inteGER;
ABCIOOL: INTEger;
ABCli10: integer)
return STD_LOGIc_vector;

function CHARToint(C: charACTER)
return iNTEGER;

function ABCii10(ABCo010: INTeger)
return std_logic_VECTOR;

component Top_Waveform_COREABC_0_instruCTRAM
generic (awidth: INTEGER range 1 to 16;
DWIDTH: INTEger range 8 to 32;
SWIDTH: INTEGEr range 0 to 4;
icwidth: integeR range 1 to 16;
ICDEPTH: inteGER range 1 to 65536;
iwwIDTH: integER range 1 to 64;
iniTWIDTH: integer range 1 to 16;
Testmode: INTEGER range 0 to 99;
IMem_apb_accESS: inteGER range 0 to 2;
UNiq_string_lENGTH: iNTEGER range 1 to 256);
port (clK: in std_logiC;
rstn: in Std_logic;
initdatval: in stD_LOGIC;
INITDONE: in STD_logic;
INITADDR: in std_logiC_VECTOR(INITWIDTH-1 downto 0);
INITDATA: in Std_logic_vECTOR(8 downto 0);
address: in STD_Logic_vector(ICWIDTH-1 downto 0);
instRUCTION: out Std_logic_veCTOR(iwwidth-1 downto 0);
pSEL: in STD_LOGic;
PENAble: in STd_logic;
PWRITE: in STD_logic;
paddr: in STD_logic_vecTOR(AWIdth-1 downto 0);
PWDATA: in std_lOGIC_VECtor(dwiDTH-1 downto 0);
prdata: out std_logic_vECTOR(DWIDTH-1 downto 0);
pSLVERR: out Std_logic;
preadY: out std_logiC);
end component;

component Top_Waveform_COREABC_0_instRUCTIONS
generic (awidth: iNTEGER range 1 to 16;
DWidth: INTEger range 8 to 32;
swidth: integer range 0 to 4;
icwidth: Integer range 1 to 16;
iiwidth: INTEGer range 1 to 32;
ifwidth: Integer range 0 to 28;
IWWIDTH: inTEGER range 1 to 64;
En_mult: INTEGER range 0 to 3;
En_inc: INTEGER range 0 to 1;
tesTMODE: Integer range 0 to 99);
port (Address: in sTD_LOGIC_vector(ICWIDTH-1 downto 0);
INSTRUCTion: out STD_logic_vecTOR(iwwidth-1 downto 0));
end component;

component Top_Waveform_COREABC_0_ACMTABLe
generic (Testmode: INTEGEr range 0 to 99);
port (acmaddr: in std_loGIC_VECTor(7 downto 0);
ACMDATA: out STD_LOGIc_vector(7 downto 0);
aCMDO: out STD_logic);
end component;

component Top_Waveform_COREABC_0_ramBLOCKS
generic (DWIDTH: INteger range 8 to 32;
FAMILY: integer range 0 to 22);
port (clk: in stD_LOGIC;
resetn: in STD_LOgic;
wen: in STD_logic;
addr: in STD_LOGic_vector(7 downto 0);
wd: in Std_logic_veCTOR(Dwidth-1 downto 0);
rd: out STD_logiC_VECTor(DWIDth-1 downto 0));
end component;

component Top_Waveform_COREABC_0_ram256x8 is
port (rwCLK: in STD_LOGic;
rESET: in std_loGIC;
WEN: in std_lOGIC;
REN: in std_LOGIC;
wADDR: in STD_LOGIc_vector(7 downto 0);
RADDR: in Std_logic_vECTOR(7 downto 0);
wd: in STD_LOgic_vector(7 downto 0);
rd: out STD_logic_vectOR(7 downto 0));
end component;

component Top_Waveform_COREABC_0_RAM256x16 is
port (rwclk: in Std_logic;
REset: in sTD_LOGIC;
wen: in STD_LOGic;
REn: in sTD_LOGIC;
wADDR: in std_logiC_VECTor(7 downto 0);
RADDr: in Std_logic_veCTOR(7 downto 0);
WD: in std_logiC_VECTOR(15 downto 0);
rd: out std_LOGIC_VEctor(15 downto 0));
end component;

component Top_Waveform_COREABC_0_DEBugblk
generic (debug: INTEGER range 0 to 1;
AWidth: INTEGER range 1 to 16;
DWIDTH: integer range 8 to 32;
swidth: INTeger range 0 to 4;
sdepth: INTEGER range 1 to 16;
ICWidth: INTEGER range 1 to 16;
icdepth: integer range 1 to 65536;
ZRWIDth: INTEGER range 0 to 16;
iiwidtH: iNTEGER range 1 to 32;
iowidth: iNTEGER range 1 to 32;
IRWIDTH: integer range 1 to 32;
en_mult: integeR range 0 to 3);
port (pCLK: in STD_logic;
resetn: in STD_Logic;
ISR: in Std_logic;
SMADDR: in STD_logic_vectOR(ICWIDTH-1 downto 0);
instr_cmd: in std_logiC_VECTOr(2 downto 0);
instR_SCMD: in Std_logic_vECTOR(2 downto 0);
INSTR_data: in STD_LOGic_vector(dwidth-1 downto 0);
instr_addr: in std_logiC_VECTOR(awidth-1 downto 0);
instr_sLOT: in std_logic_VECTOR(swidTH downto 0);
prdata: in Std_logic_veCTOR(dwidth-1 downto 0);
pwdaTA: in STD_logic_vectoR(DWIDth-1 downto 0);
ACCUM_old: in std_logic_VECTOR(dWIDTH-1 downto 0);
accum_nEW: in std_logic_VECTOR(dwidth-1 downto 0);
accum_ZERO: in std_LOGIC;
ACCUM_Neg: in STD_LOGic;
flags: in STD_Logic;
rAMDOUT: in STD_logic_vectOR(dwidth-1 downto 0);
stkptr: in std_LOGIC_VEctor(7 downto 0);
zREGISTER: in std_logic_VECTOR(ZRWIDTH downto 0);
ACMDO: in std_loGIC;
debug1: in STD_LOgic;
DEBUG2: in std_logIC);
end component;

component Top_Waveform_COREABC_0_iram512x9
generic (cid: INTEGer;
rid: integer;
uNIQ_STRIng_length: Integer);
port (RWCLK: in std_LOGIC;
Reset: in sTD_LOGIC;
Renable: in STD_LOGIc;
RADDR: in Std_logic_vECTOR(8 downto 0);
RD: out Std_logic_veCTOR(8 downto 0);
INITADDR: in std_lOGIC_VECTor(8 downto 0);
wenABLE: in STD_LOGic;
INITDATA: in std_logiC_VECTOr(8 downto 0));
end component;

component Top_Waveform_COREABC_0_insTRUCTNVM
generic (MAX_Nvmdwidth: INTEger range 16 to 32;
AWIdth: iNTEGER range 1 to 16;
dwidth: INTEGER range 8 to 32;
swiDTH: INTEGer range 0 to 4;
Icwidth: inteGER range 1 to 16;
ICDEPth: integer range 1 to 65536;
IWWIDth: integer range 1 to 64;
act_CALIBRATIondata: inTEGER range 0 to 1;
IMem_apb_accESS: INTEGEr range 0 to 2;
uNIQ_STRIng_length: INTEGER range 1 to 256);
port (CLK: in STd_logic;
RSTN: in STD_Logic;
start: in stD_LOGIC;
STALL: out std_lOGIC;
ADDress: in Std_logic_vECTOR(ICWIDTH-1 downto 0);
INSTRUCtion: out STD_logic_vectOR(iwwidth-1 downto 0);
PSEL: in sTD_LOGIC;
pENABLE: in STD_logic;
PWRITe: in std_lOGIC;
Paddr: in std_logic_VECTOR(AWIDTH-1 downto 0);
PWDATA: in std_logIC_VECTOr(dwIDTH-1 downto 0);
prdatA: out STD_LOgic_vector(DWIDTH-1 downto 0);
pslverr: out std_logic;
preaDY: out STD_logic);
end component;

constant blank: INTEGER := -1;

constant INop: Integer := 256*1;

constant ILoad: integer := 256*2;

constant iincb: integer := 256*3;

constant IAND: INTEGEr := 256*4;

constant iOR: intEGER := 256*5;

constant ixOR: iNTEGER := 256*6;

constant IADd: Integer := 256*7;

constant isub: Integer := 256*8;

constant iSHL0: INTeger := 256*9;

constant iSHL1: integer := 256*10;

constant ISHLE: iNTEGER := 256*11;

constant irol: INTEGER := 256*12;

constant ISHR0: INTEGER := 256*13;

constant iSHR1: integer := 256*14;

constant Ishre: iNTEGER := 256*15;

constant IROR: integer := 256*16;

constant ICMP: Integer := 256*17;

constant ICMPLEq: intEGER := 256*18;

constant ibitclr: INTEGER := 256*19;

constant IBItset: inteGER := 256*20;

constant ibittst: inteGER := 256*21;

constant Iapbread: inTEGER := 256*22;

constant IAPBWRT: Integer := 256*23;

constant ILOADZ: INTEger := 256*24;

constant idecZ: inTEGER := 256*25;

constant IINCZ: inTEGER := 256*26;

constant IIOWRT: INTEGer := 256*27;

constant IRAMread: INTEGer := 256*28;

constant IRAMWrt: INTEger := 256*29;

constant iPUSH: inTEGER := 256*30;

constant ipop: Integer := 256*31;

constant Iioread: INTEger := 256*32;

constant IUSEr: intEGER := 256*33;

constant iJUMPB: inteGER := 256*34;

constant icallB: INteger := 256*35;

constant IREturnb: INTEGER := 256*36;

constant iRETISRB: integer := 256*37;

constant iwAITB: INteger := 256*38;

constant ihaltb: intEGER := 256*38;

constant imult: integer := 256*39;

constant idec: intEGER := 256*40;

constant IAPbreadz: inTEGER := 256*41;

constant iAPBWRTz: inTEGER := 256*42;

constant iadDZ: integer := 256*43;

constant isubZ: INTEGER := 256*44;

constant Idat: integer := 10;

constant idat8: integER := 11;

constant idat16: integer := 12;

constant IDAT32: Integer := 13;

constant Iacm: INteger := 14;

constant iacC: integer := 15;

constant iram: INTeger := 16;

constant ABCl010: integer := 10;

constant DAT8: integer := 11;

constant DAT16: inTEGER := 12;

constant DAT32: INTEGER := 13;

constant ACM: iNTEGER := 14;

constant ACC: INTEger := 15;

constant RAM: intEGER := 16;

constant IIFNOT: Integer := 0;

constant inoTIF: iNTEger := 0;

constant iif: INteger := 1;

constant iUNTIL: INTEGEr := 0;

constant INOTUntil: INTEGEr := 1;

constant iuntilNOT: integER := 1;

constant IWhile: INTEGer := 1;

constant izzERO: inteGER := 16#08#;

constant INegativE: INTEGer := 16#04#;

constant IZero: Integer := 16#02#;

constant iltE_zero: inteGER := 16#06#;

constant ialwaYS: INteger := 16#01#;

constant IINPut0: INTEGEr := 100;

constant iinPUT1: INTeger := 101;

constant Iinput2: INTEger := 102;

constant IINput3: INTEGEr := 103;

constant iinpUT4: INTeger := 104;

constant iINPUT5: INTeger := 105;

constant Iinput6: iNTEGER := 106;

constant Iinput7: integeR := 107;

constant iinPUT8: INTEger := 108;

constant iINPUT9: Integer := 109;

constant iinput10: intEGER := 110;

constant iinpUT11: INTEger := 111;

constant iinPUT12: inteGER := 112;

constant iinPUT13: iNTEGEr := 113;

constant iINPUT14: iNTEGER := 114;

constant iinpUT15: INTEGer := 115;

constant IINput16: inteGER := 116;

constant IINPUT17: integer := 117;

constant Iinput18: INTEGer := 118;

constant IINPUT19: integeR := 119;

constant Iinput20: intEGER := 120;

constant iinPUT21: Integer := 121;

constant IINPut22: INTEGEr := 122;

constant iINPUT23: INTEGEr := 123;

constant iinpuT24: Integer := 124;

constant iinpUT25: inteGER := 125;

constant Iinput26: INTEGer := 126;

constant IINput27: INTEger := 127;

constant IANYINput: intEGER := 200;

constant ALways: inTEGER := 16#01#;

constant ZZERO: inTEGER := 16#08#;

constant negatIVE: INTEGer := 16#04#;

constant zero: iNTEGEr := 16#02#;

constant lte_ZEro: intEGER := 16#06#;

constant Input0: integER := 100;

constant input1: inTEGER := 101;

constant inPUT2: integer := 102;

constant inpUT3: intEGER := 103;

constant inpUT4: INTEGer := 104;

constant input5: INteger := 105;

constant inpuT6: integeR := 106;

constant iNPUT7: INTeger := 107;

constant input8: INTeger := 108;

constant iNPUT9: INTEger := 109;

constant Input10: iNTEGER := 110;

constant INPUT11: INTEGEr := 111;

constant input12: INTEGer := 112;

constant inPUT13: intEGER := 113;

constant input14: iNTEGEr := 114;

constant Input15: INTEGer := 115;

constant inpuT16: INTEGer := 116;

constant INPUT17: INTEGer := 117;

constant INPUT18: INTEGEr := 118;

constant input19: iNTEGEr := 119;

constant Input20: integeR := 120;

constant inPUT21: integeR := 121;

constant iNPUT22: INTeger := 122;

constant inpuT23: integeR := 123;

constant input24: integeR := 124;

constant Input25: inTEGER := 125;

constant inpuT26: INTEGer := 126;

constant inpUT27: Integer := 127;

constant anyinpUT: integER := 200;

constant ilOADLOop: INTEGer := 256*24;

constant iDECLOOP: integER := 256*25;

constant IINCLOOP: integer := 256*26;

constant iLOOPZ: integeR := 16#08#;

constant LOOPZ: Integer := 16#08#;

constant EN_USER: Integer range 0 to 1 := 0;
end Top_Waveform_COREABC_0_SupporT;

library IEee;
use ieeE.STD_logic_1164.all;
use ieEE.STD_logic_ARITH.all;
use Ieee.stD_LOGic_unsiGNED.all;
package body Top_Waveform_COREABC_0_supporT is
function ABCii10(ABCO010: Integer)
return STd_logic_VECTor is
begin
case ABCo010 is
when 0 =>
return X"00000000";
when 1 =>
return X"00000001";
when 2 =>
return X"00000002";
when 3 =>
return X"00000003";
when 4 =>
return X"00000004";
when 5 =>
return X"00000005";
when 6 =>
return X"00000006";
when 7 =>
return X"00000007";
when 8 =>
return X"00000008";
when 9 =>
return X"00000009";
when 10 =>
return X"0000000a";
when 100 =>
return X"00000010";
when 101 =>
return X"00000020";
when 102 =>
return X"00000040";
when 103 =>
return X"00000080";
when 104 =>
return X"00000100";
when 105 =>
return X"00000200";
when 106 =>
return X"00000400";
when 107 =>
return X"00000800";
when 108 =>
return X"00001000";
when 109 =>
return X"00002000";
when 110 =>
return X"00004000";
when 111 =>
return X"00008000";
when 112 =>
return X"00010000";
when 113 =>
return X"00020000";
when 114 =>
return X"00040000";
when 115 =>
return X"00080000";
when 116 =>
return X"00100000";
when 117 =>
return X"00200000";
when 118 =>
return X"00400000";
when 119 =>
return X"00800000";
when 120 =>
return X"01000000";
when 121 =>
return X"02000000";
when 122 =>
return X"04000000";
when 123 =>
return X"08000000";
when 124 =>
return X"10000000";
when 125 =>
return X"20000000";
when 126 =>
return X"40000000";
when 127 =>
return X"80000000";
when 200 =>
return X"fffffff0";
when others =>
return X"00000000";
end case;
end ABCii10;
function DOINS(s1: integeR;
ABCOOol: Integer;
ABCLool: integer;
ABCIool: integer;
ABCli10: integer)
return std_loGIC_VECtor is
begin
return (ABCiL10(5,
S1,
ABCoOOL,
ABClool,
ABCiooL,
ABCli10));
end DOINS;
function DOINS(s1: integer;
ABCoool: Integer;
ABClOOL: INTEGER;
ABCIOOl: INTEGer)
return STD_LOGic_vector is
begin
return (ABCiL10(4,
S1,
ABCoool,
ABClool,
ABCiool,
-1));
end DOINS;
function doinS(s1: Integer;
ABCOOOL: INTEGer;
ABClool: integer)
return STd_logic_vecTOR is
begin
return (ABCIL10(3,
s1,
ABCoOOL,
ABClool,
-1,
-1));
end doiNS;
function doins(S1: INTEger;
ABCOOOL: INteger)
return sTD_LOGIC_vector is
begin
return (ABCIL10(2,
S1,
ABCoool,
-1,
-1,
-1));
end Doins;
function doinS(S1: inteGER)
return std_logic_VECTOR is
begin
return (ABCIL10(1,
S1,
-1,
-1,
-1,
-1));
end DOins;
function chaRTOINT(c: CHaracter)
return Integer is
begin
return (CHAracter'Pos(C));
end CHARTOINT;
function ABCi000(ABCo100,ABCl100,ABCI100,ABCOO10,ABClo10: std_logic_VECTOR)
return STD_LOgic_vector is
variable instruCTION: std_logiC_VECTOR(32+16+4+6-1 downto 0);
begin
insTRUCTION := ABClo10&ABCoo10&ABCi100&ABCL100&ABCO100;
return (INStruction);
end ABCi000;
function ABCIL10(ABCOi10: INTEGEr;
s1: Integer;
ABCOool: INTeger;
ABClool: INteger;
ABCiool: INteger;
ABCLI10: inTEGER)
return STD_logic_vectOR is
variable ABCo100: std_LOGIC_Vector(2 downto 0);
variable ABCL100: Std_logic_vECTOR(2 downto 0);
variable ABCi100: Std_logic_VECTOR(3 downto 0);
variable ABCoo10: std_logic_VECTOR(15 downto 0);
variable ABCLo10: STD_logic_vectOR(31 downto 0);
constant ABCi010: sTD_Logic_veCTOR(31 downto 0) := ( others => '1');
constant zero: std_Logic_vecTOR(31 downto 0) := ( others => '0');
variable ABCO110: integeR;
variable FFW: iNTEGEr;
begin
ABCo100 := "---";
ABCl100 := "---";
ABCi100 := "---0";
ABCOo10 := ( others => '-');
ABCLO10 := ( others => '-');
ABCO110 := s1/256;
FFW := S1-ABCO110*256;
ABCo110 := ABCO110*256;
case ABCO110 is
when iloaD =>
ABCo100 := "000";
ABCl100 := "111";
ABCI100(0) := '0';
ABCLO10 := CONv_std_logic_VECTOr(ABCOOOL,
32);
if ABCoi10 >= 3 then
case ABCOOol is
when idaT =>
ABCLO10 := conv_std_lOGIC_VEctor(ABClool,
32);
when idat8 =>
ABCLO10 := conv_stD_LOGIC_vector(ABClool,
32);
ABClo10(31 downto 8) := ( others => '-');
when idat16 =>
ABClo10 := Conv_std_loGIC_VECtor(ABClool,
32);
ABClo10(31 downto 16) := ( others => '-');
when IDAT32 =>
ABCLO10 := cONV_STD_logic_vectOR(ABCLOOL,
32);
when IRAM =>
ABCoo10(7 downto 0) := cONV_std_lOGIC_Vector(ABClool,
8);
ABCi100(0) := '1';
ABClo10 := ( others => '-');
when others =>
end case;
end if;
when iinCB =>
if FFW > 0 then
ABCo100 := "000";
ABCl100 := "100";
ABCI100(0) := '0';
ABClo10 := CONV_std_lOGIC_VectOR(1,
32);
else
ABCO100 := "000";
ABCL100 := "000";
ABCi100(0) := '0';
end if;
when IDec =>
ABCO100 := "000";
ABCL100 := "100";
ABCi100(0) := '0';
ABClo10 := ( others => '1');
when iand =>
ABCO100 := "000";
ABCl100 := "001";
ABCi100(0) := '0';
ABCLo10 := CONV_Std_logic_vECTOR(ABCOOOl,
32);
if ABCOI10 >= 3 then
case ABCOOOl is
when idat =>
ABClo10 := CONV_std_logic_VECTOR(ABCLool,
32);
when iDAT8 =>
ABClo10 := CONV_Std_logic_vECTOR(ABCLOOL,
32);
ABCLO10(31 downto 8) := ( others => '-');
when idaT16 =>
ABClo10 := cONV_STD_logic_vecTOR(ABCLOOL,
32);
ABCLO10(31 downto 16) := ( others => '-');
when iDAT32 =>
ABClo10 := conV_STD_Logic_vectoR(ABCLOOL,
32);
when IRAM =>
ABCoo10(7 downto 0) := conv_std_LOGIC_Vector(ABClool,
8);
ABCi100(0) := '1';
ABCLO10 := ( others => '-');
when others =>
end case;
end if;
when IOR =>
ABCO100 := "000";
ABCl100 := "010";
ABCi100(0) := '0';
ABCLO10 := CONV_std_lOGIC_Vector(ABCoool,
32);
if ABCoi10 >= 3 then
case ABCoool is
when IDAT =>
ABClo10 := CONV_std_logic_VECTOR(ABClool,
32);
when idat8 =>
ABClo10 := cONV_STD_logic_vecTOR(ABCLOOL,
32);
ABClo10(31 downto 8) := ( others => '-');
when IDAT16 =>
ABCLO10 := CONV_std_logic_VECTOR(ABCLOOL,
32);
ABClo10(31 downto 16) := ( others => '-');
when iDAT32 =>
ABClo10 := Conv_std_loGIC_VECTor(ABCLool,
32);
when iram =>
ABCoo10(7 downto 0) := conv_std_LOGIC_Vector(ABClooL,
8);
ABCI100(0) := '1';
ABCLO10 := ( others => '-');
when others =>
end case;
end if;
when ixor =>
ABCo100 := "000";
ABCL100 := "011";
ABCi100(0) := '0';
ABClo10 := conv_sTD_LOGIc_vector(ABCoool,
32);
if ABCoi10 >= 3 then
case ABCoool is
when IDAT =>
ABClo10 := CONV_Std_logic_veCTOR(ABClool,
32);
when IDAT8 =>
ABClo10 := CONV_std_loGIC_VEctor(ABCLOOl,
32);
ABCLO10(31 downto 8) := ( others => '-');
when iDAT16 =>
ABClo10 := Conv_std_logIC_VECTor(ABClool,
32);
ABClo10(31 downto 16) := ( others => '-');
when iDAT32 =>
ABClo10 := Conv_std_loGIC_VECtor(ABClool,
32);
when iram =>
ABCOO10(7 downto 0) := conv_stD_LOGIC_vector(ABClool,
8);
ABCI100(0) := '1';
ABClO10 := ( others => '-');
when others =>
end case;
end if;
when IADD =>
ABCo100 := "000";
ABCl100 := "100";
ABCI100(0) := '0';
ABClo10 := Conv_std_logIC_VECTor(ABCoOOL,
32);
if ABCoi10 >= 3 then
case ABCooOL is
when idat =>
ABCLo10 := Conv_std_logIC_VECTor(ABCLOol,
32);
when IDAT8 =>
ABCLO10 := Conv_std_loGIC_VECtor(ABClool,
32);
ABClo10(31 downto 8) := ( others => '-');
when iDAT16 =>
ABClo10 := coNV_STD_logic_vectOR(ABCLool,
32);
ABCLO10(31 downto 16) := ( others => '-');
when iDAT32 =>
ABCLO10 := CONV_STD_logic_veCTOR(ABClool,
32);
when IRAm =>
ABCOO10(7 downto 0) := CONV_std_logic_VECTOR(ABCLOOL,
8);
ABCI100(0) := '1';
ABCLO10 := ( others => '-');
when others =>
end case;
end if;
when imult =>
ABCo100 := "000";
ABCL100 := "000";
ABCi100(0) := '0';
ABClo10 := conv_STD_Logic_vECTOR(ABCOOOL,
32);
if ABCOI10 >= 3 then
case ABCoool is
when IDAT =>
ABClo10 := cONV_STD_logic_vecTOR(ABCLOOl,
32);
when idat8 =>
ABClo10 := conv_STD_LOGIc_vector(ABCLOOL,
32);
ABClo10(31 downto 8) := ( others => '-');
when IDAt16 =>
ABClO10 := conv_STD_LOgic_vector(ABClool,
32);
ABClo10(31 downto 16) := ( others => '-');
when IDAT32 =>
ABCLO10 := conv_std_LOGIC_Vector(ABClool,
32);
when IRam =>
ABCoo10(7 downto 0) := CONV_std_logic_VECTOR(ABCLOOL,
8);
ABCI100(0) := '1';
ABClO10 := ( others => '-');
when others =>
end case;
end if;
when iSUB =>
ABCO100 := "000";
ABCl100 := "100";
ABCI100(0) := '0';
ABCLO10 := not (Conv_std_loGIC_VECTor(ABCOOOL,
32)-1);
if ABCoi10 >= 3 then
ABCLo10 := not (Conv_std_logIC_VECTOr(ABClool,
32)-1);
case ABCOOOL is
when idat =>
when idAT8 =>
ABCLO10(31 downto 8) := ( others => '1');
when IDAT16 =>
ABClo10(31 downto 16) := ( others => '1');
when iDAT32 =>
when iram =>
ABCoo10(7 downto 0) := CONV_std_logic_vECTOR(ABCLOol,
8);
ABCI100(0) := '1';
ABClo10 := ( others => '-');
when others =>
end case;
end if;
when ishl0 =>
ABCO100 := "000";
ABCL100 := "101";
ABClo10(1 downto 0) := "00";
ABCi100(0) := '0';
when isHL1 =>
ABCo100 := "000";
ABCl100 := "101";
ABClo10(1 downto 0) := "01";
ABCi100(0) := '0';
when ishle =>
ABCo100 := "000";
ABCl100 := "101";
ABClo10(1 downto 0) := "10";
ABCi100(0) := '0';
when irol =>
ABCO100 := "000";
ABCL100 := "101";
ABCLo10(1 downto 0) := "11";
ABCI100(0) := '0';
when ISHR0 =>
ABCO100 := "000";
ABCL100 := "110";
ABCLO10(1 downto 0) := "00";
ABCi100(0) := '0';
when Ishr1 =>
ABCo100 := "000";
ABCl100 := "110";
ABClo10(1 downto 0) := "01";
ABCi100(0) := '0';
when Ishre =>
ABCo100 := "000";
ABCL100 := "110";
ABCLo10(1 downto 0) := "10";
ABCi100(0) := '0';
when IROR =>
ABCo100 := "000";
ABCl100 := "110";
ABClo10(1 downto 0) := "11";
ABCI100(0) := '0';
when ICMP =>
ABCO100 := "001";
ABCl100 := "011";
ABCi100(0) := '0';
ABCLO10 := CONV_STd_logic_veCTOR(ABCoool,
32);
if ABCoi10 >= 3 then
case ABCoool is
when iDAT =>
ABCLO10 := Conv_std_lOGIC_VECtor(ABCLOOL,
32);
when idat8 =>
ABCLO10 := CONV_std_logic_VECTOR(ABClool,
32);
ABClO10(31 downto 8) := ( others => '-');
when idat16 =>
ABCLo10 := cONV_STD_logic_vecTOR(ABCLOol,
32);
ABCLO10(31 downto 16) := ( others => '-');
when IDAT32 =>
ABCLO10 := conv_std_LOGIC_VEctor(ABClool,
32);
when IRAM =>
ABCoo10(7 downto 0) := COnv_std_LOGIC_vecTOR(ABClool,
8);
ABCi100(0) := '1';
ABClo10 := ( others => '-');
when others =>
end case;
end if;
when icmpleq =>
ABCo100 := "001";
ABCl100 := "100";
ABCi100(0) := '0';
ABClo10 := not (conv_stD_LOGIC_vector(ABCoool,
32)-1);
if ABCOI10 >= 3 then
ABCLO10 := not (conv_STD_LOGic_vector(ABClool,
32)-1);
case ABCOOOL is
when idat =>
when IDAT8 =>
ABClO10(31 downto 8) := ( others => '1');
when Idat16 =>
ABClo10(31 downto 16) := ( others => '1');
when iDAT32 =>
when IRAM =>
ABCoo10(7 downto 0) := conV_STD_LOgic_vectoR(ABClool,
8);
ABCi100(0) := '1';
ABClo10 := ( others => '-');
when others =>
end case;
end if;
when Ibitclr =>
ABCO100 := "000";
ABCl100 := "001";
ABClO10 := ABCI010;
ABCLO10(ABCOOOL) := '0';
ABCI100(0) := '0';
when IBITSet =>
ABCo100 := "000";
ABCl100 := "010";
ABClo10 := zero;
ABClo10(ABCOOol) := '1';
ABCI100(0) := '0';
when IBIttst =>
ABCO100 := "001";
ABCl100 := "001";
ABCLO10 := ZERO;
ABCLO10(ABCoOOL) := '1';
ABCI100(0) := '0';
when IAPBREAdz =>
ABCo100 := "010";
ABCl100 := "111";
ABCi100 := conV_STD_Logic_vectOR(ABCoool,
4);
when iapbwrTZ =>
ABCo100 := "010";
ABCl100 := "---";
ABCI100 := COnv_std_logIC_VECTor(ABCloOL,
4);
case ABCOool is
when iacm =>
ABCl100 := "110";
when IACC =>
ABCL100 := "100";
when IDat =>
ABCl100 := "101";
ABClo10 := conv_STD_LOGIc_vectoR(ABCiOOL,
32);
when idat8 =>
ABCl100 := "101";
ABCLO10 := Conv_std_loGIC_VECtor(ABCiool,
32);
ABCLO10(31 downto 8) := ( others => '-');
when IDat16 =>
ABCl100 := "101";
ABCLO10 := cONV_STD_logic_vecTOR(ABCIOOl,
32);
ABCLO10(31 downto 16) := ( others => '-');
when IDAT32 =>
ABCl100 := "101";
ABClo10 := CONV_std_logic_VECTOR(ABCIOOL,
32);
when others =>
end case;
when IAPBread =>
ABCO100 := "010";
ABCl100 := "011";
ABCi100 := conv_STD_LOgic_vectoR(ABCoool,
4);
ABCoo10 := conv_std_loGIC_VEctor(ABClool,
16);
when iapbwrt =>
ABCo100 := "010";
ABCl100 := "---";
ABCi100 := cONV_STD_logic_vecTOR(ABClool,
4);
ABCOO10 := CONV_std_logic_VECTOR(ABCIOOL,
16);
case ABCoool is
when Iacm =>
ABCl100 := "010";
when IACc =>
ABCl100 := "000";
when IDAT =>
ABCL100 := "001";
ABClo10 := conV_STD_Logic_vectoR(ABCli10,
32);
when IDAT8 =>
ABCl100 := "001";
ABClo10 := Conv_std_loGIC_VECtor(ABCli10,
32);
ABClo10(31 downto 8) := ( others => '-');
when Idat16 =>
ABCL100 := "001";
ABClo10 := CONv_std_logiC_VECTOr(ABCLi10,
32);
ABCLO10(31 downto 16) := ( others => '-');
when iDAT32 =>
ABCL100 := "001";
ABClo10 := conV_STD_Logic_vectOR(ABCLi10,
32);
when others =>
end case;
when ILOADz =>
ABCo100 := "011";
ABCl100 := "000";
ABCI100(0) := '0';
case ABCOOOL is
when Iacc =>
ABCi100(0) := '1';
ABClO10 := ( others => '-');
when idat =>
ABClo10 := conV_STD_Logic_vectoR(ABCLOOL,
32);
when IDAT8 =>
ABClo10 := Conv_std_loGIC_VECtor(ABClool,
32);
ABCLo10(31 downto 8) := ( others => '-');
when idat16 =>
ABCLO10 := conv_std_lOGIC_VEctor(ABClooL,
32);
ABCLO10(31 downto 16) := ( others => '-');
when IDAT32 =>
ABCLO10 := Conv_std_loGIC_VECtor(ABClool,
32);
when others =>
end case;
when iincz =>
ABCo100 := "011";
ABCl100 := "001";
ABCi100(0) := '0';
ABCLO10 := conv_STD_LOgic_vectoR(1,
32);
when Idecz =>
ABCo100 := "011";
ABCl100 := "001";
ABCI100(0) := '0';
ABCLo10 := ( others => '1');
when iADDZ =>
ABCO100 := "011";
ABCl100 := "001";
ABCi100(0) := '0';
case ABCoool is
when IACC =>
ABCi100(0) := '1';
ABCLO10 := ( others => '-');
when IDAt =>
ABClO10 := conV_STD_LOgic_vectoR(ABCloOL,
32);
when idat8 =>
ABClo10 := CONV_std_logic_VECTOR(ABClool,
32);
ABClo10(31 downto 8) := ( others => '-');
when idat16 =>
ABCLO10 := cONV_STD_logic_vecTOR(ABCloOL,
32);
ABClo10(31 downto 16) := ( others => '-');
when IDAT32 =>
ABCLO10 := coNV_STD_Logic_vectOR(ABCloOL,
32);
when others =>
end case;
when isubZ =>
ABCO100 := "011";
ABCl100 := "001";
ABCI100(0) := '0';
case ABCOOOL is
when iacc =>
ABCI100(0) := '1';
ABClo10 := ( others => '-');
when Idat =>
ABClo10 := not (Conv_std_logIC_VECTor(ABCLool,
32)-1);
when idat8 =>
ABClO10 := not (Conv_std_logIC_VEctor(ABCloOL,
32)-1);
when idat16 =>
ABClo10 := not (coNV_STD_logic_vectOR(ABCLOOl,
32)-1);
when IDAT32 =>
ABClo10 := not (conv_STD_LOGIc_vector(ABCLOOL,
32)-1);
when others =>
end case;
when iiowrt =>
ABCO100 := "011";
ABCL100 := "111";
ABCi100(0) := '0';
case ABCooOL is
when IACC =>
ABCi100(0) := '1';
ABClo10 := ( others => '-');
when idat =>
ABClo10 := conv_std_LOGIC_vector(ABCLOOL,
32);
when Idat8 =>
ABClo10 := conv_STD_LOGIc_vector(ABClool,
32);
ABClo10(31 downto 8) := ( others => '-');
when idat16 =>
ABClo10 := Conv_std_loGIC_VECTor(ABClool,
32);
ABClo10(31 downto 16) := ( others => '-');
when IDAT32 =>
ABClo10 := CONV_std_logic_VECTOR(ABCLOol,
32);
when others =>
end case;
when Iioread =>
ABCO100 := "011";
ABCL100 := "110";
when iramread =>
ABCO100 := "011";
ABCl100 := "011";
ABCoo10 := Conv_std_logIC_VECTor(ABCoool,
16);
when iramwrT =>
ABCo100 := "011";
ABCl100 := "010";
ABCoo10 := conv_STD_LOGIc_vector(ABCOOOL,
16);
ABCi100(0) := '1';
if ABCoi10 >= 3 then
ABCI100(0) := '0';
ABCoo10 := Conv_std_logIC_VECTor(ABCoooL,
16);
case ABCLool is
when iacc =>
ABCi100(0) := '1';
ABClo10 := ( others => '-');
when Idat =>
ABClO10 := conv_STD_LOgic_vectoR(ABCIool,
32);
when idat8 =>
ABClo10 := conV_STD_Logic_vectOR(ABCiool,
32);
ABCLO10(31 downto 8) := ( others => '-');
when IDAT16 =>
ABCLO10 := coNV_STD_Logic_vectOR(ABCiool,
32);
ABClO10(31 downto 16) := ( others => '-');
when IDAT32 =>
ABCLO10 := CONV_std_logic_VECTOR(ABCiool,
32);
when others =>
end case;
end if;
when ipush =>
ABCo100 := "011";
ABCl100 := "100";
ABCi100(0) := '0';
case ABCOool is
when blank =>
ABCI100(0) := '1';
ABClo10 := ( others => '-');
when iacc =>
ABCI100(0) := '1';
ABCLo10 := ( others => '-');
when IDAT =>
ABClo10 := cONV_STD_logic_vectOR(ABCLOOl,
32);
when Idat8 =>
ABCLO10 := conv_sTD_LOGIc_vector(ABClool,
32);
ABClo10(31 downto 8) := ( others => '-');
when idaT16 =>
ABClo10 := coNV_STD_Logic_vectOR(ABCLOol,
32);
ABClo10(31 downto 16) := ( others => '-');
when iDAT32 =>
ABClo10 := CONV_std_logic_VECTOR(ABCLOOL,
32);
when others =>
end case;
when Ipop =>
ABCo100 := "011";
ABCL100 := "101";
when ijumpb =>
ABCo100 := "100";
ABCl100 := "-01";
if ABCoi10 >= 4 then
ABCl100(0) := ABCoI1(ABCoool);
ABClo10 := ABCII10(ABCLOol);
ABCoo10 := coNV_Std_logiC_VECtor(ABCIOOL,
16);
else
ABClo10(0) := '1';
ABCoO10 := conv_stD_LOGIC_vector(ABCoool,
16);
end if;
ABCLo10(31 downto FFW+4) := ( others => '-');
when IWAITB =>
ABCo100 := "100";
ABCl100 := "-11";
if ABCOI10 >= 3 then
ABCL100(0) := ABCoi1(ABCOOOl);
ABClo10 := ABCii10(ABCloOL);
else
ABClo10(0) := '1';
end if;
ABClo10(31 downto FFW+4) := ( others => '-');
when ICALLB =>
ABCO100 := "101";
ABCl100 := "-01";
if ABCoi10 >= 4 then
ABCl100(0) := ABCoi1(ABCOOOL);
ABClo10 := ABCIi10(ABClooL);
ABCOO10 := CONV_STD_logic_veCTOR(ABCIOOL,
16);
else
ABCLO10(0) := '1';
ABCoo10 := Conv_std_lOGIC_VEctor(ABCOOOL,
16);
end if;
ABCLo10(31 downto FFW+4) := ( others => '-');
when IRETurnb =>
ABCO100 := "110";
ABCL100 := "-01";
if ABCoi10 >= 3 then
ABCL100(0) := ABCoi1(ABCoool);
ABClo10 := ABCii10(ABCloOL);
else
ABCLO10(0) := '1';
end if;
ABClo10(31 downto FFW+4) := ( others => '-');
when IretisrB =>
ABCo100 := "110";
ABCl100 := "-11";
if ABCoi10 >= 3 then
ABCl100(0) := ABCoi1(ABCoool);
ABCLO10 := CONv_std_logic_VECTOR(ABCLool,
FFW);
else
ABClo10(0) := '1';
end if;
ABClo10(31 downto FFW+4) := ( others => '-');
when inop =>
ABCO100 := "111";
if EN_USER = 1 then
ABCl100 := "000";
end if;
when iuser =>
ABCO100 := "111";
ABCL100(0) := '1';
ABCl100 := CONv_std_logiC_VECTOr(ABCOOOL,
3);
ABClo10 := conv_STD_LOGIc_vector(ABCLOOL,
32);
ABCoo10 := conv_STD_LOgic_vectoR(ABCiool,
16);
ABCi100 := conv_stD_LOGIC_vector(ABCli10,
4);
when others =>
end case;
return (ABCi000(ABCo100,
ABCl100,
ABCi100,
ABCOO10,
ABClo10));
end ABCil10;
function max(A,b: INTEGEr)
return iNTEGER is
begin
if a > B then
return (a);
else
return (b);
end if;
end max;
function MIN(a,B: intEGER)
return integER is
begin
if a < b then
return (a);
else
return (b);
end if;
end MIN;
function ABCoi1(ABCIO10: Integer)
return std_logic is
begin
if ABCio10 /= 0 then
return ('1');
else
return ('0');
end if;
end ABCoi1;
function ABCoi1(ABCio10: boolean)
return STd_logic is
begin
if ABCio10 then
return ('1');
else
return ('0');
end if;
end ABCOI1;
function ABCOL10(EN_RAM,EN_CALL,dwIDTH,ICWIDTH: INTEger)
return integER is
variable ABCo0i,ABCI0I: integer;
begin
ABCO0I := 0;
ABCI0I := 0;
if EN_CALL = 1 then
ABCI0I := 8;
if ICWIDTH > 8 then
ABCi0I := 16;
end if;
end if;
if EN_RAM = 1 then
ABCo0i := DWIDTH;
end if;
if ABCO0I > ABCi0i then
return (ABCo0i);
elsif ABCI0i > 0 then
return (ABCi0i);
else
return (1);
end if;
end ABCOL10;
function calc_SWIDTH(X: iNTEGER)
return INteger is
begin
if X >= 9 then
return (4);
elsif X >= 5 then
return (3);
elsif X >= 3 then
return (2);
elsif x >= 2 then
return (1);
else
return (0);
end if;
end caLC_SWIDTh;
function Log2r(X: INTEGER)
return integer is
begin
if X >= 65536 then
return (17);
elsif x >= 32768 then
return (16);
elsif X >= 16384 then
return (15);
elsif x >= 8192 then
return (14);
elsif x >= 4096 then
return (13);
elsif X >= 2048 then
return (12);
elsif x >= 1024 then
return (11);
elsif X >= 512 then
return (10);
elsif x >= 256 then
return (9);
elsif X >= 128 then
return (8);
elsif x >= 64 then
return (7);
elsif x >= 32 then
return (6);
elsif X >= 16 then
return (5);
elsif x >= 8 then
return (4);
elsif X >= 4 then
return (3);
elsif X >= 2 then
return (2);
elsif X >= 1 then
return (1);
else
return (1);
end if;
end log2r;
function calc_iniTWIDTH(awidth,dwidth,ABCLL10,ICWIDTH: INTEGER)
return integer is
variable Swidth: integer;
variable ABCLL0: integER;
variable ABCil0: INTEger;
variable ABCOI0: integer;
variable ABCLI0: iNTEGER;
variable ABCL110: INTEGER;
variable ABCi110: integer;
variable ABCooo1: INTEGER;
begin
if ABCll10 = 0 then
swidth := CALC_SWidth(ABCLL10);
else
Swidth := 1;
end if;
ABCll0 := 2**ICWIDTH;
ABCil0 := awidtH+dwidtH+swidth+6;
ABCoi0 := 1+(ABCLL0-1)/512;
ABCli0 := 1+(ABCil0-1)/9;
ABCL110 := ABCli0*ABCOI0;
ABCI110 := ABCl110*512;
ABCOOO1 := Log2r(ABCi110);
if ABCOOO1 > 16 then
ABCooo1 := 16;
end if;
return (ABCOOO1);
end CALC_initwidth;
function CLEan(X: sTD_LOGIC_vector)
return std_loGIC_VECtor is
variable ABCio10: STD_logic_vecTOR(X'range );
begin
ABCiO10 := X;
-- synthesis translate_off
ABCIO10 := ( others => '0');
for ABCol in ABCIo10'range
loop
if x(ABCol) = '1' then
ABCio10(ABCOL) := '1';
end if;
end loop;
-- synthesis translate_on
return (ABCio10);
end CLEan;
end Top_Waveform_COREABC_0_support;
