-- Copyright 2008 Actel Corporation.  All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
-- Rev: 2.4   24Jan08 IPB  : Production Release
-- SVN Revision Information:
-- SVN $Revision: 14825 $
library ieee;
use Ieee.STD_logic_1164.all;
library SMartfusion;
entity Top_Waveform_COREABC_0_iram512X9 is
generic (Cid: integeR;
rid: Integer;
uniq_sTRING_LEngth: integER range 1 to 256 := 10); port (rwclk: in Std_logic;
reSET: in STD_LOgic;
Renable: in std_lOGIC;
RADDR: in STd_logic_veCTOR(8 downto 0);
rd: out std_LOGIC_Vector(8 downto 0);
INITADDR: in stD_LOGIC_vector(8 downto 0);
wenable: in STD_LOGic;
INITDATA: in STD_LOgic_vector(8 downto 0));
end Top_Waveform_COREABC_0_irAM512X9;

architecture RTL of Top_Waveform_COREABC_0_IRAM512x9 is

component RAM4K9
generic (MEmoryfile: STRING := "");
port (addRA11,ADDRA10,addra9,addRA8,ADDRA7,ADDRA6,ADDra5,Addra4,Addra3,Addra2,ADDRa1,ADDRA0,ADDRB11,ADDRB10,aDDRB9,addrb8,ADDRB7,addrB6,ADdrb5,adDRB4,ADDrb3,addrb2,ADDRB1,ADDrb0,dina8,dina7,dina6,Dina5,DINA4,DINA3,dina2,Dina1,DINA0,dinb8,DINB7,dinb6,DINB5,Dinb4,dinb3,diNB2,DINB1,DINB0,WIDTha0,WIdtha1,Widthb0,Widthb1,PIPea,pIPEB,wmodea,WMODeb,blka,BLKB,WEna,wenb,clka,clkb,reset: in STD_LOgic := 'U';
DOUta8,dOUTA7,douTA6,douta5,DOUta4,DOUTA3,douta2,DOUTA1,douta0,DOUTb8,doutb7,dOUTB6,DOUTb5,Doutb4,doutb3,doutb2,doutb1,doutb0: out STD_logic);
end component;

signal ABCOll0,ABClll0,ABClloi,ABCiloi: STd_logic;

-- synthesis translate_off
constant ABCoioi: sTRING(1 to (UNIQ_STRING_LENGTH+11)) := "Top_Waveform_COREABC_0_RAM_"&CHARACTER'VAL(Rid+48)&characTER'val(Cid+48)&".mem";

-- synthesis translate_on
begin
ABCllOI <= '1';
ABCiloi <= '0';
ABClll0 <= not reNABLE;
ABColl0 <= not WENAble;
iraM: raM4K9
-- synthesis translate_off
generic map (memoryFILE => ABCOIoi)
-- synthesis translate_on
port map (addrA11 => ABCILOI,
ADDRA10 => ABCIloi,
ADDRA9 => ABCiloi,
ADDRA8 => INITADDR(8),
ADDRA7 => INITADDR(7),
addra6 => INITADDR(6),
aDDRA5 => INITADDR(5),
ADDra4 => INITADDR(4),
ADDRA3 => INITADDR(3),
ADDRA2 => INITADDR(2),
Addra1 => INITADDR(1),
ADDRA0 => INITADDR(0),
addrb11 => ABCILOI,
addrb10 => ABCiloi,
addrb9 => ABCiLOI,
addrb8 => RADDR(8),
addrb7 => RADDR(7),
addrb6 => rADDR(6),
aDDRB5 => raddr(5),
ADdrb4 => raddr(4),
aDDRB3 => raddr(3),
ADDRb2 => Raddr(2),
addRB1 => RADDR(1),
addrb0 => RAddr(0),
DINa8 => INITDATA(8),
DINa7 => INITDATA(7),
DINa6 => INITDATA(6),
DINA5 => INITDATA(5),
dINA4 => INITDATA(4),
DINa3 => INITDATA(3),
dinA2 => INITDATA(2),
DIna1 => INITDATA(1),
DINA0 => INITDATA(0),
DINB8 => ABCILOi,
dinb7 => ABCILOI,
dinb6 => ABCILOi,
DINb5 => ABCiLOI,
dinb4 => ABCiloi,
DINB3 => ABCiloi,
DINB2 => ABCILOI,
dinb1 => ABCILoi,
dINB0 => ABCILOI,
widtha0 => ABClloi,
wiDTHA1 => ABCLloi,
widTHB0 => ABClloi,
WIDTHB1 => ABClLOI,
Pipea => ABCiloi,
Pipeb => ABCiloi,
wmodea => ABCiloi,
Wmodeb => ABCiloi,
blka => ABColl0,
Blkb => ABCLll0,
WENA => ABCILOI,
WENB => ABClLOI,
clka => RWCLk,
clkb => rwclk,
Reset => reSET,
DOUTa8 => open ,
Douta7 => open ,
DOuta6 => open ,
dOUTA5 => open ,
douta4 => open ,
DOUTA3 => open ,
douta2 => open ,
DOUTa1 => open ,
douta0 => open ,
doUTB8 => rd(8),
Doutb7 => rd(7),
douTB6 => RD(6),
Doutb5 => RD(5),
doutb4 => rd(4),
DOUTb3 => rd(3),
doutb2 => rd(2),
Doutb1 => RD(1),
doutb0 => rd(0));
end Rtl;
