-- Copyright 2008 Actel Corporation.  All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
-- Rev: 2.4   24Jan08 IPB  : Production Release
-- SVN Revision Information:
-- SVN $Revision: 11083 $
library ieee;
use Ieee.STD_logic_1164.all;
library Proasic3;
entity Top_Waveform_COREABC_0_irAM512X9 is
generic (ciD: INTEGer;
RID: INTEGER;
UNIQ_string_lENGTH: INTEGer range 1 to 256 := 10); port (rWCLK: in STD_LOGIc;
reset: in std_logIC;
RENAble: in std_logic;
RADDR: in std_logIC_VECTOr(8 downto 0);
Rd: out std_logiC_VECTOR(8 downto 0);
INITADDR: in sTD_LOGIC_vector(8 downto 0);
weNABLE: in std_logic;
INITDATA: in STD_LOgic_vector(8 downto 0));
end Top_Waveform_COREABC_0_IRAM512x9;

architecture rtl of Top_Waveform_COREABC_0_iRAM512X9 is

component RAM4K9
generic (memorYFILE: string := "");
port (adDRA11,ADDRA10,addra9,addrA8,ADDRA7,ADdra6,addra5,ADDRa4,addrA3,ADDra2,ADDRA1,ADDra0,adDRB11,ADDRB10,addrb9,ADdrb8,ADdrb7,adDRB6,ADDrb5,ADDRB4,addrb3,ADDRB2,Addrb1,addrb0,DINA8,DINA7,DINA6,DINA5,DINA4,DINA3,DINA2,diNA1,Dina0,DINB8,dinb7,DINB6,DInb5,dinb4,dINB3,DINB2,DInb1,Dinb0,Widtha0,widtha1,widtHB0,wiDTHB1,piPEA,Pipeb,WMODEa,WMODEB,blka,bLKB,WENA,Wenb,clkA,clKB,rESET: in std_lOGIC := 'U';
Douta8,DOUTA7,DOUTA6,dOUTA5,douta4,DOUTA3,dOUTA2,douta1,DOUTA0,doutb8,doutb7,DOUTB6,DOUtb5,doutb4,doutb3,douTB2,dOUTB1,DOUTB0: out std_LOGIC);
end component;

signal ABColL0,ABCLLL0,ABClloi,ABCIloi: STd_logic;

-- synthesis translate_off
constant ABCoioi: string(1 to (UNIQ_STRING_LENGTH+11)) := "Top_Waveform_COREABC_0_RAM_"&chARACTER'vaL(rid+48)&characTER'val(cid+48)&".mem";

-- synthesis translate_on
begin
ABCllOI <= '1';
ABCILoi <= '0';
ABCLLL0 <= not reNABLE;
ABCOll0 <= not wenable;
irAM: ram4K9
-- synthesis translate_off
generic map (meMORYFIle => ABCoioi)
-- synthesis translate_on
port map (Addra11 => ABCiloi,
Addra10 => ABCiloi,
addra9 => ABCILOI,
ADDRA8 => INITADDR(8),
ADDRA7 => INITADDR(7),
Addra6 => INITADDR(6),
addra5 => INITADDR(5),
ADDRA4 => INITADDR(4),
ADDra3 => INITADDR(3),
ADDRA2 => INITADDR(2),
addra1 => INITADDR(1),
addra0 => INITADDR(0),
addrb11 => ABCiloi,
addRB10 => ABCIloi,
ADDRB9 => ABCILOI,
Addrb8 => RAddr(8),
Addrb7 => raDDR(7),
Addrb6 => RADDR(6),
ADDRB5 => RADDR(5),
addrb4 => raddR(4),
addrb3 => raddr(3),
addrb2 => raddr(2),
ADDrb1 => raddr(1),
addrb0 => raddr(0),
Dina8 => INITDATA(8),
DINA7 => INITDATA(7),
dina6 => INITDATA(6),
DINA5 => INITDATA(5),
dina4 => INITDATA(4),
Dina3 => INITDATA(3),
DINA2 => INITDATA(2),
DINA1 => INITDATA(1),
dINA0 => INITDATA(0),
DINb8 => ABCILOI,
DINB7 => ABCiLOI,
dinb6 => ABCiloi,
DINB5 => ABCILOI,
DINB4 => ABCILOI,
DINB3 => ABCILOI,
dinb2 => ABCILOI,
DINB1 => ABCiloi,
dinb0 => ABCiloi,
WIDTHA0 => ABCLLOI,
WIDtha1 => ABClLOI,
widthb0 => ABClloi,
widthb1 => ABCLLOI,
PIpea => ABCiloI,
Pipeb => ABCILOi,
WMODea => ABCiloi,
WMODEB => ABCiloi,
BLka => ABColl0,
blKB => ABClll0,
wena => ABCiloi,
Wenb => ABCLLOI,
CLKA => rwcLK,
clkb => Rwclk,
RESET => RESET,
douta8 => open ,
DOUTA7 => open ,
doUTA6 => open ,
douta5 => open ,
DOUTA4 => open ,
douta3 => open ,
douTA2 => open ,
douta1 => open ,
DOUTA0 => open ,
DOUtb8 => RD(8),
doutb7 => rD(7),
DOUTB6 => rD(6),
DOUTB5 => RD(5),
douTB4 => rd(4),
doutb3 => RD(3),
doutb2 => Rd(2),
DOUTB1 => rd(1),
doutb0 => rd(0));
end RTL;
