********************************************************************
                            Global Usage Report
********************************************************************
  
Product: Designer
Release: v10.0
Version: 10.0.9.37
Date: Thu Dec 08 14:41:21 2011
Design Name: Top_Waveform  Family: SmartFusion  Die: A2F200M3F  Package: 484 FBGA
Design State: Post-Layout

The following nets have been routed to a chip global resource:

    Fanout            Name
    ----------------------
    84                Net   : COREABC_0_PRESETN
                      Driver: COREABC_0/ABCOIOOI_RNINBN1/U_CLKSRC/U_GL
    108               Net   : FAB_CLK
                      Driver: MSS_Waveform_0/MSS_CCC_0/I_MSSCCC/U_TILE2
    56                Net   : COREABC_0_APB3master_PADDR_[2]
                      Driver: COREABC_0/ZREGISTER_RNI9S4L_0[2]/U_CLKSRC/U_GL
    61                Net   : COREABC_0_APB3master_PADDR_[7]
                      Driver: COREABC_0/ZREGISTER_RNIUTQE_0[7]/U_CLKSRC/U_GL




