# (OPEN DESIGN)

open_design "C:/A2F_AC350_DF/A2F500/Fabric_Logic_as_Master/Verilog/Waveform_Gen/designer/impl1/Top_Waveform.adb"
export -format "FDB" {C:/A2F_AC350_DF/A2F500/Fabric_Logic_as_Master/Verilog/Waveform_Gen/designer/impl1/Top_Waveform.fdb}

save_design "C:/A2F_AC350_DF/A2F500/Fabric_Logic_as_Master/Verilog/Waveform_Gen/designer/impl1/Top_Waveform.adb"

