-- Copyright 2008 Actel Corporation.  All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
-- Rev: 2.4   24Jan08 IPB  : Production Release
-- SVN Revision Information:
-- SVN $Revision: 14578 $
library ieee;
use ieee.std_logiC_1164.all;
use IEee.STD_logic_aritH.all;
use Ieee.std_LOGIC_Unsigned.all;
package Top_Waveform_COREABC_0_COMPONents is

component Top_Waveform_COREABC_0_COREABC
generic (FAMILY: integer range 0 to 22;
APB_Awidth: INTEGer range 8 to 16;
APb_dwidth: INTEGer range 8 to 32;
apB_SDEPTH: integER range 1 to 16;
ICWIDTh: integer range 1 to 16;
Zrwidth: integER range 0 to 16;
ifWIDTH: INTEGER range 0 to 28;
IIWIDTH: Integer range 1 to 32;
Iowidth: integer range 1 to 32;
STWIDTh: INTeger range 1 to 8;
en_RAM: intEGER range 0 to 1;
en_anD: integer range 0 to 1;
EN_XOR: iNTEGER range 0 to 1;
EN_OR: INTEGER range 0 to 1;
EN_Add: iNTEGER range 0 to 1;
EN_INC: integeR range 0 to 1;
EN_shl: INTEGER range 0 to 1;
EN_shr: INTEGER range 0 to 1;
en_calL: INTEger range 0 to 1;
EN_push: integER range 0 to 1;
EN_MULT: inTEGER range 0 to 3;
EN_ACm: integer range 0 to 1;
EN_datam: intEGER range 0 to 3;
en_int: inteGER range 0 to 2;
en_ioREAD: INTeger range 0 to 1;
EN_iowrt: inteGER range 0 to 1;
en_alURAM: INTEGER range 0 to 1;
en_indirECT: INTEGER range 0 to 1;
isradDR: inTEGER range 0 to 65536;
deBUG: integER range 0 to 1;
insmodE: integer range 0 to 2;
initWIDTH: INTEGER range 1 to 16;
TEstmode: Integer range 0 to 99 := 0;
ACT_CALIbrationdatA: iNTEGER range 0 to 1 := 1;
IMEM_apb_accesS: integER range 0 to 2 := 2;
uniq_STRING_length: integer range 1 to 256 := 10);
port (pcLK: in STD_Logic;
NSYSRESET: in stD_LOGIC;
presETN: out STD_LOgic;
pENABLE_M: out std_logIC;
PWRITE_m: out std_LOGIC;
pSEL_M: out STD_logic;
PADDR_M: out STd_logic_vecTOR(19 downto 0);
PWDATA_M: out sTD_LOGIc_vector(APB_DWIDTH-1 downto 0);
PRDATA_M: in STd_logic_vecTOR(APB_DWIDTH-1 downto 0);
pready_m: in std_logic;
PSlverr_m: in STD_LOGic;
IO_IN: in STD_LOgic_vector(IIWIDTH-1 downto 0);
IO_OUT: out STD_LOGIC_vector(IOWIDTH-1 downto 0);
Intreq: in STD_Logic;
INTact: out STd_logic;
initdatVAL: in STD_LOgic;
INITDONE: in STD_LOGIc;
INITADDR: in std_logic_vECTOR(INITWIDTH-1 downto 0);
INITDATA: in std_lOGIC_VECtor(8 downto 0);
PSel_s: in STD_logic;
penable_s: in sTD_LOGIC;
PWRITE_S: in STD_LOGIc;
PADDR_S: in Std_logic_VECTOR(APB_AWIDTH-1 downto 0);
PWDATA_S: in Std_logic_VECTOR(APB_DWIDTH-1 downto 0);
PRDATA_S: out stD_LOGIC_vector(APB_DWIDTH-1 downto 0);
pslverr_s: out STD_logic;
prEADY_S: out STD_LOgic);
end component;
end Top_Waveform_COREABC_0_COMPONEnts;
