`timescale 1ns/100ps
// Copyright 2008 Actel Corporation.  All rights reserved.
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
// Rev: 2.4   24Jan08 IPB  : Production Release
// SVN Revision Information:
// SVN $Revision: 14690 $
module
Top_Waveform_COREABC_0_RAMBLOCKS
(
CLK
,
RESETN
,
WEN
,
ADDR
,
WD
,
RD
)
;
parameter
DWIDTH
=
0
;
parameter
FAMILY
=
0
;
input
CLK
;
input
RESETN
;
input
WEN
;
input
[
7
:
0
]
ADDR
;
input
[
DWIDTH
-
1
:
0
]
WD
;
output
[
DWIDTH
-
1
:
0
]
RD
;
reg
[
DWIDTH
-
1
:
0
]
RD
;
wire
[
DWIDTH
-
1
:
0
]
ABCOIO1
;
wire
[
15
:
0
]
ABCIIO1
;
wire
[
15
:
0
]
ABClIO1
;
wire
[
15
:
0
]
ABCOlO1
;
wire
[
15
:
0
]
ABCIlO1
;
wire
[
31
:
0
]
ABCllO1
;
wire
ABCO0O1
;
wire
ABClllI
;
wire
ABCO0lI
;
wire
[
8
:
0
]
ABCI0O1
;
wire
[
31
:
0
]
RD32
;
wire
[
31
:
0
]
WD32
;
assign
ABClllI
=
1
'b
0
;
assign
ABCO0lI
=
1
'b
1
;
assign
ABCO0O1
=
~
WEN
;
assign
ABCI0O1
=
{
1
'b
0
,
ADDR
}
;
generate
if
(
FAMILY
==
0
)
begin
:
ABCl0O1
always
@
(
posedge
CLK
)
begin
:
ABCO1O1
reg
[
DWIDTH
-
1
:
0
]
RAM
[
0
:
255
]
;
reg
[
7
:
0
]
ABCI1O1
;
reg
[
7
:
0
]
ABClI10
;
ABClI10
=
0
;
ABCI1O1
=
0
;
begin
:
ABCl1O1
integer
ABCOlI
;
for
(
ABCOlI
=
0
;
ABCOlI
<=
7
;
ABCOlI
=
ABCOlI
+
1
)
begin
if
(
(
ADDR
[
ABCOlI
]
)
==
1
'b
1
)
begin
ABCI1O1
[
ABCOlI
]
=
1
'b
1
;
end
end
end
ABClI10
=
ABCI1O1
;
if
(
WEN
==
1
'b
1
)
begin
RAM
[
ABClI10
]
=
WD
;
end
RD
<=
RAM
[
ABClI10
]
;
end
end
endgenerate
generate
if
(
FAMILY
==
11
|
FAMILY
==
12
)
begin
:
ABCOOI1
if
(
DWIDTH
==
8
|
DWIDTH
==
16
)
begin
:
ABCIOI1
Top_Waveform_COREABC_0_RAM256X16
ABCOO0I
(
.RWCLK
(
CLK
)
,
.RESET
(
RESETN
)
,
.WEN
(
WEN
)
,
.REN
(
ABCO0O1
)
,
.WADDR
(
ADDR
)
,
.RADDR
(
ADDR
)
,
.WD
(
ABCIIO1
)
,
.RD
(
ABClIO1
)
)
;
end
if
(
DWIDTH
==
8
)
begin
:
ABClOI1
assign
ABCIIO1
=
{
8
'b
00000000
,
WD
}
;
wire
[
DWIDTH
-
1
:
0
]
ABCOI0I
=
ABClIO1
[
7
:
0
]
;
always
@
(
ABCOI0I
)
begin
RD
<=
ABCOI0I
;
end
end
if
(
DWIDTH
==
16
)
begin
:
ABCOII1
assign
ABCIIO1
=
WD
;
wire
[
DWIDTH
-
1
:
0
]
ABCIII1
=
ABClIO1
;
always
@
(
ABCIII1
)
begin
RD
<=
ABCIII1
;
end
end
if
(
DWIDTH
==
32
)
begin
:
ABClII1
Top_Waveform_COREABC_0_RAM256X16
ABCOlI1
(
.RWCLK
(
CLK
)
,
.RESET
(
RESETN
)
,
.WEN
(
WEN
)
,
.REN
(
ABCO0O1
)
,
.WADDR
(
ADDR
)
,
.RADDR
(
ADDR
)
,
.WD
(
WD
[
15
:
0
]
)
,
.RD
(
ABCllO1
[
15
:
0
]
)
)
;
Top_Waveform_COREABC_0_RAM256X16
ABCIlI1
(
.RWCLK
(
CLK
)
,
.RESET
(
RESETN
)
,
.WEN
(
WEN
)
,
.REN
(
ABCO0O1
)
,
.WADDR
(
ADDR
)
,
.RADDR
(
ADDR
)
,
.WD
(
WD
[
31
:
16
]
)
,
.RD
(
ABCllO1
[
31
:
16
]
)
)
;
end
if
(
DWIDTH
==
32
)
begin
always
@
(
ABCllO1
)
begin
RD
<=
ABCllO1
;
end
end
end
endgenerate
generate
if
(
FAMILY
==
14
)
begin
:
ABCllI1
genvar
ABCOlI
;
for
(
ABCOlI
=
0
;
ABCOlI
<=
DWIDTH
/
8
-
1
;
ABCOlI
=
ABCOlI
+
1
)
begin
:
ABCOO0I
Top_Waveform_COREABC_0_RAM256X8
ABCO0I1
(
.RWCLK
(
CLK
)
,
.RESET
(
CLK
)
,
.WEN
(
WEN
)
,
.REN
(
ABCO0lI
)
,
.WADDR
(
ADDR
)
,
.RADDR
(
ADDR
)
,
.WD
(
WD
[
ABCOlI
*
8
+
7
:
ABCOlI
*
8
]
)
,
.RD
(
ABCOIO1
[
ABCOlI
*
8
+
7
:
ABCOlI
*
8
]
)
)
;
end
always
@
(
ABCOIO1
)
RD
<=
ABCOIO1
;
end
endgenerate
generate
if
(
FAMILY
==
15
|
FAMILY
==
16
|
FAMILY
==
17
|
FAMILY
==
18
|
FAMILY
==
20
|
FAMILY
==
21
|
FAMILY
==
22
|
FAMILY
==
23
)
begin
:
ABCI0I1
Top_Waveform_COREABC_0_RAM256X16
ABCl0I1
(
.RWCLK
(
CLK
)
,
.RESET
(
RESETN
)
,
.WEN
(
WEN
)
,
.REN
(
ABCO0O1
)
,
.WADDR
(
ADDR
)
,
.RADDR
(
ADDR
)
,
.WD
(
ABCIIO1
)
,
.RD
(
ABClIO1
)
)
;
if
(
DWIDTH
==
8
)
begin
:
ABClOI1
assign
ABCIIO1
=
{
8
'b
00000000
,
WD
}
;
wire
[
DWIDTH
-
1
:
0
]
ABCO1I1
=
ABClIO1
[
7
:
0
]
;
always
@
(
ABCO1I1
)
begin
RD
<=
ABCO1I1
;
end
end
if
(
DWIDTH
==
16
)
begin
:
ABCOII1
assign
ABCIIO1
=
WD
;
wire
[
DWIDTH
-
1
:
0
]
ABCI1I1
=
ABClIO1
;
always
@
(
ABCI1I1
)
begin
RD
<=
ABCI1I1
;
end
end
if
(
DWIDTH
==
32
)
begin
:
ABCl1I1
Top_Waveform_COREABC_0_RAM256X16
ABCOOl1
(
.RWCLK
(
CLK
)
,
.RESET
(
RESETN
)
,
.WEN
(
WEN
)
,
.REN
(
ABCO0O1
)
,
.WADDR
(
ADDR
)
,
.RADDR
(
ADDR
)
,
.WD
(
ABCOlO1
)
,
.RD
(
ABCIlO1
)
)
;
assign
ABCIIO1
=
WD
[
15
:
0
]
;
assign
ABCOlO1
=
WD
[
31
:
16
]
;
wire
[
DWIDTH
-
1
:
0
]
ABCIOl1
=
{
ABCIlO1
,
ABClIO1
}
;
always
@
(
ABCIOl1
)
begin
RD
<=
ABCIOl1
;
end
end
end
endgenerate
endmodule
