-- Copyright 2006 Actel Corporation.  All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
-- Rev: 2.0  31Oct06 IPB  : Production Release
library Ieee;
use IEEe.STD_logic_1164.all;
use iEEE.std_loGIC_UNSIgned.all;
use ieee.std_logic_ARITH.all;
entity Top_Waveform_COREABC_0_ram256X8 is
port (rwclk: in STD_LOgic;
RESET: in STD_logic;
wen: in STd_logic;
REn: in std_logic;
WADDR: in std_lOGIC_VECtor(7 downto 0);
raddr: in std_LOGIC_Vector(7 downto 0);
WD: in std_logic_VECTOr(7 downto 0);
Rd: out std_lOGIC_VECtor(7 downto 0));
end Top_Waveform_COREABC_0_ram256X8;

architecture RTL of Top_Waveform_COREABC_0_RAM256x8 is

subtype ABCl00 is sTD_LOGIC_vector(7 downto 0);

type ABCILL0 is array (Integer range <> ) of ABCL00;

begin
process (RWCLK)
variable ABCoil0: iNTEGER;
variable RAM: ABCILL0(0 to 255);
begin
if RWCLK'Event and RWCLk = '1' then
if WEN = '1' then
ABCOIl0 := CONV_integer(waddr);
RAM(ABCOil0) := wd;
end if;
ABCoil0 := Conv_integeR(RADDR);
if ren = '1' then
rd <= RAM(ABCoil0);
end if;
end if;
end process;
end RTL;
