#Build: Synplify Pro E-2010.09A-1, Build 006R, Oct 6 2010 #install: \\idm\tools\releases\production\Libero\Libero_91\PC_Libero_9_1_0_18_winxp_32\Synopsys\synplify_E201009A-1 #OS: Windows XP 5.1 #Hostname: VXP-ARNIS #Implementation: synthesis #Wed Apr 27 16:17:28 2011 $ Start of Compile #Wed Apr 27 16:17:28 2011 Synopsys Verilog Compiler, version comp520rcp1, Build 028R, built Sep 23 2010 @N: : | Running in 32-bit mode Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved @I::"\\idm\tools\releases\production\Libero\Libero_91\PC_Libero_9_1_0_18_winxp_32\Synopsys\synplify_E201009A-1\lib\proasic\smartfusion.v" @I::"\\idm\tools\releases\production\Libero\Libero_91\PC_Libero_9_1_0_18_winxp_32\Synopsys\synplify_E201009A-1\lib\vlog\hypermods.v" @I::"C:\appnotes\AC348\SmartFusion_Accessing_Ext_Mem_Using_EMC_DF\Hardware\A2F500\Verilog\Accessing_External_Memories\component\Actel\SmartFusionMSS\MSS\2.4.105\mss_comps.v" @I::"C:\appnotes\AC348\SmartFusion_Accessing_Ext_Mem_Using_EMC_DF\Hardware\A2F500\Verilog\Accessing_External_Memories\component\work\EMC_MSS\MSS_CCC_0\EMC_MSS_tmp_MSS_CCC_0_MSS_CCC.v" @I::"C:\appnotes\AC348\SmartFusion_Accessing_Ext_Mem_Using_EMC_DF\Hardware\A2F500\Verilog\Accessing_External_Memories\component\work\EMC_MSS\mss_tshell.v" @I::"C:\appnotes\AC348\SmartFusion_Accessing_Ext_Mem_Using_EMC_DF\Hardware\A2F500\Verilog\Accessing_External_Memories\component\work\EMC_MSS\EMC_MSS.v" @I::"C:\appnotes\AC348\SmartFusion_Accessing_Ext_Mem_Using_EMC_DF\Hardware\A2F500\Verilog\Accessing_External_Memories\component\work\EMC_External_Memories\EMC_External_Memories.v" Verilog syntax check successful! Compiler output is up to date. No re-compile necessary Selecting top level module EMC_External_Memories @N:CG364 : smartfusion.v(1814) | Synthesizing module VCC @N:CG364 : smartfusion.v(1133) | Synthesizing module GND @N:CG364 : mss_comps.v(67) | Synthesizing module BIBUF_MSS @N:CG364 : mss_comps.v(37) | Synthesizing module OUTBUF_MSS @N:CG364 : mss_comps.v(23) | Synthesizing module INBUF_MSS @N:CG364 : mss_comps.v(151) | Synthesizing module MSS_CCC @N:CG364 : mss_comps.v(1) | Synthesizing module MSS_XTLOSC @N:CG364 : EMC_MSS_tmp_MSS_CCC_0_MSS_CCC.v(5) | Synthesizing module EMC_MSS_tmp_MSS_CCC_0_MSS_CCC @N:CG364 : mss_tshell.v(1) | Synthesizing module MSS_APB @N:CG364 : EMC_MSS.v(5) | Synthesizing module EMC_MSS @N:CG364 : EMC_External_Memories.v(5) | Synthesizing module EMC_External_Memories @W:CL168 : EMC_External_Memories.v(37) | Pruning instance GND - not in use ... @W:CL168 : EMC_External_Memories.v(36) | Pruning instance VCC - not in use ... @W:CL157 : EMC_MSS_tmp_MSS_CCC_0_MSS_CCC.v(62) | *Output RCOSC_CLKOUT has undriven bits - a simulation mismatch is possible @W:CL157 : EMC_MSS_tmp_MSS_CCC_0_MSS_CCC.v(63) | *Output MAINXIN_CLKOUT has undriven bits - a simulation mismatch is possible @W:CL157 : EMC_MSS_tmp_MSS_CCC_0_MSS_CCC.v(64) | *Output LPXIN_CLKOUT has undriven bits - a simulation mismatch is possible @W:CL159 : EMC_MSS_tmp_MSS_CCC_0_MSS_CCC.v(36) | Input CLKA is unused @W:CL159 : EMC_MSS_tmp_MSS_CCC_0_MSS_CCC.v(37) | Input CLKA_PAD is unused @W:CL159 : EMC_MSS_tmp_MSS_CCC_0_MSS_CCC.v(38) | Input CLKA_PADP is unused @W:CL159 : EMC_MSS_tmp_MSS_CCC_0_MSS_CCC.v(39) | Input CLKA_PADN is unused @W:CL159 : EMC_MSS_tmp_MSS_CCC_0_MSS_CCC.v(40) | Input CLKB is unused @W:CL159 : EMC_MSS_tmp_MSS_CCC_0_MSS_CCC.v(41) | Input CLKB_PAD is unused @W:CL159 : EMC_MSS_tmp_MSS_CCC_0_MSS_CCC.v(42) | Input CLKB_PADP is unused @W:CL159 : EMC_MSS_tmp_MSS_CCC_0_MSS_CCC.v(43) | Input CLKB_PADN is unused @W:CL159 : EMC_MSS_tmp_MSS_CCC_0_MSS_CCC.v(44) | Input CLKC is unused @W:CL159 : EMC_MSS_tmp_MSS_CCC_0_MSS_CCC.v(45) | Input CLKC_PAD is unused @W:CL159 : EMC_MSS_tmp_MSS_CCC_0_MSS_CCC.v(46) | Input CLKC_PADP is unused @W:CL159 : EMC_MSS_tmp_MSS_CCC_0_MSS_CCC.v(47) | Input CLKC_PADN is unused @W:CL159 : EMC_MSS_tmp_MSS_CCC_0_MSS_CCC.v(49) | Input LPXIN is unused @W:CL159 : EMC_MSS_tmp_MSS_CCC_0_MSS_CCC.v(50) | Input MAC_CLK is unused @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Apr 27 16:17:28 2011 ###########################################################] Synopsys Actel Technology Mapper, Version mapact, Build 023R, Built Sep 29 2010 09:29:00 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved Product Version E-2010.09A-1 @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled @W:MO111 : emc_mss_tmp_mss_ccc_0_mss_ccc.v(62) | tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module EMC_MSS_tmp_MSS_CCC_0_MSS_CCC) @W:MO111 : emc_mss_tmp_mss_ccc_0_mss_ccc.v(63) | tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module EMC_MSS_tmp_MSS_CCC_0_MSS_CCC) @W:MO111 : emc_mss_tmp_mss_ccc_0_mss_ccc.v(64) | tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module EMC_MSS_tmp_MSS_CCC_0_MSS_CCC) Available hyper_sources - for debug and ip models None Found @W: : emc_mss_tmp_mss_ccc_0_mss_ccc.v(80) | Net EMC_MSS_0.MSS_ADLIB_INST_FCLK appears to be a clock source which was not identfied. Assuming default frequency. Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB) Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB) Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Writing Analyst data base C:\appnotes\AC348\SmartFusion_Accessing_Ext_Mem_Using_EMC_DF\Hardware\A2F500\Verilog\Accessing_External_Memories\synthesis\EMC_External_Memories.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Writing EDIF Netlist and constraint files E-2010.09A-1 Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) @W:MT246 : emc_mss_tmp_mss_ccc_0_mss_ccc.v(98) | Blackbox MSS_XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock EMC_MSS|MSS_EMI_0_CLK_D_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:EMC_MSS_0.MSS_EMI_0_CLK_D" @W:MT420 : | Found inferred clock EMC_MSS_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:EMC_MSS_0.MSS_ADLIB_INST_FCLK" ##### START OF TIMING REPORT #####[ # Timing Report written on Wed Apr 27 16:17:05 2011 # Top view: EMC_External_Memories Library name: smartfusion Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree ) Requested Frequency: 100.0 MHz Wire load mode: top Wire load model: smartfusion Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: NA Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise -------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack -------------------------------------------------------------------------------------------------------- ======================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Target Part: A2F500M3G_FBGA256_Std Report for cell EMC_External_Memories.verilog Core Cell usage: cell count area count*area GND 3 0.0 0.0 MSS_CCC 1 0.0 0.0 VCC 3 0.0 0.0 MSS_APB 1 0.0 0.0 ----- ---------- TOTAL 8 0.0 IO Cell usage: cell count BIBUF_MSS 16 INBUF_MSS 2 MSS_XTLOSC 1 OUTBUF_MSS 35 ----- TOTAL 54 Core Cells : 0 of 11520 (0%) IO Cells : 54 RAM/ROM Usage Summary Block Rams : 0 of 24 (0%) Mapper successful! Process took 0h:00m:02s realtime, 0h:00m:01s cputime # Wed Apr 27 16:17:05 2011 ###########################################################]