
ext_mem_load_and_boot:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .text         000048cc  20000000  20000000  00008000  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  1 .data         00000118  200048cc  200048cc  0000c8cc  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  2 .bss          00000194  200049e4  200049e4  0000c9e4  2**2
                  ALLOC
  3 .stack        00003000  20004b78  20004b78  0000c9e4  2**0
                  ALLOC
  4 .comment      00000158  00000000  00000000  0000c9e4  2**0
                  CONTENTS, READONLY
  5 .debug_aranges 00000100  00000000  00000000  0000cb3c  2**0
                  CONTENTS, READONLY, DEBUGGING
  6 .debug_pubnames 000007d4  00000000  00000000  0000cc3c  2**0
                  CONTENTS, READONLY, DEBUGGING
  7 .debug_info   00006ce7  00000000  00000000  0000d410  2**0
                  CONTENTS, READONLY, DEBUGGING
  8 .debug_abbrev 00000eb9  00000000  00000000  000140f7  2**0
                  CONTENTS, READONLY, DEBUGGING
  9 .debug_line   00002520  00000000  00000000  00014fb0  2**0
                  CONTENTS, READONLY, DEBUGGING
 10 .debug_frame  00000cac  00000000  00000000  000174d0  2**2
                  CONTENTS, READONLY, DEBUGGING
 11 .debug_str    000028a7  00000000  00000000  0001817c  2**0
                  CONTENTS, READONLY, DEBUGGING
 12 .debug_loc    0000155e  00000000  00000000  0001aa23  2**0
                  CONTENTS, READONLY, DEBUGGING
 13 .debug_macinfo 000329f8  00000000  00000000  0001bf81  2**0
                  CONTENTS, READONLY, DEBUGGING
 14 .ARM.attributes 00000025  00000000  00000000  0004e979  2**0
                  CONTENTS, READONLY

Disassembly of section .text:

20000000 <__text_start>:
20000000:	20010000 	.word	0x20010000
20000004:	20000299 	.word	0x20000299
20000008:	200002fd 	.word	0x200002fd
2000000c:	200002ff 	.word	0x200002ff
20000010:	20000301 	.word	0x20000301
20000014:	20000303 	.word	0x20000303
20000018:	20000305 	.word	0x20000305
	...
2000002c:	20000307 	.word	0x20000307
20000030:	20000309 	.word	0x20000309
20000034:	00000000 	.word	0x00000000
20000038:	2000030b 	.word	0x2000030b
2000003c:	2000030d 	.word	0x2000030d
20000040:	2000030f 	.word	0x2000030f
20000044:	20000311 	.word	0x20000311
20000048:	20000313 	.word	0x20000313
2000004c:	20000315 	.word	0x20000315
20000050:	20000317 	.word	0x20000317
20000054:	20000319 	.word	0x20000319
20000058:	2000031b 	.word	0x2000031b
2000005c:	2000031d 	.word	0x2000031d
20000060:	2000031f 	.word	0x2000031f
20000064:	200043d5 	.word	0x200043d5
20000068:	200028dd 	.word	0x200028dd
2000006c:	20002909 	.word	0x20002909
20000070:	20003c39 	.word	0x20003c39
20000074:	20003c65 	.word	0x20003c65
20000078:	2000032b 	.word	0x2000032b
2000007c:	2000032d 	.word	0x2000032d
20000080:	2000032f 	.word	0x2000032f
20000084:	20000331 	.word	0x20000331
20000088:	20000333 	.word	0x20000333
2000008c:	20000335 	.word	0x20000335
20000090:	20000337 	.word	0x20000337
20000094:	20000339 	.word	0x20000339
20000098:	2000033b 	.word	0x2000033b
2000009c:	2000033d 	.word	0x2000033d
200000a0:	2000033f 	.word	0x2000033f
	...
200000bc:	20000341 	.word	0x20000341
200000c0:	20000343 	.word	0x20000343
200000c4:	20000345 	.word	0x20000345
200000c8:	20000347 	.word	0x20000347
200000cc:	20000349 	.word	0x20000349
200000d0:	2000034b 	.word	0x2000034b
200000d4:	2000034d 	.word	0x2000034d
200000d8:	2000034f 	.word	0x2000034f
200000dc:	20000351 	.word	0x20000351
200000e0:	20000353 	.word	0x20000353
200000e4:	20000355 	.word	0x20000355
200000e8:	20000357 	.word	0x20000357
200000ec:	20000359 	.word	0x20000359
200000f0:	2000035b 	.word	0x2000035b
200000f4:	2000035d 	.word	0x2000035d
200000f8:	2000035f 	.word	0x2000035f
200000fc:	20000361 	.word	0x20000361
20000100:	20000363 	.word	0x20000363
20000104:	20000365 	.word	0x20000365
20000108:	20000367 	.word	0x20000367
2000010c:	20000369 	.word	0x20000369
20000110:	2000036b 	.word	0x2000036b
20000114:	2000036d 	.word	0x2000036d
20000118:	2000036f 	.word	0x2000036f
2000011c:	20000371 	.word	0x20000371
20000120:	20000373 	.word	0x20000373
20000124:	20000375 	.word	0x20000375
20000128:	20000377 	.word	0x20000377
2000012c:	20000379 	.word	0x20000379
20000130:	2000037b 	.word	0x2000037b
20000134:	2000037d 	.word	0x2000037d
20000138:	2000037f 	.word	0x2000037f
2000013c:	20000381 	.word	0x20000381
20000140:	20000383 	.word	0x20000383
20000144:	20000385 	.word	0x20000385
20000148:	20000387 	.word	0x20000387
2000014c:	20000389 	.word	0x20000389
20000150:	2000038b 	.word	0x2000038b
20000154:	2000038d 	.word	0x2000038d
20000158:	2000038f 	.word	0x2000038f
2000015c:	20000391 	.word	0x20000391
20000160:	20000393 	.word	0x20000393
20000164:	20000395 	.word	0x20000395
20000168:	20000397 	.word	0x20000397
2000016c:	20000399 	.word	0x20000399
20000170:	2000039b 	.word	0x2000039b
20000174:	2000039d 	.word	0x2000039d
20000178:	2000039f 	.word	0x2000039f
2000017c:	200003a1 	.word	0x200003a1
20000180:	200003a3 	.word	0x200003a3
20000184:	200003a5 	.word	0x200003a5
20000188:	200003a7 	.word	0x200003a7
2000018c:	200003a9 	.word	0x200003a9
20000190:	200003ab 	.word	0x200003ab
20000194:	200003ad 	.word	0x200003ad
20000198:	200003af 	.word	0x200003af
2000019c:	200003b1 	.word	0x200003b1
200001a0:	200003b3 	.word	0x200003b3
200001a4:	200003b5 	.word	0x200003b5
200001a8:	200003b7 	.word	0x200003b7
200001ac:	200003b9 	.word	0x200003b9
200001b0:	200003bb 	.word	0x200003bb
200001b4:	200003bd 	.word	0x200003bd
200001b8:	200003bf 	.word	0x200003bf
200001bc:	200003c1 	.word	0x200003c1
200001c0:	200003c3 	.word	0x200003c3
200001c4:	200003c5 	.word	0x200003c5
200001c8:	200003c7 	.word	0x200003c7
200001cc:	200003c9 	.word	0x200003c9
200001d0:	200003cb 	.word	0x200003cb
200001d4:	200003cd 	.word	0x200003cd
200001d8:	200003cf 	.word	0x200003cf
200001dc:	200003d1 	.word	0x200003d1
200001e0:	200003d3 	.word	0x200003d3
200001e4:	200003d5 	.word	0x200003d5
200001e8:	200003d7 	.word	0x200003d7
200001ec:	200003d9 	.word	0x200003d9
200001f0:	200003db 	.word	0x200003db
200001f4:	200003dd 	.word	0x200003dd
200001f8:	200003df 	.word	0x200003df
200001fc:	200003e1 	.word	0x200003e1
20000200:	200003e3 	.word	0x200003e3
20000204:	200003e5 	.word	0x200003e5
20000208:	200003e7 	.word	0x200003e7
2000020c:	200003e9 	.word	0x200003e9
20000210:	200003eb 	.word	0x200003eb
20000214:	200003ed 	.word	0x200003ed
20000218:	200003ef 	.word	0x200003ef
2000021c:	200003f1 	.word	0x200003f1
20000220:	200003f3 	.word	0x200003f3
20000224:	200003f5 	.word	0x200003f5
20000228:	200003f7 	.word	0x200003f7
2000022c:	200003f9 	.word	0x200003f9
20000230:	200003fb 	.word	0x200003fb
20000234:	200003fd 	.word	0x200003fd
20000238:	200003ff 	.word	0x200003ff
2000023c:	20000401 	.word	0x20000401
20000240:	20000403 	.word	0x20000403
20000244:	20000405 	.word	0x20000405
20000248:	20000407 	.word	0x20000407
2000024c:	20000409 	.word	0x20000409
20000250:	2000040b 	.word	0x2000040b
20000254:	2000040d 	.word	0x2000040d
20000258:	2000040f 	.word	0x2000040f
2000025c:	20000411 	.word	0x20000411
20000260:	20000413 	.word	0x20000413
20000264:	20000415 	.word	0x20000415
20000268:	20000417 	.word	0x20000417
2000026c:	20000419 	.word	0x20000419
20000270:	2000041b 	.word	0x2000041b
20000274:	2000041d 	.word	0x2000041d
20000278:	2000041f 	.word	0x2000041f
2000027c:	20000421 	.word	0x20000421
20000280:	20000423 	.word	0x20000423
20000284:	20000425 	.word	0x20000425
20000288:	20000427 	.word	0x20000427
2000028c:	20000429 	.word	0x20000429
20000290:	2000042b 	.word	0x2000042b
20000294:	2000042d 	.word	0x2000042d

20000298 <Reset_Handler>:
20000298:	4865      	ldr	r0, [pc, #404]	; (20000430 <ACE_PPE_Flag31_IRQHandler+0x4>)
2000029a:	4780      	blx	r0
2000029c:	4865      	ldr	r0, [pc, #404]	; (20000434 <ACE_PPE_Flag31_IRQHandler+0x8>)
2000029e:	2800      	cmp	r0, #0
200002a0:	d10b      	bne.n	200002ba <copy_data>
200002a2:	4865      	ldr	r0, [pc, #404]	; (20000438 <ACE_PPE_Flag31_IRQHandler+0xc>)
200002a4:	4965      	ldr	r1, [pc, #404]	; (2000043c <ACE_PPE_Flag31_IRQHandler+0x10>)
200002a6:	4a66      	ldr	r2, [pc, #408]	; (20000440 <ACE_PPE_Flag31_IRQHandler+0x14>)
200002a8:	4288      	cmp	r0, r1
200002aa:	d006      	beq.n	200002ba <copy_data>

200002ac <copy_code_loop>:
200002ac:	4291      	cmp	r1, r2
200002ae:	bf1c      	itt	ne
200002b0:	f850 3b04 	ldrne.w	r3, [r0], #4
200002b4:	f841 3b04 	strne.w	r3, [r1], #4
200002b8:	d1f8      	bne.n	200002ac <copy_code_loop>

200002ba <copy_data>:
200002ba:	4862      	ldr	r0, [pc, #392]	; (20000444 <ACE_PPE_Flag31_IRQHandler+0x18>)
200002bc:	4962      	ldr	r1, [pc, #392]	; (20000448 <ACE_PPE_Flag31_IRQHandler+0x1c>)
200002be:	4a63      	ldr	r2, [pc, #396]	; (2000044c <ACE_PPE_Flag31_IRQHandler+0x20>)
200002c0:	4288      	cmp	r0, r1
200002c2:	d006      	beq.n	200002d2 <clear_bss>

200002c4 <copy_data_loop>:
200002c4:	4291      	cmp	r1, r2
200002c6:	bf1c      	itt	ne
200002c8:	f850 3b04 	ldrne.w	r3, [r0], #4
200002cc:	f841 3b04 	strne.w	r3, [r1], #4
200002d0:	d1f8      	bne.n	200002c4 <copy_data_loop>

200002d2 <clear_bss>:
200002d2:	485f      	ldr	r0, [pc, #380]	; (20000450 <ACE_PPE_Flag31_IRQHandler+0x24>)
200002d4:	495f      	ldr	r1, [pc, #380]	; (20000454 <ACE_PPE_Flag31_IRQHandler+0x28>)
200002d6:	4a60      	ldr	r2, [pc, #384]	; (20000458 <ACE_PPE_Flag31_IRQHandler+0x2c>)

200002d8 <clear_bss_loop>:
200002d8:	4291      	cmp	r1, r2
200002da:	bf18      	it	ne
200002dc:	f841 0b04 	strne.w	r0, [r1], #4
200002e0:	d1fa      	bne.n	200002d8 <clear_bss_loop>
	...

200002e4 <call_glob_ctor>:
200002e4:	f8df 0174 	ldr.w	r0, [pc, #372]	; 2000045c <ACE_PPE_Flag31_IRQHandler+0x30>
200002e8:	f20f 0e03 	addw	lr, pc, #3
200002ec:	4700      	bx	r0

200002ee <branch_to_main>:
200002ee:	f04f 0000 	mov.w	r0, #0
200002f2:	f04f 0100 	mov.w	r1, #0
200002f6:	f8df f168 	ldr.w	pc, [pc, #360]	; 20000460 <ACE_PPE_Flag31_IRQHandler+0x34>

200002fa <ExitLoop>:
200002fa:	e7fe      	b.n	200002fa <ExitLoop>

200002fc <NMI_Handler>:
200002fc:	e7fe      	b.n	200002fc <NMI_Handler>

200002fe <HardFault_Handler>:
200002fe:	e7fe      	b.n	200002fe <HardFault_Handler>

20000300 <MemManage_Handler>:
20000300:	e7fe      	b.n	20000300 <MemManage_Handler>

20000302 <BusFault_Handler>:
20000302:	e7fe      	b.n	20000302 <BusFault_Handler>

20000304 <UsageFault_Handler>:
20000304:	e7fe      	b.n	20000304 <UsageFault_Handler>

20000306 <SVC_Handler>:
20000306:	e7fe      	b.n	20000306 <SVC_Handler>

20000308 <DebugMon_Handler>:
20000308:	e7fe      	b.n	20000308 <DebugMon_Handler>

2000030a <PendSV_Handler>:
2000030a:	e7fe      	b.n	2000030a <PendSV_Handler>

2000030c <SysTick_Handler>:
2000030c:	e7fe      	b.n	2000030c <SysTick_Handler>

2000030e <WdogWakeup_IRQHandler>:
2000030e:	e7fe      	b.n	2000030e <WdogWakeup_IRQHandler>

20000310 <BrownOut_1_5V_IRQHandler>:
20000310:	e7fe      	b.n	20000310 <BrownOut_1_5V_IRQHandler>

20000312 <BrownOut_3_3V_IRQHandler>:
20000312:	e7fe      	b.n	20000312 <BrownOut_3_3V_IRQHandler>

20000314 <RTC_Match_IRQHandler>:
20000314:	e7fe      	b.n	20000314 <RTC_Match_IRQHandler>

20000316 <RTCIF_Pub_IRQHandler>:
20000316:	e7fe      	b.n	20000316 <RTCIF_Pub_IRQHandler>

20000318 <EthernetMAC_IRQHandler>:
20000318:	e7fe      	b.n	20000318 <EthernetMAC_IRQHandler>

2000031a <IAP_IRQHandler>:
2000031a:	e7fe      	b.n	2000031a <IAP_IRQHandler>

2000031c <ENVM0_IRQHandler>:
2000031c:	e7fe      	b.n	2000031c <ENVM0_IRQHandler>

2000031e <ENVM1_IRQHandler>:
2000031e:	e7fe      	b.n	2000031e <ENVM1_IRQHandler>
20000320:	e7fe      	b.n	20000320 <ENVM1_IRQHandler+0x2>
20000322:	e7fe      	b.n	20000322 <ENVM1_IRQHandler+0x4>
20000324:	e7fe      	b.n	20000324 <ENVM1_IRQHandler+0x6>
20000326:	e7fe      	b.n	20000326 <ENVM1_IRQHandler+0x8>
20000328:	e7fe      	b.n	20000328 <ENVM1_IRQHandler+0xa>

2000032a <I2C0_IRQHandler>:
2000032a:	e7fe      	b.n	2000032a <I2C0_IRQHandler>

2000032c <I2C0_SMBAlert_IRQHandler>:
2000032c:	e7fe      	b.n	2000032c <I2C0_SMBAlert_IRQHandler>

2000032e <I2C0_SMBus_IRQHandler>:
2000032e:	e7fe      	b.n	2000032e <I2C0_SMBus_IRQHandler>

20000330 <I2C1_IRQHandler>:
20000330:	e7fe      	b.n	20000330 <I2C1_IRQHandler>

20000332 <I2C1_SMBAlert_IRQHandler>:
20000332:	e7fe      	b.n	20000332 <I2C1_SMBAlert_IRQHandler>

20000334 <I2C1_SMBus_IRQHandler>:
20000334:	e7fe      	b.n	20000334 <I2C1_SMBus_IRQHandler>

20000336 <Timer1_IRQHandler>:
20000336:	e7fe      	b.n	20000336 <Timer1_IRQHandler>

20000338 <Timer2_IRQHandler>:
20000338:	e7fe      	b.n	20000338 <Timer2_IRQHandler>

2000033a <PLL_Lock_IRQHandler>:
2000033a:	e7fe      	b.n	2000033a <PLL_Lock_IRQHandler>

2000033c <PLL_LockLost_IRQHandler>:
2000033c:	e7fe      	b.n	2000033c <PLL_LockLost_IRQHandler>

2000033e <CommError_IRQHandler>:
2000033e:	e7fe      	b.n	2000033e <CommError_IRQHandler>

20000340 <Fabric_IRQHandler>:
20000340:	e7fe      	b.n	20000340 <Fabric_IRQHandler>

20000342 <GPIO0_IRQHandler>:
20000342:	e7fe      	b.n	20000342 <GPIO0_IRQHandler>

20000344 <GPIO1_IRQHandler>:
20000344:	e7fe      	b.n	20000344 <GPIO1_IRQHandler>

20000346 <GPIO2_IRQHandler>:
20000346:	e7fe      	b.n	20000346 <GPIO2_IRQHandler>

20000348 <GPIO3_IRQHandler>:
20000348:	e7fe      	b.n	20000348 <GPIO3_IRQHandler>

2000034a <GPIO4_IRQHandler>:
2000034a:	e7fe      	b.n	2000034a <GPIO4_IRQHandler>

2000034c <GPIO5_IRQHandler>:
2000034c:	e7fe      	b.n	2000034c <GPIO5_IRQHandler>

2000034e <GPIO6_IRQHandler>:
2000034e:	e7fe      	b.n	2000034e <GPIO6_IRQHandler>

20000350 <GPIO7_IRQHandler>:
20000350:	e7fe      	b.n	20000350 <GPIO7_IRQHandler>

20000352 <GPIO8_IRQHandler>:
20000352:	e7fe      	b.n	20000352 <GPIO8_IRQHandler>

20000354 <GPIO9_IRQHandler>:
20000354:	e7fe      	b.n	20000354 <GPIO9_IRQHandler>

20000356 <GPIO10_IRQHandler>:
20000356:	e7fe      	b.n	20000356 <GPIO10_IRQHandler>

20000358 <GPIO11_IRQHandler>:
20000358:	e7fe      	b.n	20000358 <GPIO11_IRQHandler>

2000035a <GPIO12_IRQHandler>:
2000035a:	e7fe      	b.n	2000035a <GPIO12_IRQHandler>

2000035c <GPIO13_IRQHandler>:
2000035c:	e7fe      	b.n	2000035c <GPIO13_IRQHandler>

2000035e <GPIO14_IRQHandler>:
2000035e:	e7fe      	b.n	2000035e <GPIO14_IRQHandler>

20000360 <GPIO15_IRQHandler>:
20000360:	e7fe      	b.n	20000360 <GPIO15_IRQHandler>

20000362 <GPIO16_IRQHandler>:
20000362:	e7fe      	b.n	20000362 <GPIO16_IRQHandler>

20000364 <GPIO17_IRQHandler>:
20000364:	e7fe      	b.n	20000364 <GPIO17_IRQHandler>

20000366 <GPIO18_IRQHandler>:
20000366:	e7fe      	b.n	20000366 <GPIO18_IRQHandler>

20000368 <GPIO19_IRQHandler>:
20000368:	e7fe      	b.n	20000368 <GPIO19_IRQHandler>

2000036a <GPIO20_IRQHandler>:
2000036a:	e7fe      	b.n	2000036a <GPIO20_IRQHandler>

2000036c <GPIO21_IRQHandler>:
2000036c:	e7fe      	b.n	2000036c <GPIO21_IRQHandler>

2000036e <GPIO22_IRQHandler>:
2000036e:	e7fe      	b.n	2000036e <GPIO22_IRQHandler>

20000370 <GPIO23_IRQHandler>:
20000370:	e7fe      	b.n	20000370 <GPIO23_IRQHandler>

20000372 <GPIO24_IRQHandler>:
20000372:	e7fe      	b.n	20000372 <GPIO24_IRQHandler>

20000374 <GPIO25_IRQHandler>:
20000374:	e7fe      	b.n	20000374 <GPIO25_IRQHandler>

20000376 <GPIO26_IRQHandler>:
20000376:	e7fe      	b.n	20000376 <GPIO26_IRQHandler>

20000378 <GPIO27_IRQHandler>:
20000378:	e7fe      	b.n	20000378 <GPIO27_IRQHandler>

2000037a <GPIO28_IRQHandler>:
2000037a:	e7fe      	b.n	2000037a <GPIO28_IRQHandler>

2000037c <GPIO29_IRQHandler>:
2000037c:	e7fe      	b.n	2000037c <GPIO29_IRQHandler>

2000037e <GPIO30_IRQHandler>:
2000037e:	e7fe      	b.n	2000037e <GPIO30_IRQHandler>

20000380 <GPIO31_IRQHandler>:
20000380:	e7fe      	b.n	20000380 <GPIO31_IRQHandler>

20000382 <ACE_PC0_Flag0_IRQHandler>:
20000382:	e7fe      	b.n	20000382 <ACE_PC0_Flag0_IRQHandler>

20000384 <ACE_PC0_Flag1_IRQHandler>:
20000384:	e7fe      	b.n	20000384 <ACE_PC0_Flag1_IRQHandler>

20000386 <ACE_PC0_Flag2_IRQHandler>:
20000386:	e7fe      	b.n	20000386 <ACE_PC0_Flag2_IRQHandler>

20000388 <ACE_PC0_Flag3_IRQHandler>:
20000388:	e7fe      	b.n	20000388 <ACE_PC0_Flag3_IRQHandler>

2000038a <ACE_PC1_Flag0_IRQHandler>:
2000038a:	e7fe      	b.n	2000038a <ACE_PC1_Flag0_IRQHandler>

2000038c <ACE_PC1_Flag1_IRQHandler>:
2000038c:	e7fe      	b.n	2000038c <ACE_PC1_Flag1_IRQHandler>

2000038e <ACE_PC1_Flag2_IRQHandler>:
2000038e:	e7fe      	b.n	2000038e <ACE_PC1_Flag2_IRQHandler>

20000390 <ACE_PC1_Flag3_IRQHandler>:
20000390:	e7fe      	b.n	20000390 <ACE_PC1_Flag3_IRQHandler>

20000392 <ACE_PC2_Flag0_IRQHandler>:
20000392:	e7fe      	b.n	20000392 <ACE_PC2_Flag0_IRQHandler>

20000394 <ACE_PC2_Flag1_IRQHandler>:
20000394:	e7fe      	b.n	20000394 <ACE_PC2_Flag1_IRQHandler>

20000396 <ACE_PC2_Flag2_IRQHandler>:
20000396:	e7fe      	b.n	20000396 <ACE_PC2_Flag2_IRQHandler>

20000398 <ACE_PC2_Flag3_IRQHandler>:
20000398:	e7fe      	b.n	20000398 <ACE_PC2_Flag3_IRQHandler>

2000039a <ACE_ADC0_DataValid_IRQHandler>:
2000039a:	e7fe      	b.n	2000039a <ACE_ADC0_DataValid_IRQHandler>

2000039c <ACE_ADC1_DataValid_IRQHandler>:
2000039c:	e7fe      	b.n	2000039c <ACE_ADC1_DataValid_IRQHandler>

2000039e <ACE_ADC2_DataValid_IRQHandler>:
2000039e:	e7fe      	b.n	2000039e <ACE_ADC2_DataValid_IRQHandler>

200003a0 <ACE_ADC0_CalDone_IRQHandler>:
200003a0:	e7fe      	b.n	200003a0 <ACE_ADC0_CalDone_IRQHandler>

200003a2 <ACE_ADC1_CalDone_IRQHandler>:
200003a2:	e7fe      	b.n	200003a2 <ACE_ADC1_CalDone_IRQHandler>

200003a4 <ACE_ADC2_CalDone_IRQHandler>:
200003a4:	e7fe      	b.n	200003a4 <ACE_ADC2_CalDone_IRQHandler>

200003a6 <ACE_ADC0_CalStart_IRQHandler>:
200003a6:	e7fe      	b.n	200003a6 <ACE_ADC0_CalStart_IRQHandler>

200003a8 <ACE_ADC1_CalStart_IRQHandler>:
200003a8:	e7fe      	b.n	200003a8 <ACE_ADC1_CalStart_IRQHandler>

200003aa <ACE_ADC2_CalStart_IRQHandler>:
200003aa:	e7fe      	b.n	200003aa <ACE_ADC2_CalStart_IRQHandler>

200003ac <ACE_Comp0_Fall_IRQHandler>:
200003ac:	e7fe      	b.n	200003ac <ACE_Comp0_Fall_IRQHandler>

200003ae <ACE_Comp1_Fall_IRQHandler>:
200003ae:	e7fe      	b.n	200003ae <ACE_Comp1_Fall_IRQHandler>

200003b0 <ACE_Comp2_Fall_IRQHandler>:
200003b0:	e7fe      	b.n	200003b0 <ACE_Comp2_Fall_IRQHandler>

200003b2 <ACE_Comp3_Fall_IRQHandler>:
200003b2:	e7fe      	b.n	200003b2 <ACE_Comp3_Fall_IRQHandler>

200003b4 <ACE_Comp4_Fall_IRQHandler>:
200003b4:	e7fe      	b.n	200003b4 <ACE_Comp4_Fall_IRQHandler>

200003b6 <ACE_Comp5_Fall_IRQHandler>:
200003b6:	e7fe      	b.n	200003b6 <ACE_Comp5_Fall_IRQHandler>

200003b8 <ACE_Comp6_Fall_IRQHandler>:
200003b8:	e7fe      	b.n	200003b8 <ACE_Comp6_Fall_IRQHandler>

200003ba <ACE_Comp7_Fall_IRQHandler>:
200003ba:	e7fe      	b.n	200003ba <ACE_Comp7_Fall_IRQHandler>

200003bc <ACE_Comp8_Fall_IRQHandler>:
200003bc:	e7fe      	b.n	200003bc <ACE_Comp8_Fall_IRQHandler>

200003be <ACE_Comp9_Fall_IRQHandler>:
200003be:	e7fe      	b.n	200003be <ACE_Comp9_Fall_IRQHandler>

200003c0 <ACE_Comp10_Fall_IRQHandler>:
200003c0:	e7fe      	b.n	200003c0 <ACE_Comp10_Fall_IRQHandler>

200003c2 <ACE_Comp11_Fall_IRQHandler>:
200003c2:	e7fe      	b.n	200003c2 <ACE_Comp11_Fall_IRQHandler>

200003c4 <ACE_Comp0_Rise_IRQHandler>:
200003c4:	e7fe      	b.n	200003c4 <ACE_Comp0_Rise_IRQHandler>

200003c6 <ACE_Comp1_Rise_IRQHandler>:
200003c6:	e7fe      	b.n	200003c6 <ACE_Comp1_Rise_IRQHandler>

200003c8 <ACE_Comp2_Rise_IRQHandler>:
200003c8:	e7fe      	b.n	200003c8 <ACE_Comp2_Rise_IRQHandler>

200003ca <ACE_Comp3_Rise_IRQHandler>:
200003ca:	e7fe      	b.n	200003ca <ACE_Comp3_Rise_IRQHandler>

200003cc <ACE_Comp4_Rise_IRQHandler>:
200003cc:	e7fe      	b.n	200003cc <ACE_Comp4_Rise_IRQHandler>

200003ce <ACE_Comp5_Rise_IRQHandler>:
200003ce:	e7fe      	b.n	200003ce <ACE_Comp5_Rise_IRQHandler>

200003d0 <ACE_Comp6_Rise_IRQHandler>:
200003d0:	e7fe      	b.n	200003d0 <ACE_Comp6_Rise_IRQHandler>

200003d2 <ACE_Comp7_Rise_IRQHandler>:
200003d2:	e7fe      	b.n	200003d2 <ACE_Comp7_Rise_IRQHandler>

200003d4 <ACE_Comp8_Rise_IRQHandler>:
200003d4:	e7fe      	b.n	200003d4 <ACE_Comp8_Rise_IRQHandler>

200003d6 <ACE_Comp9_Rise_IRQHandler>:
200003d6:	e7fe      	b.n	200003d6 <ACE_Comp9_Rise_IRQHandler>

200003d8 <ACE_Comp10_Rise_IRQHandler>:
200003d8:	e7fe      	b.n	200003d8 <ACE_Comp10_Rise_IRQHandler>

200003da <ACE_Comp11_Rise_IRQHandler>:
200003da:	e7fe      	b.n	200003da <ACE_Comp11_Rise_IRQHandler>

200003dc <ACE_ADC0_FifoFull_IRQHandler>:
200003dc:	e7fe      	b.n	200003dc <ACE_ADC0_FifoFull_IRQHandler>

200003de <ACE_ADC0_FifoAFull_IRQHandler>:
200003de:	e7fe      	b.n	200003de <ACE_ADC0_FifoAFull_IRQHandler>

200003e0 <ACE_ADC0_FifoEmpty_IRQHandler>:
200003e0:	e7fe      	b.n	200003e0 <ACE_ADC0_FifoEmpty_IRQHandler>

200003e2 <ACE_ADC1_FifoFull_IRQHandler>:
200003e2:	e7fe      	b.n	200003e2 <ACE_ADC1_FifoFull_IRQHandler>

200003e4 <ACE_ADC1_FifoAFull_IRQHandler>:
200003e4:	e7fe      	b.n	200003e4 <ACE_ADC1_FifoAFull_IRQHandler>

200003e6 <ACE_ADC1_FifoEmpty_IRQHandler>:
200003e6:	e7fe      	b.n	200003e6 <ACE_ADC1_FifoEmpty_IRQHandler>

200003e8 <ACE_ADC2_FifoFull_IRQHandler>:
200003e8:	e7fe      	b.n	200003e8 <ACE_ADC2_FifoFull_IRQHandler>

200003ea <ACE_ADC2_FifoAFull_IRQHandler>:
200003ea:	e7fe      	b.n	200003ea <ACE_ADC2_FifoAFull_IRQHandler>

200003ec <ACE_ADC2_FifoEmpty_IRQHandler>:
200003ec:	e7fe      	b.n	200003ec <ACE_ADC2_FifoEmpty_IRQHandler>

200003ee <ACE_PPE_Flag0_IRQHandler>:
200003ee:	e7fe      	b.n	200003ee <ACE_PPE_Flag0_IRQHandler>

200003f0 <ACE_PPE_Flag1_IRQHandler>:
200003f0:	e7fe      	b.n	200003f0 <ACE_PPE_Flag1_IRQHandler>

200003f2 <ACE_PPE_Flag2_IRQHandler>:
200003f2:	e7fe      	b.n	200003f2 <ACE_PPE_Flag2_IRQHandler>

200003f4 <ACE_PPE_Flag3_IRQHandler>:
200003f4:	e7fe      	b.n	200003f4 <ACE_PPE_Flag3_IRQHandler>

200003f6 <ACE_PPE_Flag4_IRQHandler>:
200003f6:	e7fe      	b.n	200003f6 <ACE_PPE_Flag4_IRQHandler>

200003f8 <ACE_PPE_Flag5_IRQHandler>:
200003f8:	e7fe      	b.n	200003f8 <ACE_PPE_Flag5_IRQHandler>

200003fa <ACE_PPE_Flag6_IRQHandler>:
200003fa:	e7fe      	b.n	200003fa <ACE_PPE_Flag6_IRQHandler>

200003fc <ACE_PPE_Flag7_IRQHandler>:
200003fc:	e7fe      	b.n	200003fc <ACE_PPE_Flag7_IRQHandler>

200003fe <ACE_PPE_Flag8_IRQHandler>:
200003fe:	e7fe      	b.n	200003fe <ACE_PPE_Flag8_IRQHandler>

20000400 <ACE_PPE_Flag9_IRQHandler>:
20000400:	e7fe      	b.n	20000400 <ACE_PPE_Flag9_IRQHandler>

20000402 <ACE_PPE_Flag10_IRQHandler>:
20000402:	e7fe      	b.n	20000402 <ACE_PPE_Flag10_IRQHandler>

20000404 <ACE_PPE_Flag11_IRQHandler>:
20000404:	e7fe      	b.n	20000404 <ACE_PPE_Flag11_IRQHandler>

20000406 <ACE_PPE_Flag12_IRQHandler>:
20000406:	e7fe      	b.n	20000406 <ACE_PPE_Flag12_IRQHandler>

20000408 <ACE_PPE_Flag13_IRQHandler>:
20000408:	e7fe      	b.n	20000408 <ACE_PPE_Flag13_IRQHandler>

2000040a <ACE_PPE_Flag14_IRQHandler>:
2000040a:	e7fe      	b.n	2000040a <ACE_PPE_Flag14_IRQHandler>

2000040c <ACE_PPE_Flag15_IRQHandler>:
2000040c:	e7fe      	b.n	2000040c <ACE_PPE_Flag15_IRQHandler>

2000040e <ACE_PPE_Flag16_IRQHandler>:
2000040e:	e7fe      	b.n	2000040e <ACE_PPE_Flag16_IRQHandler>

20000410 <ACE_PPE_Flag17_IRQHandler>:
20000410:	e7fe      	b.n	20000410 <ACE_PPE_Flag17_IRQHandler>

20000412 <ACE_PPE_Flag18_IRQHandler>:
20000412:	e7fe      	b.n	20000412 <ACE_PPE_Flag18_IRQHandler>

20000414 <ACE_PPE_Flag19_IRQHandler>:
20000414:	e7fe      	b.n	20000414 <ACE_PPE_Flag19_IRQHandler>

20000416 <ACE_PPE_Flag20_IRQHandler>:
20000416:	e7fe      	b.n	20000416 <ACE_PPE_Flag20_IRQHandler>

20000418 <ACE_PPE_Flag21_IRQHandler>:
20000418:	e7fe      	b.n	20000418 <ACE_PPE_Flag21_IRQHandler>

2000041a <ACE_PPE_Flag22_IRQHandler>:
2000041a:	e7fe      	b.n	2000041a <ACE_PPE_Flag22_IRQHandler>

2000041c <ACE_PPE_Flag23_IRQHandler>:
2000041c:	e7fe      	b.n	2000041c <ACE_PPE_Flag23_IRQHandler>

2000041e <ACE_PPE_Flag24_IRQHandler>:
2000041e:	e7fe      	b.n	2000041e <ACE_PPE_Flag24_IRQHandler>

20000420 <ACE_PPE_Flag25_IRQHandler>:
20000420:	e7fe      	b.n	20000420 <ACE_PPE_Flag25_IRQHandler>

20000422 <ACE_PPE_Flag26_IRQHandler>:
20000422:	e7fe      	b.n	20000422 <ACE_PPE_Flag26_IRQHandler>

20000424 <ACE_PPE_Flag27_IRQHandler>:
20000424:	e7fe      	b.n	20000424 <ACE_PPE_Flag27_IRQHandler>

20000426 <ACE_PPE_Flag28_IRQHandler>:
20000426:	e7fe      	b.n	20000426 <ACE_PPE_Flag28_IRQHandler>

20000428 <ACE_PPE_Flag29_IRQHandler>:
20000428:	e7fe      	b.n	20000428 <ACE_PPE_Flag29_IRQHandler>

2000042a <ACE_PPE_Flag30_IRQHandler>:
2000042a:	e7fe      	b.n	2000042a <ACE_PPE_Flag30_IRQHandler>

2000042c <ACE_PPE_Flag31_IRQHandler>:
2000042c:	e7fe      	b.n	2000042c <ACE_PPE_Flag31_IRQHandler>
2000042e:	0000      	.short	0x0000
20000430:	20004579 	.word	0x20004579
20000434:	00000000 	.word	0x00000000
20000438:	20000000 	.word	0x20000000
2000043c:	20000000 	.word	0x20000000
20000440:	200048cc 	.word	0x200048cc
20000444:	200048cc 	.word	0x200048cc
20000448:	200048cc 	.word	0x200048cc
2000044c:	200049e4 	.word	0x200049e4
20000450:	00000000 	.word	0x00000000
20000454:	200049e4 	.word	0x200049e4
20000458:	20004b78 	.word	0x20004b78
2000045c:	200047c9 	.word	0x200047c9
20000460:	20000505 	.word	0x20000505

20000464 <__do_global_dtors_aux>:
20000464:	f644 13e4 	movw	r3, #18916	; 0x49e4
20000468:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000046c:	781a      	ldrb	r2, [r3, #0]
2000046e:	b90a      	cbnz	r2, 20000474 <__do_global_dtors_aux+0x10>
20000470:	2001      	movs	r0, #1
20000472:	7018      	strb	r0, [r3, #0]
20000474:	4770      	bx	lr
20000476:	bf00      	nop

20000478 <frame_dummy>:
20000478:	f644 00cc 	movw	r0, #18636	; 0x48cc
2000047c:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000480:	b508      	push	{r3, lr}
20000482:	6803      	ldr	r3, [r0, #0]
20000484:	b12b      	cbz	r3, 20000492 <frame_dummy+0x1a>
20000486:	f240 0300 	movw	r3, #0
2000048a:	f2c0 0300 	movt	r3, #0
2000048e:	b103      	cbz	r3, 20000492 <frame_dummy+0x1a>
20000490:	4798      	blx	r3
20000492:	bd08      	pop	{r3, pc}

20000494 <MSS_WD_disable>:
 
  @return
    This function does not return a value.
 */
static __INLINE void MSS_WD_disable( void )
{
20000494:	b480      	push	{r7}
20000496:	af00      	add	r7, sp, #0
    WATCHDOG->WDOGENABLE = MSS_WDOG_DISABLE_KEY;
20000498:	f246 0300 	movw	r3, #24576	; 0x6000
2000049c:	f2c4 0300 	movt	r3, #16384	; 0x4000
200004a0:	f245 52fa 	movw	r2, #22010	; 0x55fa
200004a4:	f6c4 426e 	movt	r2, #19566	; 0x4c6e
200004a8:	611a      	str	r2, [r3, #16]
}
200004aa:	46bd      	mov	sp, r7
200004ac:	bc80      	pop	{r7}
200004ae:	4770      	bx	lr

200004b0 <UART_Polled_Rx>:
(
    mss_uart_instance_t * this_uart,
    uint8_t * rx_buff,
    size_t buff_size
)
{
200004b0:	b480      	push	{r7}
200004b2:	b087      	sub	sp, #28
200004b4:	af00      	add	r7, sp, #0
200004b6:	60f8      	str	r0, [r7, #12]
200004b8:	60b9      	str	r1, [r7, #8]
200004ba:	607a      	str	r2, [r7, #4]
    size_t rx_size = 0U;
200004bc:	f04f 0300 	mov.w	r3, #0
200004c0:	617b      	str	r3, [r7, #20]

    while( rx_size < buff_size )
200004c2:	e013      	b.n	200004ec <UART_Polled_Rx+0x3c>
    {
       while ( this_uart->hw_reg_bit->LSR_DR != 0U  )
       {
           rx_buff[rx_size] = this_uart->hw_reg->RBR;
200004c4:	68ba      	ldr	r2, [r7, #8]
200004c6:	697b      	ldr	r3, [r7, #20]
200004c8:	4413      	add	r3, r2
200004ca:	68fa      	ldr	r2, [r7, #12]
200004cc:	6812      	ldr	r2, [r2, #0]
200004ce:	7812      	ldrb	r2, [r2, #0]
200004d0:	b2d2      	uxtb	r2, r2
200004d2:	701a      	strb	r2, [r3, #0]
           ++rx_size;
200004d4:	697b      	ldr	r3, [r7, #20]
200004d6:	f103 0301 	add.w	r3, r3, #1
200004da:	617b      	str	r3, [r7, #20]
200004dc:	e000      	b.n	200004e0 <UART_Polled_Rx+0x30>
{
    size_t rx_size = 0U;

    while( rx_size < buff_size )
    {
       while ( this_uart->hw_reg_bit->LSR_DR != 0U  )
200004de:	bf00      	nop
200004e0:	68fb      	ldr	r3, [r7, #12]
200004e2:	685b      	ldr	r3, [r3, #4]
200004e4:	f8d3 3280 	ldr.w	r3, [r3, #640]	; 0x280
200004e8:	2b00      	cmp	r3, #0
200004ea:	d1eb      	bne.n	200004c4 <UART_Polled_Rx+0x14>
    size_t buff_size
)
{
    size_t rx_size = 0U;

    while( rx_size < buff_size )
200004ec:	697a      	ldr	r2, [r7, #20]
200004ee:	687b      	ldr	r3, [r7, #4]
200004f0:	429a      	cmp	r2, r3
200004f2:	d3f4      	bcc.n	200004de <UART_Polled_Rx+0x2e>
           rx_buff[rx_size] = this_uart->hw_reg->RBR;
           ++rx_size;
       }
    }

    return rx_size;
200004f4:	697b      	ldr	r3, [r7, #20]
}
200004f6:	4618      	mov	r0, r3
200004f8:	f107 071c 	add.w	r7, r7, #28
200004fc:	46bd      	mov	sp, r7
200004fe:	bc80      	pop	{r7}
20000500:	4770      	bx	lr
20000502:	bf00      	nop

20000504 <main>:
 * main function.
 */


int main()
{
20000504:	b580      	push	{r7, lr}
20000506:	b082      	sub	sp, #8
20000508:	af00      	add	r7, sp, #0
    uint8_t rx_buff[1];
    /*--------------------------------------------------------------------------
     * Disable watchdog.
     */

    MSS_WD_disable();
2000050a:	f7ff ffc3 	bl	20000494 <MSS_WD_disable>

    /* Initialize and configure UART0. */
    MSS_UART_init( &g_mss_uart0,
2000050e:	f644 2054 	movw	r0, #19028	; 0x4a54
20000512:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000516:	f44f 4161 	mov.w	r1, #57600	; 0xe100
2000051a:	f04f 0203 	mov.w	r2, #3
2000051e:	f001 fcd1 	bl	20001ec4 <MSS_UART_init>
                  MSS_UART_57600_BAUD,
                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT );

   /* Handshake */

    while(!(UART_Polled_Rx ( &g_mss_uart0, rx_buff, 1 )))
20000522:	f107 0304 	add.w	r3, r7, #4
20000526:	f644 2054 	movw	r0, #19028	; 0x4a54
2000052a:	f2c2 0000 	movt	r0, #8192	; 0x2000
2000052e:	4619      	mov	r1, r3
20000530:	f04f 0201 	mov.w	r2, #1
20000534:	f7ff ffbc 	bl	200004b0 <UART_Polled_Rx>
20000538:	4603      	mov	r3, r0
2000053a:	2b00      	cmp	r3, #0
2000053c:	d0f1      	beq.n	20000522 <main+0x1e>
         ;
    if(rx_buff[0] == 'h')
2000053e:	793b      	ldrb	r3, [r7, #4]
20000540:	2b68      	cmp	r3, #104	; 0x68
20000542:	d10b      	bne.n	2000055c <main+0x58>
        MSS_UART_polled_tx( &g_mss_uart0, (const uint8_t *)"a", 1 );
20000544:	f644 2054 	movw	r0, #19028	; 0x4a54
20000548:	f2c2 0000 	movt	r0, #8192	; 0x2000
2000054c:	f644 0118 	movw	r1, #18456	; 0x4818
20000550:	f2c2 0100 	movt	r1, #8192	; 0x2000
20000554:	f04f 0201 	mov.w	r2, #1
20000558:	f001 fdb0 	bl	200020bc <MSS_UART_polled_tx>

    while(!(UART_Polled_Rx ( &g_mss_uart0, rx_buff, 1 )))
2000055c:	f107 0304 	add.w	r3, r7, #4
20000560:	f644 2054 	movw	r0, #19028	; 0x4a54
20000564:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000568:	4619      	mov	r1, r3
2000056a:	f04f 0201 	mov.w	r2, #1
2000056e:	f7ff ff9f 	bl	200004b0 <UART_Polled_Rx>
20000572:	4603      	mov	r3, r0
20000574:	2b00      	cmp	r3, #0
20000576:	d0f1      	beq.n	2000055c <main+0x58>
         ;

    if(rx_buff[0] == 'n')
20000578:	793b      	ldrb	r3, [r7, #4]
2000057a:	2b6e      	cmp	r3, #110	; 0x6e
2000057c:	d10b      	bne.n	20000596 <main+0x92>
        MSS_UART_polled_tx( &g_mss_uart0, (const uint8_t *)"d", 1 );
2000057e:	f644 2054 	movw	r0, #19028	; 0x4a54
20000582:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000586:	f644 011c 	movw	r1, #18460	; 0x481c
2000058a:	f2c2 0100 	movt	r1, #8192	; 0x2000
2000058e:	f04f 0201 	mov.w	r2, #1
20000592:	f001 fd93 	bl	200020bc <MSS_UART_polled_tx>

    while(!(UART_Polled_Rx ( &g_mss_uart0, rx_buff, 1 )))
20000596:	f107 0304 	add.w	r3, r7, #4
2000059a:	f644 2054 	movw	r0, #19028	; 0x4a54
2000059e:	f2c2 0000 	movt	r0, #8192	; 0x2000
200005a2:	4619      	mov	r1, r3
200005a4:	f04f 0201 	mov.w	r2, #1
200005a8:	f7ff ff82 	bl	200004b0 <UART_Polled_Rx>
200005ac:	4603      	mov	r3, r0
200005ae:	2b00      	cmp	r3, #0
200005b0:	d0f1      	beq.n	20000596 <main+0x92>
         ;

    if(rx_buff[0] == 's')
200005b2:	793b      	ldrb	r3, [r7, #4]
200005b4:	2b73      	cmp	r3, #115	; 0x73
200005b6:	d10b      	bne.n	200005d0 <main+0xcc>
        MSS_UART_polled_tx( &g_mss_uart0, (const uint8_t *)"h", 1 );
200005b8:	f644 2054 	movw	r0, #19028	; 0x4a54
200005bc:	f2c2 0000 	movt	r0, #8192	; 0x2000
200005c0:	f644 0120 	movw	r1, #18464	; 0x4820
200005c4:	f2c2 0100 	movt	r1, #8192	; 0x2000
200005c8:	f04f 0201 	mov.w	r2, #1
200005cc:	f001 fd76 	bl	200020bc <MSS_UART_polled_tx>

    while(!(UART_Polled_Rx ( &g_mss_uart0, rx_buff, 1 )))
200005d0:	f107 0304 	add.w	r3, r7, #4
200005d4:	f644 2054 	movw	r0, #19028	; 0x4a54
200005d8:	f2c2 0000 	movt	r0, #8192	; 0x2000
200005dc:	4619      	mov	r1, r3
200005de:	f04f 0201 	mov.w	r2, #1
200005e2:	f7ff ff65 	bl	200004b0 <UART_Polled_Rx>
200005e6:	4603      	mov	r3, r0
200005e8:	2b00      	cmp	r3, #0
200005ea:	d0f1      	beq.n	200005d0 <main+0xcc>
         ;

    if(rx_buff[0] == 'a')
200005ec:	793b      	ldrb	r3, [r7, #4]
200005ee:	2b61      	cmp	r3, #97	; 0x61
200005f0:	d10b      	bne.n	2000060a <main+0x106>
        MSS_UART_polled_tx( &g_mss_uart0, (const uint8_t *)"k", 1 );
200005f2:	f644 2054 	movw	r0, #19028	; 0x4a54
200005f6:	f2c2 0000 	movt	r0, #8192	; 0x2000
200005fa:	f644 0124 	movw	r1, #18468	; 0x4824
200005fe:	f2c2 0100 	movt	r1, #8192	; 0x2000
20000602:	f04f 0201 	mov.w	r2, #1
20000606:	f001 fd59 	bl	200020bc <MSS_UART_polled_tx>

    while(!(UART_Polled_Rx ( &g_mss_uart0, rx_buff, 1 )))
2000060a:	f107 0304 	add.w	r3, r7, #4
2000060e:	f644 2054 	movw	r0, #19028	; 0x4a54
20000612:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000616:	4619      	mov	r1, r3
20000618:	f04f 0201 	mov.w	r2, #1
2000061c:	f7ff ff48 	bl	200004b0 <UART_Polled_Rx>
20000620:	4603      	mov	r3, r0
20000622:	2b00      	cmp	r3, #0
20000624:	d0f1      	beq.n	2000060a <main+0x106>
         ;

    if(rx_buff[0] == 'e')
20000626:	793b      	ldrb	r3, [r7, #4]
20000628:	2b65      	cmp	r3, #101	; 0x65
2000062a:	d11a      	bne.n	20000662 <main+0x15e>
    {


/* EMC or SPI Flash*/
        while( ! UART_Polled_Rx(&g_mss_uart0, rx_buff, 1))
2000062c:	f107 0304 	add.w	r3, r7, #4
20000630:	f644 2054 	movw	r0, #19028	; 0x4a54
20000634:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000638:	4619      	mov	r1, r3
2000063a:	f04f 0201 	mov.w	r2, #1
2000063e:	f7ff ff37 	bl	200004b0 <UART_Polled_Rx>
20000642:	4603      	mov	r3, r0
20000644:	2b00      	cmp	r3, #0
20000646:	d0f1      	beq.n	2000062c <main+0x128>
             ;
        if(rx_buff[0] == 's')
20000648:	793b      	ldrb	r3, [r7, #4]
2000064a:	2b73      	cmp	r3, #115	; 0x73
2000064c:	d102      	bne.n	20000654 <main+0x150>
        {
            spi_flash_loader();
2000064e:	f000 f927 	bl	200008a0 <spi_flash_loader>
20000652:	e006      	b.n	20000662 <main+0x15e>
        }
        else if(rx_buff[0] == 'e')
20000654:	793b      	ldrb	r3, [r7, #4]
20000656:	2b65      	cmp	r3, #101	; 0x65
20000658:	d103      	bne.n	20000662 <main+0x15e>
        {
           emc_flash_loader();
2000065a:	f000 f809 	bl	20000670 <emc_flash_loader>
#ifdef BOOT_EMC_FLASH_IMAGE
           emc_flash_boot();
2000065e:	f000 f8e7 	bl	20000830 <emc_flash_boot>
#endif
        }

    }
    return 0;
20000662:	f04f 0300 	mov.w	r3, #0
}
20000666:	4618      	mov	r0, r3
20000668:	f107 0708 	add.w	r7, r7, #8
2000066c:	46bd      	mov	sp, r7
2000066e:	bd80      	pop	{r7, pc}

20000670 <emc_flash_loader>:



static void emc_flash_loader(void)
{
20000670:	b580      	push	{r7, lr}
20000672:	f5ad 6d83 	sub.w	sp, sp, #1048	; 0x418
20000676:	af00      	add	r7, sp, #0
    uint32_t  address;
    int32_t img_size,ii,length;


    /* Read the file and burn into external flash */
    while( ! UART_Polled_Rx(&g_mss_uart0, (uint8_t *)&img_size, 4))
20000678:	f107 0308 	add.w	r3, r7, #8
2000067c:	f1a3 0304 	sub.w	r3, r3, #4
20000680:	f644 2054 	movw	r0, #19028	; 0x4a54
20000684:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000688:	4619      	mov	r1, r3
2000068a:	f04f 0204 	mov.w	r2, #4
2000068e:	f7ff ff0f 	bl	200004b0 <UART_Polled_Rx>
20000692:	4603      	mov	r3, r0
20000694:	2b00      	cmp	r3, #0
20000696:	d0ef      	beq.n	20000678 <emc_flash_loader+0x8>
           ;

    emc_init();
20000698:	f000 ffec 	bl	20001674 <emc_init>

    emc_flash_chip_erase(EXT_FLASH_BASE_ADDR);
2000069c:	f04f 40e8 	mov.w	r0, #1946157056	; 0x74000000
200006a0:	f001 f8d4 	bl	2000184c <emc_flash_chip_erase>

    MSS_UART_polled_tx( &g_mss_uart0,(const uint8_t *)&img_size, 4 );
200006a4:	f107 0308 	add.w	r3, r7, #8
200006a8:	f1a3 0304 	sub.w	r3, r3, #4
200006ac:	f644 2054 	movw	r0, #19028	; 0x4a54
200006b0:	f2c2 0000 	movt	r0, #8192	; 0x2000
200006b4:	4619      	mov	r1, r3
200006b6:	f04f 0204 	mov.w	r2, #4
200006ba:	f001 fcff 	bl	200020bc <MSS_UART_polled_tx>

    /* Read the file and burn into external flash */
    while( ! UART_Polled_Rx(&g_mss_uart0, (uint8_t *)&address, 4))
200006be:	f107 0308 	add.w	r3, r7, #8
200006c2:	f644 2054 	movw	r0, #19028	; 0x4a54
200006c6:	f2c2 0000 	movt	r0, #8192	; 0x2000
200006ca:	4619      	mov	r1, r3
200006cc:	f04f 0204 	mov.w	r2, #4
200006d0:	f7ff feee 	bl	200004b0 <UART_Polled_Rx>
200006d4:	4603      	mov	r3, r0
200006d6:	2b00      	cmp	r3, #0
200006d8:	d0f1      	beq.n	200006be <emc_flash_loader+0x4e>
        ;

    MSS_UART_polled_tx( &g_mss_uart0,(const uint8_t *)&address, 4 );
200006da:	f107 0308 	add.w	r3, r7, #8
200006de:	f644 2054 	movw	r0, #19028	; 0x4a54
200006e2:	f2c2 0000 	movt	r0, #8192	; 0x2000
200006e6:	4619      	mov	r1, r3
200006e8:	f04f 0204 	mov.w	r2, #4
200006ec:	f001 fce6 	bl	200020bc <MSS_UART_polled_tx>

    ii = 0;
200006f0:	f04f 0300 	mov.w	r3, #0
200006f4:	f8c7 3410 	str.w	r3, [r7, #1040]	; 0x410
    while(img_size > 0)
200006f8:	e07c      	b.n	200007f4 <emc_flash_loader+0x184>
    {
        rx_size =0;
200006fa:	f04f 0300 	mov.w	r3, #0
200006fe:	f8c7 340c 	str.w	r3, [r7, #1036]	; 0x40c
        if (img_size >= 1024)
20000702:	f107 0308 	add.w	r3, r7, #8
20000706:	f1a3 0304 	sub.w	r3, r3, #4
2000070a:	681a      	ldr	r2, [r3, #0]
2000070c:	f240 33ff 	movw	r3, #1023	; 0x3ff
20000710:	429a      	cmp	r2, r3
20000712:	dd04      	ble.n	2000071e <emc_flash_loader+0xae>
        {
            length = 1024;
20000714:	f44f 6380 	mov.w	r3, #1024	; 0x400
20000718:	f8c7 3414 	str.w	r3, [r7, #1044]	; 0x414
2000071c:	e006      	b.n	2000072c <emc_flash_loader+0xbc>
        }
        else
        {
            length = img_size;
2000071e:	f107 0308 	add.w	r3, r7, #8
20000722:	f1a3 0304 	sub.w	r3, r3, #4
20000726:	681b      	ldr	r3, [r3, #0]
20000728:	f8c7 3414 	str.w	r3, [r7, #1044]	; 0x414
        }

        do
        {
            rx_size = UART_Polled_Rx(&g_mss_uart0, (uint8_t *)&img_buffer, length);
2000072c:	f8d7 2414 	ldr.w	r2, [r7, #1044]	; 0x414
20000730:	f107 0318 	add.w	r3, r7, #24
20000734:	f1a3 030c 	sub.w	r3, r3, #12
20000738:	f644 2054 	movw	r0, #19028	; 0x4a54
2000073c:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000740:	4619      	mov	r1, r3
20000742:	f7ff feb5 	bl	200004b0 <UART_Polled_Rx>
20000746:	4603      	mov	r3, r0
20000748:	f8c7 340c 	str.w	r3, [r7, #1036]	; 0x40c
        }
        while(!rx_size);
2000074c:	f8d7 340c 	ldr.w	r3, [r7, #1036]	; 0x40c
20000750:	2b00      	cmp	r3, #0
20000752:	d0eb      	beq.n	2000072c <emc_flash_loader+0xbc>

        if(rx_size != length)
20000754:	f8d7 2414 	ldr.w	r2, [r7, #1044]	; 0x414
20000758:	f8d7 340c 	ldr.w	r3, [r7, #1036]	; 0x40c
2000075c:	429a      	cmp	r2, r3
2000075e:	d15f      	bne.n	20000820 <emc_flash_loader+0x1b0>
        {
            return;
        }
        img_size -= length;
20000760:	f107 0308 	add.w	r3, r7, #8
20000764:	f1a3 0304 	sub.w	r3, r3, #4
20000768:	681a      	ldr	r2, [r3, #0]
2000076a:	f8d7 3414 	ldr.w	r3, [r7, #1044]	; 0x414
2000076e:	ebc3 0202 	rsb	r2, r3, r2
20000772:	f107 0308 	add.w	r3, r7, #8
20000776:	f1a3 0304 	sub.w	r3, r3, #4
2000077a:	601a      	str	r2, [r3, #0]
        /* alligning to 32 bit */
        if (length%4)
2000077c:	f8d7 3414 	ldr.w	r3, [r7, #1044]	; 0x414
20000780:	f003 0303 	and.w	r3, r3, #3
20000784:	2b00      	cmp	r3, #0
20000786:	d011      	beq.n	200007ac <emc_flash_loader+0x13c>
            length += (4-(length%4));
20000788:	f8d7 2414 	ldr.w	r2, [r7, #1044]	; 0x414
2000078c:	ea4f 73e2 	mov.w	r3, r2, asr #31
20000790:	ea4f 7393 	mov.w	r3, r3, lsr #30
20000794:	441a      	add	r2, r3
20000796:	f002 0203 	and.w	r2, r2, #3
2000079a:	ebc3 0302 	rsb	r3, r3, r2
2000079e:	f1c3 0304 	rsb	r3, r3, #4
200007a2:	f8d7 2414 	ldr.w	r2, [r7, #1044]	; 0x414
200007a6:	4413      	add	r3, r2
200007a8:	f8c7 3414 	str.w	r3, [r7, #1044]	; 0x414

        emc_flash_write(address + ii, img_buffer, length);
200007ac:	f107 0308 	add.w	r3, r7, #8
200007b0:	681a      	ldr	r2, [r3, #0]
200007b2:	f8d7 3410 	ldr.w	r3, [r7, #1040]	; 0x410
200007b6:	eb02 0103 	add.w	r1, r2, r3
200007ba:	f8d7 2414 	ldr.w	r2, [r7, #1044]	; 0x414
200007be:	f107 0318 	add.w	r3, r7, #24
200007c2:	f1a3 030c 	sub.w	r3, r3, #12
200007c6:	4608      	mov	r0, r1
200007c8:	4619      	mov	r1, r3
200007ca:	f001 f86f 	bl	200018ac <emc_flash_write>

        ii += length;
200007ce:	f8d7 2410 	ldr.w	r2, [r7, #1040]	; 0x410
200007d2:	f8d7 3414 	ldr.w	r3, [r7, #1044]	; 0x414
200007d6:	4413      	add	r3, r2
200007d8:	f8c7 3410 	str.w	r3, [r7, #1040]	; 0x410

        MSS_UART_polled_tx(&g_mss_uart0,(const uint8_t *)"a",1);
200007dc:	f644 2054 	movw	r0, #19028	; 0x4a54
200007e0:	f2c2 0000 	movt	r0, #8192	; 0x2000
200007e4:	f644 0118 	movw	r1, #18456	; 0x4818
200007e8:	f2c2 0100 	movt	r1, #8192	; 0x2000
200007ec:	f04f 0201 	mov.w	r2, #1
200007f0:	f001 fc64 	bl	200020bc <MSS_UART_polled_tx>
        ;

    MSS_UART_polled_tx( &g_mss_uart0,(const uint8_t *)&address, 4 );

    ii = 0;
    while(img_size > 0)
200007f4:	f107 0308 	add.w	r3, r7, #8
200007f8:	f1a3 0304 	sub.w	r3, r3, #4
200007fc:	681b      	ldr	r3, [r3, #0]
200007fe:	2b00      	cmp	r3, #0
20000800:	f73f af7b 	bgt.w	200006fa <emc_flash_loader+0x8a>
        ii += length;

        MSS_UART_polled_tx(&g_mss_uart0,(const uint8_t *)"a",1);

    }
    MSS_UART_polled_tx(&g_mss_uart0,(const uint8_t *)"y",1);
20000804:	f644 2054 	movw	r0, #19028	; 0x4a54
20000808:	f2c2 0000 	movt	r0, #8192	; 0x2000
2000080c:	f644 0128 	movw	r1, #18472	; 0x4828
20000810:	f2c2 0100 	movt	r1, #8192	; 0x2000
20000814:	f04f 0201 	mov.w	r2, #1
20000818:	f001 fc50 	bl	200020bc <MSS_UART_polled_tx>
    return;
2000081c:	bf00      	nop
2000081e:	e000      	b.n	20000822 <emc_flash_loader+0x1b2>
        }
        while(!rx_size);

        if(rx_size != length)
        {
            return;
20000820:	bf00      	nop
        MSS_UART_polled_tx(&g_mss_uart0,(const uint8_t *)"a",1);

    }
    MSS_UART_polled_tx(&g_mss_uart0,(const uint8_t *)"y",1);
    return;
}
20000822:	f107 0718 	add.w	r7, r7, #24
20000826:	f507 6780 	add.w	r7, r7, #1024	; 0x400
2000082a:	46bd      	mov	sp, r7
2000082c:	bd80      	pop	{r7, pc}
2000082e:	bf00      	nop

20000830 <emc_flash_boot>:

#ifdef BOOT_EMC_FLASH_IMAGE
static void   emc_flash_boot(void)
{
20000830:	b480      	push	{r7}
20000832:	b085      	sub	sp, #20
20000834:	af00      	add	r7, sp, #0
    unsigned int ii=0;
20000836:	f04f 0300 	mov.w	r3, #0
2000083a:	607b      	str	r3, [r7, #4]
    unsigned long *srcAddr = (unsigned long *)EXT_FLASH_BASE_ADDR;
2000083c:	f04f 43e8 	mov.w	r3, #1946157056	; 0x74000000
20000840:	60bb      	str	r3, [r7, #8]
    unsigned long *destAddr = (unsigned long *)ESRAM_BASE_ADDR;
20000842:	f04f 5300 	mov.w	r3, #536870912	; 0x20000000
20000846:	60fb      	str	r3, [r7, #12]

    *(volatile unsigned long *)0xE000ED08 = ESRAM_BASE_ADDR;
20000848:	f64e 5308 	movw	r3, #60680	; 0xed08
2000084c:	f2ce 0300 	movt	r3, #57344	; 0xe000
20000850:	f04f 5200 	mov.w	r2, #536870912	; 0x20000000
20000854:	601a      	str	r2, [r3, #0]

    for (ii=0; ii<166; ii++ )
20000856:	f04f 0300 	mov.w	r3, #0
2000085a:	607b      	str	r3, [r7, #4]
2000085c:	e00f      	b.n	2000087e <emc_flash_boot+0x4e>
    {
        *destAddr++ = *srcAddr++;
2000085e:	68bb      	ldr	r3, [r7, #8]
20000860:	681a      	ldr	r2, [r3, #0]
20000862:	68fb      	ldr	r3, [r7, #12]
20000864:	601a      	str	r2, [r3, #0]
20000866:	68fb      	ldr	r3, [r7, #12]
20000868:	f103 0304 	add.w	r3, r3, #4
2000086c:	60fb      	str	r3, [r7, #12]
2000086e:	68bb      	ldr	r3, [r7, #8]
20000870:	f103 0304 	add.w	r3, r3, #4
20000874:	60bb      	str	r3, [r7, #8]
    unsigned long *srcAddr = (unsigned long *)EXT_FLASH_BASE_ADDR;
    unsigned long *destAddr = (unsigned long *)ESRAM_BASE_ADDR;

    *(volatile unsigned long *)0xE000ED08 = ESRAM_BASE_ADDR;

    for (ii=0; ii<166; ii++ )
20000876:	687b      	ldr	r3, [r7, #4]
20000878:	f103 0301 	add.w	r3, r3, #1
2000087c:	607b      	str	r3, [r7, #4]
2000087e:	687b      	ldr	r3, [r7, #4]
20000880:	2ba5      	cmp	r3, #165	; 0xa5
20000882:	d9ec      	bls.n	2000085e <emc_flash_boot+0x2e>
    {
        *destAddr++ = *srcAddr++;
    }


    __asm volatile(
20000884:	f8df 240c 	ldr.w	r2, [pc, #1036]	; 20000c94 <spi_flash_to_esram+0x164>
20000888:	6810      	ldr	r0, [r2, #0]
2000088a:	f8d2 e004 	ldr.w	lr, [r2, #4]
2000088e:	f380 8808 	msr	MSP, r0
20000892:	4770      	bx	lr
           "ldr lr,[r2,#0x4]      \n"  /* Step 4. */
           "msr msp,r0            \n"  /* Step 5. */
           "bx lr                 \n"  /* Step 6. */
   );

}
20000894:	f107 0714 	add.w	r7, r7, #20
20000898:	46bd      	mov	sp, r7
2000089a:	bc80      	pop	{r7}
2000089c:	4770      	bx	lr
2000089e:	bf00      	nop

200008a0 <spi_flash_loader>:
#endif

static void spi_flash_loader(void)
{
200008a0:	b580      	push	{r7, lr}
200008a2:	f5ad 6d02 	sub.w	sp, sp, #2080	; 0x820
200008a6:	b082      	sub	sp, #8
200008a8:	af00      	add	r7, sp, #0
    uint8_t img_buffer[1024];
    uint32_t  address, oriAddress;
    int32_t img_size,ii,length, oriSize;

    /* Read the file and burn into external flash */
    while( ! UART_Polled_Rx(&g_mss_uart0, (uint8_t *)&img_size, 4))
200008aa:	f507 6383 	add.w	r3, r7, #1048	; 0x418
200008ae:	f1a3 030c 	sub.w	r3, r3, #12
200008b2:	f644 2054 	movw	r0, #19028	; 0x4a54
200008b6:	f2c2 0000 	movt	r0, #8192	; 0x2000
200008ba:	4619      	mov	r1, r3
200008bc:	f04f 0204 	mov.w	r2, #4
200008c0:	f7ff fdf6 	bl	200004b0 <UART_Polled_Rx>
200008c4:	4603      	mov	r3, r0
200008c6:	2b00      	cmp	r3, #0
200008c8:	d0ef      	beq.n	200008aa <spi_flash_loader+0xa>
         ;

    spi_flash_init();
200008ca:	f000 f9e5 	bl	20000c98 <spi_flash_init>
    spi_flash_control_hw(SPI_FLASH_GLOBAL_UNPROTECT,0,NULL);
200008ce:	f04f 0002 	mov.w	r0, #2
200008d2:	f04f 0100 	mov.w	r1, #0
200008d6:	f04f 0200 	mov.w	r2, #0
200008da:	f000 fa07 	bl	20000cec <spi_flash_control_hw>
    spi_flash_control_hw(SPI_FLASH_CHIP_ERASE,0,NULL);
200008de:	f04f 0008 	mov.w	r0, #8
200008e2:	f04f 0100 	mov.w	r1, #0
200008e6:	f04f 0200 	mov.w	r2, #0
200008ea:	f000 f9ff 	bl	20000cec <spi_flash_control_hw>

    MSS_UART_polled_tx( &g_mss_uart0,(const uint8_t *)&img_size, 4 );
200008ee:	f507 6383 	add.w	r3, r7, #1048	; 0x418
200008f2:	f1a3 030c 	sub.w	r3, r3, #12
200008f6:	f644 2054 	movw	r0, #19028	; 0x4a54
200008fa:	f2c2 0000 	movt	r0, #8192	; 0x2000
200008fe:	4619      	mov	r1, r3
20000900:	f04f 0204 	mov.w	r2, #4
20000904:	f001 fbda 	bl	200020bc <MSS_UART_polled_tx>

    oriSize = img_size;
20000908:	f507 6383 	add.w	r3, r7, #1048	; 0x418
2000090c:	f1a3 030c 	sub.w	r3, r3, #12
20000910:	681b      	ldr	r3, [r3, #0]
20000912:	f8c7 3824 	str.w	r3, [r7, #2084]	; 0x824

    /* Read the file and burn into external flash */
    while( ! UART_Polled_Rx(&g_mss_uart0, (uint8_t *)&address, 4))
20000916:	f507 6382 	add.w	r3, r7, #1040	; 0x410
2000091a:	f644 2054 	movw	r0, #19028	; 0x4a54
2000091e:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000922:	4619      	mov	r1, r3
20000924:	f04f 0204 	mov.w	r2, #4
20000928:	f7ff fdc2 	bl	200004b0 <UART_Polled_Rx>
2000092c:	4603      	mov	r3, r0
2000092e:	2b00      	cmp	r3, #0
20000930:	d0f1      	beq.n	20000916 <spi_flash_loader+0x76>
        ;

    MSS_UART_polled_tx( &g_mss_uart0,(const uint8_t *)&address, 4 );
20000932:	f507 6382 	add.w	r3, r7, #1040	; 0x410
20000936:	f644 2054 	movw	r0, #19028	; 0x4a54
2000093a:	f2c2 0000 	movt	r0, #8192	; 0x2000
2000093e:	4619      	mov	r1, r3
20000940:	f04f 0204 	mov.w	r2, #4
20000944:	f001 fbba 	bl	200020bc <MSS_UART_polled_tx>
    oriAddress = address;
20000948:	f507 6382 	add.w	r3, r7, #1040	; 0x410
2000094c:	681b      	ldr	r3, [r3, #0]
2000094e:	f8c7 3818 	str.w	r3, [r7, #2072]	; 0x818
    ii = 0;
20000952:	f04f 0300 	mov.w	r3, #0
20000956:	f8c7 381c 	str.w	r3, [r7, #2076]	; 0x81c
    while(img_size > 0)
2000095a:	e07d      	b.n	20000a58 <spi_flash_loader+0x1b8>
    {
        rx_size =0;
2000095c:	f04f 0300 	mov.w	r3, #0
20000960:	f8c7 3814 	str.w	r3, [r7, #2068]	; 0x814
        if (img_size >=1024)
20000964:	f507 6383 	add.w	r3, r7, #1048	; 0x418
20000968:	f1a3 030c 	sub.w	r3, r3, #12
2000096c:	681a      	ldr	r2, [r3, #0]
2000096e:	f240 33ff 	movw	r3, #1023	; 0x3ff
20000972:	429a      	cmp	r2, r3
20000974:	dd04      	ble.n	20000980 <spi_flash_loader+0xe0>
        {
            length = 1024;
20000976:	f44f 6380 	mov.w	r3, #1024	; 0x400
2000097a:	f8c7 3820 	str.w	r3, [r7, #2080]	; 0x820
2000097e:	e006      	b.n	2000098e <spi_flash_loader+0xee>
        }
        else
        {
            length = img_size;
20000980:	f507 6383 	add.w	r3, r7, #1048	; 0x418
20000984:	f1a3 030c 	sub.w	r3, r3, #12
20000988:	681b      	ldr	r3, [r3, #0]
2000098a:	f8c7 3820 	str.w	r3, [r7, #2080]	; 0x820
        }

        do
        {
            rx_size = UART_Polled_Rx(&g_mss_uart0, (uint8_t *)&img_buffer, length);
2000098e:	f8d7 2820 	ldr.w	r2, [r7, #2080]	; 0x820
20000992:	f507 6383 	add.w	r3, r7, #1048	; 0x418
20000996:	f1a3 0304 	sub.w	r3, r3, #4
2000099a:	f644 2054 	movw	r0, #19028	; 0x4a54
2000099e:	f2c2 0000 	movt	r0, #8192	; 0x2000
200009a2:	4619      	mov	r1, r3
200009a4:	f7ff fd84 	bl	200004b0 <UART_Polled_Rx>
200009a8:	4603      	mov	r3, r0
200009aa:	f8c7 3814 	str.w	r3, [r7, #2068]	; 0x814
        }
        while(!rx_size);
200009ae:	f8d7 3814 	ldr.w	r3, [r7, #2068]	; 0x814
200009b2:	2b00      	cmp	r3, #0
200009b4:	d0eb      	beq.n	2000098e <spi_flash_loader+0xee>

        if(rx_size != length)
200009b6:	f8d7 2820 	ldr.w	r2, [r7, #2080]	; 0x820
200009ba:	f8d7 3814 	ldr.w	r3, [r7, #2068]	; 0x814
200009be:	429a      	cmp	r2, r3
200009c0:	f040 80ae 	bne.w	20000b20 <spi_flash_loader+0x280>
        {
            return;
        }
        img_size -= length;
200009c4:	f507 6383 	add.w	r3, r7, #1048	; 0x418
200009c8:	f1a3 030c 	sub.w	r3, r3, #12
200009cc:	681a      	ldr	r2, [r3, #0]
200009ce:	f8d7 3820 	ldr.w	r3, [r7, #2080]	; 0x820
200009d2:	ebc3 0202 	rsb	r2, r3, r2
200009d6:	f507 6383 	add.w	r3, r7, #1048	; 0x418
200009da:	f1a3 030c 	sub.w	r3, r3, #12
200009de:	601a      	str	r2, [r3, #0]
          /* alligning to 32 bit */
        if ((length%4) != 0)
200009e0:	f8d7 3820 	ldr.w	r3, [r7, #2080]	; 0x820
200009e4:	f003 0303 	and.w	r3, r3, #3
200009e8:	2b00      	cmp	r3, #0
200009ea:	d011      	beq.n	20000a10 <spi_flash_loader+0x170>
        {
            length += (4-(length%4));
200009ec:	f8d7 2820 	ldr.w	r2, [r7, #2080]	; 0x820
200009f0:	ea4f 73e2 	mov.w	r3, r2, asr #31
200009f4:	ea4f 7393 	mov.w	r3, r3, lsr #30
200009f8:	441a      	add	r2, r3
200009fa:	f002 0203 	and.w	r2, r2, #3
200009fe:	ebc3 0302 	rsb	r3, r3, r2
20000a02:	f1c3 0304 	rsb	r3, r3, #4
20000a06:	f8d7 2820 	ldr.w	r2, [r7, #2080]	; 0x820
20000a0a:	4413      	add	r3, r2
20000a0c:	f8c7 3820 	str.w	r3, [r7, #2080]	; 0x820
        }
        spi_flash_write(address + ii, img_buffer, length);
20000a10:	f507 6382 	add.w	r3, r7, #1040	; 0x410
20000a14:	681a      	ldr	r2, [r3, #0]
20000a16:	f8d7 381c 	ldr.w	r3, [r7, #2076]	; 0x81c
20000a1a:	eb02 0103 	add.w	r1, r2, r3
20000a1e:	f8d7 2820 	ldr.w	r2, [r7, #2080]	; 0x820
20000a22:	f507 6383 	add.w	r3, r7, #1048	; 0x418
20000a26:	f1a3 0304 	sub.w	r3, r3, #4
20000a2a:	4608      	mov	r0, r1
20000a2c:	4619      	mov	r1, r3
20000a2e:	f000 fd07 	bl	20001440 <spi_flash_write>

        ii += length;
20000a32:	f8d7 281c 	ldr.w	r2, [r7, #2076]	; 0x81c
20000a36:	f8d7 3820 	ldr.w	r3, [r7, #2080]	; 0x820
20000a3a:	4413      	add	r3, r2
20000a3c:	f8c7 381c 	str.w	r3, [r7, #2076]	; 0x81c

        MSS_UART_polled_tx(&g_mss_uart0,(const uint8_t *)"a",1);
20000a40:	f644 2054 	movw	r0, #19028	; 0x4a54
20000a44:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000a48:	f644 0118 	movw	r1, #18456	; 0x4818
20000a4c:	f2c2 0100 	movt	r1, #8192	; 0x2000
20000a50:	f04f 0201 	mov.w	r2, #1
20000a54:	f001 fb32 	bl	200020bc <MSS_UART_polled_tx>
        ;

    MSS_UART_polled_tx( &g_mss_uart0,(const uint8_t *)&address, 4 );
    oriAddress = address;
    ii = 0;
    while(img_size > 0)
20000a58:	f507 6383 	add.w	r3, r7, #1048	; 0x418
20000a5c:	f1a3 030c 	sub.w	r3, r3, #12
20000a60:	681b      	ldr	r3, [r3, #0]
20000a62:	2b00      	cmp	r3, #0
20000a64:	f73f af7a 	bgt.w	2000095c <spi_flash_loader+0xbc>

    }
           /* Verify the last bytes */
    {
        uint8_t img_buffer2[1030];
        ii -= length;
20000a68:	f8d7 281c 	ldr.w	r2, [r7, #2076]	; 0x81c
20000a6c:	f8d7 3820 	ldr.w	r3, [r7, #2080]	; 0x820
20000a70:	ebc3 0302 	rsb	r3, r3, r2
20000a74:	f8c7 381c 	str.w	r3, [r7, #2076]	; 0x81c
        spi_flash_read(address + ii, img_buffer2, length);
20000a78:	f507 6382 	add.w	r3, r7, #1040	; 0x410
20000a7c:	681a      	ldr	r2, [r3, #0]
20000a7e:	f8d7 381c 	ldr.w	r3, [r7, #2076]	; 0x81c
20000a82:	eb02 0103 	add.w	r1, r2, r3
20000a86:	f8d7 2820 	ldr.w	r2, [r7, #2080]	; 0x820
20000a8a:	f107 0308 	add.w	r3, r7, #8
20000a8e:	f1a3 0304 	sub.w	r3, r3, #4
20000a92:	4608      	mov	r0, r1
20000a94:	4619      	mov	r1, r3
20000a96:	f000 fc51 	bl	2000133c <spi_flash_read>
        for(ii=0; ii<length; ii++)
20000a9a:	f04f 0300 	mov.w	r3, #0
20000a9e:	f8c7 381c 	str.w	r3, [r7, #2076]	; 0x81c
20000aa2:	e022      	b.n	20000aea <spi_flash_loader+0x24a>
        {
            if(img_buffer[ii] != img_buffer2[ii])
20000aa4:	f8d7 281c 	ldr.w	r2, [r7, #2076]	; 0x81c
20000aa8:	f507 6383 	add.w	r3, r7, #1048	; 0x418
20000aac:	f1a3 0304 	sub.w	r3, r3, #4
20000ab0:	5c9a      	ldrb	r2, [r3, r2]
20000ab2:	f8d7 181c 	ldr.w	r1, [r7, #2076]	; 0x81c
20000ab6:	f107 0308 	add.w	r3, r7, #8
20000aba:	f1a3 0304 	sub.w	r3, r3, #4
20000abe:	5c5b      	ldrb	r3, [r3, r1]
20000ac0:	429a      	cmp	r2, r3
20000ac2:	d00c      	beq.n	20000ade <spi_flash_loader+0x23e>
            {
                MSS_UART_polled_tx(&g_mss_uart0,(const uint8_t *)"z",1);
20000ac4:	f644 2054 	movw	r0, #19028	; 0x4a54
20000ac8:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000acc:	f644 012c 	movw	r1, #18476	; 0x482c
20000ad0:	f2c2 0100 	movt	r1, #8192	; 0x2000
20000ad4:	f04f 0201 	mov.w	r2, #1
20000ad8:	f001 faf0 	bl	200020bc <MSS_UART_polled_tx>
                return;
20000adc:	e021      	b.n	20000b22 <spi_flash_loader+0x282>
           /* Verify the last bytes */
    {
        uint8_t img_buffer2[1030];
        ii -= length;
        spi_flash_read(address + ii, img_buffer2, length);
        for(ii=0; ii<length; ii++)
20000ade:	f8d7 381c 	ldr.w	r3, [r7, #2076]	; 0x81c
20000ae2:	f103 0301 	add.w	r3, r3, #1
20000ae6:	f8c7 381c 	str.w	r3, [r7, #2076]	; 0x81c
20000aea:	f8d7 281c 	ldr.w	r2, [r7, #2076]	; 0x81c
20000aee:	f8d7 3820 	ldr.w	r3, [r7, #2080]	; 0x820
20000af2:	429a      	cmp	r2, r3
20000af4:	dbd6      	blt.n	20000aa4 <spi_flash_loader+0x204>
            {
                MSS_UART_polled_tx(&g_mss_uart0,(const uint8_t *)"z",1);
                return;
            }
        }
        MSS_UART_polled_tx(&g_mss_uart0,(const uint8_t *)"y",1);
20000af6:	f644 2054 	movw	r0, #19028	; 0x4a54
20000afa:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000afe:	f644 0128 	movw	r1, #18472	; 0x4828
20000b02:	f2c2 0100 	movt	r1, #8192	; 0x2000
20000b06:	f04f 0201 	mov.w	r2, #1
20000b0a:	f001 fad7 	bl	200020bc <MSS_UART_polled_tx>

#ifdef BOOT_SPI_FLASH_IMAGE
        spi_flash_to_esram(oriAddress, oriSize);
20000b0e:	f8d7 3824 	ldr.w	r3, [r7, #2084]	; 0x824
20000b12:	f8d7 0818 	ldr.w	r0, [r7, #2072]	; 0x818
20000b16:	4619      	mov	r1, r3
20000b18:	f000 f80a 	bl	20000b30 <spi_flash_to_esram>
#endif

    }
    return;
20000b1c:	bf00      	nop
20000b1e:	e000      	b.n	20000b22 <spi_flash_loader+0x282>
        }
        while(!rx_size);

        if(rx_size != length)
        {
            return;
20000b20:	bf00      	nop
        spi_flash_to_esram(oriAddress, oriSize);
#endif

    }
    return;
}
20000b22:	f107 0728 	add.w	r7, r7, #40	; 0x28
20000b26:	f507 6700 	add.w	r7, r7, #2048	; 0x800
20000b2a:	46bd      	mov	sp, r7
20000b2c:	bd80      	pop	{r7, pc}
20000b2e:	bf00      	nop

20000b30 <spi_flash_to_esram>:


#ifdef BOOT_SPI_FLASH_IMAGE
void spi_flash_to_esram(uint32_t srcAddr, uint32_t size)
{
20000b30:	b580      	push	{r7, lr}
20000b32:	f5ad 6d84 	sub.w	sp, sp, #1056	; 0x420
20000b36:	af00      	add	r7, sp, #0
20000b38:	f107 0310 	add.w	r3, r7, #16
20000b3c:	f1a3 030c 	sub.w	r3, r3, #12
20000b40:	6018      	str	r0, [r3, #0]
20000b42:	463b      	mov	r3, r7
20000b44:	6019      	str	r1, [r3, #0]

    uint8_t img_buffer[1024];
    unsigned int ii=0, jj =0;
20000b46:	f04f 0300 	mov.w	r3, #0
20000b4a:	f8c7 3408 	str.w	r3, [r7, #1032]	; 0x408
20000b4e:	f04f 0300 	mov.w	r3, #0
20000b52:	f8c7 340c 	str.w	r3, [r7, #1036]	; 0x40c
    unsigned long length = 0;
20000b56:	f04f 0300 	mov.w	r3, #0
20000b5a:	f8c7 3410 	str.w	r3, [r7, #1040]	; 0x410
    unsigned long *exeDestAddr, *exeSrcAddr;

    unsigned char *destAddr = (unsigned char *)EXT_ASRAM_BASE_ADDR;
20000b5e:	f04f 43e0 	mov.w	r3, #1879048192	; 0x70000000
20000b62:	f8c7 341c 	str.w	r3, [r7, #1052]	; 0x41c

    *(volatile unsigned long *)0xE000ED08 = ESRAM_BASE_ADDR;
20000b66:	f64e 5308 	movw	r3, #60680	; 0xed08
20000b6a:	f2ce 0300 	movt	r3, #57344	; 0xe000
20000b6e:	f04f 5200 	mov.w	r2, #536870912	; 0x20000000
20000b72:	601a      	str	r2, [r3, #0]

    emc_init();
20000b74:	f000 fd7e 	bl	20001674 <emc_init>

    ii = 0;
20000b78:	f04f 0300 	mov.w	r3, #0
20000b7c:	f8c7 3408 	str.w	r3, [r7, #1032]	; 0x408
    jj = 0;
20000b80:	f04f 0300 	mov.w	r3, #0
20000b84:	f8c7 340c 	str.w	r3, [r7, #1036]	; 0x40c
    while(size > 0)
20000b88:	e04c      	b.n	20000c24 <spi_flash_to_esram+0xf4>
    {
        if (size >=1024)
20000b8a:	463b      	mov	r3, r7
20000b8c:	681a      	ldr	r2, [r3, #0]
20000b8e:	f240 33ff 	movw	r3, #1023	; 0x3ff
20000b92:	429a      	cmp	r2, r3
20000b94:	d904      	bls.n	20000ba0 <spi_flash_to_esram+0x70>
        {
            length = 1024;
20000b96:	f44f 6380 	mov.w	r3, #1024	; 0x400
20000b9a:	f8c7 3410 	str.w	r3, [r7, #1040]	; 0x410
20000b9e:	e003      	b.n	20000ba8 <spi_flash_to_esram+0x78>
        }
        else
        {
            length = size;
20000ba0:	463b      	mov	r3, r7
20000ba2:	681b      	ldr	r3, [r3, #0]
20000ba4:	f8c7 3410 	str.w	r3, [r7, #1040]	; 0x410
        }
        spi_flash_read(srcAddr + jj, img_buffer, length);
20000ba8:	f107 0310 	add.w	r3, r7, #16
20000bac:	f1a3 030c 	sub.w	r3, r3, #12
20000bb0:	681a      	ldr	r2, [r3, #0]
20000bb2:	f8d7 340c 	ldr.w	r3, [r7, #1036]	; 0x40c
20000bb6:	441a      	add	r2, r3
20000bb8:	f107 0308 	add.w	r3, r7, #8
20000bbc:	4610      	mov	r0, r2
20000bbe:	4619      	mov	r1, r3
20000bc0:	f8d7 2410 	ldr.w	r2, [r7, #1040]	; 0x410
20000bc4:	f000 fbba 	bl	2000133c <spi_flash_read>

        for(ii=0; ii<length; ii++)
20000bc8:	f04f 0300 	mov.w	r3, #0
20000bcc:	f8c7 3408 	str.w	r3, [r7, #1032]	; 0x408
20000bd0:	e013      	b.n	20000bfa <spi_flash_to_esram+0xca>
        {
            *destAddr++ = img_buffer[ii];
20000bd2:	f8d7 3408 	ldr.w	r3, [r7, #1032]	; 0x408
20000bd6:	f107 0208 	add.w	r2, r7, #8
20000bda:	5cd2      	ldrb	r2, [r2, r3]
20000bdc:	f8d7 341c 	ldr.w	r3, [r7, #1052]	; 0x41c
20000be0:	701a      	strb	r2, [r3, #0]
20000be2:	f8d7 341c 	ldr.w	r3, [r7, #1052]	; 0x41c
20000be6:	f103 0301 	add.w	r3, r3, #1
20000bea:	f8c7 341c 	str.w	r3, [r7, #1052]	; 0x41c
        {
            length = size;
        }
        spi_flash_read(srcAddr + jj, img_buffer, length);

        for(ii=0; ii<length; ii++)
20000bee:	f8d7 3408 	ldr.w	r3, [r7, #1032]	; 0x408
20000bf2:	f103 0301 	add.w	r3, r3, #1
20000bf6:	f8c7 3408 	str.w	r3, [r7, #1032]	; 0x408
20000bfa:	f8d7 2408 	ldr.w	r2, [r7, #1032]	; 0x408
20000bfe:	f8d7 3410 	ldr.w	r3, [r7, #1040]	; 0x410
20000c02:	429a      	cmp	r2, r3
20000c04:	d3e5      	bcc.n	20000bd2 <spi_flash_to_esram+0xa2>
        {
            *destAddr++ = img_buffer[ii];
        }
        jj += length;
20000c06:	f8d7 240c 	ldr.w	r2, [r7, #1036]	; 0x40c
20000c0a:	f8d7 3410 	ldr.w	r3, [r7, #1040]	; 0x410
20000c0e:	4413      	add	r3, r2
20000c10:	f8c7 340c 	str.w	r3, [r7, #1036]	; 0x40c
        size -= length;
20000c14:	463b      	mov	r3, r7
20000c16:	463a      	mov	r2, r7
20000c18:	6811      	ldr	r1, [r2, #0]
20000c1a:	f8d7 2410 	ldr.w	r2, [r7, #1040]	; 0x410
20000c1e:	ebc2 0201 	rsb	r2, r2, r1
20000c22:	601a      	str	r2, [r3, #0]

    emc_init();

    ii = 0;
    jj = 0;
    while(size > 0)
20000c24:	463b      	mov	r3, r7
20000c26:	681b      	ldr	r3, [r3, #0]
20000c28:	2b00      	cmp	r3, #0
20000c2a:	d1ae      	bne.n	20000b8a <spi_flash_to_esram+0x5a>
        jj += length;
        size -= length;

    }

    exeDestAddr = (unsigned long *)ESRAM_BASE_ADDR;
20000c2c:	f04f 5300 	mov.w	r3, #536870912	; 0x20000000
20000c30:	f8c7 3414 	str.w	r3, [r7, #1044]	; 0x414

    exeSrcAddr = (unsigned long *)EXT_ASRAM_BASE_ADDR;
20000c34:	f04f 43e0 	mov.w	r3, #1879048192	; 0x70000000
20000c38:	f8c7 3418 	str.w	r3, [r7, #1048]	; 0x418
    for (ii=0; ii<166; ii++ )
20000c3c:	f04f 0300 	mov.w	r3, #0
20000c40:	f8c7 3408 	str.w	r3, [r7, #1032]	; 0x408
20000c44:	e017      	b.n	20000c76 <spi_flash_to_esram+0x146>
    {
       *exeDestAddr++ = *exeSrcAddr++;
20000c46:	f8d7 3418 	ldr.w	r3, [r7, #1048]	; 0x418
20000c4a:	681a      	ldr	r2, [r3, #0]
20000c4c:	f8d7 3414 	ldr.w	r3, [r7, #1044]	; 0x414
20000c50:	601a      	str	r2, [r3, #0]
20000c52:	f8d7 3414 	ldr.w	r3, [r7, #1044]	; 0x414
20000c56:	f103 0304 	add.w	r3, r3, #4
20000c5a:	f8c7 3414 	str.w	r3, [r7, #1044]	; 0x414
20000c5e:	f8d7 3418 	ldr.w	r3, [r7, #1048]	; 0x418
20000c62:	f103 0304 	add.w	r3, r3, #4
20000c66:	f8c7 3418 	str.w	r3, [r7, #1048]	; 0x418
    }

    exeDestAddr = (unsigned long *)ESRAM_BASE_ADDR;

    exeSrcAddr = (unsigned long *)EXT_ASRAM_BASE_ADDR;
    for (ii=0; ii<166; ii++ )
20000c6a:	f8d7 3408 	ldr.w	r3, [r7, #1032]	; 0x408
20000c6e:	f103 0301 	add.w	r3, r3, #1
20000c72:	f8c7 3408 	str.w	r3, [r7, #1032]	; 0x408
20000c76:	f8d7 3408 	ldr.w	r3, [r7, #1032]	; 0x408
20000c7a:	2ba5      	cmp	r3, #165	; 0xa5
20000c7c:	d9e3      	bls.n	20000c46 <spi_flash_to_esram+0x116>
    {
       *exeDestAddr++ = *exeSrcAddr++;
    }

    __asm volatile(
20000c7e:	4a05      	ldr	r2, [pc, #20]	; (20000c94 <spi_flash_to_esram+0x164>)
20000c80:	6810      	ldr	r0, [r2, #0]
20000c82:	f8d2 e004 	ldr.w	lr, [r2, #4]
20000c86:	f380 8808 	msr	MSP, r0
20000c8a:	4770      	bx	lr
           "msr msp,r0            \n"  /* Step 5. */
           "bx lr                 \n"  /* Step 6. */

    );

}
20000c8c:	f507 6784 	add.w	r7, r7, #1056	; 0x420
20000c90:	46bd      	mov	sp, r7
20000c92:	bd80      	pop	{r7, pc}
20000c94:	20000000 	.word	0x20000000

20000c98 <spi_flash_init>:

/******************************************************************************
 *For more details please refer the spi_flash.h file
 ******************************************************************************/
spi_flash_status_t spi_flash_init( void )
{
20000c98:	b580      	push	{r7, lr}
20000c9a:	b082      	sub	sp, #8
20000c9c:	af02      	add	r7, sp, #8
    /*--------------------------------------------------------------------------
     * Configure MSS_SPI.
     */
    MSS_SPI_init( SPI_INSTANCE );
20000c9e:	f644 207c 	movw	r0, #19068	; 0x4a7c
20000ca2:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000ca6:	f002 f863 	bl	20002d70 <MSS_SPI_init>
    MSS_SPI_configure_master_mode
20000caa:	f04f 0308 	mov.w	r3, #8
20000cae:	9300      	str	r3, [sp, #0]
20000cb0:	f644 207c 	movw	r0, #19068	; 0x4a7c
20000cb4:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000cb8:	f04f 0100 	mov.w	r1, #0
20000cbc:	f04f 7240 	mov.w	r2, #50331648	; 0x3000000
20000cc0:	f04f 0306 	mov.w	r3, #6
20000cc4:	f002 fa22 	bl	2000310c <MSS_SPI_configure_master_mode>

#ifdef USE_DMA_FOR_SPI_FLASH
    /*--------------------------------------------------------------------------
     * Configure DMA channel used as part of this MSS_SPI Flash driver.
     */
    PDMA_init();
20000cc8:	f003 f81c 	bl	20003d04 <PDMA_init>

    PDMA_configure
20000ccc:	f04f 0000 	mov.w	r0, #0
20000cd0:	f04f 0107 	mov.w	r1, #7
20000cd4:	f44f 6280 	mov.w	r2, #1024	; 0x400
20000cd8:	f04f 030a 	mov.w	r3, #10
20000cdc:	f003 f86e 	bl	20003dbc <PDMA_configure>
        DMA_TO_PERI,
        PDMA_LOW_PRIORITY | PDMA_BYTE_TRANSFER | PDMA_INC_SRC_ONE_BYTE,
        PDMA_DEFAULT_WRITE_ADJ
    );
#endif
    return 0;
20000ce0:	f04f 0300 	mov.w	r3, #0
}
20000ce4:	4618      	mov	r0, r3
20000ce6:	46bd      	mov	sp, r7
20000ce8:	bd80      	pop	{r7, pc}
20000cea:	bf00      	nop

20000cec <spi_flash_control_hw>:
(
    spi_flash_control_hw_t operation,
    uint32_t peram1,
    void *   ptrPeram
)
{
20000cec:	b580      	push	{r7, lr}
20000cee:	b096      	sub	sp, #88	; 0x58
20000cf0:	af02      	add	r7, sp, #8
20000cf2:	4603      	mov	r3, r0
20000cf4:	60b9      	str	r1, [r7, #8]
20000cf6:	607a      	str	r2, [r7, #4]
20000cf8:	73fb      	strb	r3, [r7, #15]
    switch(operation){
20000cfa:	7bfb      	ldrb	r3, [r7, #15]
20000cfc:	2b0a      	cmp	r3, #10
20000cfe:	f200 8313 	bhi.w	20001328 <spi_flash_control_hw+0x63c>
20000d02:	a201      	add	r2, pc, #4	; (adr r2, 20000d08 <spi_flash_control_hw+0x1c>)
20000d04:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
20000d08:	20000e49 	.word	0x20000e49
20000d0c:	20000d93 	.word	0x20000d93
20000d10:	20000eff 	.word	0x20000eff
20000d14:	20000eff 	.word	0x20000eff
20000d18:	200012ff 	.word	0x200012ff
20000d1c:	200010b5 	.word	0x200010b5
20000d20:	20001183 	.word	0x20001183
20000d24:	2000123b 	.word	0x2000123b
20000d28:	20000fa9 	.word	0x20000fa9
20000d2c:	20000d35 	.word	0x20000d35
20000d30:	2000104b 	.word	0x2000104b
        case SPI_FLASH_READ_DEVICE_ID:
        {
            uint8_t read_device_id_cmd = DEVICE_ID_READ;
20000d34:	f06f 0360 	mvn.w	r3, #96	; 0x60
20000d38:	f887 3037 	strb.w	r3, [r7, #55]	; 0x37
            uint8_t read_buffer[2];
            struct device_Info *ptrDevInfo = (struct device_Info *)ptrPeram;
20000d3c:	687b      	ldr	r3, [r7, #4]
20000d3e:	63bb      	str	r3, [r7, #56]	; 0x38

            MSS_SPI_set_slave_select( SPI_INSTANCE, SPI_SLAVE );
20000d40:	f644 207c 	movw	r0, #19068	; 0x4a7c
20000d44:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000d48:	f04f 0100 	mov.w	r1, #0
20000d4c:	f002 fa3c 	bl	200031c8 <MSS_SPI_set_slave_select>

            MSS_SPI_transfer_block( SPI_INSTANCE,
20000d50:	f107 0237 	add.w	r2, r7, #55	; 0x37
20000d54:	f107 0334 	add.w	r3, r7, #52	; 0x34
20000d58:	f04f 0102 	mov.w	r1, #2
20000d5c:	9100      	str	r1, [sp, #0]
20000d5e:	f644 207c 	movw	r0, #19068	; 0x4a7c
20000d62:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000d66:	4611      	mov	r1, r2
20000d68:	f04f 0201 	mov.w	r2, #1
20000d6c:	f002 fb44 	bl	200033f8 <MSS_SPI_transfer_block>
                                    &read_device_id_cmd,
                                    1,
                                    read_buffer,
                                    sizeof(read_buffer) );
            MSS_SPI_clear_slave_select( SPI_INSTANCE, SPI_SLAVE );
20000d70:	f644 207c 	movw	r0, #19068	; 0x4a7c
20000d74:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000d78:	f04f 0100 	mov.w	r1, #0
20000d7c:	f002 fa98 	bl	200032b0 <MSS_SPI_clear_slave_select>

            ptrDevInfo->manufacturer_id = read_buffer[0];
20000d80:	f897 2034 	ldrb.w	r2, [r7, #52]	; 0x34
20000d84:	6bbb      	ldr	r3, [r7, #56]	; 0x38
20000d86:	701a      	strb	r2, [r3, #0]
            ptrDevInfo->device_id = read_buffer[1];
20000d88:	f897 2035 	ldrb.w	r2, [r7, #53]	; 0x35
20000d8c:	6bbb      	ldr	r3, [r7, #56]	; 0x38
20000d8e:	705a      	strb	r2, [r3, #1]

        }
        break;
20000d90:	e2cd      	b.n	2000132e <spi_flash_control_hw+0x642>
        case SPI_FLASH_SECTOR_PROTECT:
        {
            uint8_t cmd_buffer[4];
            uint32_t address = peram1;
20000d92:	68bb      	ldr	r3, [r7, #8]
20000d94:	63fb      	str	r3, [r7, #60]	; 0x3c

            MSS_SPI_set_slave_select( SPI_INSTANCE, SPI_SLAVE );
20000d96:	f644 207c 	movw	r0, #19068	; 0x4a7c
20000d9a:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000d9e:	f04f 0100 	mov.w	r1, #0
20000da2:	f002 fa11 	bl	200031c8 <MSS_SPI_set_slave_select>

            /* Send Write Enable command */
            cmd_buffer[0] = WRITE_ENABLE_CMD;
20000da6:	f04f 0306 	mov.w	r3, #6
20000daa:	f887 3030 	strb.w	r3, [r7, #48]	; 0x30
            if(wait_ready())
20000dae:	f000 fc3b 	bl	20001628 <wait_ready>
20000db2:	4603      	mov	r3, r0
20000db4:	2b00      	cmp	r3, #0
20000db6:	d002      	beq.n	20000dbe <spi_flash_control_hw+0xd2>
                   return SPI_FLASH_UNSUCCESS; 
20000db8:	f04f 0305 	mov.w	r3, #5
20000dbc:	e2b9      	b.n	20001332 <spi_flash_control_hw+0x646>

            MSS_SPI_transfer_block( SPI_INSTANCE, cmd_buffer, 1, 0, 0 );
20000dbe:	f107 0330 	add.w	r3, r7, #48	; 0x30
20000dc2:	f04f 0200 	mov.w	r2, #0
20000dc6:	9200      	str	r2, [sp, #0]
20000dc8:	f644 207c 	movw	r0, #19068	; 0x4a7c
20000dcc:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000dd0:	4619      	mov	r1, r3
20000dd2:	f04f 0201 	mov.w	r2, #1
20000dd6:	f04f 0300 	mov.w	r3, #0
20000dda:	f002 fb0d 	bl	200033f8 <MSS_SPI_transfer_block>

            /* protect sector */
            cmd_buffer[0] = PROTECT_SECTOR_OPCODE;
20000dde:	f04f 0336 	mov.w	r3, #54	; 0x36
20000de2:	f887 3030 	strb.w	r3, [r7, #48]	; 0x30
            cmd_buffer[1] = (address >> 16) & 0xFF;
20000de6:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
20000de8:	ea4f 4313 	mov.w	r3, r3, lsr #16
20000dec:	b2db      	uxtb	r3, r3
20000dee:	f887 3031 	strb.w	r3, [r7, #49]	; 0x31
            cmd_buffer[2] = (address >> 8 ) & 0xFF;
20000df2:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
20000df4:	ea4f 2313 	mov.w	r3, r3, lsr #8
20000df8:	b2db      	uxtb	r3, r3
20000dfa:	f887 3032 	strb.w	r3, [r7, #50]	; 0x32
            cmd_buffer[3] = address & 0xFF;
20000dfe:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
20000e00:	b2db      	uxtb	r3, r3
20000e02:	f887 3033 	strb.w	r3, [r7, #51]	; 0x33
            if(wait_ready())
20000e06:	f000 fc0f 	bl	20001628 <wait_ready>
20000e0a:	4603      	mov	r3, r0
20000e0c:	2b00      	cmp	r3, #0
20000e0e:	d002      	beq.n	20000e16 <spi_flash_control_hw+0x12a>
                return SPI_FLASH_UNSUCCESS; 
20000e10:	f04f 0305 	mov.w	r3, #5
20000e14:	e28d      	b.n	20001332 <spi_flash_control_hw+0x646>

            MSS_SPI_transfer_block( SPI_INSTANCE,
20000e16:	f107 0330 	add.w	r3, r7, #48	; 0x30
20000e1a:	f04f 0200 	mov.w	r2, #0
20000e1e:	9200      	str	r2, [sp, #0]
20000e20:	f644 207c 	movw	r0, #19068	; 0x4a7c
20000e24:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000e28:	4619      	mov	r1, r3
20000e2a:	f04f 0204 	mov.w	r2, #4
20000e2e:	f04f 0300 	mov.w	r3, #0
20000e32:	f002 fae1 	bl	200033f8 <MSS_SPI_transfer_block>
                                    cmd_buffer,
                                    sizeof(cmd_buffer),
                                    0,
                                    0 );
            MSS_SPI_clear_slave_select( SPI_INSTANCE, SPI_SLAVE );
20000e36:	f644 207c 	movw	r0, #19068	; 0x4a7c
20000e3a:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000e3e:	f04f 0100 	mov.w	r1, #0
20000e42:	f002 fa35 	bl	200032b0 <MSS_SPI_clear_slave_select>

        }
        break;
20000e46:	e272      	b.n	2000132e <spi_flash_control_hw+0x642>
        case SPI_FLASH_SECTOR_UNPROTECT:
        {
            uint8_t cmd_buffer[4];
            uint32_t address = peram1;
20000e48:	68bb      	ldr	r3, [r7, #8]
20000e4a:	643b      	str	r3, [r7, #64]	; 0x40

            MSS_SPI_set_slave_select( SPI_INSTANCE, SPI_SLAVE );
20000e4c:	f644 207c 	movw	r0, #19068	; 0x4a7c
20000e50:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000e54:	f04f 0100 	mov.w	r1, #0
20000e58:	f002 f9b6 	bl	200031c8 <MSS_SPI_set_slave_select>

            /* Send Write Enable command */
            cmd_buffer[0] = WRITE_ENABLE_CMD;
20000e5c:	f04f 0306 	mov.w	r3, #6
20000e60:	f887 302c 	strb.w	r3, [r7, #44]	; 0x2c
            if(wait_ready())
20000e64:	f000 fbe0 	bl	20001628 <wait_ready>
20000e68:	4603      	mov	r3, r0
20000e6a:	2b00      	cmp	r3, #0
20000e6c:	d002      	beq.n	20000e74 <spi_flash_control_hw+0x188>
                return SPI_FLASH_UNSUCCESS; 
20000e6e:	f04f 0305 	mov.w	r3, #5
20000e72:	e25e      	b.n	20001332 <spi_flash_control_hw+0x646>

            MSS_SPI_transfer_block( SPI_INSTANCE, cmd_buffer, 1, 0, 0 );
20000e74:	f107 032c 	add.w	r3, r7, #44	; 0x2c
20000e78:	f04f 0200 	mov.w	r2, #0
20000e7c:	9200      	str	r2, [sp, #0]
20000e7e:	f644 207c 	movw	r0, #19068	; 0x4a7c
20000e82:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000e86:	4619      	mov	r1, r3
20000e88:	f04f 0201 	mov.w	r2, #1
20000e8c:	f04f 0300 	mov.w	r3, #0
20000e90:	f002 fab2 	bl	200033f8 <MSS_SPI_transfer_block>

            /* Unprotect sector */
            cmd_buffer[0] = UNPROTECT_SECTOR_OPCODE;
20000e94:	f04f 0339 	mov.w	r3, #57	; 0x39
20000e98:	f887 302c 	strb.w	r3, [r7, #44]	; 0x2c
            cmd_buffer[1] = (address >> 16) & 0xFF;
20000e9c:	6c3b      	ldr	r3, [r7, #64]	; 0x40
20000e9e:	ea4f 4313 	mov.w	r3, r3, lsr #16
20000ea2:	b2db      	uxtb	r3, r3
20000ea4:	f887 302d 	strb.w	r3, [r7, #45]	; 0x2d
            cmd_buffer[2] = (address >> 8 ) & 0xFF;
20000ea8:	6c3b      	ldr	r3, [r7, #64]	; 0x40
20000eaa:	ea4f 2313 	mov.w	r3, r3, lsr #8
20000eae:	b2db      	uxtb	r3, r3
20000eb0:	f887 302e 	strb.w	r3, [r7, #46]	; 0x2e
            cmd_buffer[3] = address & 0xFF;
20000eb4:	6c3b      	ldr	r3, [r7, #64]	; 0x40
20000eb6:	b2db      	uxtb	r3, r3
20000eb8:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
            if(wait_ready())
20000ebc:	f000 fbb4 	bl	20001628 <wait_ready>
20000ec0:	4603      	mov	r3, r0
20000ec2:	2b00      	cmp	r3, #0
20000ec4:	d002      	beq.n	20000ecc <spi_flash_control_hw+0x1e0>
                return SPI_FLASH_UNSUCCESS; 
20000ec6:	f04f 0305 	mov.w	r3, #5
20000eca:	e232      	b.n	20001332 <spi_flash_control_hw+0x646>

            MSS_SPI_transfer_block( SPI_INSTANCE,
20000ecc:	f107 032c 	add.w	r3, r7, #44	; 0x2c
20000ed0:	f04f 0200 	mov.w	r2, #0
20000ed4:	9200      	str	r2, [sp, #0]
20000ed6:	f644 207c 	movw	r0, #19068	; 0x4a7c
20000eda:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000ede:	4619      	mov	r1, r3
20000ee0:	f04f 0204 	mov.w	r2, #4
20000ee4:	f04f 0300 	mov.w	r3, #0
20000ee8:	f002 fa86 	bl	200033f8 <MSS_SPI_transfer_block>
                                    cmd_buffer,
                                    sizeof(cmd_buffer),
                                    0,
                                    0 );
            MSS_SPI_clear_slave_select( SPI_INSTANCE, SPI_SLAVE );
20000eec:	f644 207c 	movw	r0, #19068	; 0x4a7c
20000ef0:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000ef4:	f04f 0100 	mov.w	r1, #0
20000ef8:	f002 f9da 	bl	200032b0 <MSS_SPI_clear_slave_select>

        }
        break;
20000efc:	e217      	b.n	2000132e <spi_flash_control_hw+0x642>
        case SPI_FLASH_GLOBAL_UNPROTECT:
        {
            uint8_t cmd_buffer[2];

            /* Send Write Enable command */
            cmd_buffer[0] = WRITE_ENABLE_CMD;
20000efe:	f04f 0306 	mov.w	r3, #6
20000f02:	f887 3028 	strb.w	r3, [r7, #40]	; 0x28

            MSS_SPI_set_slave_select( SPI_INSTANCE, SPI_SLAVE );
20000f06:	f644 207c 	movw	r0, #19068	; 0x4a7c
20000f0a:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000f0e:	f04f 0100 	mov.w	r1, #0
20000f12:	f002 f959 	bl	200031c8 <MSS_SPI_set_slave_select>

            if(wait_ready())
20000f16:	f000 fb87 	bl	20001628 <wait_ready>
20000f1a:	4603      	mov	r3, r0
20000f1c:	2b00      	cmp	r3, #0
20000f1e:	d002      	beq.n	20000f26 <spi_flash_control_hw+0x23a>
               return SPI_FLASH_UNSUCCESS;
20000f20:	f04f 0305 	mov.w	r3, #5
20000f24:	e205      	b.n	20001332 <spi_flash_control_hw+0x646>

            MSS_SPI_transfer_block( SPI_INSTANCE, cmd_buffer, 1, 0, 0 );
20000f26:	f107 0328 	add.w	r3, r7, #40	; 0x28
20000f2a:	f04f 0200 	mov.w	r2, #0
20000f2e:	9200      	str	r2, [sp, #0]
20000f30:	f644 207c 	movw	r0, #19068	; 0x4a7c
20000f34:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000f38:	4619      	mov	r1, r3
20000f3a:	f04f 0201 	mov.w	r2, #1
20000f3e:	f04f 0300 	mov.w	r3, #0
20000f42:	f002 fa59 	bl	200033f8 <MSS_SPI_transfer_block>

            /* Send Chip Erase command */
            cmd_buffer[0] = WRITE_STATUS1_OPCODE;
20000f46:	f04f 0301 	mov.w	r3, #1
20000f4a:	f887 3028 	strb.w	r3, [r7, #40]	; 0x28
            cmd_buffer[1] = 0;
20000f4e:	f04f 0300 	mov.w	r3, #0
20000f52:	f887 3029 	strb.w	r3, [r7, #41]	; 0x29

            if(wait_ready())
20000f56:	f000 fb67 	bl	20001628 <wait_ready>
20000f5a:	4603      	mov	r3, r0
20000f5c:	2b00      	cmp	r3, #0
20000f5e:	d002      	beq.n	20000f66 <spi_flash_control_hw+0x27a>
               return SPI_FLASH_UNSUCCESS;
20000f60:	f04f 0305 	mov.w	r3, #5
20000f64:	e1e5      	b.n	20001332 <spi_flash_control_hw+0x646>

            MSS_SPI_transfer_block( SPI_INSTANCE, cmd_buffer, 2, 0, 0 );
20000f66:	f107 0328 	add.w	r3, r7, #40	; 0x28
20000f6a:	f04f 0200 	mov.w	r2, #0
20000f6e:	9200      	str	r2, [sp, #0]
20000f70:	f644 207c 	movw	r0, #19068	; 0x4a7c
20000f74:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000f78:	4619      	mov	r1, r3
20000f7a:	f04f 0202 	mov.w	r2, #2
20000f7e:	f04f 0300 	mov.w	r3, #0
20000f82:	f002 fa39 	bl	200033f8 <MSS_SPI_transfer_block>
            if(wait_ready())
20000f86:	f000 fb4f 	bl	20001628 <wait_ready>
20000f8a:	4603      	mov	r3, r0
20000f8c:	2b00      	cmp	r3, #0
20000f8e:	d002      	beq.n	20000f96 <spi_flash_control_hw+0x2aa>
                return SPI_FLASH_UNSUCCESS;
20000f90:	f04f 0305 	mov.w	r3, #5
20000f94:	e1cd      	b.n	20001332 <spi_flash_control_hw+0x646>

            MSS_SPI_clear_slave_select( SPI_INSTANCE, SPI_SLAVE );
20000f96:	f644 207c 	movw	r0, #19068	; 0x4a7c
20000f9a:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000f9e:	f04f 0100 	mov.w	r1, #0
20000fa2:	f002 f985 	bl	200032b0 <MSS_SPI_clear_slave_select>
        }
        break;
20000fa6:	e1c2      	b.n	2000132e <spi_flash_control_hw+0x642>
        case SPI_FLASH_CHIP_ERASE:
        {
            uint8_t cmd_buffer;
            /* Send Write Enable command */
            cmd_buffer = WRITE_ENABLE_CMD;
20000fa8:	f04f 0306 	mov.w	r3, #6
20000fac:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27

            MSS_SPI_set_slave_select( SPI_INSTANCE, SPI_SLAVE );
20000fb0:	f644 207c 	movw	r0, #19068	; 0x4a7c
20000fb4:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000fb8:	f04f 0100 	mov.w	r1, #0
20000fbc:	f002 f904 	bl	200031c8 <MSS_SPI_set_slave_select>

            if(wait_ready())
20000fc0:	f000 fb32 	bl	20001628 <wait_ready>
20000fc4:	4603      	mov	r3, r0
20000fc6:	2b00      	cmp	r3, #0
20000fc8:	d002      	beq.n	20000fd0 <spi_flash_control_hw+0x2e4>
                return SPI_FLASH_UNSUCCESS; 
20000fca:	f04f 0305 	mov.w	r3, #5
20000fce:	e1b0      	b.n	20001332 <spi_flash_control_hw+0x646>

            MSS_SPI_transfer_block( SPI_INSTANCE, &cmd_buffer, 1, 0, 0 );
20000fd0:	f107 0327 	add.w	r3, r7, #39	; 0x27
20000fd4:	f04f 0200 	mov.w	r2, #0
20000fd8:	9200      	str	r2, [sp, #0]
20000fda:	f644 207c 	movw	r0, #19068	; 0x4a7c
20000fde:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000fe2:	4619      	mov	r1, r3
20000fe4:	f04f 0201 	mov.w	r2, #1
20000fe8:	f04f 0300 	mov.w	r3, #0
20000fec:	f002 fa04 	bl	200033f8 <MSS_SPI_transfer_block>

            /* Send Chip Erase command */
            cmd_buffer = CHIP_ERASE_OPCODE;
20000ff0:	f04f 0360 	mov.w	r3, #96	; 0x60
20000ff4:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27

            if(wait_ready())
20000ff8:	f000 fb16 	bl	20001628 <wait_ready>
20000ffc:	4603      	mov	r3, r0
20000ffe:	2b00      	cmp	r3, #0
20001000:	d002      	beq.n	20001008 <spi_flash_control_hw+0x31c>
                return SPI_FLASH_UNSUCCESS; 
20001002:	f04f 0305 	mov.w	r3, #5
20001006:	e194      	b.n	20001332 <spi_flash_control_hw+0x646>

            MSS_SPI_transfer_block( SPI_INSTANCE, &cmd_buffer, 1, 0, 0 );
20001008:	f107 0327 	add.w	r3, r7, #39	; 0x27
2000100c:	f04f 0200 	mov.w	r2, #0
20001010:	9200      	str	r2, [sp, #0]
20001012:	f644 207c 	movw	r0, #19068	; 0x4a7c
20001016:	f2c2 0000 	movt	r0, #8192	; 0x2000
2000101a:	4619      	mov	r1, r3
2000101c:	f04f 0201 	mov.w	r2, #1
20001020:	f04f 0300 	mov.w	r3, #0
20001024:	f002 f9e8 	bl	200033f8 <MSS_SPI_transfer_block>
            if(wait_ready())
20001028:	f000 fafe 	bl	20001628 <wait_ready>
2000102c:	4603      	mov	r3, r0
2000102e:	2b00      	cmp	r3, #0
20001030:	d002      	beq.n	20001038 <spi_flash_control_hw+0x34c>
                return SPI_FLASH_UNSUCCESS; 
20001032:	f04f 0305 	mov.w	r3, #5
20001036:	e17c      	b.n	20001332 <spi_flash_control_hw+0x646>

            MSS_SPI_clear_slave_select( SPI_INSTANCE, SPI_SLAVE );
20001038:	f644 207c 	movw	r0, #19068	; 0x4a7c
2000103c:	f2c2 0000 	movt	r0, #8192	; 0x2000
20001040:	f04f 0100 	mov.w	r1, #0
20001044:	f002 f934 	bl	200032b0 <MSS_SPI_clear_slave_select>
        }
        break;
20001048:	e171      	b.n	2000132e <spi_flash_control_hw+0x642>
        case SPI_FLASH_RESET:
        {
            uint8_t cmd_buffer;
            /* Send Write Enable command */
            cmd_buffer = WRITE_ENABLE_CMD;
2000104a:	f04f 0306 	mov.w	r3, #6
2000104e:	f887 3026 	strb.w	r3, [r7, #38]	; 0x26

            if(wait_ready())
20001052:	f000 fae9 	bl	20001628 <wait_ready>
20001056:	4603      	mov	r3, r0
20001058:	2b00      	cmp	r3, #0
2000105a:	d002      	beq.n	20001062 <spi_flash_control_hw+0x376>
                return SPI_FLASH_UNSUCCESS; 
2000105c:	f04f 0305 	mov.w	r3, #5
20001060:	e167      	b.n	20001332 <spi_flash_control_hw+0x646>

            MSS_SPI_set_slave_select( SPI_INSTANCE, SPI_SLAVE );
20001062:	f644 207c 	movw	r0, #19068	; 0x4a7c
20001066:	f2c2 0000 	movt	r0, #8192	; 0x2000
2000106a:	f04f 0100 	mov.w	r1, #0
2000106e:	f002 f8ab 	bl	200031c8 <MSS_SPI_set_slave_select>
            MSS_SPI_transfer_block( SPI_INSTANCE, &cmd_buffer, 1, 0, 0 );
20001072:	f107 0326 	add.w	r3, r7, #38	; 0x26
20001076:	f04f 0200 	mov.w	r2, #0
2000107a:	9200      	str	r2, [sp, #0]
2000107c:	f644 207c 	movw	r0, #19068	; 0x4a7c
20001080:	f2c2 0000 	movt	r0, #8192	; 0x2000
20001084:	4619      	mov	r1, r3
20001086:	f04f 0201 	mov.w	r2, #1
2000108a:	f04f 0300 	mov.w	r3, #0
2000108e:	f002 f9b3 	bl	200033f8 <MSS_SPI_transfer_block>
            if(wait_ready())
20001092:	f000 fac9 	bl	20001628 <wait_ready>
20001096:	4603      	mov	r3, r0
20001098:	2b00      	cmp	r3, #0
2000109a:	d002      	beq.n	200010a2 <spi_flash_control_hw+0x3b6>
                return SPI_FLASH_UNSUCCESS; 
2000109c:	f04f 0305 	mov.w	r3, #5
200010a0:	e147      	b.n	20001332 <spi_flash_control_hw+0x646>

            MSS_SPI_clear_slave_select( SPI_INSTANCE, SPI_SLAVE );
200010a2:	f644 207c 	movw	r0, #19068	; 0x4a7c
200010a6:	f2c2 0000 	movt	r0, #8192	; 0x2000
200010aa:	f04f 0100 	mov.w	r1, #0
200010ae:	f002 f8ff 	bl	200032b0 <MSS_SPI_clear_slave_select>

        }
        break;
200010b2:	e13c      	b.n	2000132e <spi_flash_control_hw+0x642>

        case SPI_FLASH_4KBLOCK_ERASE:
        {
            uint32_t address = peram1 & BLOCK_ALIGN_MASK_4K;
200010b4:	68bb      	ldr	r3, [r7, #8]
200010b6:	f423 637e 	bic.w	r3, r3, #4064	; 0xfe0
200010ba:	f023 031f 	bic.w	r3, r3, #31
200010be:	647b      	str	r3, [r7, #68]	; 0x44
            uint8_t cmd_buffer[4];
            /* Send Write Enable command */
            cmd_buffer[0] = WRITE_ENABLE_CMD;
200010c0:	f04f 0306 	mov.w	r3, #6
200010c4:	f887 3020 	strb.w	r3, [r7, #32]

            if(wait_ready())
200010c8:	f000 faae 	bl	20001628 <wait_ready>
200010cc:	4603      	mov	r3, r0
200010ce:	2b00      	cmp	r3, #0
200010d0:	d002      	beq.n	200010d8 <spi_flash_control_hw+0x3ec>
                return SPI_FLASH_UNSUCCESS; 
200010d2:	f04f 0305 	mov.w	r3, #5
200010d6:	e12c      	b.n	20001332 <spi_flash_control_hw+0x646>

            MSS_SPI_set_slave_select( SPI_INSTANCE, SPI_SLAVE );
200010d8:	f644 207c 	movw	r0, #19068	; 0x4a7c
200010dc:	f2c2 0000 	movt	r0, #8192	; 0x2000
200010e0:	f04f 0100 	mov.w	r1, #0
200010e4:	f002 f870 	bl	200031c8 <MSS_SPI_set_slave_select>
            MSS_SPI_transfer_block( SPI_INSTANCE, cmd_buffer, 1, 0, 0 );
200010e8:	f107 0320 	add.w	r3, r7, #32
200010ec:	f04f 0200 	mov.w	r2, #0
200010f0:	9200      	str	r2, [sp, #0]
200010f2:	f644 207c 	movw	r0, #19068	; 0x4a7c
200010f6:	f2c2 0000 	movt	r0, #8192	; 0x2000
200010fa:	4619      	mov	r1, r3
200010fc:	f04f 0201 	mov.w	r2, #1
20001100:	f04f 0300 	mov.w	r3, #0
20001104:	f002 f978 	bl	200033f8 <MSS_SPI_transfer_block>

            /* Send Chip Erase command */
            cmd_buffer[0] = ERASE_4K_BLOCK_OPCODE;
20001108:	f04f 0320 	mov.w	r3, #32
2000110c:	f887 3020 	strb.w	r3, [r7, #32]
            cmd_buffer[1] = (address >> 16) & 0xFF;
20001110:	6c7b      	ldr	r3, [r7, #68]	; 0x44
20001112:	ea4f 4313 	mov.w	r3, r3, lsr #16
20001116:	b2db      	uxtb	r3, r3
20001118:	f887 3021 	strb.w	r3, [r7, #33]	; 0x21
            cmd_buffer[2] = (address >> 8 ) & 0xFF;
2000111c:	6c7b      	ldr	r3, [r7, #68]	; 0x44
2000111e:	ea4f 2313 	mov.w	r3, r3, lsr #8
20001122:	b2db      	uxtb	r3, r3
20001124:	f887 3022 	strb.w	r3, [r7, #34]	; 0x22
            cmd_buffer[3] = address & 0xFF;
20001128:	6c7b      	ldr	r3, [r7, #68]	; 0x44
2000112a:	b2db      	uxtb	r3, r3
2000112c:	f887 3023 	strb.w	r3, [r7, #35]	; 0x23

            if(wait_ready())
20001130:	f000 fa7a 	bl	20001628 <wait_ready>
20001134:	4603      	mov	r3, r0
20001136:	2b00      	cmp	r3, #0
20001138:	d002      	beq.n	20001140 <spi_flash_control_hw+0x454>
                return SPI_FLASH_UNSUCCESS; 
2000113a:	f04f 0305 	mov.w	r3, #5
2000113e:	e0f8      	b.n	20001332 <spi_flash_control_hw+0x646>

            MSS_SPI_transfer_block( SPI_INSTANCE,
20001140:	f107 0320 	add.w	r3, r7, #32
20001144:	f04f 0200 	mov.w	r2, #0
20001148:	9200      	str	r2, [sp, #0]
2000114a:	f644 207c 	movw	r0, #19068	; 0x4a7c
2000114e:	f2c2 0000 	movt	r0, #8192	; 0x2000
20001152:	4619      	mov	r1, r3
20001154:	f04f 0204 	mov.w	r2, #4
20001158:	f04f 0300 	mov.w	r3, #0
2000115c:	f002 f94c 	bl	200033f8 <MSS_SPI_transfer_block>
                                    cmd_buffer,
                                    sizeof(cmd_buffer),
                                    0,
                                    0 );
            if(wait_ready())
20001160:	f000 fa62 	bl	20001628 <wait_ready>
20001164:	4603      	mov	r3, r0
20001166:	2b00      	cmp	r3, #0
20001168:	d002      	beq.n	20001170 <spi_flash_control_hw+0x484>
                return SPI_FLASH_UNSUCCESS; 
2000116a:	f04f 0305 	mov.w	r3, #5
2000116e:	e0e0      	b.n	20001332 <spi_flash_control_hw+0x646>
            MSS_SPI_clear_slave_select( SPI_INSTANCE, SPI_SLAVE );
20001170:	f644 207c 	movw	r0, #19068	; 0x4a7c
20001174:	f2c2 0000 	movt	r0, #8192	; 0x2000
20001178:	f04f 0100 	mov.w	r1, #0
2000117c:	f002 f898 	bl	200032b0 <MSS_SPI_clear_slave_select>
        }
        break;
20001180:	e0d5      	b.n	2000132e <spi_flash_control_hw+0x642>
        case SPI_FLASH_32KBLOCK_ERASE:
        {
            uint32_t address = peram1 & BLOCK_ALIGN_MASK_32K;
20001182:	68bb      	ldr	r3, [r7, #8]
20001184:	f423 43fe 	bic.w	r3, r3, #32512	; 0x7f00
20001188:	f023 03ff 	bic.w	r3, r3, #255	; 0xff
2000118c:	64bb      	str	r3, [r7, #72]	; 0x48
            uint8_t cmd_buffer[4];
            /* Send Write Enable command */
            cmd_buffer[0] = WRITE_ENABLE_CMD;
2000118e:	f04f 0306 	mov.w	r3, #6
20001192:	773b      	strb	r3, [r7, #28]

            wait_ready();
20001194:	f000 fa48 	bl	20001628 <wait_ready>
            MSS_SPI_set_slave_select( SPI_INSTANCE, SPI_SLAVE );
20001198:	f644 207c 	movw	r0, #19068	; 0x4a7c
2000119c:	f2c2 0000 	movt	r0, #8192	; 0x2000
200011a0:	f04f 0100 	mov.w	r1, #0
200011a4:	f002 f810 	bl	200031c8 <MSS_SPI_set_slave_select>
            MSS_SPI_transfer_block( SPI_INSTANCE, cmd_buffer, 1, 0, 0 );
200011a8:	f107 031c 	add.w	r3, r7, #28
200011ac:	f04f 0200 	mov.w	r2, #0
200011b0:	9200      	str	r2, [sp, #0]
200011b2:	f644 207c 	movw	r0, #19068	; 0x4a7c
200011b6:	f2c2 0000 	movt	r0, #8192	; 0x2000
200011ba:	4619      	mov	r1, r3
200011bc:	f04f 0201 	mov.w	r2, #1
200011c0:	f04f 0300 	mov.w	r3, #0
200011c4:	f002 f918 	bl	200033f8 <MSS_SPI_transfer_block>

            /* Send Chip Erase command */
            cmd_buffer[0] = ERASE_32K_BLOCK_OPCODE;
200011c8:	f04f 0352 	mov.w	r3, #82	; 0x52
200011cc:	773b      	strb	r3, [r7, #28]
            cmd_buffer[1] = (address >> 16) & 0xFF;
200011ce:	6cbb      	ldr	r3, [r7, #72]	; 0x48
200011d0:	ea4f 4313 	mov.w	r3, r3, lsr #16
200011d4:	b2db      	uxtb	r3, r3
200011d6:	777b      	strb	r3, [r7, #29]
            cmd_buffer[2] = (address >> 8 ) & 0xFF;
200011d8:	6cbb      	ldr	r3, [r7, #72]	; 0x48
200011da:	ea4f 2313 	mov.w	r3, r3, lsr #8
200011de:	b2db      	uxtb	r3, r3
200011e0:	77bb      	strb	r3, [r7, #30]
            cmd_buffer[3] = address & 0xFF;
200011e2:	6cbb      	ldr	r3, [r7, #72]	; 0x48
200011e4:	b2db      	uxtb	r3, r3
200011e6:	77fb      	strb	r3, [r7, #31]

            if(wait_ready())
200011e8:	f000 fa1e 	bl	20001628 <wait_ready>
200011ec:	4603      	mov	r3, r0
200011ee:	2b00      	cmp	r3, #0
200011f0:	d002      	beq.n	200011f8 <spi_flash_control_hw+0x50c>
                return SPI_FLASH_UNSUCCESS; 
200011f2:	f04f 0305 	mov.w	r3, #5
200011f6:	e09c      	b.n	20001332 <spi_flash_control_hw+0x646>

            MSS_SPI_transfer_block( SPI_INSTANCE,
200011f8:	f107 031c 	add.w	r3, r7, #28
200011fc:	f04f 0200 	mov.w	r2, #0
20001200:	9200      	str	r2, [sp, #0]
20001202:	f644 207c 	movw	r0, #19068	; 0x4a7c
20001206:	f2c2 0000 	movt	r0, #8192	; 0x2000
2000120a:	4619      	mov	r1, r3
2000120c:	f04f 0204 	mov.w	r2, #4
20001210:	f04f 0300 	mov.w	r3, #0
20001214:	f002 f8f0 	bl	200033f8 <MSS_SPI_transfer_block>
                                    cmd_buffer,
                                    sizeof(cmd_buffer),
                                    0,
                                    0 );
            if(wait_ready())
20001218:	f000 fa06 	bl	20001628 <wait_ready>
2000121c:	4603      	mov	r3, r0
2000121e:	2b00      	cmp	r3, #0
20001220:	d002      	beq.n	20001228 <spi_flash_control_hw+0x53c>
                return SPI_FLASH_UNSUCCESS; 
20001222:	f04f 0305 	mov.w	r3, #5
20001226:	e084      	b.n	20001332 <spi_flash_control_hw+0x646>

            MSS_SPI_clear_slave_select( SPI_INSTANCE, SPI_SLAVE );
20001228:	f644 207c 	movw	r0, #19068	; 0x4a7c
2000122c:	f2c2 0000 	movt	r0, #8192	; 0x2000
20001230:	f04f 0100 	mov.w	r1, #0
20001234:	f002 f83c 	bl	200032b0 <MSS_SPI_clear_slave_select>
        }
        break;
20001238:	e079      	b.n	2000132e <spi_flash_control_hw+0x642>
        case SPI_FLASH_64KBLOCK_ERASE:
        {
            uint32_t address = peram1 & BLOCK_ALIGN_MASK_64K;
2000123a:	68bb      	ldr	r3, [r7, #8]
2000123c:	ea4f 4313 	mov.w	r3, r3, lsr #16
20001240:	ea4f 4303 	mov.w	r3, r3, lsl #16
20001244:	64fb      	str	r3, [r7, #76]	; 0x4c
            uint8_t cmd_buffer[4];
            /* Send Write Enable command */
            cmd_buffer[0] = WRITE_ENABLE_CMD;
20001246:	f04f 0306 	mov.w	r3, #6
2000124a:	763b      	strb	r3, [r7, #24]

            if(wait_ready())
2000124c:	f000 f9ec 	bl	20001628 <wait_ready>
20001250:	4603      	mov	r3, r0
20001252:	2b00      	cmp	r3, #0
20001254:	d002      	beq.n	2000125c <spi_flash_control_hw+0x570>
                return SPI_FLASH_UNSUCCESS; 
20001256:	f04f 0305 	mov.w	r3, #5
2000125a:	e06a      	b.n	20001332 <spi_flash_control_hw+0x646>

            MSS_SPI_set_slave_select( SPI_INSTANCE, SPI_SLAVE );
2000125c:	f644 207c 	movw	r0, #19068	; 0x4a7c
20001260:	f2c2 0000 	movt	r0, #8192	; 0x2000
20001264:	f04f 0100 	mov.w	r1, #0
20001268:	f001 ffae 	bl	200031c8 <MSS_SPI_set_slave_select>
            MSS_SPI_transfer_block( SPI_INSTANCE, cmd_buffer, 1, 0, 0 );
2000126c:	f107 0318 	add.w	r3, r7, #24
20001270:	f04f 0200 	mov.w	r2, #0
20001274:	9200      	str	r2, [sp, #0]
20001276:	f644 207c 	movw	r0, #19068	; 0x4a7c
2000127a:	f2c2 0000 	movt	r0, #8192	; 0x2000
2000127e:	4619      	mov	r1, r3
20001280:	f04f 0201 	mov.w	r2, #1
20001284:	f04f 0300 	mov.w	r3, #0
20001288:	f002 f8b6 	bl	200033f8 <MSS_SPI_transfer_block>

             /* Send Chip Erase command */
            cmd_buffer[0] = ERASE_64K_BLOCK_OPCODE;
2000128c:	f06f 0327 	mvn.w	r3, #39	; 0x27
20001290:	763b      	strb	r3, [r7, #24]
            cmd_buffer[1] = (address >> 16) & 0xFF;
20001292:	6cfb      	ldr	r3, [r7, #76]	; 0x4c
20001294:	ea4f 4313 	mov.w	r3, r3, lsr #16
20001298:	b2db      	uxtb	r3, r3
2000129a:	767b      	strb	r3, [r7, #25]
            cmd_buffer[2] = (address >> 8 ) & 0xFF;
2000129c:	6cfb      	ldr	r3, [r7, #76]	; 0x4c
2000129e:	ea4f 2313 	mov.w	r3, r3, lsr #8
200012a2:	b2db      	uxtb	r3, r3
200012a4:	76bb      	strb	r3, [r7, #26]
            cmd_buffer[3] = address & 0xFF;
200012a6:	6cfb      	ldr	r3, [r7, #76]	; 0x4c
200012a8:	b2db      	uxtb	r3, r3
200012aa:	76fb      	strb	r3, [r7, #27]

            if(wait_ready())
200012ac:	f000 f9bc 	bl	20001628 <wait_ready>
200012b0:	4603      	mov	r3, r0
200012b2:	2b00      	cmp	r3, #0
200012b4:	d002      	beq.n	200012bc <spi_flash_control_hw+0x5d0>
                return SPI_FLASH_UNSUCCESS; 
200012b6:	f04f 0305 	mov.w	r3, #5
200012ba:	e03a      	b.n	20001332 <spi_flash_control_hw+0x646>
            MSS_SPI_transfer_block( SPI_INSTANCE,
200012bc:	f107 0318 	add.w	r3, r7, #24
200012c0:	f04f 0200 	mov.w	r2, #0
200012c4:	9200      	str	r2, [sp, #0]
200012c6:	f644 207c 	movw	r0, #19068	; 0x4a7c
200012ca:	f2c2 0000 	movt	r0, #8192	; 0x2000
200012ce:	4619      	mov	r1, r3
200012d0:	f04f 0204 	mov.w	r2, #4
200012d4:	f04f 0300 	mov.w	r3, #0
200012d8:	f002 f88e 	bl	200033f8 <MSS_SPI_transfer_block>
                                    cmd_buffer,
                                    sizeof(cmd_buffer),
                                    0,
                                    0 );
            if(wait_ready())
200012dc:	f000 f9a4 	bl	20001628 <wait_ready>
200012e0:	4603      	mov	r3, r0
200012e2:	2b00      	cmp	r3, #0
200012e4:	d002      	beq.n	200012ec <spi_flash_control_hw+0x600>
                return SPI_FLASH_UNSUCCESS; 
200012e6:	f04f 0305 	mov.w	r3, #5
200012ea:	e022      	b.n	20001332 <spi_flash_control_hw+0x646>

            MSS_SPI_clear_slave_select( SPI_INSTANCE, SPI_SLAVE );
200012ec:	f644 207c 	movw	r0, #19068	; 0x4a7c
200012f0:	f2c2 0000 	movt	r0, #8192	; 0x2000
200012f4:	f04f 0100 	mov.w	r1, #0
200012f8:	f001 ffda 	bl	200032b0 <MSS_SPI_clear_slave_select>
        }
        break;
200012fc:	e017      	b.n	2000132e <spi_flash_control_hw+0x642>
        case SPI_FLASH_GET_STATUS:
        {
            uint8_t status;
            uint8_t command = READ_STATUS;
200012fe:	f04f 0305 	mov.w	r3, #5
20001302:	75bb      	strb	r3, [r7, #22]

            MSS_SPI_transfer_block( SPI_INSTANCE,
20001304:	f107 0216 	add.w	r2, r7, #22
20001308:	f107 0317 	add.w	r3, r7, #23
2000130c:	f04f 0101 	mov.w	r1, #1
20001310:	9100      	str	r1, [sp, #0]
20001312:	f644 207c 	movw	r0, #19068	; 0x4a7c
20001316:	f2c2 0000 	movt	r0, #8192	; 0x2000
2000131a:	4611      	mov	r1, r2
2000131c:	f04f 0201 	mov.w	r2, #1
20001320:	f002 f86a 	bl	200033f8 <MSS_SPI_transfer_block>
                                    &command,
                                    sizeof(uint8_t),
                                    &status,
                                    sizeof(status) );
            return status;
20001324:	7dfb      	ldrb	r3, [r7, #23]
20001326:	e004      	b.n	20001332 <spi_flash_control_hw+0x646>
        }
        break;

        default:
              return SPI_FLASH_INVALID_ARGUMENTS;
20001328:	f04f 0303 	mov.w	r3, #3
2000132c:	e001      	b.n	20001332 <spi_flash_control_hw+0x646>
        break;
    }
    return 0;
2000132e:	f04f 0300 	mov.w	r3, #0
}
20001332:	4618      	mov	r0, r3
20001334:	f107 0750 	add.w	r7, r7, #80	; 0x50
20001338:	46bd      	mov	sp, r7
2000133a:	bd80      	pop	{r7, pc}

2000133c <spi_flash_read>:
(
    uint32_t address,
    uint8_t * rx_buffer,
    size_t size_in_bytes
)
{
2000133c:	b580      	push	{r7, lr}
2000133e:	b088      	sub	sp, #32
20001340:	af02      	add	r7, sp, #8
20001342:	60f8      	str	r0, [r7, #12]
20001344:	60b9      	str	r1, [r7, #8]
20001346:	607a      	str	r2, [r7, #4]
    uint8_t cmd_buffer[6];

    cmd_buffer[0] = READ_ARRAY_OPCODE;
20001348:	f04f 031b 	mov.w	r3, #27
2000134c:	743b      	strb	r3, [r7, #16]
    cmd_buffer[1] = (uint8_t)((address >> 16) & 0xFF);
2000134e:	68fb      	ldr	r3, [r7, #12]
20001350:	ea4f 4313 	mov.w	r3, r3, lsr #16
20001354:	b2db      	uxtb	r3, r3
20001356:	747b      	strb	r3, [r7, #17]
    cmd_buffer[2] = (uint8_t)((address >> 8) & 0xFF);;
20001358:	68fb      	ldr	r3, [r7, #12]
2000135a:	ea4f 2313 	mov.w	r3, r3, lsr #8
2000135e:	b2db      	uxtb	r3, r3
20001360:	74bb      	strb	r3, [r7, #18]
    cmd_buffer[3] = (uint8_t)(address & 0xFF);
20001362:	68fb      	ldr	r3, [r7, #12]
20001364:	b2db      	uxtb	r3, r3
20001366:	74fb      	strb	r3, [r7, #19]
    cmd_buffer[4] = DONT_CARE;
20001368:	f04f 0300 	mov.w	r3, #0
2000136c:	753b      	strb	r3, [r7, #20]
    cmd_buffer[5] = DONT_CARE;
2000136e:	f04f 0300 	mov.w	r3, #0
20001372:	757b      	strb	r3, [r7, #21]

    MSS_SPI_set_slave_select( SPI_INSTANCE, SPI_SLAVE );
20001374:	f644 207c 	movw	r0, #19068	; 0x4a7c
20001378:	f2c2 0000 	movt	r0, #8192	; 0x2000
2000137c:	f04f 0100 	mov.w	r1, #0
20001380:	f001 ff22 	bl	200031c8 <MSS_SPI_set_slave_select>
    if(wait_ready())
20001384:	f000 f950 	bl	20001628 <wait_ready>
20001388:	4603      	mov	r3, r0
2000138a:	2b00      	cmp	r3, #0
2000138c:	d002      	beq.n	20001394 <spi_flash_read+0x58>
        return SPI_FLASH_UNSUCCESS; 
2000138e:	f04f 0305 	mov.w	r3, #5
20001392:	e018      	b.n	200013c6 <spi_flash_read+0x8a>
    MSS_SPI_transfer_block( SPI_INSTANCE,
20001394:	687b      	ldr	r3, [r7, #4]
20001396:	b29a      	uxth	r2, r3
20001398:	f107 0310 	add.w	r3, r7, #16
2000139c:	9200      	str	r2, [sp, #0]
2000139e:	f644 207c 	movw	r0, #19068	; 0x4a7c
200013a2:	f2c2 0000 	movt	r0, #8192	; 0x2000
200013a6:	4619      	mov	r1, r3
200013a8:	f04f 0206 	mov.w	r2, #6
200013ac:	68bb      	ldr	r3, [r7, #8]
200013ae:	f002 f823 	bl	200033f8 <MSS_SPI_transfer_block>
                            cmd_buffer,
                            sizeof(cmd_buffer),
                            rx_buffer,
                            size_in_bytes );
    MSS_SPI_clear_slave_select( SPI_INSTANCE, SPI_SLAVE );
200013b2:	f644 207c 	movw	r0, #19068	; 0x4a7c
200013b6:	f2c2 0000 	movt	r0, #8192	; 0x2000
200013ba:	f04f 0100 	mov.w	r1, #0
200013be:	f001 ff77 	bl	200032b0 <MSS_SPI_clear_slave_select>
    return 0;
200013c2:	f04f 0300 	mov.w	r3, #0
}
200013c6:	4618      	mov	r0, r3
200013c8:	f107 0718 	add.w	r7, r7, #24
200013cc:	46bd      	mov	sp, r7
200013ce:	bd80      	pop	{r7, pc}

200013d0 <write_cmd_data>:
    const uint8_t * cmd_buffer,
    uint16_t cmd_byte_size,
    uint8_t * data_buffer,
    uint16_t data_byte_size
)
{
200013d0:	b580      	push	{r7, lr}
200013d2:	b086      	sub	sp, #24
200013d4:	af00      	add	r7, sp, #0
200013d6:	60f8      	str	r0, [r7, #12]
200013d8:	60b9      	str	r1, [r7, #8]
200013da:	603b      	str	r3, [r7, #0]
200013dc:	4613      	mov	r3, r2
200013de:	80fb      	strh	r3, [r7, #6]
    uint32_t transfer_size;

    transfer_size = cmd_byte_size + data_byte_size;
200013e0:	88fa      	ldrh	r2, [r7, #6]
200013e2:	8c3b      	ldrh	r3, [r7, #32]
200013e4:	4413      	add	r3, r2
200013e6:	617b      	str	r3, [r7, #20]


#ifdef USE_DMA_FOR_SPI_FLASH
    MSS_SPI_disable( this_spi );
200013e8:	68f8      	ldr	r0, [r7, #12]
200013ea:	f002 fab3 	bl	20003954 <MSS_SPI_disable>
    MSS_SPI_set_transfer_byte_count( this_spi, transfer_size );
200013ee:	697b      	ldr	r3, [r7, #20]
200013f0:	b29b      	uxth	r3, r3
200013f2:	68f8      	ldr	r0, [r7, #12]
200013f4:	4619      	mov	r1, r3
200013f6:	f002 fabf 	bl	20003978 <MSS_SPI_set_transfer_byte_count>

    PDMA_start
200013fa:	68ba      	ldr	r2, [r7, #8]
200013fc:	88fb      	ldrh	r3, [r7, #6]
200013fe:	f04f 0000 	mov.w	r0, #0
20001402:	4611      	mov	r1, r2
20001404:	f241 0214 	movw	r2, #4116	; 0x1014
20001408:	f2c4 0201 	movt	r2, #16385	; 0x4001
2000140c:	f002 fd6c 	bl	20003ee8 <PDMA_start>
            (uint32_t)cmd_buffer,   /* src_addr */
            SPI_DEST_TXBUFF,             /* dest_addr */
            cmd_byte_size           /* transfer_count */
        );

    PDMA_load_next_buffer
20001410:	683a      	ldr	r2, [r7, #0]
20001412:	8c3b      	ldrh	r3, [r7, #32]
20001414:	f04f 0000 	mov.w	r0, #0
20001418:	4611      	mov	r1, r2
2000141a:	f241 0214 	movw	r2, #4116	; 0x1014
2000141e:	f2c4 0201 	movt	r2, #16385	; 0x4001
20001422:	f002 fe7b 	bl	2000411c <PDMA_load_next_buffer>
            SPI_FLASH_DMA_CHANNEL,  /* channel_id */
            (uint32_t)data_buffer,  /* src_addr */
            SPI_DEST_TXBUFF,             /* dest_addr */
            data_byte_size          /* transfer_count */
        );
    MSS_SPI_enable( this_spi );
20001426:	68f8      	ldr	r0, [r7, #12]
20001428:	f002 fa82 	bl	20003930 <MSS_SPI_enable>
    while ( !MSS_SPI_tx_done(this_spi) )
2000142c:	68f8      	ldr	r0, [r7, #12]
2000142e:	f002 facb 	bl	200039c8 <MSS_SPI_tx_done>
20001432:	4603      	mov	r3, r0
20001434:	2b00      	cmp	r3, #0
20001436:	d0f9      	beq.n	2000142c <write_cmd_data+0x5c>
#error "Non-DMA Transfers are not implemented. USE only DMA for TX"
    }

#endif

}
20001438:	f107 0718 	add.w	r7, r7, #24
2000143c:	46bd      	mov	sp, r7
2000143e:	bd80      	pop	{r7, pc}

20001440 <spi_flash_write>:
(
    uint32_t address,
    uint8_t * write_buffer,
    size_t size_in_bytes
)
{
20001440:	b580      	push	{r7, lr}
20001442:	b08c      	sub	sp, #48	; 0x30
20001444:	af02      	add	r7, sp, #8
20001446:	60f8      	str	r0, [r7, #12]
20001448:	60b9      	str	r1, [r7, #8]
2000144a:	607a      	str	r2, [r7, #4]

    uint32_t in_buffer_idx;
    uint32_t nb_bytes_to_write;
    uint32_t target_addr;

    MSS_SPI_set_slave_select( SPI_INSTANCE, SPI_SLAVE );
2000144c:	f644 207c 	movw	r0, #19068	; 0x4a7c
20001450:	f2c2 0000 	movt	r0, #8192	; 0x2000
20001454:	f04f 0100 	mov.w	r1, #0
20001458:	f001 feb6 	bl	200031c8 <MSS_SPI_set_slave_select>

    /* Send Write Enable command */
    cmd_buffer[0] = WRITE_ENABLE_CMD;
2000145c:	f04f 0306 	mov.w	r3, #6
20001460:	753b      	strb	r3, [r7, #20]
    wait_ready();
20001462:	f000 f8e1 	bl	20001628 <wait_ready>
    MSS_SPI_transfer_block( SPI_INSTANCE, cmd_buffer, 1, 0, 0 );
20001466:	f107 0314 	add.w	r3, r7, #20
2000146a:	f04f 0200 	mov.w	r2, #0
2000146e:	9200      	str	r2, [sp, #0]
20001470:	f644 207c 	movw	r0, #19068	; 0x4a7c
20001474:	f2c2 0000 	movt	r0, #8192	; 0x2000
20001478:	4619      	mov	r1, r3
2000147a:	f04f 0201 	mov.w	r2, #1
2000147e:	f04f 0300 	mov.w	r3, #0
20001482:	f001 ffb9 	bl	200033f8 <MSS_SPI_transfer_block>

    /* Unprotect sector */
    cmd_buffer[0] = UNPROTECT_SECTOR_OPCODE;
20001486:	f04f 0339 	mov.w	r3, #57	; 0x39
2000148a:	753b      	strb	r3, [r7, #20]
    cmd_buffer[1] = (address >> 16) & 0xFF;
2000148c:	68fb      	ldr	r3, [r7, #12]
2000148e:	ea4f 4313 	mov.w	r3, r3, lsr #16
20001492:	b2db      	uxtb	r3, r3
20001494:	757b      	strb	r3, [r7, #21]
    cmd_buffer[2] = (address >> 8 ) & 0xFF;
20001496:	68fb      	ldr	r3, [r7, #12]
20001498:	ea4f 2313 	mov.w	r3, r3, lsr #8
2000149c:	b2db      	uxtb	r3, r3
2000149e:	75bb      	strb	r3, [r7, #22]
    cmd_buffer[3] = address & 0xFF;
200014a0:	68fb      	ldr	r3, [r7, #12]
200014a2:	b2db      	uxtb	r3, r3
200014a4:	75fb      	strb	r3, [r7, #23]
    wait_ready();
200014a6:	f000 f8bf 	bl	20001628 <wait_ready>
    MSS_SPI_transfer_block( SPI_INSTANCE,
200014aa:	f107 0314 	add.w	r3, r7, #20
200014ae:	f04f 0200 	mov.w	r2, #0
200014b2:	9200      	str	r2, [sp, #0]
200014b4:	f644 207c 	movw	r0, #19068	; 0x4a7c
200014b8:	f2c2 0000 	movt	r0, #8192	; 0x2000
200014bc:	4619      	mov	r1, r3
200014be:	f04f 0204 	mov.w	r2, #4
200014c2:	f04f 0300 	mov.w	r3, #0
200014c6:	f001 ff97 	bl	200033f8 <MSS_SPI_transfer_block>
                            sizeof(cmd_buffer),
                            0,
                            0 );

    /* Send Write Enable command */
    cmd_buffer[0] = WRITE_ENABLE_CMD;
200014ca:	f04f 0306 	mov.w	r3, #6
200014ce:	753b      	strb	r3, [r7, #20]
    if(wait_ready())
200014d0:	f000 f8aa 	bl	20001628 <wait_ready>
200014d4:	4603      	mov	r3, r0
200014d6:	2b00      	cmp	r3, #0
200014d8:	d002      	beq.n	200014e0 <spi_flash_write+0xa0>
        return SPI_FLASH_UNSUCCESS; 
200014da:	f04f 0305 	mov.w	r3, #5
200014de:	e09d      	b.n	2000161c <spi_flash_write+0x1dc>

    MSS_SPI_transfer_block( SPI_INSTANCE, cmd_buffer, 1, 0, 0 );
200014e0:	f107 0314 	add.w	r3, r7, #20
200014e4:	f04f 0200 	mov.w	r2, #0
200014e8:	9200      	str	r2, [sp, #0]
200014ea:	f644 207c 	movw	r0, #19068	; 0x4a7c
200014ee:	f2c2 0000 	movt	r0, #8192	; 0x2000
200014f2:	4619      	mov	r1, r3
200014f4:	f04f 0201 	mov.w	r2, #1
200014f8:	f04f 0300 	mov.w	r3, #0
200014fc:	f001 ff7c 	bl	200033f8 <MSS_SPI_transfer_block>

    /**/
    in_buffer_idx = 0;
20001500:	f04f 0300 	mov.w	r3, #0
20001504:	61bb      	str	r3, [r7, #24]
    nb_bytes_to_write = size_in_bytes;
20001506:	687b      	ldr	r3, [r7, #4]
20001508:	61fb      	str	r3, [r7, #28]
    target_addr = address;
2000150a:	68fb      	ldr	r3, [r7, #12]
2000150c:	623b      	str	r3, [r7, #32]

    while ( in_buffer_idx < size_in_bytes )
2000150e:	e05c      	b.n	200015ca <spi_flash_write+0x18a>
    {
        uint32_t size_left;
        nb_bytes_to_write = 0x100 - (target_addr & 0xFF);
20001510:	6a3b      	ldr	r3, [r7, #32]
20001512:	f003 03ff 	and.w	r3, r3, #255	; 0xff
20001516:	f5c3 7380 	rsb	r3, r3, #256	; 0x100
2000151a:	61fb      	str	r3, [r7, #28]
        /* adjust max possible size to page boundary. */
        size_left = size_in_bytes - in_buffer_idx;
2000151c:	687a      	ldr	r2, [r7, #4]
2000151e:	69bb      	ldr	r3, [r7, #24]
20001520:	ebc3 0302 	rsb	r3, r3, r2
20001524:	627b      	str	r3, [r7, #36]	; 0x24
        if ( size_left < nb_bytes_to_write )
20001526:	6a7a      	ldr	r2, [r7, #36]	; 0x24
20001528:	69fb      	ldr	r3, [r7, #28]
2000152a:	429a      	cmp	r2, r3
2000152c:	d201      	bcs.n	20001532 <spi_flash_write+0xf2>
        {
            nb_bytes_to_write = size_left;
2000152e:	6a7b      	ldr	r3, [r7, #36]	; 0x24
20001530:	61fb      	str	r3, [r7, #28]
        }

        if(wait_ready())
20001532:	f000 f879 	bl	20001628 <wait_ready>
20001536:	4603      	mov	r3, r0
20001538:	2b00      	cmp	r3, #0
2000153a:	d002      	beq.n	20001542 <spi_flash_write+0x102>
            return SPI_FLASH_UNSUCCESS; 
2000153c:	f04f 0305 	mov.w	r3, #5
20001540:	e06c      	b.n	2000161c <spi_flash_write+0x1dc>

        /* Send Write Enable command */
        cmd_buffer[0] = WRITE_ENABLE_CMD;
20001542:	f04f 0306 	mov.w	r3, #6
20001546:	753b      	strb	r3, [r7, #20]
        MSS_SPI_transfer_block( SPI_INSTANCE, cmd_buffer, 1, 0, 0 );
20001548:	f107 0314 	add.w	r3, r7, #20
2000154c:	f04f 0200 	mov.w	r2, #0
20001550:	9200      	str	r2, [sp, #0]
20001552:	f644 207c 	movw	r0, #19068	; 0x4a7c
20001556:	f2c2 0000 	movt	r0, #8192	; 0x2000
2000155a:	4619      	mov	r1, r3
2000155c:	f04f 0201 	mov.w	r2, #1
20001560:	f04f 0300 	mov.w	r3, #0
20001564:	f001 ff48 	bl	200033f8 <MSS_SPI_transfer_block>

        /* Program page */
        if(wait_ready())
20001568:	f000 f85e 	bl	20001628 <wait_ready>
2000156c:	4603      	mov	r3, r0
2000156e:	2b00      	cmp	r3, #0
20001570:	d002      	beq.n	20001578 <spi_flash_write+0x138>
            return SPI_FLASH_UNSUCCESS; 
20001572:	f04f 0305 	mov.w	r3, #5
20001576:	e051      	b.n	2000161c <spi_flash_write+0x1dc>


        cmd_buffer[0] = PROGRAM_PAGE_CMD;
20001578:	f04f 0302 	mov.w	r3, #2
2000157c:	753b      	strb	r3, [r7, #20]
        cmd_buffer[1] = (target_addr >> 16) & 0xFF;
2000157e:	6a3b      	ldr	r3, [r7, #32]
20001580:	ea4f 4313 	mov.w	r3, r3, lsr #16
20001584:	b2db      	uxtb	r3, r3
20001586:	757b      	strb	r3, [r7, #21]
        cmd_buffer[2] = (target_addr >> 8 ) & 0xFF;
20001588:	6a3b      	ldr	r3, [r7, #32]
2000158a:	ea4f 2313 	mov.w	r3, r3, lsr #8
2000158e:	b2db      	uxtb	r3, r3
20001590:	75bb      	strb	r3, [r7, #22]
        cmd_buffer[3] = target_addr & 0xFF;
20001592:	6a3b      	ldr	r3, [r7, #32]
20001594:	b2db      	uxtb	r3, r3
20001596:	75fb      	strb	r3, [r7, #23]

        write_cmd_data
20001598:	68ba      	ldr	r2, [r7, #8]
2000159a:	69bb      	ldr	r3, [r7, #24]
2000159c:	4413      	add	r3, r2
2000159e:	69fa      	ldr	r2, [r7, #28]
200015a0:	b291      	uxth	r1, r2
200015a2:	f107 0214 	add.w	r2, r7, #20
200015a6:	9100      	str	r1, [sp, #0]
200015a8:	f644 207c 	movw	r0, #19068	; 0x4a7c
200015ac:	f2c2 0000 	movt	r0, #8192	; 0x2000
200015b0:	4611      	mov	r1, r2
200015b2:	f04f 0204 	mov.w	r2, #4
200015b6:	f7ff ff0b 	bl	200013d0 <write_cmd_data>
            sizeof(cmd_buffer),
            &write_buffer[in_buffer_idx],
            nb_bytes_to_write
          );

        target_addr += nb_bytes_to_write;
200015ba:	6a3a      	ldr	r2, [r7, #32]
200015bc:	69fb      	ldr	r3, [r7, #28]
200015be:	4413      	add	r3, r2
200015c0:	623b      	str	r3, [r7, #32]
        in_buffer_idx += nb_bytes_to_write;
200015c2:	69ba      	ldr	r2, [r7, #24]
200015c4:	69fb      	ldr	r3, [r7, #28]
200015c6:	4413      	add	r3, r2
200015c8:	61bb      	str	r3, [r7, #24]
    /**/
    in_buffer_idx = 0;
    nb_bytes_to_write = size_in_bytes;
    target_addr = address;

    while ( in_buffer_idx < size_in_bytes )
200015ca:	69ba      	ldr	r2, [r7, #24]
200015cc:	687b      	ldr	r3, [r7, #4]
200015ce:	429a      	cmp	r2, r3
200015d0:	d39e      	bcc.n	20001510 <spi_flash_write+0xd0>
        target_addr += nb_bytes_to_write;
        in_buffer_idx += nb_bytes_to_write;
    }

    /* Send Write Disable command. */
    cmd_buffer[0] = WRITE_DISABLE_CMD;
200015d2:	f04f 0304 	mov.w	r3, #4
200015d6:	753b      	strb	r3, [r7, #20]

    if(wait_ready())
200015d8:	f000 f826 	bl	20001628 <wait_ready>
200015dc:	4603      	mov	r3, r0
200015de:	2b00      	cmp	r3, #0
200015e0:	d002      	beq.n	200015e8 <spi_flash_write+0x1a8>
        return SPI_FLASH_UNSUCCESS; 
200015e2:	f04f 0305 	mov.w	r3, #5
200015e6:	e019      	b.n	2000161c <spi_flash_write+0x1dc>

    MSS_SPI_transfer_block( SPI_INSTANCE, cmd_buffer, 1, 0, 0 );
200015e8:	f107 0314 	add.w	r3, r7, #20
200015ec:	f04f 0200 	mov.w	r2, #0
200015f0:	9200      	str	r2, [sp, #0]
200015f2:	f644 207c 	movw	r0, #19068	; 0x4a7c
200015f6:	f2c2 0000 	movt	r0, #8192	; 0x2000
200015fa:	4619      	mov	r1, r3
200015fc:	f04f 0201 	mov.w	r2, #1
20001600:	f04f 0300 	mov.w	r3, #0
20001604:	f001 fef8 	bl	200033f8 <MSS_SPI_transfer_block>
    MSS_SPI_clear_slave_select( SPI_INSTANCE, SPI_SLAVE );
20001608:	f644 207c 	movw	r0, #19068	; 0x4a7c
2000160c:	f2c2 0000 	movt	r0, #8192	; 0x2000
20001610:	f04f 0100 	mov.w	r1, #0
20001614:	f001 fe4c 	bl	200032b0 <MSS_SPI_clear_slave_select>
    return 0;
20001618:	f04f 0300 	mov.w	r3, #0
}
2000161c:	4618      	mov	r0, r3
2000161e:	f107 0728 	add.w	r7, r7, #40	; 0x28
20001622:	46bd      	mov	sp, r7
20001624:	bd80      	pop	{r7, pc}
20001626:	bf00      	nop

20001628 <wait_ready>:

/******************************************************************************
 * This function waits for the SPI operation to complete
 ******************************************************************************/
static uint8_t wait_ready( void )
{
20001628:	b580      	push	{r7, lr}
2000162a:	b084      	sub	sp, #16
2000162c:	af02      	add	r7, sp, #8
    uint8_t ready_bit = 1;
2000162e:	f04f 0301 	mov.w	r3, #1
20001632:	71fb      	strb	r3, [r7, #7]
    uint8_t command = READ_STATUS;
20001634:	f04f 0305 	mov.w	r3, #5
20001638:	71bb      	strb	r3, [r7, #6]

    do {
        MSS_SPI_transfer_block( SPI_INSTANCE,
2000163a:	f107 0206 	add.w	r2, r7, #6
2000163e:	f107 0307 	add.w	r3, r7, #7
20001642:	f04f 0101 	mov.w	r1, #1
20001646:	9100      	str	r1, [sp, #0]
20001648:	f644 207c 	movw	r0, #19068	; 0x4a7c
2000164c:	f2c2 0000 	movt	r0, #8192	; 0x2000
20001650:	4611      	mov	r1, r2
20001652:	f04f 0201 	mov.w	r2, #1
20001656:	f001 fecf 	bl	200033f8 <MSS_SPI_transfer_block>
                                &command, 
                                sizeof(command),
                                &ready_bit,
                                sizeof(ready_bit) );
        ready_bit = ready_bit & READY_BIT_MASK;
2000165a:	79fb      	ldrb	r3, [r7, #7]
2000165c:	f003 0301 	and.w	r3, r3, #1
20001660:	71fb      	strb	r3, [r7, #7]
    } while( ready_bit == 1 );
20001662:	79fb      	ldrb	r3, [r7, #7]
20001664:	2b01      	cmp	r3, #1
20001666:	d0e8      	beq.n	2000163a <wait_ready+0x12>

    return (ready_bit);
20001668:	79fb      	ldrb	r3, [r7, #7]
}
2000166a:	4618      	mov	r0, r3
2000166c:	f107 0708 	add.w	r7, r7, #8
20001670:	46bd      	mov	sp, r7
20001672:	bd80      	pop	{r7, pc}

20001674 <emc_init>:
extern uint32_t SystemFrequency;
/*****************************************************************************/
/* See nor.h for details. */
/*****************************************************************************/
void emc_init(void)
{
20001674:	b480      	push	{r7}
20001676:	af00      	add	r7, sp, #0
	if(SystemFrequency <= EIGHTY_MHZ)
20001678:	f644 03d8 	movw	r3, #18648	; 0x48d8
2000167c:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001680:	681a      	ldr	r2, [r3, #0]
20001682:	f24b 4300 	movw	r3, #46080	; 0xb400
20001686:	f2c0 43c4 	movt	r3, #1220	; 0x4c4
2000168a:	429a      	cmp	r2, r3
2000168c:	d80e      	bhi.n	200016ac <emc_init+0x38>
    {
	   *(volatile unsigned long *)0xE0042040 = 0x8D;
2000168e:	f242 0340 	movw	r3, #8256	; 0x2040
20001692:	f2ce 0304 	movt	r3, #57348	; 0xe004
20001696:	f04f 028d 	mov.w	r2, #141	; 0x8d
2000169a:	601a      	str	r2, [r3, #0]
       *(volatile unsigned long *)0xE0042044 = 0xA7;
2000169c:	f242 0344 	movw	r3, #8260	; 0x2044
200016a0:	f2ce 0304 	movt	r3, #57348	; 0xe004
200016a4:	f04f 02a7 	mov.w	r2, #167	; 0xa7
200016a8:	601a      	str	r2, [r3, #0]
200016aa:	e036      	b.n	2000171a <emc_init+0xa6>
    }
    else if((SystemFrequency > EIGHTY_MHZ) &&
200016ac:	f644 03d8 	movw	r3, #18648	; 0x48d8
200016b0:	f2c2 0300 	movt	r3, #8192	; 0x2000
200016b4:	681a      	ldr	r2, [r3, #0]
200016b6:	f24b 4300 	movw	r3, #46080	; 0xb400
200016ba:	f2c0 43c4 	movt	r3, #1220	; 0x4c4
200016be:	429a      	cmp	r2, r3
200016c0:	d919      	bls.n	200016f6 <emc_init+0x82>
    		(SystemFrequency <= HUNDRED_MHZ))
200016c2:	f644 03d8 	movw	r3, #18648	; 0x48d8
200016c6:	f2c2 0300 	movt	r3, #8192	; 0x2000
200016ca:	681a      	ldr	r2, [r3, #0]
	if(SystemFrequency <= EIGHTY_MHZ)
    {
	   *(volatile unsigned long *)0xE0042040 = 0x8D;
       *(volatile unsigned long *)0xE0042044 = 0xA7;
    }
    else if((SystemFrequency > EIGHTY_MHZ) &&
200016cc:	f24e 1300 	movw	r3, #57600	; 0xe100
200016d0:	f2c0 53f5 	movt	r3, #1525	; 0x5f5
200016d4:	429a      	cmp	r2, r3
200016d6:	d80e      	bhi.n	200016f6 <emc_init+0x82>
    		(SystemFrequency <= HUNDRED_MHZ))
    {
       *(volatile unsigned long *)0xE0042040 = 0x8D;
200016d8:	f242 0340 	movw	r3, #8256	; 0x2040
200016dc:	f2ce 0304 	movt	r3, #57348	; 0xe004
200016e0:	f04f 028d 	mov.w	r2, #141	; 0x8d
200016e4:	601a      	str	r2, [r3, #0]
       *(volatile unsigned long *)0xE0042044 = 0xAF;
200016e6:	f242 0344 	movw	r3, #8260	; 0x2044
200016ea:	f2ce 0304 	movt	r3, #57348	; 0xe004
200016ee:	f04f 02af 	mov.w	r2, #175	; 0xaf
200016f2:	601a      	str	r2, [r3, #0]
	if(SystemFrequency <= EIGHTY_MHZ)
    {
	   *(volatile unsigned long *)0xE0042040 = 0x8D;
       *(volatile unsigned long *)0xE0042044 = 0xA7;
    }
    else if((SystemFrequency > EIGHTY_MHZ) &&
200016f4:	e011      	b.n	2000171a <emc_init+0xa6>
       *(volatile unsigned long *)0xE0042040 = 0x8D;
       *(volatile unsigned long *)0xE0042044 = 0xAF;
    }
    else
    {
        *(volatile unsigned long *)0xE0042040 = 0x00207FFD;
200016f6:	f242 0340 	movw	r3, #8256	; 0x2040
200016fa:	f2ce 0304 	movt	r3, #57348	; 0xe004
200016fe:	f647 72fd 	movw	r2, #32765	; 0x7ffd
20001702:	f2c0 0220 	movt	r2, #32
20001706:	601a      	str	r2, [r3, #0]
        *(volatile unsigned long *)0xE0042044 = 0x00265557;
20001708:	f242 0344 	movw	r3, #8260	; 0x2044
2000170c:	f2ce 0304 	movt	r3, #57348	; 0xe004
20001710:	f245 5257 	movw	r2, #21847	; 0x5557
20001714:	f2c0 0226 	movt	r2, #38	; 0x26
20001718:	601a      	str	r2, [r3, #0]

    }
}
2000171a:	46bd      	mov	sp, r7
2000171c:	bc80      	pop	{r7}
2000171e:	4770      	bx	lr

20001720 <flash_delay>:

static void flash_delay(void)
{
20001720:	b480      	push	{r7}
20001722:	b083      	sub	sp, #12
20001724:	af00      	add	r7, sp, #0
    uint32_t i;
    volatile uint32_t a=0;
20001726:	f04f 0300 	mov.w	r3, #0
2000172a:	603b      	str	r3, [r7, #0]
    for (i=0; i<40; i++)
2000172c:	f04f 0300 	mov.w	r3, #0
20001730:	607b      	str	r3, [r7, #4]
20001732:	e007      	b.n	20001744 <flash_delay+0x24>
    a++;
20001734:	683b      	ldr	r3, [r7, #0]
20001736:	f103 0301 	add.w	r3, r3, #1
2000173a:	603b      	str	r3, [r7, #0]

static void flash_delay(void)
{
    uint32_t i;
    volatile uint32_t a=0;
    for (i=0; i<40; i++)
2000173c:	687b      	ldr	r3, [r7, #4]
2000173e:	f103 0301 	add.w	r3, r3, #1
20001742:	607b      	str	r3, [r7, #4]
20001744:	687b      	ldr	r3, [r7, #4]
20001746:	2b27      	cmp	r3, #39	; 0x27
20001748:	d9f4      	bls.n	20001734 <flash_delay+0x14>
    a++;
}
2000174a:	f107 070c 	add.w	r7, r7, #12
2000174e:	46bd      	mov	sp, r7
20001750:	bc80      	pop	{r7}
20001752:	4770      	bx	lr

20001754 <status_wait>:

static int status_wait (uint32_t address)
{
20001754:	b580      	push	{r7, lr}
20001756:	b084      	sub	sp, #16
20001758:	af00      	add	r7, sp, #0
2000175a:	6078      	str	r0, [r7, #4]
    volatile uint16_t status;
    uint32_t a=0;
2000175c:	f04f 0300 	mov.w	r3, #0
20001760:	60fb      	str	r3, [r7, #12]

    do
    {
        a++;
20001762:	68fb      	ldr	r3, [r7, #12]
20001764:	f103 0301 	add.w	r3, r3, #1
20001768:	60fb      	str	r3, [r7, #12]
        flash_delay();
2000176a:	f7ff ffd9 	bl	20001720 <flash_delay>
        status = *((volatile uint16_t *)address);
2000176e:	687b      	ldr	r3, [r7, #4]
20001770:	881b      	ldrh	r3, [r3, #0]
20001772:	b29b      	uxth	r3, r3
20001774:	817b      	strh	r3, [r7, #10]
    } while (((status) != 0x0080) && (a < 0x7ffffff));
20001776:	897b      	ldrh	r3, [r7, #10]
20001778:	b29b      	uxth	r3, r3
2000177a:	2b80      	cmp	r3, #128	; 0x80
2000177c:	d006      	beq.n	2000178c <status_wait+0x38>
2000177e:	68fa      	ldr	r2, [r7, #12]
20001780:	f64f 73fe 	movw	r3, #65534	; 0xfffe
20001784:	f2c0 73ff 	movt	r3, #2047	; 0x7ff
20001788:	429a      	cmp	r2, r3
2000178a:	d9ea      	bls.n	20001762 <status_wait+0xe>
    flash_delay();
2000178c:	f7ff ffc8 	bl	20001720 <flash_delay>
    if( (a >=0x7ffffff) && (status != 0x80))
20001790:	68fa      	ldr	r2, [r7, #12]
20001792:	f64f 73fe 	movw	r3, #65534	; 0xfffe
20001796:	f2c0 73ff 	movt	r3, #2047	; 0x7ff
2000179a:	429a      	cmp	r2, r3
2000179c:	d906      	bls.n	200017ac <status_wait+0x58>
2000179e:	897b      	ldrh	r3, [r7, #10]
200017a0:	b29b      	uxth	r3, r3
200017a2:	2b80      	cmp	r3, #128	; 0x80
200017a4:	d002      	beq.n	200017ac <status_wait+0x58>
    {
       return 1;
200017a6:	f04f 0301 	mov.w	r3, #1
200017aa:	e001      	b.n	200017b0 <status_wait+0x5c>
    }

    return 0;
200017ac:	f04f 0300 	mov.w	r3, #0
}
200017b0:	4618      	mov	r0, r3
200017b2:	f107 0710 	add.w	r7, r7, #16
200017b6:	46bd      	mov	sp, r7
200017b8:	bd80      	pop	{r7, pc}
200017ba:	bf00      	nop

200017bc <emc_flash_block_erase>:
emc_flash_status_t
emc_flash_block_erase
(
    uint16_t *blockAddr
)
{
200017bc:	b580      	push	{r7, lr}
200017be:	b082      	sub	sp, #8
200017c0:	af00      	add	r7, sp, #0
200017c2:	6078      	str	r0, [r7, #4]

    *(volatile uint16_t*)blockAddr = CLEAR_STATUS_REG;
200017c4:	687b      	ldr	r3, [r7, #4]
200017c6:	f04f 0250 	mov.w	r2, #80	; 0x50
200017ca:	801a      	strh	r2, [r3, #0]
    *(volatile uint16_t*)blockAddr = UNLOCK_BLOCK;
200017cc:	687b      	ldr	r3, [r7, #4]
200017ce:	f04f 0260 	mov.w	r2, #96	; 0x60
200017d2:	801a      	strh	r2, [r3, #0]
    *(volatile uint16_t*)blockAddr = PROGRAM_RESUME;
200017d4:	687b      	ldr	r3, [r7, #4]
200017d6:	f04f 02d0 	mov.w	r2, #208	; 0xd0
200017da:	801a      	strh	r2, [r3, #0]
    *(volatile uint16_t*)blockAddr = READ_STATUS_REGISTER;
200017dc:	687b      	ldr	r3, [r7, #4]
200017de:	f04f 0270 	mov.w	r2, #112	; 0x70
200017e2:	801a      	strh	r2, [r3, #0]

    if(status_wait((uint32_t)blockAddr))
200017e4:	687b      	ldr	r3, [r7, #4]
200017e6:	4618      	mov	r0, r3
200017e8:	f7ff ffb4 	bl	20001754 <status_wait>
200017ec:	4603      	mov	r3, r0
200017ee:	2b00      	cmp	r3, #0
200017f0:	d004      	beq.n	200017fc <emc_flash_block_erase+0x40>
    {
        return (*((volatile uint16_t *)blockAddr));
200017f2:	687b      	ldr	r3, [r7, #4]
200017f4:	881b      	ldrh	r3, [r3, #0]
200017f6:	b29b      	uxth	r3, r3
200017f8:	b2db      	uxtb	r3, r3
200017fa:	e021      	b.n	20001840 <emc_flash_block_erase+0x84>
    }

    *(volatile uint16_t*)blockAddr = CLEAR_STATUS_REG;
200017fc:	687b      	ldr	r3, [r7, #4]
200017fe:	f04f 0250 	mov.w	r2, #80	; 0x50
20001802:	801a      	strh	r2, [r3, #0]
    *(volatile uint16_t*)blockAddr = READ_ARRAY;
20001804:	687b      	ldr	r3, [r7, #4]
20001806:	f04f 02ff 	mov.w	r2, #255	; 0xff
2000180a:	801a      	strh	r2, [r3, #0]
    *(volatile uint16_t*)blockAddr = BLOCK_ERASE;
2000180c:	687b      	ldr	r3, [r7, #4]
2000180e:	f04f 0220 	mov.w	r2, #32
20001812:	801a      	strh	r2, [r3, #0]
    *(volatile uint16_t*)blockAddr = ERASE_RESUME;
20001814:	687b      	ldr	r3, [r7, #4]
20001816:	f04f 02d0 	mov.w	r2, #208	; 0xd0
2000181a:	801a      	strh	r2, [r3, #0]
    *(volatile uint16_t*)blockAddr = READ_STATUS_REGISTER;
2000181c:	687b      	ldr	r3, [r7, #4]
2000181e:	f04f 0270 	mov.w	r2, #112	; 0x70
20001822:	801a      	strh	r2, [r3, #0]

    if(status_wait((uint32_t)blockAddr))
20001824:	687b      	ldr	r3, [r7, #4]
20001826:	4618      	mov	r0, r3
20001828:	f7ff ff94 	bl	20001754 <status_wait>
2000182c:	4603      	mov	r3, r0
2000182e:	2b00      	cmp	r3, #0
20001830:	d004      	beq.n	2000183c <emc_flash_block_erase+0x80>
    {
        return (*((volatile uint16_t *)blockAddr));
20001832:	687b      	ldr	r3, [r7, #4]
20001834:	881b      	ldrh	r3, [r3, #0]
20001836:	b29b      	uxth	r3, r3
20001838:	b2db      	uxtb	r3, r3
2000183a:	e001      	b.n	20001840 <emc_flash_block_erase+0x84>
    }
    return 0;
2000183c:	f04f 0300 	mov.w	r3, #0
}
20001840:	4618      	mov	r0, r3
20001842:	f107 0708 	add.w	r7, r7, #8
20001846:	46bd      	mov	sp, r7
20001848:	bd80      	pop	{r7, pc}
2000184a:	bf00      	nop

2000184c <emc_flash_chip_erase>:
emc_flash_status_t
emc_flash_chip_erase
(
    uint32_t startAddr
)
{
2000184c:	b580      	push	{r7, lr}
2000184e:	b086      	sub	sp, #24
20001850:	af00      	add	r7, sp, #0
20001852:	6078      	str	r0, [r7, #4]
    uint32_t status = 0;
20001854:	f04f 0300 	mov.w	r3, #0
20001858:	60fb      	str	r3, [r7, #12]
    uint32_t blkNumber = 0;
2000185a:	f04f 0300 	mov.w	r3, #0
2000185e:	613b      	str	r3, [r7, #16]
    uint16_t *baseAddr = (uint16_t *) startAddr;
20001860:	687b      	ldr	r3, [r7, #4]
20001862:	617b      	str	r3, [r7, #20]

    for(blkNumber=0; blkNumber < NO_OF_BLOCKS; blkNumber++)
20001864:	f04f 0300 	mov.w	r3, #0
20001868:	613b      	str	r3, [r7, #16]
2000186a:	e015      	b.n	20001898 <emc_flash_chip_erase+0x4c>
    {
        status += emc_flash_block_erase(baseAddr + (blkNumber)*(0x10000) );
2000186c:	693b      	ldr	r3, [r7, #16]
2000186e:	ea4f 4243 	mov.w	r2, r3, lsl #17
20001872:	697b      	ldr	r3, [r7, #20]
20001874:	4413      	add	r3, r2
20001876:	4618      	mov	r0, r3
20001878:	f7ff ffa0 	bl	200017bc <emc_flash_block_erase>
2000187c:	4603      	mov	r3, r0
2000187e:	68fa      	ldr	r2, [r7, #12]
20001880:	4413      	add	r3, r2
20001882:	60fb      	str	r3, [r7, #12]
        if (status > 0)
20001884:	68fb      	ldr	r3, [r7, #12]
20001886:	2b00      	cmp	r3, #0
20001888:	d002      	beq.n	20001890 <emc_flash_chip_erase+0x44>
        {
            return status;
2000188a:	68fb      	ldr	r3, [r7, #12]
2000188c:	b2db      	uxtb	r3, r3
2000188e:	e008      	b.n	200018a2 <emc_flash_chip_erase+0x56>
{
    uint32_t status = 0;
    uint32_t blkNumber = 0;
    uint16_t *baseAddr = (uint16_t *) startAddr;

    for(blkNumber=0; blkNumber < NO_OF_BLOCKS; blkNumber++)
20001890:	693b      	ldr	r3, [r7, #16]
20001892:	f103 0301 	add.w	r3, r3, #1
20001896:	613b      	str	r3, [r7, #16]
20001898:	693b      	ldr	r3, [r7, #16]
2000189a:	2b3f      	cmp	r3, #63	; 0x3f
2000189c:	d9e6      	bls.n	2000186c <emc_flash_chip_erase+0x20>
        if (status > 0)
        {
            return status;
        }
    }
    return status;
2000189e:	68fb      	ldr	r3, [r7, #12]
200018a0:	b2db      	uxtb	r3, r3
}
200018a2:	4618      	mov	r0, r3
200018a4:	f107 0718 	add.w	r7, r7, #24
200018a8:	46bd      	mov	sp, r7
200018aa:	bd80      	pop	{r7, pc}

200018ac <emc_flash_write>:
(
    uint32_t start_addr,
    const uint8_t * p_data,
    size_t nb_bytes
)
{
200018ac:	b580      	push	{r7, lr}
200018ae:	b08a      	sub	sp, #40	; 0x28
200018b0:	af00      	add	r7, sp, #0
200018b2:	60f8      	str	r0, [r7, #12]
200018b4:	60b9      	str	r1, [r7, #8]
200018b6:	607a      	str	r2, [r7, #4]
    volatile uint16_t *currAddr;
    uint16_t *buffPtr = (uint16_t *)p_data;
200018b8:	68bb      	ldr	r3, [r7, #8]
200018ba:	617b      	str	r3, [r7, #20]
    int16_t nb_left_bytes = nb_bytes;
200018bc:	687b      	ldr	r3, [r7, #4]
200018be:	837b      	strh	r3, [r7, #26]
    uint32_t ii =0, temp =0;
200018c0:	f04f 0300 	mov.w	r3, #0
200018c4:	61fb      	str	r3, [r7, #28]
200018c6:	f04f 0300 	mov.w	r3, #0
200018ca:	623b      	str	r3, [r7, #32]
    uint16_t loopCnt = 0;
200018cc:	f04f 0300 	mov.w	r3, #0
200018d0:	84fb      	strh	r3, [r7, #38]	; 0x26

    if( (start_addr == (uint32_t)NULL) ||
200018d2:	68fb      	ldr	r3, [r7, #12]
200018d4:	2b00      	cmp	r3, #0
200018d6:	d005      	beq.n	200018e4 <emc_flash_write+0x38>
200018d8:	68bb      	ldr	r3, [r7, #8]
200018da:	2b00      	cmp	r3, #0
200018dc:	d002      	beq.n	200018e4 <emc_flash_write+0x38>
200018de:	687b      	ldr	r3, [r7, #4]
200018e0:	2b00      	cmp	r3, #0
200018e2:	d102      	bne.n	200018ea <emc_flash_write+0x3e>
         (p_data == NULL)      ||
         (nb_bytes <= 0))
    {
         return NOR_INVALID_ARGUMENTS;
200018e4:	f04f 0341 	mov.w	r3, #65	; 0x41
200018e8:	e0dd      	b.n	20001aa6 <emc_flash_write+0x1fa>
    }
    if( ! (IS_VALID_ADDR(start_addr)))
200018ea:	68fa      	ldr	r2, [r7, #12]
200018ec:	f06f 430b 	mvn.w	r3, #2332033024	; 0x8b000000
200018f0:	429a      	cmp	r2, r3
200018f2:	d804      	bhi.n	200018fe <emc_flash_write+0x52>
200018f4:	68fa      	ldr	r2, [r7, #12]
200018f6:	f06f 430c 	mvn.w	r3, #2348810240	; 0x8c000000
200018fa:	429a      	cmp	r2, r3
200018fc:	d802      	bhi.n	20001904 <emc_flash_write+0x58>
    {
         return NOR_INVALID_ADDRESS;
200018fe:	f04f 0342 	mov.w	r3, #66	; 0x42
20001902:	e0d0      	b.n	20001aa6 <emc_flash_write+0x1fa>
    }

    currAddr = (volatile uint16_t *)start_addr;
20001904:	68fb      	ldr	r3, [r7, #12]
20001906:	613b      	str	r3, [r7, #16]

    loopCnt = nb_bytes/BUFFER_SIZE_BYTES;
20001908:	687b      	ldr	r3, [r7, #4]
2000190a:	ea4f 1353 	mov.w	r3, r3, lsr #5
2000190e:	84fb      	strh	r3, [r7, #38]	; 0x26

    for(ii=0; ii<loopCnt; ii++)
20001910:	f04f 0300 	mov.w	r3, #0
20001914:	61fb      	str	r3, [r7, #28]
20001916:	e074      	b.n	20001a02 <emc_flash_write+0x156>
    {
        *(volatile uint16_t *)currAddr = CLEAR_STATUS_REG;
20001918:	693b      	ldr	r3, [r7, #16]
2000191a:	f04f 0250 	mov.w	r2, #80	; 0x50
2000191e:	801a      	strh	r2, [r3, #0]
        *(volatile uint16_t *)currAddr = READ_ARRAY;
20001920:	693b      	ldr	r3, [r7, #16]
20001922:	f04f 02ff 	mov.w	r2, #255	; 0xff
20001926:	801a      	strh	r2, [r3, #0]
        *(volatile uint16_t *)currAddr = BUFFERED_PROGRAM;
20001928:	693b      	ldr	r3, [r7, #16]
2000192a:	f04f 02e8 	mov.w	r2, #232	; 0xe8
2000192e:	801a      	strh	r2, [r3, #0]

        *(volatile uint16_t *)currAddr = BUFFER_SIZE_WORDS -1;
20001930:	693b      	ldr	r3, [r7, #16]
20001932:	f04f 020f 	mov.w	r2, #15
20001936:	801a      	strh	r2, [r3, #0]
        for(temp=0; temp<BUFFER_SIZE_WORDS; temp++)
20001938:	f04f 0300 	mov.w	r3, #0
2000193c:	623b      	str	r3, [r7, #32]
2000193e:	e00f      	b.n	20001960 <emc_flash_write+0xb4>
        {
             *(currAddr +temp ) = *(uint16_t *) (buffPtr+temp);
20001940:	6a3b      	ldr	r3, [r7, #32]
20001942:	ea4f 0243 	mov.w	r2, r3, lsl #1
20001946:	693b      	ldr	r3, [r7, #16]
20001948:	4413      	add	r3, r2
2000194a:	6a3a      	ldr	r2, [r7, #32]
2000194c:	ea4f 0142 	mov.w	r1, r2, lsl #1
20001950:	697a      	ldr	r2, [r7, #20]
20001952:	440a      	add	r2, r1
20001954:	8812      	ldrh	r2, [r2, #0]
20001956:	801a      	strh	r2, [r3, #0]
        *(volatile uint16_t *)currAddr = CLEAR_STATUS_REG;
        *(volatile uint16_t *)currAddr = READ_ARRAY;
        *(volatile uint16_t *)currAddr = BUFFERED_PROGRAM;

        *(volatile uint16_t *)currAddr = BUFFER_SIZE_WORDS -1;
        for(temp=0; temp<BUFFER_SIZE_WORDS; temp++)
20001958:	6a3b      	ldr	r3, [r7, #32]
2000195a:	f103 0301 	add.w	r3, r3, #1
2000195e:	623b      	str	r3, [r7, #32]
20001960:	6a3b      	ldr	r3, [r7, #32]
20001962:	2b0f      	cmp	r3, #15
20001964:	d9ec      	bls.n	20001940 <emc_flash_write+0x94>
        {
             *(currAddr +temp ) = *(uint16_t *) (buffPtr+temp);
        }
        *(volatile uint16_t *)currAddr = PROGRAM_RESUME;
20001966:	693b      	ldr	r3, [r7, #16]
20001968:	f04f 02d0 	mov.w	r2, #208	; 0xd0
2000196c:	801a      	strh	r2, [r3, #0]
        *(volatile uint16_t *)currAddr = READ_STATUS_REGISTER;
2000196e:	693b      	ldr	r3, [r7, #16]
20001970:	f04f 0270 	mov.w	r2, #112	; 0x70
20001974:	801a      	strh	r2, [r3, #0]

        if(status_wait((uint32_t)currAddr))
20001976:	693b      	ldr	r3, [r7, #16]
20001978:	4618      	mov	r0, r3
2000197a:	f7ff feeb 	bl	20001754 <status_wait>
2000197e:	4603      	mov	r3, r0
20001980:	2b00      	cmp	r3, #0
20001982:	d004      	beq.n	2000198e <emc_flash_write+0xe2>
        {
            return (*((volatile uint16_t *)currAddr));
20001984:	693b      	ldr	r3, [r7, #16]
20001986:	881b      	ldrh	r3, [r3, #0]
20001988:	b29b      	uxth	r3, r3
2000198a:	b2db      	uxtb	r3, r3
2000198c:	e08b      	b.n	20001aa6 <emc_flash_write+0x1fa>
        }

         for(temp=0; temp<BUFFER_SIZE_WORDS; temp++)
2000198e:	f04f 0300 	mov.w	r3, #0
20001992:	623b      	str	r3, [r7, #32]
20001994:	e01d      	b.n	200019d2 <emc_flash_write+0x126>
         {
             *(currAddr+temp) = READ_ARRAY;
20001996:	6a3b      	ldr	r3, [r7, #32]
20001998:	ea4f 0243 	mov.w	r2, r3, lsl #1
2000199c:	693b      	ldr	r3, [r7, #16]
2000199e:	4413      	add	r3, r2
200019a0:	f04f 02ff 	mov.w	r2, #255	; 0xff
200019a4:	801a      	strh	r2, [r3, #0]
             if( *(buffPtr + temp) != *(volatile uint16_t *)(currAddr + temp))
200019a6:	6a3b      	ldr	r3, [r7, #32]
200019a8:	ea4f 0243 	mov.w	r2, r3, lsl #1
200019ac:	697b      	ldr	r3, [r7, #20]
200019ae:	4413      	add	r3, r2
200019b0:	881a      	ldrh	r2, [r3, #0]
200019b2:	6a3b      	ldr	r3, [r7, #32]
200019b4:	ea4f 0143 	mov.w	r1, r3, lsl #1
200019b8:	693b      	ldr	r3, [r7, #16]
200019ba:	440b      	add	r3, r1
200019bc:	881b      	ldrh	r3, [r3, #0]
200019be:	b29b      	uxth	r3, r3
200019c0:	429a      	cmp	r2, r3
200019c2:	d002      	beq.n	200019ca <emc_flash_write+0x11e>
             {
                 /* Write Failed */
                 return NOR_UNSUCCESS;
200019c4:	f04f 0343 	mov.w	r3, #67	; 0x43
200019c8:	e06d      	b.n	20001aa6 <emc_flash_write+0x1fa>
        if(status_wait((uint32_t)currAddr))
        {
            return (*((volatile uint16_t *)currAddr));
        }

         for(temp=0; temp<BUFFER_SIZE_WORDS; temp++)
200019ca:	6a3b      	ldr	r3, [r7, #32]
200019cc:	f103 0301 	add.w	r3, r3, #1
200019d0:	623b      	str	r3, [r7, #32]
200019d2:	6a3b      	ldr	r3, [r7, #32]
200019d4:	2b0f      	cmp	r3, #15
200019d6:	d9de      	bls.n	20001996 <emc_flash_write+0xea>
             {
                 /* Write Failed */
                 return NOR_UNSUCCESS;
              }
          }
          *currAddr = CLEAR_STATUS_REG;
200019d8:	693b      	ldr	r3, [r7, #16]
200019da:	f04f 0250 	mov.w	r2, #80	; 0x50
200019de:	801a      	strh	r2, [r3, #0]
          nb_left_bytes -= BUFFER_SIZE_BYTES;
200019e0:	8b7b      	ldrh	r3, [r7, #26]
200019e2:	f1a3 0320 	sub.w	r3, r3, #32
200019e6:	b29b      	uxth	r3, r3
200019e8:	837b      	strh	r3, [r7, #26]
          currAddr += BUFFER_SIZE_WORDS;
200019ea:	693b      	ldr	r3, [r7, #16]
200019ec:	f103 0320 	add.w	r3, r3, #32
200019f0:	613b      	str	r3, [r7, #16]
          buffPtr += BUFFER_SIZE_WORDS;
200019f2:	697b      	ldr	r3, [r7, #20]
200019f4:	f103 0320 	add.w	r3, r3, #32
200019f8:	617b      	str	r3, [r7, #20]

    currAddr = (volatile uint16_t *)start_addr;

    loopCnt = nb_bytes/BUFFER_SIZE_BYTES;

    for(ii=0; ii<loopCnt; ii++)
200019fa:	69fb      	ldr	r3, [r7, #28]
200019fc:	f103 0301 	add.w	r3, r3, #1
20001a00:	61fb      	str	r3, [r7, #28]
20001a02:	8cfa      	ldrh	r2, [r7, #38]	; 0x26
20001a04:	69fb      	ldr	r3, [r7, #28]
20001a06:	429a      	cmp	r2, r3
20001a08:	d886      	bhi.n	20001918 <emc_flash_write+0x6c>
          currAddr += BUFFER_SIZE_WORDS;
          buffPtr += BUFFER_SIZE_WORDS;

    }

    if (nb_left_bytes > 0)
20001a0a:	f9b7 301a 	ldrsh.w	r3, [r7, #26]
20001a0e:	2b00      	cmp	r3, #0
20001a10:	dd47      	ble.n	20001aa2 <emc_flash_write+0x1f6>
    {

        for(ii=0; ii<nb_left_bytes; ii += 2)
20001a12:	f04f 0300 	mov.w	r3, #0
20001a16:	61fb      	str	r3, [r7, #28]
20001a18:	e03b      	b.n	20001a92 <emc_flash_write+0x1e6>
        {
            *((volatile uint16_t *)(currAddr)) = CLEAR_STATUS_REG;
20001a1a:	693b      	ldr	r3, [r7, #16]
20001a1c:	f04f 0250 	mov.w	r2, #80	; 0x50
20001a20:	801a      	strh	r2, [r3, #0]
            *((volatile uint16_t *)(currAddr)) = READ_ARRAY;
20001a22:	693b      	ldr	r3, [r7, #16]
20001a24:	f04f 02ff 	mov.w	r2, #255	; 0xff
20001a28:	801a      	strh	r2, [r3, #0]
            *((volatile uint16_t *)(currAddr)) = WORD_PROGRAM;
20001a2a:	693b      	ldr	r3, [r7, #16]
20001a2c:	f04f 0240 	mov.w	r2, #64	; 0x40
20001a30:	801a      	strh	r2, [r3, #0]
            *((volatile uint16_t *)(currAddr)) = *((volatile uint16_t *)buffPtr);
20001a32:	697b      	ldr	r3, [r7, #20]
20001a34:	881b      	ldrh	r3, [r3, #0]
20001a36:	b29a      	uxth	r2, r3
20001a38:	693b      	ldr	r3, [r7, #16]
20001a3a:	801a      	strh	r2, [r3, #0]

            *((volatile uint16_t *)(currAddr )) = READ_STATUS_REGISTER;
20001a3c:	693b      	ldr	r3, [r7, #16]
20001a3e:	f04f 0270 	mov.w	r2, #112	; 0x70
20001a42:	801a      	strh	r2, [r3, #0]

            if(status_wait((uint32_t)currAddr))
20001a44:	693b      	ldr	r3, [r7, #16]
20001a46:	4618      	mov	r0, r3
20001a48:	f7ff fe84 	bl	20001754 <status_wait>
20001a4c:	4603      	mov	r3, r0
20001a4e:	2b00      	cmp	r3, #0
20001a50:	d004      	beq.n	20001a5c <emc_flash_write+0x1b0>
            {
                return (*((volatile uint16_t *)currAddr));
20001a52:	693b      	ldr	r3, [r7, #16]
20001a54:	881b      	ldrh	r3, [r3, #0]
20001a56:	b29b      	uxth	r3, r3
20001a58:	b2db      	uxtb	r3, r3
20001a5a:	e024      	b.n	20001aa6 <emc_flash_write+0x1fa>
            }

            *((volatile uint16_t *)currAddr) = READ_ARRAY;
20001a5c:	693b      	ldr	r3, [r7, #16]
20001a5e:	f04f 02ff 	mov.w	r2, #255	; 0xff
20001a62:	801a      	strh	r2, [r3, #0]
            if(*((volatile uint16_t *)buffPtr) != *((volatile uint16_t *)currAddr))
20001a64:	697b      	ldr	r3, [r7, #20]
20001a66:	881b      	ldrh	r3, [r3, #0]
20001a68:	b29a      	uxth	r2, r3
20001a6a:	693b      	ldr	r3, [r7, #16]
20001a6c:	881b      	ldrh	r3, [r3, #0]
20001a6e:	b29b      	uxth	r3, r3
20001a70:	429a      	cmp	r2, r3
20001a72:	d002      	beq.n	20001a7a <emc_flash_write+0x1ce>
            {
                /* write word failed */
                return NOR_UNSUCCESS;
20001a74:	f04f 0343 	mov.w	r3, #67	; 0x43
20001a78:	e015      	b.n	20001aa6 <emc_flash_write+0x1fa>
            }
            currAddr++;
20001a7a:	693b      	ldr	r3, [r7, #16]
20001a7c:	f103 0302 	add.w	r3, r3, #2
20001a80:	613b      	str	r3, [r7, #16]
            buffPtr++;
20001a82:	697b      	ldr	r3, [r7, #20]
20001a84:	f103 0302 	add.w	r3, r3, #2
20001a88:	617b      	str	r3, [r7, #20]
    }

    if (nb_left_bytes > 0)
    {

        for(ii=0; ii<nb_left_bytes; ii += 2)
20001a8a:	69fb      	ldr	r3, [r7, #28]
20001a8c:	f103 0302 	add.w	r3, r3, #2
20001a90:	61fb      	str	r3, [r7, #28]
20001a92:	f9b7 201a 	ldrsh.w	r2, [r7, #26]
20001a96:	69fb      	ldr	r3, [r7, #28]
20001a98:	429a      	cmp	r2, r3
20001a9a:	d8be      	bhi.n	20001a1a <emc_flash_write+0x16e>
            }
            currAddr++;
            buffPtr++;

        }
        nb_left_bytes = 0;
20001a9c:	f04f 0300 	mov.w	r3, #0
20001aa0:	837b      	strh	r3, [r7, #26]
    }
    return NOR_SUCCESS;
20001aa2:	f04f 0300 	mov.w	r3, #0
}
20001aa6:	4618      	mov	r0, r3
20001aa8:	f107 0728 	add.w	r7, r7, #40	; 0x28
20001aac:	46bd      	mov	sp, r7
20001aae:	bd80      	pop	{r7, pc}

20001ab0 <emc_flash_read>:
(
    uint32_t start_addr,
    uint8_t * p_data,
    size_t nb_bytes
)
{
20001ab0:	b480      	push	{r7}
20001ab2:	b089      	sub	sp, #36	; 0x24
20001ab4:	af00      	add	r7, sp, #0
20001ab6:	60f8      	str	r0, [r7, #12]
20001ab8:	60b9      	str	r1, [r7, #8]
20001aba:	607a      	str	r2, [r7, #4]
    volatile uint16_t *currAddr = (volatile uint16_t *)start_addr;
20001abc:	68fb      	ldr	r3, [r7, #12]
20001abe:	617b      	str	r3, [r7, #20]
    uint16_t *buffPtr = (uint16_t *)p_data;
20001ac0:	68bb      	ldr	r3, [r7, #8]
20001ac2:	61bb      	str	r3, [r7, #24]
    uint32_t loop = 0;
20001ac4:	f04f 0300 	mov.w	r3, #0
20001ac8:	61fb      	str	r3, [r7, #28]

    if( (start_addr == (uint32_t)NULL) ||
20001aca:	68fb      	ldr	r3, [r7, #12]
20001acc:	2b00      	cmp	r3, #0
20001ace:	d005      	beq.n	20001adc <emc_flash_read+0x2c>
20001ad0:	68bb      	ldr	r3, [r7, #8]
20001ad2:	2b00      	cmp	r3, #0
20001ad4:	d002      	beq.n	20001adc <emc_flash_read+0x2c>
20001ad6:	687b      	ldr	r3, [r7, #4]
20001ad8:	2b00      	cmp	r3, #0
20001ada:	d102      	bne.n	20001ae2 <emc_flash_read+0x32>
         (p_data == NULL)      ||
         (nb_bytes <= 0))
    {
        return NOR_INVALID_ARGUMENTS;
20001adc:	f04f 0341 	mov.w	r3, #65	; 0x41
20001ae0:	e031      	b.n	20001b46 <emc_flash_read+0x96>
    }
    if( ! (IS_VALID_ADDR(start_addr)))
20001ae2:	68fa      	ldr	r2, [r7, #12]
20001ae4:	f06f 430b 	mvn.w	r3, #2332033024	; 0x8b000000
20001ae8:	429a      	cmp	r2, r3
20001aea:	d804      	bhi.n	20001af6 <emc_flash_read+0x46>
20001aec:	68fa      	ldr	r2, [r7, #12]
20001aee:	f06f 430c 	mvn.w	r3, #2348810240	; 0x8c000000
20001af2:	429a      	cmp	r2, r3
20001af4:	d802      	bhi.n	20001afc <emc_flash_read+0x4c>
    {
        return NOR_INVALID_ADDRESS;
20001af6:	f04f 0342 	mov.w	r3, #66	; 0x42
20001afa:	e024      	b.n	20001b46 <emc_flash_read+0x96>
    }

    for(loop=0; loop < nb_bytes/2; loop += 1)
20001afc:	f04f 0300 	mov.w	r3, #0
20001b00:	61fb      	str	r3, [r7, #28]
20001b02:	e018      	b.n	20001b36 <emc_flash_read+0x86>
    {
        *(currAddr+loop) = READ_ARRAY;
20001b04:	69fb      	ldr	r3, [r7, #28]
20001b06:	ea4f 0243 	mov.w	r2, r3, lsl #1
20001b0a:	697b      	ldr	r3, [r7, #20]
20001b0c:	4413      	add	r3, r2
20001b0e:	f04f 02ff 	mov.w	r2, #255	; 0xff
20001b12:	801a      	strh	r2, [r3, #0]
        *(buffPtr+loop)  = *(volatile uint16_t *)(currAddr + loop);
20001b14:	69fb      	ldr	r3, [r7, #28]
20001b16:	ea4f 0243 	mov.w	r2, r3, lsl #1
20001b1a:	69bb      	ldr	r3, [r7, #24]
20001b1c:	4413      	add	r3, r2
20001b1e:	69fa      	ldr	r2, [r7, #28]
20001b20:	ea4f 0142 	mov.w	r1, r2, lsl #1
20001b24:	697a      	ldr	r2, [r7, #20]
20001b26:	440a      	add	r2, r1
20001b28:	8812      	ldrh	r2, [r2, #0]
20001b2a:	b292      	uxth	r2, r2
20001b2c:	801a      	strh	r2, [r3, #0]
    if( ! (IS_VALID_ADDR(start_addr)))
    {
        return NOR_INVALID_ADDRESS;
    }

    for(loop=0; loop < nb_bytes/2; loop += 1)
20001b2e:	69fb      	ldr	r3, [r7, #28]
20001b30:	f103 0301 	add.w	r3, r3, #1
20001b34:	61fb      	str	r3, [r7, #28]
20001b36:	687b      	ldr	r3, [r7, #4]
20001b38:	ea4f 0253 	mov.w	r2, r3, lsr #1
20001b3c:	69fb      	ldr	r3, [r7, #28]
20001b3e:	429a      	cmp	r2, r3
20001b40:	d8e0      	bhi.n	20001b04 <emc_flash_read+0x54>
    {
        *(currAddr+loop) = READ_ARRAY;
        *(buffPtr+loop)  = *(volatile uint16_t *)(currAddr + loop);
    }

    return NOR_SUCCESS;
20001b42:	f04f 0300 	mov.w	r3, #0

}
20001b46:	4618      	mov	r0, r3
20001b48:	f107 0724 	add.w	r7, r7, #36	; 0x24
20001b4c:	46bd      	mov	sp, r7
20001b4e:	bc80      	pop	{r7}
20001b50:	4770      	bx	lr
20001b52:	bf00      	nop

20001b54 <_close>:

/*==============================================================================
 * Close a file.
 */
int _close(int file)
{
20001b54:	b480      	push	{r7}
20001b56:	b083      	sub	sp, #12
20001b58:	af00      	add	r7, sp, #0
20001b5a:	6078      	str	r0, [r7, #4]
    return -1;
20001b5c:	f04f 33ff 	mov.w	r3, #4294967295
}
20001b60:	4618      	mov	r0, r3
20001b62:	f107 070c 	add.w	r7, r7, #12
20001b66:	46bd      	mov	sp, r7
20001b68:	bc80      	pop	{r7}
20001b6a:	4770      	bx	lr

20001b6c <_execve>:

/*==============================================================================
 * Transfer control to a new process.
 */
int _execve(char *name, char **argv, char **env)
{
20001b6c:	b580      	push	{r7, lr}
20001b6e:	b084      	sub	sp, #16
20001b70:	af00      	add	r7, sp, #0
20001b72:	60f8      	str	r0, [r7, #12]
20001b74:	60b9      	str	r1, [r7, #8]
20001b76:	607a      	str	r2, [r7, #4]
    errno = ENOMEM;
20001b78:	f002 fe20 	bl	200047bc <__errno>
20001b7c:	4603      	mov	r3, r0
20001b7e:	f04f 020c 	mov.w	r2, #12
20001b82:	601a      	str	r2, [r3, #0]
    return -1;
20001b84:	f04f 33ff 	mov.w	r3, #4294967295
}
20001b88:	4618      	mov	r0, r3
20001b8a:	f107 0710 	add.w	r7, r7, #16
20001b8e:	46bd      	mov	sp, r7
20001b90:	bd80      	pop	{r7, pc}
20001b92:	bf00      	nop

20001b94 <_exit>:
{
	/* Should we force a system reset? */
	while( 1 )
	{
		;
	}
20001b94:	b480      	push	{r7}
20001b96:	b083      	sub	sp, #12
20001b98:	af00      	add	r7, sp, #0
20001b9a:	6078      	str	r0, [r7, #4]
20001b9c:	e7fe      	b.n	20001b9c <_exit+0x8>
20001b9e:	bf00      	nop

20001ba0 <_fork>:

/*==============================================================================
 * Create a new process.
 */
int _fork(void)
{
20001ba0:	b580      	push	{r7, lr}
20001ba2:	af00      	add	r7, sp, #0
    errno = EAGAIN;
20001ba4:	f002 fe0a 	bl	200047bc <__errno>
20001ba8:	4603      	mov	r3, r0
20001baa:	f04f 020b 	mov.w	r2, #11
20001bae:	601a      	str	r2, [r3, #0]
    return -1;
20001bb0:	f04f 33ff 	mov.w	r3, #4294967295
}
20001bb4:	4618      	mov	r0, r3
20001bb6:	bd80      	pop	{r7, pc}

20001bb8 <_fstat>:

/*==============================================================================
 * Status of an open file.
 */
int _fstat(int file, struct stat *st)
{
20001bb8:	b480      	push	{r7}
20001bba:	b083      	sub	sp, #12
20001bbc:	af00      	add	r7, sp, #0
20001bbe:	6078      	str	r0, [r7, #4]
20001bc0:	6039      	str	r1, [r7, #0]
    st->st_mode = S_IFCHR;
20001bc2:	683b      	ldr	r3, [r7, #0]
20001bc4:	f44f 5200 	mov.w	r2, #8192	; 0x2000
20001bc8:	605a      	str	r2, [r3, #4]
    return 0;
20001bca:	f04f 0300 	mov.w	r3, #0
}
20001bce:	4618      	mov	r0, r3
20001bd0:	f107 070c 	add.w	r7, r7, #12
20001bd4:	46bd      	mov	sp, r7
20001bd6:	bc80      	pop	{r7}
20001bd8:	4770      	bx	lr
20001bda:	bf00      	nop

20001bdc <_getpid>:

/*==============================================================================
 * Process-ID
 */
int _getpid(void)
{
20001bdc:	b480      	push	{r7}
20001bde:	af00      	add	r7, sp, #0
    return 1;
20001be0:	f04f 0301 	mov.w	r3, #1
}
20001be4:	4618      	mov	r0, r3
20001be6:	46bd      	mov	sp, r7
20001be8:	bc80      	pop	{r7}
20001bea:	4770      	bx	lr

20001bec <_isatty>:

/*==============================================================================
 * Query whether output stream is a terminal.
 */
int _isatty(int file)
{
20001bec:	b480      	push	{r7}
20001bee:	b083      	sub	sp, #12
20001bf0:	af00      	add	r7, sp, #0
20001bf2:	6078      	str	r0, [r7, #4]
    return 1;
20001bf4:	f04f 0301 	mov.w	r3, #1
}
20001bf8:	4618      	mov	r0, r3
20001bfa:	f107 070c 	add.w	r7, r7, #12
20001bfe:	46bd      	mov	sp, r7
20001c00:	bc80      	pop	{r7}
20001c02:	4770      	bx	lr

20001c04 <_kill>:

/*==============================================================================
 * Send a signal.
 */
int _kill(int pid, int sig)
{
20001c04:	b580      	push	{r7, lr}
20001c06:	b082      	sub	sp, #8
20001c08:	af00      	add	r7, sp, #0
20001c0a:	6078      	str	r0, [r7, #4]
20001c0c:	6039      	str	r1, [r7, #0]
    errno = EINVAL;
20001c0e:	f002 fdd5 	bl	200047bc <__errno>
20001c12:	4603      	mov	r3, r0
20001c14:	f04f 0216 	mov.w	r2, #22
20001c18:	601a      	str	r2, [r3, #0]
    return -1;
20001c1a:	f04f 33ff 	mov.w	r3, #4294967295
}
20001c1e:	4618      	mov	r0, r3
20001c20:	f107 0708 	add.w	r7, r7, #8
20001c24:	46bd      	mov	sp, r7
20001c26:	bd80      	pop	{r7, pc}

20001c28 <_link>:

/*==============================================================================
 * Establish a new name for an existing file.
 */
int _link(char *old, char *new)
{
20001c28:	b580      	push	{r7, lr}
20001c2a:	b082      	sub	sp, #8
20001c2c:	af00      	add	r7, sp, #0
20001c2e:	6078      	str	r0, [r7, #4]
20001c30:	6039      	str	r1, [r7, #0]
    errno = EMLINK;
20001c32:	f002 fdc3 	bl	200047bc <__errno>
20001c36:	4603      	mov	r3, r0
20001c38:	f04f 021f 	mov.w	r2, #31
20001c3c:	601a      	str	r2, [r3, #0]
    return -1;
20001c3e:	f04f 33ff 	mov.w	r3, #4294967295
}
20001c42:	4618      	mov	r0, r3
20001c44:	f107 0708 	add.w	r7, r7, #8
20001c48:	46bd      	mov	sp, r7
20001c4a:	bd80      	pop	{r7, pc}

20001c4c <_lseek>:

/*==============================================================================
 * Set position in a file.
 */
int _lseek(int file, int ptr, int dir)
{
20001c4c:	b480      	push	{r7}
20001c4e:	b085      	sub	sp, #20
20001c50:	af00      	add	r7, sp, #0
20001c52:	60f8      	str	r0, [r7, #12]
20001c54:	60b9      	str	r1, [r7, #8]
20001c56:	607a      	str	r2, [r7, #4]
    return 0;
20001c58:	f04f 0300 	mov.w	r3, #0
}
20001c5c:	4618      	mov	r0, r3
20001c5e:	f107 0714 	add.w	r7, r7, #20
20001c62:	46bd      	mov	sp, r7
20001c64:	bc80      	pop	{r7}
20001c66:	4770      	bx	lr

20001c68 <_open>:

/*==============================================================================
 * Open a file.
 */
int _open(const char *name, int flags, int mode)
{
20001c68:	b480      	push	{r7}
20001c6a:	b085      	sub	sp, #20
20001c6c:	af00      	add	r7, sp, #0
20001c6e:	60f8      	str	r0, [r7, #12]
20001c70:	60b9      	str	r1, [r7, #8]
20001c72:	607a      	str	r2, [r7, #4]
    return -1;
20001c74:	f04f 33ff 	mov.w	r3, #4294967295
}
20001c78:	4618      	mov	r0, r3
20001c7a:	f107 0714 	add.w	r7, r7, #20
20001c7e:	46bd      	mov	sp, r7
20001c80:	bc80      	pop	{r7}
20001c82:	4770      	bx	lr

20001c84 <_read>:

/*==============================================================================
 * Read from a file.
 */
int _read(int file, char *ptr, int len)
{
20001c84:	b480      	push	{r7}
20001c86:	b085      	sub	sp, #20
20001c88:	af00      	add	r7, sp, #0
20001c8a:	60f8      	str	r0, [r7, #12]
20001c8c:	60b9      	str	r1, [r7, #8]
20001c8e:	607a      	str	r2, [r7, #4]
    return 0;
20001c90:	f04f 0300 	mov.w	r3, #0
}
20001c94:	4618      	mov	r0, r3
20001c96:	f107 0714 	add.w	r7, r7, #20
20001c9a:	46bd      	mov	sp, r7
20001c9c:	bc80      	pop	{r7}
20001c9e:	4770      	bx	lr

20001ca0 <_write_r>:
 * all files, including stdoutso if you need to generate any output, for
 * example to a serial port for debugging, you should make your minimal write
 * capable of doing this.
 */
int _write_r( void * reent, int file, char * ptr, int len )
{
20001ca0:	b580      	push	{r7, lr}
20001ca2:	b084      	sub	sp, #16
20001ca4:	af00      	add	r7, sp, #0
20001ca6:	60f8      	str	r0, [r7, #12]
20001ca8:	60b9      	str	r1, [r7, #8]
20001caa:	607a      	str	r2, [r7, #4]
20001cac:	603b      	str	r3, [r7, #0]
#ifdef ACTEL_STDIO_THRU_UART
    /*--------------------------------------------------------------------------
     * Initialize the UART driver if it is the first time this function is
     * called.
     */
    if ( !g_stdio_uart_init_done )
20001cae:	f644 13e8 	movw	r3, #18920	; 0x49e8
20001cb2:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001cb6:	681b      	ldr	r3, [r3, #0]
20001cb8:	2b00      	cmp	r3, #0
20001cba:	d110      	bne.n	20001cde <_write_r+0x3e>
    {
        MSS_UART_init( &g_mss_uart0, ACTEL_STDIO_BAUD_RATE, (MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY));
20001cbc:	f644 2054 	movw	r0, #19028	; 0x4a54
20001cc0:	f2c2 0000 	movt	r0, #8192	; 0x2000
20001cc4:	f44f 4161 	mov.w	r1, #57600	; 0xe100
20001cc8:	f04f 0203 	mov.w	r2, #3
20001ccc:	f000 f8fa 	bl	20001ec4 <MSS_UART_init>
        g_stdio_uart_init_done = 1;
20001cd0:	f644 13e8 	movw	r3, #18920	; 0x49e8
20001cd4:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001cd8:	f04f 0201 	mov.w	r2, #1
20001cdc:	601a      	str	r2, [r3, #0]
    }
    
    /*--------------------------------------------------------------------------
     * Output text to the UART.
     */
    MSS_UART_polled_tx( &g_mss_uart0, (uint8_t *)ptr, len );
20001cde:	683b      	ldr	r3, [r7, #0]
20001ce0:	f644 2054 	movw	r0, #19028	; 0x4a54
20001ce4:	f2c2 0000 	movt	r0, #8192	; 0x2000
20001ce8:	6879      	ldr	r1, [r7, #4]
20001cea:	461a      	mov	r2, r3
20001cec:	f000 f9e6 	bl	200020bc <MSS_UART_polled_tx>
    
    return len;
20001cf0:	683b      	ldr	r3, [r7, #0]
#else   /* ACTEL_STDIO_THRU_UART */
    return 0;
#endif  /* ACTEL_STDIO_THRU_UART */
}
20001cf2:	4618      	mov	r0, r3
20001cf4:	f107 0710 	add.w	r7, r7, #16
20001cf8:	46bd      	mov	sp, r7
20001cfa:	bd80      	pop	{r7, pc}

20001cfc <_sbrk>:
 * it is useful to have a working implementation. The following suffices for a
 * standalone system; it exploits the symbol _end automatically defined by the
 * GNU linker. 
 */
caddr_t _sbrk(int incr)
{
20001cfc:	b580      	push	{r7, lr}
20001cfe:	b084      	sub	sp, #16
20001d00:	af00      	add	r7, sp, #0
20001d02:	6078      	str	r0, [r7, #4]
    extern char _end;		/* Defined by the linker */
    static char *heap_end;
    char *prev_heap_end;
    char * stack_ptr;
    
    if (heap_end == 0)
20001d04:	f644 13f0 	movw	r3, #18928	; 0x49f0
20001d08:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001d0c:	681b      	ldr	r3, [r3, #0]
20001d0e:	2b00      	cmp	r3, #0
20001d10:	d108      	bne.n	20001d24 <_sbrk+0x28>
    {
      heap_end = &_end;
20001d12:	f644 13f0 	movw	r3, #18928	; 0x49f0
20001d16:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001d1a:	f644 3278 	movw	r2, #19320	; 0x4b78
20001d1e:	f2c2 0200 	movt	r2, #8192	; 0x2000
20001d22:	601a      	str	r2, [r3, #0]
    }
    
    prev_heap_end = heap_end;
20001d24:	f644 13f0 	movw	r3, #18928	; 0x49f0
20001d28:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001d2c:	681b      	ldr	r3, [r3, #0]
20001d2e:	60bb      	str	r3, [r7, #8]
    asm volatile ("MRS %0, msp" : "=r" (stack_ptr) );
20001d30:	f3ef 8308 	mrs	r3, MSP
20001d34:	60fb      	str	r3, [r7, #12]
    if (heap_end + incr > stack_ptr)
20001d36:	f644 13f0 	movw	r3, #18928	; 0x49f0
20001d3a:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001d3e:	681a      	ldr	r2, [r3, #0]
20001d40:	687b      	ldr	r3, [r7, #4]
20001d42:	441a      	add	r2, r3
20001d44:	68fb      	ldr	r3, [r7, #12]
20001d46:	429a      	cmp	r2, r3
20001d48:	d90f      	bls.n	20001d6a <_sbrk+0x6e>
    {
      _write_r ((void *)0, 1, "Heap and stack collision\n", 25);
20001d4a:	f04f 0000 	mov.w	r0, #0
20001d4e:	f04f 0101 	mov.w	r1, #1
20001d52:	f644 0230 	movw	r2, #18480	; 0x4830
20001d56:	f2c2 0200 	movt	r2, #8192	; 0x2000
20001d5a:	f04f 0319 	mov.w	r3, #25
20001d5e:	f7ff ff9f 	bl	20001ca0 <_write_r>
      _exit (1);
20001d62:	f04f 0001 	mov.w	r0, #1
20001d66:	f7ff ff15 	bl	20001b94 <_exit>
    }
  
    heap_end += incr;
20001d6a:	f644 13f0 	movw	r3, #18928	; 0x49f0
20001d6e:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001d72:	681a      	ldr	r2, [r3, #0]
20001d74:	687b      	ldr	r3, [r7, #4]
20001d76:	441a      	add	r2, r3
20001d78:	f644 13f0 	movw	r3, #18928	; 0x49f0
20001d7c:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001d80:	601a      	str	r2, [r3, #0]
    return (caddr_t) prev_heap_end;
20001d82:	68bb      	ldr	r3, [r7, #8]
}
20001d84:	4618      	mov	r0, r3
20001d86:	f107 0710 	add.w	r7, r7, #16
20001d8a:	46bd      	mov	sp, r7
20001d8c:	bd80      	pop	{r7, pc}
20001d8e:	bf00      	nop

20001d90 <_stat>:

/*==============================================================================
 * Status of a file (by name).
 */
int _stat(char *file, struct stat *st)
{
20001d90:	b480      	push	{r7}
20001d92:	b083      	sub	sp, #12
20001d94:	af00      	add	r7, sp, #0
20001d96:	6078      	str	r0, [r7, #4]
20001d98:	6039      	str	r1, [r7, #0]
    st->st_mode = S_IFCHR;
20001d9a:	683b      	ldr	r3, [r7, #0]
20001d9c:	f44f 5200 	mov.w	r2, #8192	; 0x2000
20001da0:	605a      	str	r2, [r3, #4]
    return 0;
20001da2:	f04f 0300 	mov.w	r3, #0
}
20001da6:	4618      	mov	r0, r3
20001da8:	f107 070c 	add.w	r7, r7, #12
20001dac:	46bd      	mov	sp, r7
20001dae:	bc80      	pop	{r7}
20001db0:	4770      	bx	lr
20001db2:	bf00      	nop

20001db4 <_times>:

/*==============================================================================
 * Timing information for current process.
 */
int _times(struct tms *buf)
{
20001db4:	b480      	push	{r7}
20001db6:	b083      	sub	sp, #12
20001db8:	af00      	add	r7, sp, #0
20001dba:	6078      	str	r0, [r7, #4]
    return -1;
20001dbc:	f04f 33ff 	mov.w	r3, #4294967295
}
20001dc0:	4618      	mov	r0, r3
20001dc2:	f107 070c 	add.w	r7, r7, #12
20001dc6:	46bd      	mov	sp, r7
20001dc8:	bc80      	pop	{r7}
20001dca:	4770      	bx	lr

20001dcc <_unlink>:

/*==============================================================================
 * Remove a file's directory entry.
 */
int _unlink(char *name)
{
20001dcc:	b580      	push	{r7, lr}
20001dce:	b082      	sub	sp, #8
20001dd0:	af00      	add	r7, sp, #0
20001dd2:	6078      	str	r0, [r7, #4]
    errno = ENOENT;
20001dd4:	f002 fcf2 	bl	200047bc <__errno>
20001dd8:	4603      	mov	r3, r0
20001dda:	f04f 0202 	mov.w	r2, #2
20001dde:	601a      	str	r2, [r3, #0]
    return -1;
20001de0:	f04f 33ff 	mov.w	r3, #4294967295
}
20001de4:	4618      	mov	r0, r3
20001de6:	f107 0708 	add.w	r7, r7, #8
20001dea:	46bd      	mov	sp, r7
20001dec:	bd80      	pop	{r7, pc}
20001dee:	bf00      	nop

20001df0 <_wait>:

/*==============================================================================
 * Wait for a child process.
 */
int _wait(int *status)
{
20001df0:	b580      	push	{r7, lr}
20001df2:	b082      	sub	sp, #8
20001df4:	af00      	add	r7, sp, #0
20001df6:	6078      	str	r0, [r7, #4]
    errno = ECHILD;
20001df8:	f002 fce0 	bl	200047bc <__errno>
20001dfc:	4603      	mov	r3, r0
20001dfe:	f04f 020a 	mov.w	r2, #10
20001e02:	601a      	str	r2, [r3, #0]
    return -1;
20001e04:	f04f 33ff 	mov.w	r3, #4294967295
}
20001e08:	4618      	mov	r0, r3
20001e0a:	f107 0708 	add.w	r7, r7, #8
20001e0e:	46bd      	mov	sp, r7
20001e10:	bd80      	pop	{r7, pc}
20001e12:	bf00      	nop

20001e14 <NVIC_EnableIRQ>:
 *
 * Enable a device specific interupt in the NVIC interrupt controller.
 * The interrupt number cannot be a negative value.
 */
static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
20001e14:	b480      	push	{r7}
20001e16:	b083      	sub	sp, #12
20001e18:	af00      	add	r7, sp, #0
20001e1a:	4603      	mov	r3, r0
20001e1c:	80fb      	strh	r3, [r7, #6]
  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
20001e1e:	f24e 1300 	movw	r3, #57600	; 0xe100
20001e22:	f2ce 0300 	movt	r3, #57344	; 0xe000
20001e26:	f9b7 2006 	ldrsh.w	r2, [r7, #6]
20001e2a:	ea4f 1252 	mov.w	r2, r2, lsr #5
20001e2e:	88f9      	ldrh	r1, [r7, #6]
20001e30:	f001 011f 	and.w	r1, r1, #31
20001e34:	f04f 0001 	mov.w	r0, #1
20001e38:	fa00 f101 	lsl.w	r1, r0, r1
20001e3c:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
}
20001e40:	f107 070c 	add.w	r7, r7, #12
20001e44:	46bd      	mov	sp, r7
20001e46:	bc80      	pop	{r7}
20001e48:	4770      	bx	lr
20001e4a:	bf00      	nop

20001e4c <NVIC_DisableIRQ>:
 * 
 * Disable a device specific interupt in the NVIC interrupt controller.
 * The interrupt number cannot be a negative value.
 */
static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
20001e4c:	b480      	push	{r7}
20001e4e:	b083      	sub	sp, #12
20001e50:	af00      	add	r7, sp, #0
20001e52:	4603      	mov	r3, r0
20001e54:	80fb      	strh	r3, [r7, #6]
  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
20001e56:	f24e 1300 	movw	r3, #57600	; 0xe100
20001e5a:	f2ce 0300 	movt	r3, #57344	; 0xe000
20001e5e:	f9b7 2006 	ldrsh.w	r2, [r7, #6]
20001e62:	ea4f 1252 	mov.w	r2, r2, lsr #5
20001e66:	88f9      	ldrh	r1, [r7, #6]
20001e68:	f001 011f 	and.w	r1, r1, #31
20001e6c:	f04f 0001 	mov.w	r0, #1
20001e70:	fa00 f101 	lsl.w	r1, r0, r1
20001e74:	f102 0220 	add.w	r2, r2, #32
20001e78:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
}
20001e7c:	f107 070c 	add.w	r7, r7, #12
20001e80:	46bd      	mov	sp, r7
20001e82:	bc80      	pop	{r7}
20001e84:	4770      	bx	lr
20001e86:	bf00      	nop

20001e88 <NVIC_ClearPendingIRQ>:
 *
 * Clear the pending bit for the specified interrupt. 
 * The interrupt number cannot be a negative value.
 */
static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
20001e88:	b480      	push	{r7}
20001e8a:	b083      	sub	sp, #12
20001e8c:	af00      	add	r7, sp, #0
20001e8e:	4603      	mov	r3, r0
20001e90:	80fb      	strh	r3, [r7, #6]
  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
20001e92:	f24e 1300 	movw	r3, #57600	; 0xe100
20001e96:	f2ce 0300 	movt	r3, #57344	; 0xe000
20001e9a:	f9b7 2006 	ldrsh.w	r2, [r7, #6]
20001e9e:	ea4f 1252 	mov.w	r2, r2, lsr #5
20001ea2:	88f9      	ldrh	r1, [r7, #6]
20001ea4:	f001 011f 	and.w	r1, r1, #31
20001ea8:	f04f 0001 	mov.w	r0, #1
20001eac:	fa00 f101 	lsl.w	r1, r0, r1
20001eb0:	f102 0260 	add.w	r2, r2, #96	; 0x60
20001eb4:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
}
20001eb8:	f107 070c 	add.w	r7, r7, #12
20001ebc:	46bd      	mov	sp, r7
20001ebe:	bc80      	pop	{r7}
20001ec0:	4770      	bx	lr
20001ec2:	bf00      	nop

20001ec4 <MSS_UART_init>:
(
    mss_uart_instance_t* this_uart,
    uint32_t baud_rate,
    uint8_t line_config
)
{
20001ec4:	b580      	push	{r7, lr}
20001ec6:	b086      	sub	sp, #24
20001ec8:	af00      	add	r7, sp, #0
20001eca:	60f8      	str	r0, [r7, #12]
20001ecc:	60b9      	str	r1, [r7, #8]
20001ece:	4613      	mov	r3, r2
20001ed0:	71fb      	strb	r3, [r7, #7]
    uint16_t baud_value;
    uint32_t pclk_freq;

    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );
20001ed2:	68fa      	ldr	r2, [r7, #12]
20001ed4:	f644 2354 	movw	r3, #19028	; 0x4a54
20001ed8:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001edc:	429a      	cmp	r2, r3
20001ede:	d007      	beq.n	20001ef0 <MSS_UART_init+0x2c>
20001ee0:	68fa      	ldr	r2, [r7, #12]
20001ee2:	f644 232c 	movw	r3, #18988	; 0x4a2c
20001ee6:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001eea:	429a      	cmp	r2, r3
20001eec:	d000      	beq.n	20001ef0 <MSS_UART_init+0x2c>
20001eee:	be00      	bkpt	0x0000

    /* Force the value of the CMSIS global variables holding the various system
     * clock frequencies to be updated. */
    SystemCoreClockUpdate();
20001ef0:	f002 fb48 	bl	20004584 <SystemCoreClockUpdate>

    if ( this_uart == &g_mss_uart0 )
20001ef4:	68fa      	ldr	r2, [r7, #12]
20001ef6:	f644 2354 	movw	r3, #19028	; 0x4a54
20001efa:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001efe:	429a      	cmp	r2, r3
20001f00:	d12e      	bne.n	20001f60 <MSS_UART_init+0x9c>
    {
        this_uart->hw_reg = UART0;
20001f02:	68fb      	ldr	r3, [r7, #12]
20001f04:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
20001f08:	601a      	str	r2, [r3, #0]
        this_uart->hw_reg_bit = UART0_BITBAND;
20001f0a:	68fb      	ldr	r3, [r7, #12]
20001f0c:	f04f 4284 	mov.w	r2, #1107296256	; 0x42000000
20001f10:	605a      	str	r2, [r3, #4]
        this_uart->irqn = UART0_IRQn;
20001f12:	68fb      	ldr	r3, [r7, #12]
20001f14:	f04f 020a 	mov.w	r2, #10
20001f18:	811a      	strh	r2, [r3, #8]

        pclk_freq = g_FrequencyPCLK0;
20001f1a:	f644 03e0 	movw	r3, #18656	; 0x48e0
20001f1e:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001f22:	681b      	ldr	r3, [r3, #0]
20001f24:	617b      	str	r3, [r7, #20]

        /* reset UART0 */
        SYSREG->SOFT_RST_CR |= SYSREG_UART0_SOFTRESET_MASK;
20001f26:	f242 0300 	movw	r3, #8192	; 0x2000
20001f2a:	f2ce 0304 	movt	r3, #57348	; 0xe004
20001f2e:	f242 0200 	movw	r2, #8192	; 0x2000
20001f32:	f2ce 0204 	movt	r2, #57348	; 0xe004
20001f36:	6b12      	ldr	r2, [r2, #48]	; 0x30
20001f38:	f042 0280 	orr.w	r2, r2, #128	; 0x80
20001f3c:	631a      	str	r2, [r3, #48]	; 0x30
        /* Clear any previously pended UART0 interrupt */
        NVIC_ClearPendingIRQ( UART0_IRQn );
20001f3e:	f04f 000a 	mov.w	r0, #10
20001f42:	f7ff ffa1 	bl	20001e88 <NVIC_ClearPendingIRQ>
        /* Take UART0 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_UART0_SOFTRESET_MASK;
20001f46:	f242 0300 	movw	r3, #8192	; 0x2000
20001f4a:	f2ce 0304 	movt	r3, #57348	; 0xe004
20001f4e:	f242 0200 	movw	r2, #8192	; 0x2000
20001f52:	f2ce 0204 	movt	r2, #57348	; 0xe004
20001f56:	6b12      	ldr	r2, [r2, #48]	; 0x30
20001f58:	f022 0280 	bic.w	r2, r2, #128	; 0x80
20001f5c:	631a      	str	r2, [r3, #48]	; 0x30
20001f5e:	e031      	b.n	20001fc4 <MSS_UART_init+0x100>
    }
    else
    {
        this_uart->hw_reg = UART1;
20001f60:	68fa      	ldr	r2, [r7, #12]
20001f62:	f240 0300 	movw	r3, #0
20001f66:	f2c4 0301 	movt	r3, #16385	; 0x4001
20001f6a:	6013      	str	r3, [r2, #0]
        this_uart->hw_reg_bit = UART1_BITBAND;
20001f6c:	68fa      	ldr	r2, [r7, #12]
20001f6e:	f240 0300 	movw	r3, #0
20001f72:	f2c4 2320 	movt	r3, #16928	; 0x4220
20001f76:	6053      	str	r3, [r2, #4]
        this_uart->irqn = UART1_IRQn;
20001f78:	68fb      	ldr	r3, [r7, #12]
20001f7a:	f04f 020b 	mov.w	r2, #11
20001f7e:	811a      	strh	r2, [r3, #8]

        pclk_freq = g_FrequencyPCLK1;
20001f80:	f644 03e4 	movw	r3, #18660	; 0x48e4
20001f84:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001f88:	681b      	ldr	r3, [r3, #0]
20001f8a:	617b      	str	r3, [r7, #20]

        /* Reset UART1 */
        SYSREG->SOFT_RST_CR |= SYSREG_UART1_SOFTRESET_MASK;
20001f8c:	f242 0300 	movw	r3, #8192	; 0x2000
20001f90:	f2ce 0304 	movt	r3, #57348	; 0xe004
20001f94:	f242 0200 	movw	r2, #8192	; 0x2000
20001f98:	f2ce 0204 	movt	r2, #57348	; 0xe004
20001f9c:	6b12      	ldr	r2, [r2, #48]	; 0x30
20001f9e:	f442 7280 	orr.w	r2, r2, #256	; 0x100
20001fa2:	631a      	str	r2, [r3, #48]	; 0x30
        /* Clear any previously pended UART1 interrupt */
        NVIC_ClearPendingIRQ( UART1_IRQn );
20001fa4:	f04f 000b 	mov.w	r0, #11
20001fa8:	f7ff ff6e 	bl	20001e88 <NVIC_ClearPendingIRQ>
        /* Take UART1 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_UART1_SOFTRESET_MASK;
20001fac:	f242 0300 	movw	r3, #8192	; 0x2000
20001fb0:	f2ce 0304 	movt	r3, #57348	; 0xe004
20001fb4:	f242 0200 	movw	r2, #8192	; 0x2000
20001fb8:	f2ce 0204 	movt	r2, #57348	; 0xe004
20001fbc:	6b12      	ldr	r2, [r2, #48]	; 0x30
20001fbe:	f422 7280 	bic.w	r2, r2, #256	; 0x100
20001fc2:	631a      	str	r2, [r3, #48]	; 0x30
    }

    /* disable interrupts */
    this_uart->hw_reg->IER = 0U;
20001fc4:	68fb      	ldr	r3, [r7, #12]
20001fc6:	681b      	ldr	r3, [r3, #0]
20001fc8:	f04f 0200 	mov.w	r2, #0
20001fcc:	711a      	strb	r2, [r3, #4]
     * The baud value is computed using the following equation:
     *      baud_value = PCLK_Frequency / (baud_rate * 16)
     * The baud value is rounded up or down depending on what would be the remainder
     * of the divide by 16 operation.
     */
    baud_value = (uint16_t)(pclk_freq / baud_rate);
20001fce:	697a      	ldr	r2, [r7, #20]
20001fd0:	68bb      	ldr	r3, [r7, #8]
20001fd2:	fbb2 f3f3 	udiv	r3, r2, r3
20001fd6:	827b      	strh	r3, [r7, #18]
    if ( baud_value & 0x00000008U )
20001fd8:	8a7b      	ldrh	r3, [r7, #18]
20001fda:	f003 0308 	and.w	r3, r3, #8
20001fde:	2b00      	cmp	r3, #0
20001fe0:	d007      	beq.n	20001ff2 <MSS_UART_init+0x12e>
    {
        /* remainder above 0.5 */
        baud_value = (baud_value >> 4U) + 1U;
20001fe2:	8a7b      	ldrh	r3, [r7, #18]
20001fe4:	ea4f 1313 	mov.w	r3, r3, lsr #4
20001fe8:	b29b      	uxth	r3, r3
20001fea:	f103 0301 	add.w	r3, r3, #1
20001fee:	827b      	strh	r3, [r7, #18]
20001ff0:	e003      	b.n	20001ffa <MSS_UART_init+0x136>
    }
    else
    {
        /* remainder below 0.5 */
        baud_value = (baud_value >> 4U);
20001ff2:	8a7b      	ldrh	r3, [r7, #18]
20001ff4:	ea4f 1313 	mov.w	r3, r3, lsr #4
20001ff8:	827b      	strh	r3, [r7, #18]
    }

    /* set divisor latch */
    this_uart->hw_reg_bit->LCR_DLAB = (uint32_t)1;
20001ffa:	68fb      	ldr	r3, [r7, #12]
20001ffc:	685b      	ldr	r3, [r3, #4]
20001ffe:	f04f 0201 	mov.w	r2, #1
20002002:	f8c3 219c 	str.w	r2, [r3, #412]	; 0x19c

    /* msb of baud value */
    this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8);
20002006:	68fb      	ldr	r3, [r7, #12]
20002008:	681b      	ldr	r3, [r3, #0]
2000200a:	8a7a      	ldrh	r2, [r7, #18]
2000200c:	ea4f 2212 	mov.w	r2, r2, lsr #8
20002010:	b292      	uxth	r2, r2
20002012:	b2d2      	uxtb	r2, r2
20002014:	711a      	strb	r2, [r3, #4]
    /* lsb of baud value */
    this_uart->hw_reg->DLR = (uint8_t)baud_value;
20002016:	68fb      	ldr	r3, [r7, #12]
20002018:	681b      	ldr	r3, [r3, #0]
2000201a:	8a7a      	ldrh	r2, [r7, #18]
2000201c:	b2d2      	uxtb	r2, r2
2000201e:	701a      	strb	r2, [r3, #0]

    /* reset divisor latch */
    this_uart->hw_reg_bit->LCR_DLAB = (uint32_t)0;
20002020:	68fb      	ldr	r3, [r7, #12]
20002022:	685b      	ldr	r3, [r3, #4]
20002024:	f04f 0200 	mov.w	r2, #0
20002028:	f8c3 219c 	str.w	r2, [r3, #412]	; 0x19c

    /* set the line control register (bit length, stop bits, parity) */
    this_uart->hw_reg->LCR = line_config;
2000202c:	68fb      	ldr	r3, [r7, #12]
2000202e:	681b      	ldr	r3, [r3, #0]
20002030:	79fa      	ldrb	r2, [r7, #7]
20002032:	731a      	strb	r2, [r3, #12]

    /* FIFO configuration */
    this_uart->hw_reg->FCR = (uint8_t)MSS_UART_FIFO_SINGLE_BYTE;
20002034:	68fb      	ldr	r3, [r7, #12]
20002036:	681b      	ldr	r3, [r3, #0]
20002038:	f04f 0200 	mov.w	r2, #0
2000203c:	721a      	strb	r2, [r3, #8]
    /* clear receiver FIFO */
    this_uart->hw_reg_bit->FCR_CLEAR_RX_FIFO = (uint32_t)1;
2000203e:	68fb      	ldr	r3, [r7, #12]
20002040:	685b      	ldr	r3, [r3, #4]
20002042:	f04f 0201 	mov.w	r2, #1
20002046:	f8c3 2104 	str.w	r2, [r3, #260]	; 0x104
    /* clear transmitter FIFO */
    this_uart->hw_reg_bit->FCR_CLEAR_TX_FIFO = (uint32_t)1;
2000204a:	68fb      	ldr	r3, [r7, #12]
2000204c:	685b      	ldr	r3, [r3, #4]
2000204e:	f04f 0201 	mov.w	r2, #1
20002052:	f8c3 2108 	str.w	r2, [r3, #264]	; 0x108
    /* enable RXRDYN and TXRDYN pins. The earlier FCR write to set the TX FIFO
     * trigger level inadvertently disabled the FCR_RXRDY_TXRDYN_EN bit. */
    this_uart->hw_reg_bit->FCR_RXRDY_TXRDYN_EN = (uint32_t)1;
20002056:	68fb      	ldr	r3, [r7, #12]
20002058:	685b      	ldr	r3, [r3, #4]
2000205a:	f04f 0201 	mov.w	r2, #1
2000205e:	f8c3 210c 	str.w	r2, [r3, #268]	; 0x10c

    /* disable loopback */
    this_uart->hw_reg_bit->MCR_LOOP = (uint32_t)0;
20002062:	68fb      	ldr	r3, [r7, #12]
20002064:	685b      	ldr	r3, [r3, #4]
20002066:	f04f 0200 	mov.w	r2, #0
2000206a:	f8c3 2210 	str.w	r2, [r3, #528]	; 0x210

    /* Instance setup */
    this_uart->tx_buff_size = TX_COMPLETE;
2000206e:	68fb      	ldr	r3, [r7, #12]
20002070:	f04f 0200 	mov.w	r2, #0
20002074:	611a      	str	r2, [r3, #16]
    this_uart->tx_buffer = (const uint8_t *)0;
20002076:	68fb      	ldr	r3, [r7, #12]
20002078:	f04f 0200 	mov.w	r2, #0
2000207c:	60da      	str	r2, [r3, #12]
    this_uart->tx_idx = 0U;
2000207e:	68fb      	ldr	r3, [r7, #12]
20002080:	f04f 0200 	mov.w	r2, #0
20002084:	615a      	str	r2, [r3, #20]

    /* Default handlers for MSS UART interrupts */
    this_uart->rx_handler       = NULL_HANDLER;
20002086:	68fb      	ldr	r3, [r7, #12]
20002088:	f04f 0200 	mov.w	r2, #0
2000208c:	61da      	str	r2, [r3, #28]
    this_uart->tx_handler       = default_tx_handler;
2000208e:	68fa      	ldr	r2, [r7, #12]
20002090:	f242 63ad 	movw	r3, #9901	; 0x26ad
20002094:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002098:	6213      	str	r3, [r2, #32]
    this_uart->linests_handler  = NULL_HANDLER;
2000209a:	68fb      	ldr	r3, [r7, #12]
2000209c:	f04f 0200 	mov.w	r2, #0
200020a0:	619a      	str	r2, [r3, #24]
    this_uart->modemsts_handler = NULL_HANDLER;
200020a2:	68fb      	ldr	r3, [r7, #12]
200020a4:	f04f 0200 	mov.w	r2, #0
200020a8:	625a      	str	r2, [r3, #36]	; 0x24

    /* Initialize the sticky status */
    this_uart->status = 0U;
200020aa:	68fb      	ldr	r3, [r7, #12]
200020ac:	f04f 0200 	mov.w	r2, #0
200020b0:	729a      	strb	r2, [r3, #10]
}
200020b2:	f107 0718 	add.w	r7, r7, #24
200020b6:	46bd      	mov	sp, r7
200020b8:	bd80      	pop	{r7, pc}
200020ba:	bf00      	nop

200020bc <MSS_UART_polled_tx>:
(
    mss_uart_instance_t * this_uart,
    const uint8_t * pbuff,
    uint32_t tx_size
)
{
200020bc:	b480      	push	{r7}
200020be:	b089      	sub	sp, #36	; 0x24
200020c0:	af00      	add	r7, sp, #0
200020c2:	60f8      	str	r0, [r7, #12]
200020c4:	60b9      	str	r1, [r7, #8]
200020c6:	607a      	str	r2, [r7, #4]
    uint32_t char_idx = 0U;
200020c8:	f04f 0300 	mov.w	r3, #0
200020cc:	613b      	str	r3, [r7, #16]
    uint32_t size_sent;
    uint8_t status;

    ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );
200020ce:	68fa      	ldr	r2, [r7, #12]
200020d0:	f644 2354 	movw	r3, #19028	; 0x4a54
200020d4:	f2c2 0300 	movt	r3, #8192	; 0x2000
200020d8:	429a      	cmp	r2, r3
200020da:	d007      	beq.n	200020ec <MSS_UART_polled_tx+0x30>
200020dc:	68fa      	ldr	r2, [r7, #12]
200020de:	f644 232c 	movw	r3, #18988	; 0x4a2c
200020e2:	f2c2 0300 	movt	r3, #8192	; 0x2000
200020e6:	429a      	cmp	r2, r3
200020e8:	d000      	beq.n	200020ec <MSS_UART_polled_tx+0x30>
200020ea:	be00      	bkpt	0x0000
    ASSERT( pbuff != ( (uint8_t *)0 ) );
200020ec:	68bb      	ldr	r3, [r7, #8]
200020ee:	2b00      	cmp	r3, #0
200020f0:	d100      	bne.n	200020f4 <MSS_UART_polled_tx+0x38>
200020f2:	be00      	bkpt	0x0000
    ASSERT( tx_size > 0U );
200020f4:	687b      	ldr	r3, [r7, #4]
200020f6:	2b00      	cmp	r3, #0
200020f8:	d100      	bne.n	200020fc <MSS_UART_polled_tx+0x40>
200020fa:	be00      	bkpt	0x0000

    if( ( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) ) &&
200020fc:	68fa      	ldr	r2, [r7, #12]
200020fe:	f644 2354 	movw	r3, #19028	; 0x4a54
20002102:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002106:	429a      	cmp	r2, r3
20002108:	d006      	beq.n	20002118 <MSS_UART_polled_tx+0x5c>
2000210a:	68fa      	ldr	r2, [r7, #12]
2000210c:	f644 232c 	movw	r3, #18988	; 0x4a2c
20002110:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002114:	429a      	cmp	r2, r3
20002116:	d13d      	bne.n	20002194 <MSS_UART_polled_tx+0xd8>
20002118:	68bb      	ldr	r3, [r7, #8]
2000211a:	2b00      	cmp	r3, #0
2000211c:	d03a      	beq.n	20002194 <MSS_UART_polled_tx+0xd8>
2000211e:	687b      	ldr	r3, [r7, #4]
20002120:	2b00      	cmp	r3, #0
20002122:	d037      	beq.n	20002194 <MSS_UART_polled_tx+0xd8>
         /* Remain in this loop until the entire input buffer
          * has been transferred to the UART.
          */
        do {
            /* Read the Line Status Register and update the sticky record */
            status = this_uart->hw_reg->LSR;
20002124:	68fb      	ldr	r3, [r7, #12]
20002126:	681b      	ldr	r3, [r3, #0]
20002128:	7d1b      	ldrb	r3, [r3, #20]
2000212a:	76fb      	strb	r3, [r7, #27]
            this_uart->status |= status;
2000212c:	68fb      	ldr	r3, [r7, #12]
2000212e:	7a9a      	ldrb	r2, [r3, #10]
20002130:	7efb      	ldrb	r3, [r7, #27]
20002132:	ea42 0303 	orr.w	r3, r2, r3
20002136:	b2da      	uxtb	r2, r3
20002138:	68fb      	ldr	r3, [r7, #12]
2000213a:	729a      	strb	r2, [r3, #10]

            /* Check if TX FIFO is empty. */
            if( status & MSS_UART_THRE )
2000213c:	7efb      	ldrb	r3, [r7, #27]
2000213e:	f003 0320 	and.w	r3, r3, #32
20002142:	2b00      	cmp	r3, #0
20002144:	d023      	beq.n	2000218e <MSS_UART_polled_tx+0xd2>
            {
                uint32_t fill_size = TX_FIFO_SIZE;
20002146:	f04f 0310 	mov.w	r3, #16
2000214a:	61fb      	str	r3, [r7, #28]

                /* Calculate the number of bytes to transmit. */
                if ( tx_size < TX_FIFO_SIZE )
2000214c:	687b      	ldr	r3, [r7, #4]
2000214e:	2b0f      	cmp	r3, #15
20002150:	d801      	bhi.n	20002156 <MSS_UART_polled_tx+0x9a>
                {
                    fill_size = tx_size;
20002152:	687b      	ldr	r3, [r7, #4]
20002154:	61fb      	str	r3, [r7, #28]
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for ( size_sent = 0U; size_sent < fill_size; ++size_sent )
20002156:	f04f 0300 	mov.w	r3, #0
2000215a:	617b      	str	r3, [r7, #20]
2000215c:	e00e      	b.n	2000217c <MSS_UART_polled_tx+0xc0>
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx++];
2000215e:	68fb      	ldr	r3, [r7, #12]
20002160:	681b      	ldr	r3, [r3, #0]
20002162:	68b9      	ldr	r1, [r7, #8]
20002164:	693a      	ldr	r2, [r7, #16]
20002166:	440a      	add	r2, r1
20002168:	7812      	ldrb	r2, [r2, #0]
2000216a:	701a      	strb	r2, [r3, #0]
2000216c:	693b      	ldr	r3, [r7, #16]
2000216e:	f103 0301 	add.w	r3, r3, #1
20002172:	613b      	str	r3, [r7, #16]
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for ( size_sent = 0U; size_sent < fill_size; ++size_sent )
20002174:	697b      	ldr	r3, [r7, #20]
20002176:	f103 0301 	add.w	r3, r3, #1
2000217a:	617b      	str	r3, [r7, #20]
2000217c:	697a      	ldr	r2, [r7, #20]
2000217e:	69fb      	ldr	r3, [r7, #28]
20002180:	429a      	cmp	r2, r3
20002182:	d3ec      	bcc.n	2000215e <MSS_UART_polled_tx+0xa2>
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx++];
                }

                /* Calculate the number of untransmitted bytes remaining. */
                tx_size -= size_sent;
20002184:	687a      	ldr	r2, [r7, #4]
20002186:	697b      	ldr	r3, [r7, #20]
20002188:	ebc3 0302 	rsb	r3, r3, r2
2000218c:	607b      	str	r3, [r7, #4]
            }
        }while( tx_size );
2000218e:	687b      	ldr	r3, [r7, #4]
20002190:	2b00      	cmp	r3, #0
20002192:	d1c7      	bne.n	20002124 <MSS_UART_polled_tx+0x68>
    }
}
20002194:	f107 0724 	add.w	r7, r7, #36	; 0x24
20002198:	46bd      	mov	sp, r7
2000219a:	bc80      	pop	{r7}
2000219c:	4770      	bx	lr
2000219e:	bf00      	nop

200021a0 <MSS_UART_polled_tx_string>:
MSS_UART_polled_tx_string
(
    mss_uart_instance_t * this_uart,
    const uint8_t * p_sz_string
)
{
200021a0:	b480      	push	{r7}
200021a2:	b087      	sub	sp, #28
200021a4:	af00      	add	r7, sp, #0
200021a6:	6078      	str	r0, [r7, #4]
200021a8:	6039      	str	r1, [r7, #0]
    uint32_t char_idx = 0U;
200021aa:	f04f 0300 	mov.w	r3, #0
200021ae:	60bb      	str	r3, [r7, #8]
    uint32_t fill_size;
    uint_fast8_t data_byte;
    uint8_t status;

    ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );
200021b0:	687a      	ldr	r2, [r7, #4]
200021b2:	f644 2354 	movw	r3, #19028	; 0x4a54
200021b6:	f2c2 0300 	movt	r3, #8192	; 0x2000
200021ba:	429a      	cmp	r2, r3
200021bc:	d007      	beq.n	200021ce <MSS_UART_polled_tx_string+0x2e>
200021be:	687a      	ldr	r2, [r7, #4]
200021c0:	f644 232c 	movw	r3, #18988	; 0x4a2c
200021c4:	f2c2 0300 	movt	r3, #8192	; 0x2000
200021c8:	429a      	cmp	r2, r3
200021ca:	d000      	beq.n	200021ce <MSS_UART_polled_tx_string+0x2e>
200021cc:	be00      	bkpt	0x0000
    ASSERT( p_sz_string != ( (uint8_t *)0 ) );
200021ce:	683b      	ldr	r3, [r7, #0]
200021d0:	2b00      	cmp	r3, #0
200021d2:	d100      	bne.n	200021d6 <MSS_UART_polled_tx_string+0x36>
200021d4:	be00      	bkpt	0x0000

    if( ( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) ) &&
200021d6:	687a      	ldr	r2, [r7, #4]
200021d8:	f644 2354 	movw	r3, #19028	; 0x4a54
200021dc:	f2c2 0300 	movt	r3, #8192	; 0x2000
200021e0:	429a      	cmp	r2, r3
200021e2:	d006      	beq.n	200021f2 <MSS_UART_polled_tx_string+0x52>
200021e4:	687a      	ldr	r2, [r7, #4]
200021e6:	f644 232c 	movw	r3, #18988	; 0x4a2c
200021ea:	f2c2 0300 	movt	r3, #8192	; 0x2000
200021ee:	429a      	cmp	r2, r3
200021f0:	d138      	bne.n	20002264 <MSS_UART_polled_tx_string+0xc4>
200021f2:	683b      	ldr	r3, [r7, #0]
200021f4:	2b00      	cmp	r3, #0
200021f6:	d035      	beq.n	20002264 <MSS_UART_polled_tx_string+0xc4>
          ( p_sz_string != ( (uint8_t *)0 ) ) )
    {
        /* Get the first data byte from the input buffer */
        data_byte = (uint_fast8_t)p_sz_string[char_idx];
200021f8:	683a      	ldr	r2, [r7, #0]
200021fa:	68bb      	ldr	r3, [r7, #8]
200021fc:	4413      	add	r3, r2
200021fe:	781b      	ldrb	r3, [r3, #0]
20002200:	613b      	str	r3, [r7, #16]

        /* First check for the NULL terminator byte.
         * Then remain in this loop until the entire string in the input buffer
         * has been transferred to the UART.
         */
        while ( 0U != data_byte )
20002202:	e02c      	b.n	2000225e <MSS_UART_polled_tx_string+0xbe>
        {
            /* Wait until TX FIFO is empty. */
            do {
                status = this_uart->hw_reg->LSR;
20002204:	687b      	ldr	r3, [r7, #4]
20002206:	681b      	ldr	r3, [r3, #0]
20002208:	7d1b      	ldrb	r3, [r3, #20]
2000220a:	75fb      	strb	r3, [r7, #23]
                this_uart->status |= status;
2000220c:	687b      	ldr	r3, [r7, #4]
2000220e:	7a9a      	ldrb	r2, [r3, #10]
20002210:	7dfb      	ldrb	r3, [r7, #23]
20002212:	ea42 0303 	orr.w	r3, r2, r3
20002216:	b2da      	uxtb	r2, r3
20002218:	687b      	ldr	r3, [r7, #4]
2000221a:	729a      	strb	r2, [r3, #10]
            } while ( !( status & MSS_UART_THRE ) );
2000221c:	7dfb      	ldrb	r3, [r7, #23]
2000221e:	f003 0320 	and.w	r3, r3, #32
20002222:	2b00      	cmp	r3, #0
20002224:	d0ee      	beq.n	20002204 <MSS_UART_polled_tx_string+0x64>

            /* Send bytes from the input buffer until the TX FIFO is full
             * or we reach the NULL terminator byte.
             */
            fill_size = 0U;
20002226:	f04f 0300 	mov.w	r3, #0
2000222a:	60fb      	str	r3, [r7, #12]
            while ( (0U != data_byte) && (fill_size < TX_FIFO_SIZE) )
2000222c:	e011      	b.n	20002252 <MSS_UART_polled_tx_string+0xb2>
            {
                /* Send the data byte */
                this_uart->hw_reg->THR = data_byte;
2000222e:	687b      	ldr	r3, [r7, #4]
20002230:	681b      	ldr	r3, [r3, #0]
20002232:	693a      	ldr	r2, [r7, #16]
20002234:	b2d2      	uxtb	r2, r2
20002236:	701a      	strb	r2, [r3, #0]
                ++fill_size;
20002238:	68fb      	ldr	r3, [r7, #12]
2000223a:	f103 0301 	add.w	r3, r3, #1
2000223e:	60fb      	str	r3, [r7, #12]
                char_idx++;
20002240:	68bb      	ldr	r3, [r7, #8]
20002242:	f103 0301 	add.w	r3, r3, #1
20002246:	60bb      	str	r3, [r7, #8]
                /* Get the next data byte from the input buffer */
                data_byte = (uint_fast8_t)p_sz_string[char_idx];
20002248:	683a      	ldr	r2, [r7, #0]
2000224a:	68bb      	ldr	r3, [r7, #8]
2000224c:	4413      	add	r3, r2
2000224e:	781b      	ldrb	r3, [r3, #0]
20002250:	613b      	str	r3, [r7, #16]

            /* Send bytes from the input buffer until the TX FIFO is full
             * or we reach the NULL terminator byte.
             */
            fill_size = 0U;
            while ( (0U != data_byte) && (fill_size < TX_FIFO_SIZE) )
20002252:	693b      	ldr	r3, [r7, #16]
20002254:	2b00      	cmp	r3, #0
20002256:	d002      	beq.n	2000225e <MSS_UART_polled_tx_string+0xbe>
20002258:	68fb      	ldr	r3, [r7, #12]
2000225a:	2b0f      	cmp	r3, #15
2000225c:	d9e7      	bls.n	2000222e <MSS_UART_polled_tx_string+0x8e>

        /* First check for the NULL terminator byte.
         * Then remain in this loop until the entire string in the input buffer
         * has been transferred to the UART.
         */
        while ( 0U != data_byte )
2000225e:	693b      	ldr	r3, [r7, #16]
20002260:	2b00      	cmp	r3, #0
20002262:	d1cf      	bne.n	20002204 <MSS_UART_polled_tx_string+0x64>
                /* Get the next data byte from the input buffer */
                data_byte = (uint_fast8_t)p_sz_string[char_idx];
            }
        }
    }
}
20002264:	f107 071c 	add.w	r7, r7, #28
20002268:	46bd      	mov	sp, r7
2000226a:	bc80      	pop	{r7}
2000226c:	4770      	bx	lr
2000226e:	bf00      	nop

20002270 <MSS_UART_irq_tx>:
(
    mss_uart_instance_t * this_uart,
    const uint8_t * pbuff,
    uint32_t tx_size
)
{
20002270:	b580      	push	{r7, lr}
20002272:	b084      	sub	sp, #16
20002274:	af00      	add	r7, sp, #0
20002276:	60f8      	str	r0, [r7, #12]
20002278:	60b9      	str	r1, [r7, #8]
2000227a:	607a      	str	r2, [r7, #4]
    ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );
2000227c:	68fa      	ldr	r2, [r7, #12]
2000227e:	f644 2354 	movw	r3, #19028	; 0x4a54
20002282:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002286:	429a      	cmp	r2, r3
20002288:	d007      	beq.n	2000229a <MSS_UART_irq_tx+0x2a>
2000228a:	68fa      	ldr	r2, [r7, #12]
2000228c:	f644 232c 	movw	r3, #18988	; 0x4a2c
20002290:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002294:	429a      	cmp	r2, r3
20002296:	d000      	beq.n	2000229a <MSS_UART_irq_tx+0x2a>
20002298:	be00      	bkpt	0x0000
    ASSERT( pbuff != ((uint8_t *)0) );
2000229a:	68bb      	ldr	r3, [r7, #8]
2000229c:	2b00      	cmp	r3, #0
2000229e:	d100      	bne.n	200022a2 <MSS_UART_irq_tx+0x32>
200022a0:	be00      	bkpt	0x0000
    ASSERT( tx_size > 0U );
200022a2:	687b      	ldr	r3, [r7, #4]
200022a4:	2b00      	cmp	r3, #0
200022a6:	d100      	bne.n	200022aa <MSS_UART_irq_tx+0x3a>
200022a8:	be00      	bkpt	0x0000

    if ( ( tx_size > 0U ) && ( pbuff != ((uint8_t *)0) ) &&
200022aa:	687b      	ldr	r3, [r7, #4]
200022ac:	2b00      	cmp	r3, #0
200022ae:	d032      	beq.n	20002316 <MSS_UART_irq_tx+0xa6>
200022b0:	68bb      	ldr	r3, [r7, #8]
200022b2:	2b00      	cmp	r3, #0
200022b4:	d02f      	beq.n	20002316 <MSS_UART_irq_tx+0xa6>
       ( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) ) )
200022b6:	68fa      	ldr	r2, [r7, #12]
200022b8:	f644 2354 	movw	r3, #19028	; 0x4a54
200022bc:	f2c2 0300 	movt	r3, #8192	; 0x2000
200022c0:	429a      	cmp	r2, r3
200022c2:	d006      	beq.n	200022d2 <MSS_UART_irq_tx+0x62>
200022c4:	68fa      	ldr	r2, [r7, #12]
200022c6:	f644 232c 	movw	r3, #18988	; 0x4a2c
200022ca:	f2c2 0300 	movt	r3, #8192	; 0x2000
200022ce:	429a      	cmp	r2, r3
200022d0:	d121      	bne.n	20002316 <MSS_UART_irq_tx+0xa6>
    {
        /*Initialise the transmit info for the UART instance with the arguments.*/
        this_uart->tx_buffer = pbuff;
200022d2:	68fb      	ldr	r3, [r7, #12]
200022d4:	68ba      	ldr	r2, [r7, #8]
200022d6:	60da      	str	r2, [r3, #12]
        this_uart->tx_buff_size = tx_size;
200022d8:	68fb      	ldr	r3, [r7, #12]
200022da:	687a      	ldr	r2, [r7, #4]
200022dc:	611a      	str	r2, [r3, #16]
        this_uart->tx_idx = (uint16_t)0;
200022de:	68fb      	ldr	r3, [r7, #12]
200022e0:	f04f 0200 	mov.w	r2, #0
200022e4:	615a      	str	r2, [r3, #20]

        /* Clear any previously pended interrupts */
        NVIC_ClearPendingIRQ( this_uart->irqn );
200022e6:	68fb      	ldr	r3, [r7, #12]
200022e8:	891b      	ldrh	r3, [r3, #8]
200022ea:	b21b      	sxth	r3, r3
200022ec:	4618      	mov	r0, r3
200022ee:	f7ff fdcb 	bl	20001e88 <NVIC_ClearPendingIRQ>

        /* assign default handler for data transfer */
        this_uart->tx_handler = default_tx_handler;
200022f2:	68fa      	ldr	r2, [r7, #12]
200022f4:	f242 63ad 	movw	r3, #9901	; 0x26ad
200022f8:	f2c2 0300 	movt	r3, #8192	; 0x2000
200022fc:	6213      	str	r3, [r2, #32]

        /* enables TX interrupt */
        this_uart->hw_reg_bit->IER_ETBEI = (uint32_t)1;
200022fe:	68fb      	ldr	r3, [r7, #12]
20002300:	685b      	ldr	r3, [r3, #4]
20002302:	f04f 0201 	mov.w	r2, #1
20002306:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84

        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
        NVIC_EnableIRQ( this_uart->irqn );
2000230a:	68fb      	ldr	r3, [r7, #12]
2000230c:	891b      	ldrh	r3, [r3, #8]
2000230e:	b21b      	sxth	r3, r3
20002310:	4618      	mov	r0, r3
20002312:	f7ff fd7f 	bl	20001e14 <NVIC_EnableIRQ>
    }
}
20002316:	f107 0710 	add.w	r7, r7, #16
2000231a:	46bd      	mov	sp, r7
2000231c:	bd80      	pop	{r7, pc}
2000231e:	bf00      	nop

20002320 <MSS_UART_tx_complete>:
int8_t
MSS_UART_tx_complete
(
    mss_uart_instance_t * this_uart
)
{
20002320:	b480      	push	{r7}
20002322:	b085      	sub	sp, #20
20002324:	af00      	add	r7, sp, #0
20002326:	6078      	str	r0, [r7, #4]
    int8_t ret_value = 0;
20002328:	f04f 0300 	mov.w	r3, #0
2000232c:	73bb      	strb	r3, [r7, #14]
    uint8_t status = 0U;
2000232e:	f04f 0300 	mov.w	r3, #0
20002332:	73fb      	strb	r3, [r7, #15]

    ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );
20002334:	687a      	ldr	r2, [r7, #4]
20002336:	f644 2354 	movw	r3, #19028	; 0x4a54
2000233a:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000233e:	429a      	cmp	r2, r3
20002340:	d007      	beq.n	20002352 <MSS_UART_tx_complete+0x32>
20002342:	687a      	ldr	r2, [r7, #4]
20002344:	f644 232c 	movw	r3, #18988	; 0x4a2c
20002348:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000234c:	429a      	cmp	r2, r3
2000234e:	d000      	beq.n	20002352 <MSS_UART_tx_complete+0x32>
20002350:	be00      	bkpt	0x0000

    if ( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) )
20002352:	687a      	ldr	r2, [r7, #4]
20002354:	f644 2354 	movw	r3, #19028	; 0x4a54
20002358:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000235c:	429a      	cmp	r2, r3
2000235e:	d006      	beq.n	2000236e <MSS_UART_tx_complete+0x4e>
20002360:	687a      	ldr	r2, [r7, #4]
20002362:	f644 232c 	movw	r3, #18988	; 0x4a2c
20002366:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000236a:	429a      	cmp	r2, r3
2000236c:	d117      	bne.n	2000239e <MSS_UART_tx_complete+0x7e>
    {
        /* Read the Line Status Register and update the sticky record. */
        status = this_uart->hw_reg->LSR;
2000236e:	687b      	ldr	r3, [r7, #4]
20002370:	681b      	ldr	r3, [r3, #0]
20002372:	7d1b      	ldrb	r3, [r3, #20]
20002374:	73fb      	strb	r3, [r7, #15]
        this_uart->status |= status;
20002376:	687b      	ldr	r3, [r7, #4]
20002378:	7a9a      	ldrb	r2, [r3, #10]
2000237a:	7bfb      	ldrb	r3, [r7, #15]
2000237c:	ea42 0303 	orr.w	r3, r2, r3
20002380:	b2da      	uxtb	r2, r3
20002382:	687b      	ldr	r3, [r7, #4]
20002384:	729a      	strb	r2, [r3, #10]

        if ( ( TX_COMPLETE == this_uart->tx_buff_size ) &&
20002386:	687b      	ldr	r3, [r7, #4]
20002388:	691b      	ldr	r3, [r3, #16]
2000238a:	2b00      	cmp	r3, #0
2000238c:	d107      	bne.n	2000239e <MSS_UART_tx_complete+0x7e>
             ( status & MSS_UART_TEMT ) )
2000238e:	7bfb      	ldrb	r3, [r7, #15]
20002390:	f003 0340 	and.w	r3, r3, #64	; 0x40
    {
        /* Read the Line Status Register and update the sticky record. */
        status = this_uart->hw_reg->LSR;
        this_uart->status |= status;

        if ( ( TX_COMPLETE == this_uart->tx_buff_size ) &&
20002394:	2b00      	cmp	r3, #0
20002396:	d002      	beq.n	2000239e <MSS_UART_tx_complete+0x7e>
             ( status & MSS_UART_TEMT ) )
        {
            ret_value = (int8_t)1;
20002398:	f04f 0301 	mov.w	r3, #1
2000239c:	73bb      	strb	r3, [r7, #14]
        }
    }
    return ret_value;
2000239e:	7bbb      	ldrb	r3, [r7, #14]
200023a0:	b25b      	sxtb	r3, r3
}
200023a2:	4618      	mov	r0, r3
200023a4:	f107 0714 	add.w	r7, r7, #20
200023a8:	46bd      	mov	sp, r7
200023aa:	bc80      	pop	{r7}
200023ac:	4770      	bx	lr
200023ae:	bf00      	nop

200023b0 <MSS_UART_get_rx>:
(
    mss_uart_instance_t * this_uart,
    uint8_t * rx_buff,
    size_t buff_size
)
{
200023b0:	b480      	push	{r7}
200023b2:	b087      	sub	sp, #28
200023b4:	af00      	add	r7, sp, #0
200023b6:	60f8      	str	r0, [r7, #12]
200023b8:	60b9      	str	r1, [r7, #8]
200023ba:	607a      	str	r2, [r7, #4]
    size_t rx_size = 0U;
200023bc:	f04f 0300 	mov.w	r3, #0
200023c0:	613b      	str	r3, [r7, #16]
    uint8_t status = 0U;
200023c2:	f04f 0300 	mov.w	r3, #0
200023c6:	75fb      	strb	r3, [r7, #23]

    ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );
200023c8:	68fa      	ldr	r2, [r7, #12]
200023ca:	f644 2354 	movw	r3, #19028	; 0x4a54
200023ce:	f2c2 0300 	movt	r3, #8192	; 0x2000
200023d2:	429a      	cmp	r2, r3
200023d4:	d007      	beq.n	200023e6 <MSS_UART_get_rx+0x36>
200023d6:	68fa      	ldr	r2, [r7, #12]
200023d8:	f644 232c 	movw	r3, #18988	; 0x4a2c
200023dc:	f2c2 0300 	movt	r3, #8192	; 0x2000
200023e0:	429a      	cmp	r2, r3
200023e2:	d000      	beq.n	200023e6 <MSS_UART_get_rx+0x36>
200023e4:	be00      	bkpt	0x0000
    ASSERT( rx_buff != ((uint8_t *)0) );
200023e6:	68bb      	ldr	r3, [r7, #8]
200023e8:	2b00      	cmp	r3, #0
200023ea:	d100      	bne.n	200023ee <MSS_UART_get_rx+0x3e>
200023ec:	be00      	bkpt	0x0000
    ASSERT( buff_size > 0U );
200023ee:	687b      	ldr	r3, [r7, #4]
200023f0:	2b00      	cmp	r3, #0
200023f2:	d100      	bne.n	200023f6 <MSS_UART_get_rx+0x46>
200023f4:	be00      	bkpt	0x0000

    if( ( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) ) &&
200023f6:	68fa      	ldr	r2, [r7, #12]
200023f8:	f644 2354 	movw	r3, #19028	; 0x4a54
200023fc:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002400:	429a      	cmp	r2, r3
20002402:	d006      	beq.n	20002412 <MSS_UART_get_rx+0x62>
20002404:	68fa      	ldr	r2, [r7, #12]
20002406:	f644 232c 	movw	r3, #18988	; 0x4a2c
2000240a:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000240e:	429a      	cmp	r2, r3
20002410:	d134      	bne.n	2000247c <MSS_UART_get_rx+0xcc>
20002412:	68bb      	ldr	r3, [r7, #8]
20002414:	2b00      	cmp	r3, #0
20002416:	d031      	beq.n	2000247c <MSS_UART_get_rx+0xcc>
20002418:	687b      	ldr	r3, [r7, #4]
2000241a:	2b00      	cmp	r3, #0
2000241c:	d02e      	beq.n	2000247c <MSS_UART_get_rx+0xcc>
          ( rx_buff != ((uint8_t *)0) ) && ( buff_size > 0U ) )
    {
        status = this_uart->hw_reg->LSR;
2000241e:	68fb      	ldr	r3, [r7, #12]
20002420:	681b      	ldr	r3, [r3, #0]
20002422:	7d1b      	ldrb	r3, [r3, #20]
20002424:	75fb      	strb	r3, [r7, #23]
        this_uart->status |= status;
20002426:	68fb      	ldr	r3, [r7, #12]
20002428:	7a9a      	ldrb	r2, [r3, #10]
2000242a:	7dfb      	ldrb	r3, [r7, #23]
2000242c:	ea42 0303 	orr.w	r3, r2, r3
20002430:	b2da      	uxtb	r2, r3
20002432:	68fb      	ldr	r3, [r7, #12]
20002434:	729a      	strb	r2, [r3, #10]

        while (( (status & MSS_UART_DATA_READY) != 0U) &&
20002436:	e017      	b.n	20002468 <MSS_UART_get_rx+0xb8>
               ( rx_size < buff_size ) )
        {
            rx_buff[rx_size] = this_uart->hw_reg->RBR;
20002438:	68ba      	ldr	r2, [r7, #8]
2000243a:	693b      	ldr	r3, [r7, #16]
2000243c:	4413      	add	r3, r2
2000243e:	68fa      	ldr	r2, [r7, #12]
20002440:	6812      	ldr	r2, [r2, #0]
20002442:	7812      	ldrb	r2, [r2, #0]
20002444:	b2d2      	uxtb	r2, r2
20002446:	701a      	strb	r2, [r3, #0]
            ++rx_size;
20002448:	693b      	ldr	r3, [r7, #16]
2000244a:	f103 0301 	add.w	r3, r3, #1
2000244e:	613b      	str	r3, [r7, #16]
            status = this_uart->hw_reg->LSR;
20002450:	68fb      	ldr	r3, [r7, #12]
20002452:	681b      	ldr	r3, [r3, #0]
20002454:	7d1b      	ldrb	r3, [r3, #20]
20002456:	75fb      	strb	r3, [r7, #23]
            this_uart->status |= status;
20002458:	68fb      	ldr	r3, [r7, #12]
2000245a:	7a9a      	ldrb	r2, [r3, #10]
2000245c:	7dfb      	ldrb	r3, [r7, #23]
2000245e:	ea42 0303 	orr.w	r3, r2, r3
20002462:	b2da      	uxtb	r2, r3
20002464:	68fb      	ldr	r3, [r7, #12]
20002466:	729a      	strb	r2, [r3, #10]
          ( rx_buff != ((uint8_t *)0) ) && ( buff_size > 0U ) )
    {
        status = this_uart->hw_reg->LSR;
        this_uart->status |= status;

        while (( (status & MSS_UART_DATA_READY) != 0U) &&
20002468:	7dfb      	ldrb	r3, [r7, #23]
2000246a:	f003 0301 	and.w	r3, r3, #1
2000246e:	b2db      	uxtb	r3, r3
20002470:	2b00      	cmp	r3, #0
20002472:	d003      	beq.n	2000247c <MSS_UART_get_rx+0xcc>
20002474:	693a      	ldr	r2, [r7, #16]
20002476:	687b      	ldr	r3, [r7, #4]
20002478:	429a      	cmp	r2, r3
2000247a:	d3dd      	bcc.n	20002438 <MSS_UART_get_rx+0x88>
            ++rx_size;
            status = this_uart->hw_reg->LSR;
            this_uart->status |= status;
        }
    }
    return rx_size;
2000247c:	693b      	ldr	r3, [r7, #16]
}
2000247e:	4618      	mov	r0, r3
20002480:	f107 071c 	add.w	r7, r7, #28
20002484:	46bd      	mov	sp, r7
20002486:	bc80      	pop	{r7}
20002488:	4770      	bx	lr
2000248a:	bf00      	nop

2000248c <MSS_UART_enable_irq>:
MSS_UART_enable_irq
(
    mss_uart_instance_t * this_uart,
    uint8_t irq_mask
)
{
2000248c:	b580      	push	{r7, lr}
2000248e:	b082      	sub	sp, #8
20002490:	af00      	add	r7, sp, #0
20002492:	6078      	str	r0, [r7, #4]
20002494:	460b      	mov	r3, r1
20002496:	70fb      	strb	r3, [r7, #3]
    ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );
20002498:	687a      	ldr	r2, [r7, #4]
2000249a:	f644 2354 	movw	r3, #19028	; 0x4a54
2000249e:	f2c2 0300 	movt	r3, #8192	; 0x2000
200024a2:	429a      	cmp	r2, r3
200024a4:	d007      	beq.n	200024b6 <MSS_UART_enable_irq+0x2a>
200024a6:	687a      	ldr	r2, [r7, #4]
200024a8:	f644 232c 	movw	r3, #18988	; 0x4a2c
200024ac:	f2c2 0300 	movt	r3, #8192	; 0x2000
200024b0:	429a      	cmp	r2, r3
200024b2:	d000      	beq.n	200024b6 <MSS_UART_enable_irq+0x2a>
200024b4:	be00      	bkpt	0x0000

    if( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) )
200024b6:	687a      	ldr	r2, [r7, #4]
200024b8:	f644 2354 	movw	r3, #19028	; 0x4a54
200024bc:	f2c2 0300 	movt	r3, #8192	; 0x2000
200024c0:	429a      	cmp	r2, r3
200024c2:	d006      	beq.n	200024d2 <MSS_UART_enable_irq+0x46>
200024c4:	687a      	ldr	r2, [r7, #4]
200024c6:	f644 232c 	movw	r3, #18988	; 0x4a2c
200024ca:	f2c2 0300 	movt	r3, #8192	; 0x2000
200024ce:	429a      	cmp	r2, r3
200024d0:	d116      	bne.n	20002500 <MSS_UART_enable_irq+0x74>
    {
        /* Clear any previously pended interrupts */
        NVIC_ClearPendingIRQ( this_uart->irqn );
200024d2:	687b      	ldr	r3, [r7, #4]
200024d4:	891b      	ldrh	r3, [r3, #8]
200024d6:	b21b      	sxth	r3, r3
200024d8:	4618      	mov	r0, r3
200024da:	f7ff fcd5 	bl	20001e88 <NVIC_ClearPendingIRQ>
         * bit 0 - Receive Data Available Interrupt
         * bit 1 - Transmitter Holding  Register Empty Interrupt
         * bit 2 - Receiver Line Status Interrupt
         * bit 3 - Modem Status Interrupt
         */
        this_uart->hw_reg->IER |= irq_mask;
200024de:	687b      	ldr	r3, [r7, #4]
200024e0:	681b      	ldr	r3, [r3, #0]
200024e2:	687a      	ldr	r2, [r7, #4]
200024e4:	6812      	ldr	r2, [r2, #0]
200024e6:	7912      	ldrb	r2, [r2, #4]
200024e8:	b2d1      	uxtb	r1, r2
200024ea:	78fa      	ldrb	r2, [r7, #3]
200024ec:	ea41 0202 	orr.w	r2, r1, r2
200024f0:	b2d2      	uxtb	r2, r2
200024f2:	711a      	strb	r2, [r3, #4]

        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
        NVIC_EnableIRQ( this_uart->irqn );
200024f4:	687b      	ldr	r3, [r7, #4]
200024f6:	891b      	ldrh	r3, [r3, #8]
200024f8:	b21b      	sxth	r3, r3
200024fa:	4618      	mov	r0, r3
200024fc:	f7ff fc8a 	bl	20001e14 <NVIC_EnableIRQ>
    }
}
20002500:	f107 0708 	add.w	r7, r7, #8
20002504:	46bd      	mov	sp, r7
20002506:	bd80      	pop	{r7, pc}

20002508 <MSS_UART_disable_irq>:
MSS_UART_disable_irq
(
    mss_uart_instance_t * this_uart,
    uint8_t irq_mask
)
{
20002508:	b580      	push	{r7, lr}
2000250a:	b082      	sub	sp, #8
2000250c:	af00      	add	r7, sp, #0
2000250e:	6078      	str	r0, [r7, #4]
20002510:	460b      	mov	r3, r1
20002512:	70fb      	strb	r3, [r7, #3]
    ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );
20002514:	687a      	ldr	r2, [r7, #4]
20002516:	f644 2354 	movw	r3, #19028	; 0x4a54
2000251a:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000251e:	429a      	cmp	r2, r3
20002520:	d007      	beq.n	20002532 <MSS_UART_disable_irq+0x2a>
20002522:	687a      	ldr	r2, [r7, #4]
20002524:	f644 232c 	movw	r3, #18988	; 0x4a2c
20002528:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000252c:	429a      	cmp	r2, r3
2000252e:	d000      	beq.n	20002532 <MSS_UART_disable_irq+0x2a>
20002530:	be00      	bkpt	0x0000

    if( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) )
20002532:	687a      	ldr	r2, [r7, #4]
20002534:	f644 2354 	movw	r3, #19028	; 0x4a54
20002538:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000253c:	429a      	cmp	r2, r3
2000253e:	d006      	beq.n	2000254e <MSS_UART_disable_irq+0x46>
20002540:	687a      	ldr	r2, [r7, #4]
20002542:	f644 232c 	movw	r3, #18988	; 0x4a2c
20002546:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000254a:	429a      	cmp	r2, r3
2000254c:	d11c      	bne.n	20002588 <MSS_UART_disable_irq+0x80>
         * bit 0 - Receive Data Available Interrupt
         * bit 1 - Transmitter Holding  Register Empty Interrupt
         * bit 2 - Receiver Line Status Interrupt
         * bit 3 - Modem Status Interrupt
         */
        this_uart->hw_reg->IER &= ( (uint8_t)~irq_mask );
2000254e:	687b      	ldr	r3, [r7, #4]
20002550:	681b      	ldr	r3, [r3, #0]
20002552:	687a      	ldr	r2, [r7, #4]
20002554:	6812      	ldr	r2, [r2, #0]
20002556:	7912      	ldrb	r2, [r2, #4]
20002558:	b2d1      	uxtb	r1, r2
2000255a:	78fa      	ldrb	r2, [r7, #3]
2000255c:	ea6f 0202 	mvn.w	r2, r2
20002560:	b2d2      	uxtb	r2, r2
20002562:	ea01 0202 	and.w	r2, r1, r2
20002566:	b2d2      	uxtb	r2, r2
20002568:	711a      	strb	r2, [r3, #4]

        /* Clear any previously pended interrupts */
        NVIC_ClearPendingIRQ( this_uart->irqn );
2000256a:	687b      	ldr	r3, [r7, #4]
2000256c:	891b      	ldrh	r3, [r3, #8]
2000256e:	b21b      	sxth	r3, r3
20002570:	4618      	mov	r0, r3
20002572:	f7ff fc89 	bl	20001e88 <NVIC_ClearPendingIRQ>

        if( irq_mask == IIRF_MASK )
20002576:	78fb      	ldrb	r3, [r7, #3]
20002578:	2b0f      	cmp	r3, #15
2000257a:	d105      	bne.n	20002588 <MSS_UART_disable_irq+0x80>
        {
            /* Disable UART instance interrupt in Cortex-M3 NVIC. */
            NVIC_DisableIRQ( this_uart->irqn );
2000257c:	687b      	ldr	r3, [r7, #4]
2000257e:	891b      	ldrh	r3, [r3, #8]
20002580:	b21b      	sxth	r3, r3
20002582:	4618      	mov	r0, r3
20002584:	f7ff fc62 	bl	20001e4c <NVIC_DisableIRQ>

        }
    }
}
20002588:	f107 0708 	add.w	r7, r7, #8
2000258c:	46bd      	mov	sp, r7
2000258e:	bd80      	pop	{r7, pc}

20002590 <MSS_UART_isr>:
static void
MSS_UART_isr
(
    mss_uart_instance_t * this_uart
)
{
20002590:	b580      	push	{r7, lr}
20002592:	b084      	sub	sp, #16
20002594:	af00      	add	r7, sp, #0
20002596:	6078      	str	r0, [r7, #4]
    uint8_t iirf;

    ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );
20002598:	687a      	ldr	r2, [r7, #4]
2000259a:	f644 2354 	movw	r3, #19028	; 0x4a54
2000259e:	f2c2 0300 	movt	r3, #8192	; 0x2000
200025a2:	429a      	cmp	r2, r3
200025a4:	d007      	beq.n	200025b6 <MSS_UART_isr+0x26>
200025a6:	687a      	ldr	r2, [r7, #4]
200025a8:	f644 232c 	movw	r3, #18988	; 0x4a2c
200025ac:	f2c2 0300 	movt	r3, #8192	; 0x2000
200025b0:	429a      	cmp	r2, r3
200025b2:	d000      	beq.n	200025b6 <MSS_UART_isr+0x26>
200025b4:	be00      	bkpt	0x0000

    if ( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) )
200025b6:	687a      	ldr	r2, [r7, #4]
200025b8:	f644 2354 	movw	r3, #19028	; 0x4a54
200025bc:	f2c2 0300 	movt	r3, #8192	; 0x2000
200025c0:	429a      	cmp	r2, r3
200025c2:	d006      	beq.n	200025d2 <MSS_UART_isr+0x42>
200025c4:	687a      	ldr	r2, [r7, #4]
200025c6:	f644 232c 	movw	r3, #18988	; 0x4a2c
200025ca:	f2c2 0300 	movt	r3, #8192	; 0x2000
200025ce:	429a      	cmp	r2, r3
200025d0:	d167      	bne.n	200026a2 <MSS_UART_isr+0x112>
    {
        iirf = this_uart->hw_reg->IIR & IIRF_MASK;
200025d2:	687b      	ldr	r3, [r7, #4]
200025d4:	681b      	ldr	r3, [r3, #0]
200025d6:	7a1b      	ldrb	r3, [r3, #8]
200025d8:	b2db      	uxtb	r3, r3
200025da:	f003 030f 	and.w	r3, r3, #15
200025de:	73fb      	strb	r3, [r7, #15]

        switch ( iirf )
200025e0:	7bfb      	ldrb	r3, [r7, #15]
200025e2:	2b0c      	cmp	r3, #12
200025e4:	d854      	bhi.n	20002690 <MSS_UART_isr+0x100>
200025e6:	a201      	add	r2, pc, #4	; (adr r2, 200025ec <MSS_UART_isr+0x5c>)
200025e8:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
200025ec:	20002621 	.word	0x20002621
200025f0:	20002691 	.word	0x20002691
200025f4:	2000263d 	.word	0x2000263d
200025f8:	20002691 	.word	0x20002691
200025fc:	20002659 	.word	0x20002659
20002600:	20002691 	.word	0x20002691
20002604:	20002675 	.word	0x20002675
20002608:	20002691 	.word	0x20002691
2000260c:	20002691 	.word	0x20002691
20002610:	20002691 	.word	0x20002691
20002614:	20002691 	.word	0x20002691
20002618:	20002691 	.word	0x20002691
2000261c:	20002659 	.word	0x20002659
        {
            case IIRF_MODEM_STATUS:  /* Modem status interrupt */
            {
                ASSERT( NULL_HANDLER != this_uart->modemsts_handler );
20002620:	687b      	ldr	r3, [r7, #4]
20002622:	6a5b      	ldr	r3, [r3, #36]	; 0x24
20002624:	2b00      	cmp	r3, #0
20002626:	d100      	bne.n	2000262a <MSS_UART_isr+0x9a>
20002628:	be00      	bkpt	0x0000
                if( NULL_HANDLER != this_uart->modemsts_handler )
2000262a:	687b      	ldr	r3, [r7, #4]
2000262c:	6a5b      	ldr	r3, [r3, #36]	; 0x24
2000262e:	2b00      	cmp	r3, #0
20002630:	d030      	beq.n	20002694 <MSS_UART_isr+0x104>
                {
                   (*(this_uart->modemsts_handler))( this_uart );
20002632:	687b      	ldr	r3, [r7, #4]
20002634:	6a5b      	ldr	r3, [r3, #36]	; 0x24
20002636:	6878      	ldr	r0, [r7, #4]
20002638:	4798      	blx	r3
                }
            }
            break;
2000263a:	e032      	b.n	200026a2 <MSS_UART_isr+0x112>

            case IIRF_THRE: /* Transmitter Holding Register Empty */
            {
                ASSERT( NULL_HANDLER != this_uart->tx_handler );
2000263c:	687b      	ldr	r3, [r7, #4]
2000263e:	6a1b      	ldr	r3, [r3, #32]
20002640:	2b00      	cmp	r3, #0
20002642:	d100      	bne.n	20002646 <MSS_UART_isr+0xb6>
20002644:	be00      	bkpt	0x0000
                if ( NULL_HANDLER != this_uart->tx_handler )
20002646:	687b      	ldr	r3, [r7, #4]
20002648:	6a1b      	ldr	r3, [r3, #32]
2000264a:	2b00      	cmp	r3, #0
2000264c:	d024      	beq.n	20002698 <MSS_UART_isr+0x108>
                {
                    (*(this_uart->tx_handler))( this_uart );
2000264e:	687b      	ldr	r3, [r7, #4]
20002650:	6a1b      	ldr	r3, [r3, #32]
20002652:	6878      	ldr	r0, [r7, #4]
20002654:	4798      	blx	r3
                }
            }
            break;
20002656:	e024      	b.n	200026a2 <MSS_UART_isr+0x112>

            case IIRF_RX_DATA:      /* Received Data Available */
            case IIRF_DATA_TIMEOUT: /* Received Data Timed-out */
            {
                ASSERT( NULL_HANDLER != this_uart->rx_handler );
20002658:	687b      	ldr	r3, [r7, #4]
2000265a:	69db      	ldr	r3, [r3, #28]
2000265c:	2b00      	cmp	r3, #0
2000265e:	d100      	bne.n	20002662 <MSS_UART_isr+0xd2>
20002660:	be00      	bkpt	0x0000
                if ( NULL_HANDLER != this_uart->rx_handler )
20002662:	687b      	ldr	r3, [r7, #4]
20002664:	69db      	ldr	r3, [r3, #28]
20002666:	2b00      	cmp	r3, #0
20002668:	d018      	beq.n	2000269c <MSS_UART_isr+0x10c>
                {
                    (*(this_uart->rx_handler))( this_uart );
2000266a:	687b      	ldr	r3, [r7, #4]
2000266c:	69db      	ldr	r3, [r3, #28]
2000266e:	6878      	ldr	r0, [r7, #4]
20002670:	4798      	blx	r3
                }
            }
            break;
20002672:	e016      	b.n	200026a2 <MSS_UART_isr+0x112>

            case IIRF_RX_LINE_STATUS:  /* Line Status Interrupt */
            {
                ASSERT( NULL_HANDLER != this_uart->linests_handler );
20002674:	687b      	ldr	r3, [r7, #4]
20002676:	699b      	ldr	r3, [r3, #24]
20002678:	2b00      	cmp	r3, #0
2000267a:	d100      	bne.n	2000267e <MSS_UART_isr+0xee>
2000267c:	be00      	bkpt	0x0000
                if ( NULL_HANDLER != this_uart->linests_handler )
2000267e:	687b      	ldr	r3, [r7, #4]
20002680:	699b      	ldr	r3, [r3, #24]
20002682:	2b00      	cmp	r3, #0
20002684:	d00c      	beq.n	200026a0 <MSS_UART_isr+0x110>
                {
                   (*(this_uart->linests_handler))( this_uart );
20002686:	687b      	ldr	r3, [r7, #4]
20002688:	699b      	ldr	r3, [r3, #24]
2000268a:	6878      	ldr	r0, [r7, #4]
2000268c:	4798      	blx	r3
                }
            }
            break;
2000268e:	e008      	b.n	200026a2 <MSS_UART_isr+0x112>

            default:
            {
                ASSERT( INVALID_INTERRUPT );
20002690:	be00      	bkpt	0x0000
20002692:	e006      	b.n	200026a2 <MSS_UART_isr+0x112>
                if( NULL_HANDLER != this_uart->modemsts_handler )
                {
                   (*(this_uart->modemsts_handler))( this_uart );
                }
            }
            break;
20002694:	bf00      	nop
20002696:	e004      	b.n	200026a2 <MSS_UART_isr+0x112>
                if ( NULL_HANDLER != this_uart->tx_handler )
                {
                    (*(this_uart->tx_handler))( this_uart );
                }
            }
            break;
20002698:	bf00      	nop
2000269a:	e002      	b.n	200026a2 <MSS_UART_isr+0x112>
                if ( NULL_HANDLER != this_uart->rx_handler )
                {
                    (*(this_uart->rx_handler))( this_uart );
                }
            }
            break;
2000269c:	bf00      	nop
2000269e:	e000      	b.n	200026a2 <MSS_UART_isr+0x112>
                if ( NULL_HANDLER != this_uart->linests_handler )
                {
                   (*(this_uart->linests_handler))( this_uart );
                }
            }
            break;
200026a0:	bf00      	nop
                ASSERT( INVALID_INTERRUPT );
            }
            break;
        }
    }
}
200026a2:	f107 0710 	add.w	r7, r7, #16
200026a6:	46bd      	mov	sp, r7
200026a8:	bd80      	pop	{r7, pc}
200026aa:	bf00      	nop

200026ac <default_tx_handler>:
static void
default_tx_handler
(
    mss_uart_instance_t * this_uart
)
{
200026ac:	b480      	push	{r7}
200026ae:	b087      	sub	sp, #28
200026b0:	af00      	add	r7, sp, #0
200026b2:	6078      	str	r0, [r7, #4]
    uint8_t status;

    ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );
200026b4:	687a      	ldr	r2, [r7, #4]
200026b6:	f644 2354 	movw	r3, #19028	; 0x4a54
200026ba:	f2c2 0300 	movt	r3, #8192	; 0x2000
200026be:	429a      	cmp	r2, r3
200026c0:	d007      	beq.n	200026d2 <default_tx_handler+0x26>
200026c2:	687a      	ldr	r2, [r7, #4]
200026c4:	f644 232c 	movw	r3, #18988	; 0x4a2c
200026c8:	f2c2 0300 	movt	r3, #8192	; 0x2000
200026cc:	429a      	cmp	r2, r3
200026ce:	d000      	beq.n	200026d2 <default_tx_handler+0x26>
200026d0:	be00      	bkpt	0x0000
    ASSERT( ( (uint8_t *)0 ) != this_uart->tx_buffer );
200026d2:	687b      	ldr	r3, [r7, #4]
200026d4:	68db      	ldr	r3, [r3, #12]
200026d6:	2b00      	cmp	r3, #0
200026d8:	d100      	bne.n	200026dc <default_tx_handler+0x30>
200026da:	be00      	bkpt	0x0000
    ASSERT( 0U < this_uart->tx_buff_size );
200026dc:	687b      	ldr	r3, [r7, #4]
200026de:	691b      	ldr	r3, [r3, #16]
200026e0:	2b00      	cmp	r3, #0
200026e2:	d100      	bne.n	200026e6 <default_tx_handler+0x3a>
200026e4:	be00      	bkpt	0x0000

    if( ( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) ) &&
200026e6:	687a      	ldr	r2, [r7, #4]
200026e8:	f644 2354 	movw	r3, #19028	; 0x4a54
200026ec:	f2c2 0300 	movt	r3, #8192	; 0x2000
200026f0:	429a      	cmp	r2, r3
200026f2:	d006      	beq.n	20002702 <default_tx_handler+0x56>
200026f4:	687a      	ldr	r2, [r7, #4]
200026f6:	f644 232c 	movw	r3, #18988	; 0x4a2c
200026fa:	f2c2 0300 	movt	r3, #8192	; 0x2000
200026fe:	429a      	cmp	r2, r3
20002700:	d152      	bne.n	200027a8 <default_tx_handler+0xfc>
        ( ( (uint8_t *)0 ) != this_uart->tx_buffer ) &&
20002702:	687b      	ldr	r3, [r7, #4]
20002704:	68db      	ldr	r3, [r3, #12]

    ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );
    ASSERT( ( (uint8_t *)0 ) != this_uart->tx_buffer );
    ASSERT( 0U < this_uart->tx_buff_size );

    if( ( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) ) &&
20002706:	2b00      	cmp	r3, #0
20002708:	d04e      	beq.n	200027a8 <default_tx_handler+0xfc>
        ( ( (uint8_t *)0 ) != this_uart->tx_buffer ) &&
        ( 0U < this_uart->tx_buff_size ) )
2000270a:	687b      	ldr	r3, [r7, #4]
2000270c:	691b      	ldr	r3, [r3, #16]

    ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );
    ASSERT( ( (uint8_t *)0 ) != this_uart->tx_buffer );
    ASSERT( 0U < this_uart->tx_buff_size );

    if( ( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) ) &&
2000270e:	2b00      	cmp	r3, #0
20002710:	d04a      	beq.n	200027a8 <default_tx_handler+0xfc>
        ( ( (uint8_t *)0 ) != this_uart->tx_buffer ) &&
        ( 0U < this_uart->tx_buff_size ) )
    {
        /* Read the Line Status Register and update the sticky record. */
        status = this_uart->hw_reg->LSR;
20002712:	687b      	ldr	r3, [r7, #4]
20002714:	681b      	ldr	r3, [r3, #0]
20002716:	7d1b      	ldrb	r3, [r3, #20]
20002718:	72fb      	strb	r3, [r7, #11]
        this_uart->status |= status;
2000271a:	687b      	ldr	r3, [r7, #4]
2000271c:	7a9a      	ldrb	r2, [r3, #10]
2000271e:	7afb      	ldrb	r3, [r7, #11]
20002720:	ea42 0303 	orr.w	r3, r2, r3
20002724:	b2da      	uxtb	r2, r3
20002726:	687b      	ldr	r3, [r7, #4]
20002728:	729a      	strb	r2, [r3, #10]

        /*
         * This function should only be called as a result of a THRE interrupt.
         * Verify that this is true before proceeding to transmit data.
         */
        if ( status & MSS_UART_THRE )
2000272a:	7afb      	ldrb	r3, [r7, #11]
2000272c:	f003 0320 	and.w	r3, r3, #32
20002730:	2b00      	cmp	r3, #0
20002732:	d029      	beq.n	20002788 <default_tx_handler+0xdc>
        {
            uint32_t i;
            uint32_t fill_size = TX_FIFO_SIZE;
20002734:	f04f 0310 	mov.w	r3, #16
20002738:	613b      	str	r3, [r7, #16]
            uint32_t tx_remain = this_uart->tx_buff_size - this_uart->tx_idx;
2000273a:	687b      	ldr	r3, [r7, #4]
2000273c:	691a      	ldr	r2, [r3, #16]
2000273e:	687b      	ldr	r3, [r7, #4]
20002740:	695b      	ldr	r3, [r3, #20]
20002742:	ebc3 0302 	rsb	r3, r3, r2
20002746:	617b      	str	r3, [r7, #20]

            /* Calculate the number of bytes to transmit. */
            if ( tx_remain < TX_FIFO_SIZE )
20002748:	697b      	ldr	r3, [r7, #20]
2000274a:	2b0f      	cmp	r3, #15
2000274c:	d801      	bhi.n	20002752 <default_tx_handler+0xa6>
            {
                fill_size = tx_remain;
2000274e:	697b      	ldr	r3, [r7, #20]
20002750:	613b      	str	r3, [r7, #16]
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for ( i = 0U; i < fill_size; ++i )
20002752:	f04f 0300 	mov.w	r3, #0
20002756:	60fb      	str	r3, [r7, #12]
20002758:	e012      	b.n	20002780 <default_tx_handler+0xd4>
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
2000275a:	687b      	ldr	r3, [r7, #4]
2000275c:	681b      	ldr	r3, [r3, #0]
2000275e:	687a      	ldr	r2, [r7, #4]
20002760:	68d1      	ldr	r1, [r2, #12]
20002762:	687a      	ldr	r2, [r7, #4]
20002764:	6952      	ldr	r2, [r2, #20]
20002766:	440a      	add	r2, r1
20002768:	7812      	ldrb	r2, [r2, #0]
2000276a:	701a      	strb	r2, [r3, #0]
                ++this_uart->tx_idx;
2000276c:	687b      	ldr	r3, [r7, #4]
2000276e:	695b      	ldr	r3, [r3, #20]
20002770:	f103 0201 	add.w	r2, r3, #1
20002774:	687b      	ldr	r3, [r7, #4]
20002776:	615a      	str	r2, [r3, #20]
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for ( i = 0U; i < fill_size; ++i )
20002778:	68fb      	ldr	r3, [r7, #12]
2000277a:	f103 0301 	add.w	r3, r3, #1
2000277e:	60fb      	str	r3, [r7, #12]
20002780:	68fa      	ldr	r2, [r7, #12]
20002782:	693b      	ldr	r3, [r7, #16]
20002784:	429a      	cmp	r2, r3
20002786:	d3e8      	bcc.n	2000275a <default_tx_handler+0xae>
                ++this_uart->tx_idx;
            }
        }

        /* Flag Tx as complete if all data has been pushed into the Tx FIFO. */
        if ( this_uart->tx_idx == this_uart->tx_buff_size )
20002788:	687b      	ldr	r3, [r7, #4]
2000278a:	695a      	ldr	r2, [r3, #20]
2000278c:	687b      	ldr	r3, [r7, #4]
2000278e:	691b      	ldr	r3, [r3, #16]
20002790:	429a      	cmp	r2, r3
20002792:	d109      	bne.n	200027a8 <default_tx_handler+0xfc>
        {
            this_uart->tx_buff_size = TX_COMPLETE;
20002794:	687b      	ldr	r3, [r7, #4]
20002796:	f04f 0200 	mov.w	r2, #0
2000279a:	611a      	str	r2, [r3, #16]
            /* disables TX interrupt */
            this_uart->hw_reg_bit->IER_ETBEI = 0U;
2000279c:	687b      	ldr	r3, [r7, #4]
2000279e:	685b      	ldr	r3, [r3, #4]
200027a0:	f04f 0200 	mov.w	r2, #0
200027a4:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84
        }
    }
}
200027a8:	f107 071c 	add.w	r7, r7, #28
200027ac:	46bd      	mov	sp, r7
200027ae:	bc80      	pop	{r7}
200027b0:	4770      	bx	lr
200027b2:	bf00      	nop

200027b4 <MSS_UART_set_rx_handler>:
(
    mss_uart_instance_t *       this_uart,
    mss_uart_irq_handler_t      handler,
    mss_uart_rx_trig_level_t    trigger_level
)
{
200027b4:	b580      	push	{r7, lr}
200027b6:	b084      	sub	sp, #16
200027b8:	af00      	add	r7, sp, #0
200027ba:	60f8      	str	r0, [r7, #12]
200027bc:	60b9      	str	r1, [r7, #8]
200027be:	4613      	mov	r3, r2
200027c0:	71fb      	strb	r3, [r7, #7]
    ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );
200027c2:	68fa      	ldr	r2, [r7, #12]
200027c4:	f644 2354 	movw	r3, #19028	; 0x4a54
200027c8:	f2c2 0300 	movt	r3, #8192	; 0x2000
200027cc:	429a      	cmp	r2, r3
200027ce:	d007      	beq.n	200027e0 <MSS_UART_set_rx_handler+0x2c>
200027d0:	68fa      	ldr	r2, [r7, #12]
200027d2:	f644 232c 	movw	r3, #18988	; 0x4a2c
200027d6:	f2c2 0300 	movt	r3, #8192	; 0x2000
200027da:	429a      	cmp	r2, r3
200027dc:	d000      	beq.n	200027e0 <MSS_UART_set_rx_handler+0x2c>
200027de:	be00      	bkpt	0x0000
    ASSERT( handler != INVALID_IRQ_HANDLER );
200027e0:	68bb      	ldr	r3, [r7, #8]
200027e2:	2b00      	cmp	r3, #0
200027e4:	d100      	bne.n	200027e8 <MSS_UART_set_rx_handler+0x34>
200027e6:	be00      	bkpt	0x0000
    ASSERT( trigger_level < MSS_UART_FIFO_INVALID_TRIG_LEVEL );
200027e8:	79fb      	ldrb	r3, [r7, #7]
200027ea:	2bc0      	cmp	r3, #192	; 0xc0
200027ec:	d900      	bls.n	200027f0 <MSS_UART_set_rx_handler+0x3c>
200027ee:	be00      	bkpt	0x0000

    if( ( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) ) &&
200027f0:	68fa      	ldr	r2, [r7, #12]
200027f2:	f644 2354 	movw	r3, #19028	; 0x4a54
200027f6:	f2c2 0300 	movt	r3, #8192	; 0x2000
200027fa:	429a      	cmp	r2, r3
200027fc:	d006      	beq.n	2000280c <MSS_UART_set_rx_handler+0x58>
200027fe:	68fa      	ldr	r2, [r7, #12]
20002800:	f644 232c 	movw	r3, #18988	; 0x4a2c
20002804:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002808:	429a      	cmp	r2, r3
2000280a:	d12b      	bne.n	20002864 <MSS_UART_set_rx_handler+0xb0>
2000280c:	68bb      	ldr	r3, [r7, #8]
2000280e:	2b00      	cmp	r3, #0
20002810:	d028      	beq.n	20002864 <MSS_UART_set_rx_handler+0xb0>
20002812:	79fb      	ldrb	r3, [r7, #7]
20002814:	2bc0      	cmp	r3, #192	; 0xc0
20002816:	d825      	bhi.n	20002864 <MSS_UART_set_rx_handler+0xb0>
        ( handler != INVALID_IRQ_HANDLER) &&
        ( trigger_level < MSS_UART_FIFO_INVALID_TRIG_LEVEL) )
    {
        this_uart->rx_handler = handler;
20002818:	68fb      	ldr	r3, [r7, #12]
2000281a:	68ba      	ldr	r2, [r7, #8]
2000281c:	61da      	str	r2, [r3, #28]

        /* Set the receive interrupt trigger level. */
        this_uart->hw_reg->FCR = (this_uart->hw_reg->FCR &
2000281e:	68fb      	ldr	r3, [r7, #12]
20002820:	681a      	ldr	r2, [r3, #0]
20002822:	68fb      	ldr	r3, [r7, #12]
20002824:	681b      	ldr	r3, [r3, #0]
20002826:	7a1b      	ldrb	r3, [r3, #8]
20002828:	b2db      	uxtb	r3, r3
2000282a:	b2db      	uxtb	r3, r3
2000282c:	f003 033f 	and.w	r3, r3, #63	; 0x3f
20002830:	79f8      	ldrb	r0, [r7, #7]
20002832:	4619      	mov	r1, r3
20002834:	4603      	mov	r3, r0
20002836:	ea41 0303 	orr.w	r3, r1, r3
2000283a:	b2db      	uxtb	r3, r3
2000283c:	b2db      	uxtb	r3, r3
2000283e:	7213      	strb	r3, [r2, #8]
                              (uint8_t)(~((uint8_t)FCR_TRIG_LEVEL_MASK))) |
                              (uint8_t)trigger_level;
        /* Clear any previously pended interrupts */
        NVIC_ClearPendingIRQ( this_uart->irqn );
20002840:	68fb      	ldr	r3, [r7, #12]
20002842:	891b      	ldrh	r3, [r3, #8]
20002844:	b21b      	sxth	r3, r3
20002846:	4618      	mov	r0, r3
20002848:	f7ff fb1e 	bl	20001e88 <NVIC_ClearPendingIRQ>

        /* Enable receive interrupt. */
        this_uart->hw_reg_bit->IER_ERBFI = 1U;
2000284c:	68fb      	ldr	r3, [r7, #12]
2000284e:	685b      	ldr	r3, [r3, #4]
20002850:	f04f 0201 	mov.w	r2, #1
20002854:	f8c3 2080 	str.w	r2, [r3, #128]	; 0x80

        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
        NVIC_EnableIRQ( this_uart->irqn );
20002858:	68fb      	ldr	r3, [r7, #12]
2000285a:	891b      	ldrh	r3, [r3, #8]
2000285c:	b21b      	sxth	r3, r3
2000285e:	4618      	mov	r0, r3
20002860:	f7ff fad8 	bl	20001e14 <NVIC_EnableIRQ>
    }
}
20002864:	f107 0710 	add.w	r7, r7, #16
20002868:	46bd      	mov	sp, r7
2000286a:	bd80      	pop	{r7, pc}

2000286c <MSS_UART_set_loopback>:
MSS_UART_set_loopback
(
    mss_uart_instance_t *   this_uart,
    mss_uart_loopback_t     loopback
)
{
2000286c:	b480      	push	{r7}
2000286e:	b083      	sub	sp, #12
20002870:	af00      	add	r7, sp, #0
20002872:	6078      	str	r0, [r7, #4]
20002874:	460b      	mov	r3, r1
20002876:	70fb      	strb	r3, [r7, #3]
    ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );
20002878:	687a      	ldr	r2, [r7, #4]
2000287a:	f644 2354 	movw	r3, #19028	; 0x4a54
2000287e:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002882:	429a      	cmp	r2, r3
20002884:	d007      	beq.n	20002896 <MSS_UART_set_loopback+0x2a>
20002886:	687a      	ldr	r2, [r7, #4]
20002888:	f644 232c 	movw	r3, #18988	; 0x4a2c
2000288c:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002890:	429a      	cmp	r2, r3
20002892:	d000      	beq.n	20002896 <MSS_UART_set_loopback+0x2a>
20002894:	be00      	bkpt	0x0000

    if( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) )
20002896:	687a      	ldr	r2, [r7, #4]
20002898:	f644 2354 	movw	r3, #19028	; 0x4a54
2000289c:	f2c2 0300 	movt	r3, #8192	; 0x2000
200028a0:	429a      	cmp	r2, r3
200028a2:	d006      	beq.n	200028b2 <MSS_UART_set_loopback+0x46>
200028a4:	687a      	ldr	r2, [r7, #4]
200028a6:	f644 232c 	movw	r3, #18988	; 0x4a2c
200028aa:	f2c2 0300 	movt	r3, #8192	; 0x2000
200028ae:	429a      	cmp	r2, r3
200028b0:	d10f      	bne.n	200028d2 <MSS_UART_set_loopback+0x66>
    {
        if ( loopback == MSS_UART_LOOPBACK_OFF )
200028b2:	78fb      	ldrb	r3, [r7, #3]
200028b4:	2b00      	cmp	r3, #0
200028b6:	d106      	bne.n	200028c6 <MSS_UART_set_loopback+0x5a>
        {
            this_uart->hw_reg_bit->MCR_LOOP = 0U;
200028b8:	687b      	ldr	r3, [r7, #4]
200028ba:	685b      	ldr	r3, [r3, #4]
200028bc:	f04f 0200 	mov.w	r2, #0
200028c0:	f8c3 2210 	str.w	r2, [r3, #528]	; 0x210
200028c4:	e005      	b.n	200028d2 <MSS_UART_set_loopback+0x66>
        }
        else
        {
            this_uart->hw_reg_bit->MCR_LOOP = 1U;
200028c6:	687b      	ldr	r3, [r7, #4]
200028c8:	685b      	ldr	r3, [r3, #4]
200028ca:	f04f 0201 	mov.w	r2, #1
200028ce:	f8c3 2210 	str.w	r2, [r3, #528]	; 0x210
        }
    }
}
200028d2:	f107 070c 	add.w	r7, r7, #12
200028d6:	46bd      	mov	sp, r7
200028d8:	bc80      	pop	{r7}
200028da:	4770      	bx	lr

200028dc <UART0_IRQHandler>:
#if defined(__GNUC__)
__attribute__((__interrupt__)) void UART0_IRQHandler( void )
#else
void UART0_IRQHandler( void )
#endif
{
200028dc:	4668      	mov	r0, sp
200028de:	f020 0107 	bic.w	r1, r0, #7
200028e2:	468d      	mov	sp, r1
200028e4:	b589      	push	{r0, r3, r7, lr}
200028e6:	af00      	add	r7, sp, #0
    MSS_UART_isr( &g_mss_uart0 );
200028e8:	f644 2054 	movw	r0, #19028	; 0x4a54
200028ec:	f2c2 0000 	movt	r0, #8192	; 0x2000
200028f0:	f7ff fe4e 	bl	20002590 <MSS_UART_isr>
    NVIC_ClearPendingIRQ( UART0_IRQn );
200028f4:	f04f 000a 	mov.w	r0, #10
200028f8:	f7ff fac6 	bl	20001e88 <NVIC_ClearPendingIRQ>
}
200028fc:	46bd      	mov	sp, r7
200028fe:	e8bd 4089 	ldmia.w	sp!, {r0, r3, r7, lr}
20002902:	4685      	mov	sp, r0
20002904:	4770      	bx	lr
20002906:	bf00      	nop

20002908 <UART1_IRQHandler>:
#if defined(__GNUC__)
__attribute__((__interrupt__)) void UART1_IRQHandler( void )
#else
void UART1_IRQHandler( void )
#endif
{
20002908:	4668      	mov	r0, sp
2000290a:	f020 0107 	bic.w	r1, r0, #7
2000290e:	468d      	mov	sp, r1
20002910:	b589      	push	{r0, r3, r7, lr}
20002912:	af00      	add	r7, sp, #0
    MSS_UART_isr( &g_mss_uart1 );
20002914:	f644 202c 	movw	r0, #18988	; 0x4a2c
20002918:	f2c2 0000 	movt	r0, #8192	; 0x2000
2000291c:	f7ff fe38 	bl	20002590 <MSS_UART_isr>
    NVIC_ClearPendingIRQ( UART1_IRQn );
20002920:	f04f 000b 	mov.w	r0, #11
20002924:	f7ff fab0 	bl	20001e88 <NVIC_ClearPendingIRQ>
}
20002928:	46bd      	mov	sp, r7
2000292a:	e8bd 4089 	ldmia.w	sp!, {r0, r3, r7, lr}
2000292e:	4685      	mov	sp, r0
20002930:	4770      	bx	lr
20002932:	bf00      	nop

20002934 <MSS_UART_set_rxstatus_handler>:
MSS_UART_set_rxstatus_handler
(
    mss_uart_instance_t * this_uart,
    mss_uart_irq_handler_t handler
)
{
20002934:	b580      	push	{r7, lr}
20002936:	b082      	sub	sp, #8
20002938:	af00      	add	r7, sp, #0
2000293a:	6078      	str	r0, [r7, #4]
2000293c:	6039      	str	r1, [r7, #0]
    ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );
2000293e:	687a      	ldr	r2, [r7, #4]
20002940:	f644 2354 	movw	r3, #19028	; 0x4a54
20002944:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002948:	429a      	cmp	r2, r3
2000294a:	d007      	beq.n	2000295c <MSS_UART_set_rxstatus_handler+0x28>
2000294c:	687a      	ldr	r2, [r7, #4]
2000294e:	f644 232c 	movw	r3, #18988	; 0x4a2c
20002952:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002956:	429a      	cmp	r2, r3
20002958:	d000      	beq.n	2000295c <MSS_UART_set_rxstatus_handler+0x28>
2000295a:	be00      	bkpt	0x0000
    ASSERT( handler != INVALID_IRQ_HANDLER);
2000295c:	683b      	ldr	r3, [r7, #0]
2000295e:	2b00      	cmp	r3, #0
20002960:	d100      	bne.n	20002964 <MSS_UART_set_rxstatus_handler+0x30>
20002962:	be00      	bkpt	0x0000

    if( ( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) ) &&
20002964:	687a      	ldr	r2, [r7, #4]
20002966:	f644 2354 	movw	r3, #19028	; 0x4a54
2000296a:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000296e:	429a      	cmp	r2, r3
20002970:	d006      	beq.n	20002980 <MSS_UART_set_rxstatus_handler+0x4c>
20002972:	687a      	ldr	r2, [r7, #4]
20002974:	f644 232c 	movw	r3, #18988	; 0x4a2c
20002978:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000297c:	429a      	cmp	r2, r3
2000297e:	d117      	bne.n	200029b0 <MSS_UART_set_rxstatus_handler+0x7c>
20002980:	683b      	ldr	r3, [r7, #0]
20002982:	2b00      	cmp	r3, #0
20002984:	d014      	beq.n	200029b0 <MSS_UART_set_rxstatus_handler+0x7c>
        ( handler != INVALID_IRQ_HANDLER) )
    {
        this_uart->linests_handler = handler;
20002986:	687b      	ldr	r3, [r7, #4]
20002988:	683a      	ldr	r2, [r7, #0]
2000298a:	619a      	str	r2, [r3, #24]

        /* Clear any previously pended interrupts */
        NVIC_ClearPendingIRQ( this_uart->irqn );
2000298c:	687b      	ldr	r3, [r7, #4]
2000298e:	891b      	ldrh	r3, [r3, #8]
20002990:	b21b      	sxth	r3, r3
20002992:	4618      	mov	r0, r3
20002994:	f7ff fa78 	bl	20001e88 <NVIC_ClearPendingIRQ>

        /* Enable receiver line status interrupt. */
        this_uart->hw_reg_bit->IER_ELSI = 1U;
20002998:	687b      	ldr	r3, [r7, #4]
2000299a:	685b      	ldr	r3, [r3, #4]
2000299c:	f04f 0201 	mov.w	r2, #1
200029a0:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88

        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
        NVIC_EnableIRQ( this_uart->irqn );
200029a4:	687b      	ldr	r3, [r7, #4]
200029a6:	891b      	ldrh	r3, [r3, #8]
200029a8:	b21b      	sxth	r3, r3
200029aa:	4618      	mov	r0, r3
200029ac:	f7ff fa32 	bl	20001e14 <NVIC_EnableIRQ>
    }
}
200029b0:	f107 0708 	add.w	r7, r7, #8
200029b4:	46bd      	mov	sp, r7
200029b6:	bd80      	pop	{r7, pc}

200029b8 <MSS_UART_set_tx_handler>:
MSS_UART_set_tx_handler
(
    mss_uart_instance_t * this_uart,
    mss_uart_irq_handler_t handler
)
{
200029b8:	b580      	push	{r7, lr}
200029ba:	b082      	sub	sp, #8
200029bc:	af00      	add	r7, sp, #0
200029be:	6078      	str	r0, [r7, #4]
200029c0:	6039      	str	r1, [r7, #0]
    ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );
200029c2:	687a      	ldr	r2, [r7, #4]
200029c4:	f644 2354 	movw	r3, #19028	; 0x4a54
200029c8:	f2c2 0300 	movt	r3, #8192	; 0x2000
200029cc:	429a      	cmp	r2, r3
200029ce:	d007      	beq.n	200029e0 <MSS_UART_set_tx_handler+0x28>
200029d0:	687a      	ldr	r2, [r7, #4]
200029d2:	f644 232c 	movw	r3, #18988	; 0x4a2c
200029d6:	f2c2 0300 	movt	r3, #8192	; 0x2000
200029da:	429a      	cmp	r2, r3
200029dc:	d000      	beq.n	200029e0 <MSS_UART_set_tx_handler+0x28>
200029de:	be00      	bkpt	0x0000
    ASSERT( handler != INVALID_IRQ_HANDLER);
200029e0:	683b      	ldr	r3, [r7, #0]
200029e2:	2b00      	cmp	r3, #0
200029e4:	d100      	bne.n	200029e8 <MSS_UART_set_tx_handler+0x30>
200029e6:	be00      	bkpt	0x0000

    if( ( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) ) &&
200029e8:	687a      	ldr	r2, [r7, #4]
200029ea:	f644 2354 	movw	r3, #19028	; 0x4a54
200029ee:	f2c2 0300 	movt	r3, #8192	; 0x2000
200029f2:	429a      	cmp	r2, r3
200029f4:	d006      	beq.n	20002a04 <MSS_UART_set_tx_handler+0x4c>
200029f6:	687a      	ldr	r2, [r7, #4]
200029f8:	f644 232c 	movw	r3, #18988	; 0x4a2c
200029fc:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002a00:	429a      	cmp	r2, r3
20002a02:	d11f      	bne.n	20002a44 <MSS_UART_set_tx_handler+0x8c>
20002a04:	683b      	ldr	r3, [r7, #0]
20002a06:	2b00      	cmp	r3, #0
20002a08:	d01c      	beq.n	20002a44 <MSS_UART_set_tx_handler+0x8c>
        ( handler != INVALID_IRQ_HANDLER) )
    {
        this_uart->tx_handler = handler;
20002a0a:	687b      	ldr	r3, [r7, #4]
20002a0c:	683a      	ldr	r2, [r7, #0]
20002a0e:	621a      	str	r2, [r3, #32]

        /* Make TX buffer info invalid */
        this_uart->tx_buffer = (const uint8_t *)0;
20002a10:	687b      	ldr	r3, [r7, #4]
20002a12:	f04f 0200 	mov.w	r2, #0
20002a16:	60da      	str	r2, [r3, #12]
        this_uart->tx_buff_size = 0U;
20002a18:	687b      	ldr	r3, [r7, #4]
20002a1a:	f04f 0200 	mov.w	r2, #0
20002a1e:	611a      	str	r2, [r3, #16]

        /* Clear any previously pended interrupts */
        NVIC_ClearPendingIRQ( this_uart->irqn );
20002a20:	687b      	ldr	r3, [r7, #4]
20002a22:	891b      	ldrh	r3, [r3, #8]
20002a24:	b21b      	sxth	r3, r3
20002a26:	4618      	mov	r0, r3
20002a28:	f7ff fa2e 	bl	20001e88 <NVIC_ClearPendingIRQ>

        /* Enable transmitter holding register Empty interrupt. */
        this_uart->hw_reg_bit->IER_ETBEI = 1U;
20002a2c:	687b      	ldr	r3, [r7, #4]
20002a2e:	685b      	ldr	r3, [r3, #4]
20002a30:	f04f 0201 	mov.w	r2, #1
20002a34:	f8c3 2084 	str.w	r2, [r3, #132]	; 0x84

        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
        NVIC_EnableIRQ( this_uart->irqn );
20002a38:	687b      	ldr	r3, [r7, #4]
20002a3a:	891b      	ldrh	r3, [r3, #8]
20002a3c:	b21b      	sxth	r3, r3
20002a3e:	4618      	mov	r0, r3
20002a40:	f7ff f9e8 	bl	20001e14 <NVIC_EnableIRQ>
    }
}
20002a44:	f107 0708 	add.w	r7, r7, #8
20002a48:	46bd      	mov	sp, r7
20002a4a:	bd80      	pop	{r7, pc}

20002a4c <MSS_UART_set_modemstatus_handler>:
MSS_UART_set_modemstatus_handler
(
    mss_uart_instance_t * this_uart,
    mss_uart_irq_handler_t handler
)
{
20002a4c:	b580      	push	{r7, lr}
20002a4e:	b082      	sub	sp, #8
20002a50:	af00      	add	r7, sp, #0
20002a52:	6078      	str	r0, [r7, #4]
20002a54:	6039      	str	r1, [r7, #0]
    ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );
20002a56:	687a      	ldr	r2, [r7, #4]
20002a58:	f644 2354 	movw	r3, #19028	; 0x4a54
20002a5c:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002a60:	429a      	cmp	r2, r3
20002a62:	d007      	beq.n	20002a74 <MSS_UART_set_modemstatus_handler+0x28>
20002a64:	687a      	ldr	r2, [r7, #4]
20002a66:	f644 232c 	movw	r3, #18988	; 0x4a2c
20002a6a:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002a6e:	429a      	cmp	r2, r3
20002a70:	d000      	beq.n	20002a74 <MSS_UART_set_modemstatus_handler+0x28>
20002a72:	be00      	bkpt	0x0000
    ASSERT( handler != INVALID_IRQ_HANDLER );
20002a74:	683b      	ldr	r3, [r7, #0]
20002a76:	2b00      	cmp	r3, #0
20002a78:	d100      	bne.n	20002a7c <MSS_UART_set_modemstatus_handler+0x30>
20002a7a:	be00      	bkpt	0x0000

    if( ( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) ) &&
20002a7c:	687a      	ldr	r2, [r7, #4]
20002a7e:	f644 2354 	movw	r3, #19028	; 0x4a54
20002a82:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002a86:	429a      	cmp	r2, r3
20002a88:	d006      	beq.n	20002a98 <MSS_UART_set_modemstatus_handler+0x4c>
20002a8a:	687a      	ldr	r2, [r7, #4]
20002a8c:	f644 232c 	movw	r3, #18988	; 0x4a2c
20002a90:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002a94:	429a      	cmp	r2, r3
20002a96:	d117      	bne.n	20002ac8 <MSS_UART_set_modemstatus_handler+0x7c>
20002a98:	683b      	ldr	r3, [r7, #0]
20002a9a:	2b00      	cmp	r3, #0
20002a9c:	d014      	beq.n	20002ac8 <MSS_UART_set_modemstatus_handler+0x7c>
        ( handler != INVALID_IRQ_HANDLER) )
    {
        this_uart->modemsts_handler = handler;
20002a9e:	687b      	ldr	r3, [r7, #4]
20002aa0:	683a      	ldr	r2, [r7, #0]
20002aa2:	625a      	str	r2, [r3, #36]	; 0x24

        /* Clear any previously pended interrupts */
        NVIC_ClearPendingIRQ( this_uart->irqn );
20002aa4:	687b      	ldr	r3, [r7, #4]
20002aa6:	891b      	ldrh	r3, [r3, #8]
20002aa8:	b21b      	sxth	r3, r3
20002aaa:	4618      	mov	r0, r3
20002aac:	f7ff f9ec 	bl	20001e88 <NVIC_ClearPendingIRQ>

        /* Enable modem status interrupt. */
        this_uart->hw_reg_bit->IER_EDSSI = 1U;
20002ab0:	687b      	ldr	r3, [r7, #4]
20002ab2:	685b      	ldr	r3, [r3, #4]
20002ab4:	f04f 0201 	mov.w	r2, #1
20002ab8:	f8c3 208c 	str.w	r2, [r3, #140]	; 0x8c

        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
        NVIC_EnableIRQ( this_uart->irqn );
20002abc:	687b      	ldr	r3, [r7, #4]
20002abe:	891b      	ldrh	r3, [r3, #8]
20002ac0:	b21b      	sxth	r3, r3
20002ac2:	4618      	mov	r0, r3
20002ac4:	f7ff f9a6 	bl	20001e14 <NVIC_EnableIRQ>
    }
}
20002ac8:	f107 0708 	add.w	r7, r7, #8
20002acc:	46bd      	mov	sp, r7
20002ace:	bd80      	pop	{r7, pc}

20002ad0 <MSS_UART_fill_tx_fifo>:
(
    mss_uart_instance_t * this_uart,
    const uint8_t * tx_buffer,
    size_t tx_size
)
{
20002ad0:	b480      	push	{r7}
20002ad2:	b089      	sub	sp, #36	; 0x24
20002ad4:	af00      	add	r7, sp, #0
20002ad6:	60f8      	str	r0, [r7, #12]
20002ad8:	60b9      	str	r1, [r7, #8]
20002ada:	607a      	str	r2, [r7, #4]
    uint8_t status = 0U;
20002adc:	f04f 0300 	mov.w	r3, #0
20002ae0:	75fb      	strb	r3, [r7, #23]
    size_t size_sent = 0U;
20002ae2:	f04f 0300 	mov.w	r3, #0
20002ae6:	61bb      	str	r3, [r7, #24]

    ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );
20002ae8:	68fa      	ldr	r2, [r7, #12]
20002aea:	f644 2354 	movw	r3, #19028	; 0x4a54
20002aee:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002af2:	429a      	cmp	r2, r3
20002af4:	d007      	beq.n	20002b06 <MSS_UART_fill_tx_fifo+0x36>
20002af6:	68fa      	ldr	r2, [r7, #12]
20002af8:	f644 232c 	movw	r3, #18988	; 0x4a2c
20002afc:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002b00:	429a      	cmp	r2, r3
20002b02:	d000      	beq.n	20002b06 <MSS_UART_fill_tx_fifo+0x36>
20002b04:	be00      	bkpt	0x0000
    ASSERT( tx_buffer != ( (uint8_t *)0 ) );
20002b06:	68bb      	ldr	r3, [r7, #8]
20002b08:	2b00      	cmp	r3, #0
20002b0a:	d100      	bne.n	20002b0e <MSS_UART_fill_tx_fifo+0x3e>
20002b0c:	be00      	bkpt	0x0000
    ASSERT( tx_size > 0 );
20002b0e:	687b      	ldr	r3, [r7, #4]
20002b10:	2b00      	cmp	r3, #0
20002b12:	d100      	bne.n	20002b16 <MSS_UART_fill_tx_fifo+0x46>
20002b14:	be00      	bkpt	0x0000

    /* Fill the UART's Tx FIFO until the FIFO is full or the complete input
     * buffer has been written. */
    if( ( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1 ) ) &&
20002b16:	68fa      	ldr	r2, [r7, #12]
20002b18:	f644 2354 	movw	r3, #19028	; 0x4a54
20002b1c:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002b20:	429a      	cmp	r2, r3
20002b22:	d006      	beq.n	20002b32 <MSS_UART_fill_tx_fifo+0x62>
20002b24:	68fa      	ldr	r2, [r7, #12]
20002b26:	f644 232c 	movw	r3, #18988	; 0x4a2c
20002b2a:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002b2e:	429a      	cmp	r2, r3
20002b30:	d131      	bne.n	20002b96 <MSS_UART_fill_tx_fifo+0xc6>
20002b32:	68bb      	ldr	r3, [r7, #8]
20002b34:	2b00      	cmp	r3, #0
20002b36:	d02e      	beq.n	20002b96 <MSS_UART_fill_tx_fifo+0xc6>
20002b38:	687b      	ldr	r3, [r7, #4]
20002b3a:	2b00      	cmp	r3, #0
20002b3c:	d02b      	beq.n	20002b96 <MSS_UART_fill_tx_fifo+0xc6>
        (tx_buffer != ( (uint8_t *)0 ))   &&
        (tx_size > 0u) )
    {
        status = this_uart->hw_reg->LSR;
20002b3e:	68fb      	ldr	r3, [r7, #12]
20002b40:	681b      	ldr	r3, [r3, #0]
20002b42:	7d1b      	ldrb	r3, [r3, #20]
20002b44:	75fb      	strb	r3, [r7, #23]
        this_uart->status |= status;
20002b46:	68fb      	ldr	r3, [r7, #12]
20002b48:	7a9a      	ldrb	r2, [r3, #10]
20002b4a:	7dfb      	ldrb	r3, [r7, #23]
20002b4c:	ea42 0303 	orr.w	r3, r2, r3
20002b50:	b2da      	uxtb	r2, r3
20002b52:	68fb      	ldr	r3, [r7, #12]
20002b54:	729a      	strb	r2, [r3, #10]

        if( status & MSS_UART_THRE )
20002b56:	7dfb      	ldrb	r3, [r7, #23]
20002b58:	f003 0320 	and.w	r3, r3, #32
20002b5c:	2b00      	cmp	r3, #0
20002b5e:	d01a      	beq.n	20002b96 <MSS_UART_fill_tx_fifo+0xc6>
        {
            uint32_t fill_size = TX_FIFO_SIZE;
20002b60:	f04f 0310 	mov.w	r3, #16
20002b64:	61fb      	str	r3, [r7, #28]

            if ( tx_size < TX_FIFO_SIZE )
20002b66:	687b      	ldr	r3, [r7, #4]
20002b68:	2b0f      	cmp	r3, #15
20002b6a:	d801      	bhi.n	20002b70 <MSS_UART_fill_tx_fifo+0xa0>
            {
                fill_size = tx_size;
20002b6c:	687b      	ldr	r3, [r7, #4]
20002b6e:	61fb      	str	r3, [r7, #28]
            }
            /* Fill up FIFO */
            for ( size_sent = 0U; size_sent < fill_size; ++size_sent )
20002b70:	f04f 0300 	mov.w	r3, #0
20002b74:	61bb      	str	r3, [r7, #24]
20002b76:	e00a      	b.n	20002b8e <MSS_UART_fill_tx_fifo+0xbe>
            {

                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = tx_buffer[size_sent];
20002b78:	68fb      	ldr	r3, [r7, #12]
20002b7a:	681b      	ldr	r3, [r3, #0]
20002b7c:	68b9      	ldr	r1, [r7, #8]
20002b7e:	69ba      	ldr	r2, [r7, #24]
20002b80:	440a      	add	r2, r1
20002b82:	7812      	ldrb	r2, [r2, #0]
20002b84:	701a      	strb	r2, [r3, #0]
            if ( tx_size < TX_FIFO_SIZE )
            {
                fill_size = tx_size;
            }
            /* Fill up FIFO */
            for ( size_sent = 0U; size_sent < fill_size; ++size_sent )
20002b86:	69bb      	ldr	r3, [r7, #24]
20002b88:	f103 0301 	add.w	r3, r3, #1
20002b8c:	61bb      	str	r3, [r7, #24]
20002b8e:	69ba      	ldr	r2, [r7, #24]
20002b90:	69fb      	ldr	r3, [r7, #28]
20002b92:	429a      	cmp	r2, r3
20002b94:	d3f0      	bcc.n	20002b78 <MSS_UART_fill_tx_fifo+0xa8>
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = tx_buffer[size_sent];
            }
        }
    }
    return size_sent;
20002b96:	69bb      	ldr	r3, [r7, #24]
}
20002b98:	4618      	mov	r0, r3
20002b9a:	f107 0724 	add.w	r7, r7, #36	; 0x24
20002b9e:	46bd      	mov	sp, r7
20002ba0:	bc80      	pop	{r7}
20002ba2:	4770      	bx	lr

20002ba4 <MSS_UART_get_rx_status>:
uint8_t
MSS_UART_get_rx_status
(
    mss_uart_instance_t * this_uart
)
{
20002ba4:	b480      	push	{r7}
20002ba6:	b085      	sub	sp, #20
20002ba8:	af00      	add	r7, sp, #0
20002baa:	6078      	str	r0, [r7, #4]
    uint8_t status = MSS_UART_INVALID_PARAM;
20002bac:	f04f 33ff 	mov.w	r3, #4294967295
20002bb0:	73fb      	strb	r3, [r7, #15]

    ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );
20002bb2:	687a      	ldr	r2, [r7, #4]
20002bb4:	f644 2354 	movw	r3, #19028	; 0x4a54
20002bb8:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002bbc:	429a      	cmp	r2, r3
20002bbe:	d007      	beq.n	20002bd0 <MSS_UART_get_rx_status+0x2c>
20002bc0:	687a      	ldr	r2, [r7, #4]
20002bc2:	f644 232c 	movw	r3, #18988	; 0x4a2c
20002bc6:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002bca:	429a      	cmp	r2, r3
20002bcc:	d000      	beq.n	20002bd0 <MSS_UART_get_rx_status+0x2c>
20002bce:	be00      	bkpt	0x0000

    if( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) )
20002bd0:	687a      	ldr	r2, [r7, #4]
20002bd2:	f644 2354 	movw	r3, #19028	; 0x4a54
20002bd6:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002bda:	429a      	cmp	r2, r3
20002bdc:	d006      	beq.n	20002bec <MSS_UART_get_rx_status+0x48>
20002bde:	687a      	ldr	r2, [r7, #4]
20002be0:	f644 232c 	movw	r3, #18988	; 0x4a2c
20002be4:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002be8:	429a      	cmp	r2, r3
20002bea:	d113      	bne.n	20002c14 <MSS_UART_get_rx_status+0x70>
         * Bit 2 - Parity error status
         * Bit 3 - Frame error status
         * Bit 4 - Break interrupt indicator
         * Bit 7 - FIFO data error status
         */
        this_uart->status |= (this_uart->hw_reg->LSR);
20002bec:	687b      	ldr	r3, [r7, #4]
20002bee:	7a9a      	ldrb	r2, [r3, #10]
20002bf0:	687b      	ldr	r3, [r7, #4]
20002bf2:	681b      	ldr	r3, [r3, #0]
20002bf4:	7d1b      	ldrb	r3, [r3, #20]
20002bf6:	b2db      	uxtb	r3, r3
20002bf8:	ea42 0303 	orr.w	r3, r2, r3
20002bfc:	b2da      	uxtb	r2, r3
20002bfe:	687b      	ldr	r3, [r7, #4]
20002c00:	729a      	strb	r2, [r3, #10]
        status = (this_uart->status & STATUS_ERROR_MASK );
20002c02:	687b      	ldr	r3, [r7, #4]
20002c04:	7a9b      	ldrb	r3, [r3, #10]
20002c06:	f023 0361 	bic.w	r3, r3, #97	; 0x61
20002c0a:	73fb      	strb	r3, [r7, #15]
        /* Clear the sticky status after reading */
        this_uart->status = 0U;
20002c0c:	687b      	ldr	r3, [r7, #4]
20002c0e:	f04f 0200 	mov.w	r2, #0
20002c12:	729a      	strb	r2, [r3, #10]
    }
    return status;
20002c14:	7bfb      	ldrb	r3, [r7, #15]
}
20002c16:	4618      	mov	r0, r3
20002c18:	f107 0714 	add.w	r7, r7, #20
20002c1c:	46bd      	mov	sp, r7
20002c1e:	bc80      	pop	{r7}
20002c20:	4770      	bx	lr
20002c22:	bf00      	nop

20002c24 <MSS_UART_get_modem_status>:
uint8_t
MSS_UART_get_modem_status
(
    mss_uart_instance_t * this_uart
)
{
20002c24:	b480      	push	{r7}
20002c26:	b085      	sub	sp, #20
20002c28:	af00      	add	r7, sp, #0
20002c2a:	6078      	str	r0, [r7, #4]
    uint8_t status = MSS_UART_INVALID_PARAM;
20002c2c:	f04f 33ff 	mov.w	r3, #4294967295
20002c30:	73fb      	strb	r3, [r7, #15]

    ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );
20002c32:	687a      	ldr	r2, [r7, #4]
20002c34:	f644 2354 	movw	r3, #19028	; 0x4a54
20002c38:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002c3c:	429a      	cmp	r2, r3
20002c3e:	d007      	beq.n	20002c50 <MSS_UART_get_modem_status+0x2c>
20002c40:	687a      	ldr	r2, [r7, #4]
20002c42:	f644 232c 	movw	r3, #18988	; 0x4a2c
20002c46:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002c4a:	429a      	cmp	r2, r3
20002c4c:	d000      	beq.n	20002c50 <MSS_UART_get_modem_status+0x2c>
20002c4e:	be00      	bkpt	0x0000

    if( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) )
20002c50:	687a      	ldr	r2, [r7, #4]
20002c52:	f644 2354 	movw	r3, #19028	; 0x4a54
20002c56:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002c5a:	429a      	cmp	r2, r3
20002c5c:	d006      	beq.n	20002c6c <MSS_UART_get_modem_status+0x48>
20002c5e:	687a      	ldr	r2, [r7, #4]
20002c60:	f644 232c 	movw	r3, #18988	; 0x4a2c
20002c64:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002c68:	429a      	cmp	r2, r3
20002c6a:	d103      	bne.n	20002c74 <MSS_UART_get_modem_status+0x50>
         * Bit 4 - Clear To Send
         * Bit 5 - Data Set Ready
         * Bit 6 - Ring Indicator
         * Bit 7 - Data Carrier Detect
         */
        status = this_uart->hw_reg->MSR;
20002c6c:	687b      	ldr	r3, [r7, #4]
20002c6e:	681b      	ldr	r3, [r3, #0]
20002c70:	7e1b      	ldrb	r3, [r3, #24]
20002c72:	73fb      	strb	r3, [r7, #15]
    }
    return status;
20002c74:	7bfb      	ldrb	r3, [r7, #15]
}
20002c76:	4618      	mov	r0, r3
20002c78:	f107 0714 	add.w	r7, r7, #20
20002c7c:	46bd      	mov	sp, r7
20002c7e:	bc80      	pop	{r7}
20002c80:	4770      	bx	lr
20002c82:	bf00      	nop

20002c84 <MSS_UART_get_tx_status>:
uint8_t
MSS_UART_get_tx_status
(
    mss_uart_instance_t * this_uart
)
{
20002c84:	b480      	push	{r7}
20002c86:	b085      	sub	sp, #20
20002c88:	af00      	add	r7, sp, #0
20002c8a:	6078      	str	r0, [r7, #4]
    uint8_t status = MSS_UART_TX_BUSY;
20002c8c:	f04f 0300 	mov.w	r3, #0
20002c90:	73fb      	strb	r3, [r7, #15]

    ASSERT( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) );
20002c92:	687a      	ldr	r2, [r7, #4]
20002c94:	f644 2354 	movw	r3, #19028	; 0x4a54
20002c98:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002c9c:	429a      	cmp	r2, r3
20002c9e:	d007      	beq.n	20002cb0 <MSS_UART_get_tx_status+0x2c>
20002ca0:	687a      	ldr	r2, [r7, #4]
20002ca2:	f644 232c 	movw	r3, #18988	; 0x4a2c
20002ca6:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002caa:	429a      	cmp	r2, r3
20002cac:	d000      	beq.n	20002cb0 <MSS_UART_get_tx_status+0x2c>
20002cae:	be00      	bkpt	0x0000

    if( (this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1) )
20002cb0:	687a      	ldr	r2, [r7, #4]
20002cb2:	f644 2354 	movw	r3, #19028	; 0x4a54
20002cb6:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002cba:	429a      	cmp	r2, r3
20002cbc:	d006      	beq.n	20002ccc <MSS_UART_get_tx_status+0x48>
20002cbe:	687a      	ldr	r2, [r7, #4]
20002cc0:	f644 232c 	movw	r3, #18988	; 0x4a2c
20002cc4:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002cc8:	429a      	cmp	r2, r3
20002cca:	d10f      	bne.n	20002cec <MSS_UART_get_tx_status+0x68>
    {
        /* Read the Line Status Register and update the sticky record. */
        status = this_uart->hw_reg->LSR;
20002ccc:	687b      	ldr	r3, [r7, #4]
20002cce:	681b      	ldr	r3, [r3, #0]
20002cd0:	7d1b      	ldrb	r3, [r3, #20]
20002cd2:	73fb      	strb	r3, [r7, #15]
        this_uart->status |= status;
20002cd4:	687b      	ldr	r3, [r7, #4]
20002cd6:	7a9a      	ldrb	r2, [r3, #10]
20002cd8:	7bfb      	ldrb	r3, [r7, #15]
20002cda:	ea42 0303 	orr.w	r3, r2, r3
20002cde:	b2da      	uxtb	r2, r3
20002ce0:	687b      	ldr	r3, [r7, #4]
20002ce2:	729a      	strb	r2, [r3, #10]
        /*
         * Extract the transmit status bits from the UART's Line Status Register.
         * Bit 5 - Transmitter Holding Register/FIFO Empty (THRE) status. (If = 1, TX FIFO is empty)
         * Bit 6 - Transmitter Empty (TEMT) status. (If = 1, both TX FIFO and shift register are empty)
         */
        status &= ( MSS_UART_THRE | MSS_UART_TEMT );
20002ce4:	7bfb      	ldrb	r3, [r7, #15]
20002ce6:	f003 0360 	and.w	r3, r3, #96	; 0x60
20002cea:	73fb      	strb	r3, [r7, #15]
    }
    return status;
20002cec:	7bfb      	ldrb	r3, [r7, #15]
}
20002cee:	4618      	mov	r0, r3
20002cf0:	f107 0714 	add.w	r7, r7, #20
20002cf4:	46bd      	mov	sp, r7
20002cf6:	bc80      	pop	{r7}
20002cf8:	4770      	bx	lr
20002cfa:	bf00      	nop

20002cfc <NVIC_EnableIRQ>:
 *
 * Enable a device specific interupt in the NVIC interrupt controller.
 * The interrupt number cannot be a negative value.
 */
static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
20002cfc:	b480      	push	{r7}
20002cfe:	b083      	sub	sp, #12
20002d00:	af00      	add	r7, sp, #0
20002d02:	4603      	mov	r3, r0
20002d04:	80fb      	strh	r3, [r7, #6]
  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
20002d06:	f24e 1300 	movw	r3, #57600	; 0xe100
20002d0a:	f2ce 0300 	movt	r3, #57344	; 0xe000
20002d0e:	f9b7 2006 	ldrsh.w	r2, [r7, #6]
20002d12:	ea4f 1252 	mov.w	r2, r2, lsr #5
20002d16:	88f9      	ldrh	r1, [r7, #6]
20002d18:	f001 011f 	and.w	r1, r1, #31
20002d1c:	f04f 0001 	mov.w	r0, #1
20002d20:	fa00 f101 	lsl.w	r1, r0, r1
20002d24:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
}
20002d28:	f107 070c 	add.w	r7, r7, #12
20002d2c:	46bd      	mov	sp, r7
20002d2e:	bc80      	pop	{r7}
20002d30:	4770      	bx	lr
20002d32:	bf00      	nop

20002d34 <NVIC_ClearPendingIRQ>:
 *
 * Clear the pending bit for the specified interrupt. 
 * The interrupt number cannot be a negative value.
 */
static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
20002d34:	b480      	push	{r7}
20002d36:	b083      	sub	sp, #12
20002d38:	af00      	add	r7, sp, #0
20002d3a:	4603      	mov	r3, r0
20002d3c:	80fb      	strh	r3, [r7, #6]
  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
20002d3e:	f24e 1300 	movw	r3, #57600	; 0xe100
20002d42:	f2ce 0300 	movt	r3, #57344	; 0xe000
20002d46:	f9b7 2006 	ldrsh.w	r2, [r7, #6]
20002d4a:	ea4f 1252 	mov.w	r2, r2, lsr #5
20002d4e:	88f9      	ldrh	r1, [r7, #6]
20002d50:	f001 011f 	and.w	r1, r1, #31
20002d54:	f04f 0001 	mov.w	r0, #1
20002d58:	fa00 f101 	lsl.w	r1, r0, r1
20002d5c:	f102 0260 	add.w	r2, r2, #96	; 0x60
20002d60:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
}
20002d64:	f107 070c 	add.w	r7, r7, #12
20002d68:	46bd      	mov	sp, r7
20002d6a:	bc80      	pop	{r7}
20002d6c:	4770      	bx	lr
20002d6e:	bf00      	nop

20002d70 <MSS_SPI_init>:
 */
void MSS_SPI_init
(
	mss_spi_instance_t * this_spi
)
{
20002d70:	b580      	push	{r7, lr}
20002d72:	b084      	sub	sp, #16
20002d74:	af00      	add	r7, sp, #0
20002d76:	6078      	str	r0, [r7, #4]
    uint16_t i;
    
    ASSERT((this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1));
20002d78:	687a      	ldr	r2, [r7, #4]
20002d7a:	f644 23f8 	movw	r3, #19192	; 0x4af8
20002d7e:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002d82:	429a      	cmp	r2, r3
20002d84:	d007      	beq.n	20002d96 <MSS_SPI_init+0x26>
20002d86:	687a      	ldr	r2, [r7, #4]
20002d88:	f644 237c 	movw	r3, #19068	; 0x4a7c
20002d8c:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002d90:	429a      	cmp	r2, r3
20002d92:	d000      	beq.n	20002d96 <MSS_SPI_init+0x26>
20002d94:	be00      	bkpt	0x0000
    
    if(this_spi == &g_mss_spi0)
20002d96:	687a      	ldr	r2, [r7, #4]
20002d98:	f644 23f8 	movw	r3, #19192	; 0x4af8
20002d9c:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002da0:	429a      	cmp	r2, r3
20002da2:	d126      	bne.n	20002df2 <MSS_SPI_init+0x82>
    {
        this_spi->hw_reg = ((SPI_REVB_TypeDef *) SPI0_BASE);
20002da4:	687a      	ldr	r2, [r7, #4]
20002da6:	f241 0300 	movw	r3, #4096	; 0x1000
20002daa:	f2c4 0300 	movt	r3, #16384	; 0x4000
20002dae:	6013      	str	r3, [r2, #0]
        this_spi->irqn = SPI0_IRQn;
20002db0:	687b      	ldr	r3, [r7, #4]
20002db2:	f04f 020c 	mov.w	r2, #12
20002db6:	809a      	strh	r2, [r3, #4]

        /* reset SPI0 */
        SYSREG->SOFT_RST_CR |= SYSREG_SPI0_SOFTRESET_MASK;
20002db8:	f242 0300 	movw	r3, #8192	; 0x2000
20002dbc:	f2ce 0304 	movt	r3, #57348	; 0xe004
20002dc0:	f242 0200 	movw	r2, #8192	; 0x2000
20002dc4:	f2ce 0204 	movt	r2, #57348	; 0xe004
20002dc8:	6b12      	ldr	r2, [r2, #48]	; 0x30
20002dca:	f442 7200 	orr.w	r2, r2, #512	; 0x200
20002dce:	631a      	str	r2, [r3, #48]	; 0x30
        /* Clear any previously pended SPI0 interrupt */
        NVIC_ClearPendingIRQ(SPI0_IRQn);
20002dd0:	f04f 000c 	mov.w	r0, #12
20002dd4:	f7ff ffae 	bl	20002d34 <NVIC_ClearPendingIRQ>
        /* Take SPI0 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_SPI0_SOFTRESET_MASK;
20002dd8:	f242 0300 	movw	r3, #8192	; 0x2000
20002ddc:	f2ce 0304 	movt	r3, #57348	; 0xe004
20002de0:	f242 0200 	movw	r2, #8192	; 0x2000
20002de4:	f2ce 0204 	movt	r2, #57348	; 0xe004
20002de8:	6b12      	ldr	r2, [r2, #48]	; 0x30
20002dea:	f422 7200 	bic.w	r2, r2, #512	; 0x200
20002dee:	631a      	str	r2, [r3, #48]	; 0x30
20002df0:	e025      	b.n	20002e3e <MSS_SPI_init+0xce>
    }
    else
    {
        this_spi->hw_reg = ((SPI_REVB_TypeDef *) SPI1_BASE);
20002df2:	687a      	ldr	r2, [r7, #4]
20002df4:	f241 0300 	movw	r3, #4096	; 0x1000
20002df8:	f2c4 0301 	movt	r3, #16385	; 0x4001
20002dfc:	6013      	str	r3, [r2, #0]
        this_spi->irqn = SPI1_IRQn;
20002dfe:	687b      	ldr	r3, [r7, #4]
20002e00:	f04f 020d 	mov.w	r2, #13
20002e04:	809a      	strh	r2, [r3, #4]
        
        /* reset SPI1 */
        SYSREG->SOFT_RST_CR |= SYSREG_SPI1_SOFTRESET_MASK;
20002e06:	f242 0300 	movw	r3, #8192	; 0x2000
20002e0a:	f2ce 0304 	movt	r3, #57348	; 0xe004
20002e0e:	f242 0200 	movw	r2, #8192	; 0x2000
20002e12:	f2ce 0204 	movt	r2, #57348	; 0xe004
20002e16:	6b12      	ldr	r2, [r2, #48]	; 0x30
20002e18:	f442 6280 	orr.w	r2, r2, #1024	; 0x400
20002e1c:	631a      	str	r2, [r3, #48]	; 0x30
        /* Clear any previously pended SPI1 interrupt */
        NVIC_ClearPendingIRQ(SPI1_IRQn);
20002e1e:	f04f 000d 	mov.w	r0, #13
20002e22:	f7ff ff87 	bl	20002d34 <NVIC_ClearPendingIRQ>
        /* Take SPI1 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_SPI1_SOFTRESET_MASK;
20002e26:	f242 0300 	movw	r3, #8192	; 0x2000
20002e2a:	f2ce 0304 	movt	r3, #57348	; 0xe004
20002e2e:	f242 0200 	movw	r2, #8192	; 0x2000
20002e32:	f2ce 0204 	movt	r2, #57348	; 0xe004
20002e36:	6b12      	ldr	r2, [r2, #48]	; 0x30
20002e38:	f422 6280 	bic.w	r2, r2, #1024	; 0x400
20002e3c:	631a      	str	r2, [r3, #48]	; 0x30
    }
    
    /* De-assert reset bit. */
    this_spi->hw_reg->CONTROL &= ~CTRL_REG_RESET_MASK;
20002e3e:	687b      	ldr	r3, [r7, #4]
20002e40:	681b      	ldr	r3, [r3, #0]
20002e42:	687a      	ldr	r2, [r7, #4]
20002e44:	6812      	ldr	r2, [r2, #0]
20002e46:	6812      	ldr	r2, [r2, #0]
20002e48:	f022 4200 	bic.w	r2, r2, #2147483648	; 0x80000000
20002e4c:	601a      	str	r2, [r3, #0]
    
    /* Initialize SPI driver instance data. */
    this_spi->frame_rx_handler = 0u;
20002e4e:	687b      	ldr	r3, [r7, #4]
20002e50:	f04f 0200 	mov.w	r2, #0
20002e54:	671a      	str	r2, [r3, #112]	; 0x70
    this_spi->slave_tx_frame = 0u;
20002e56:	687b      	ldr	r3, [r7, #4]
20002e58:	f04f 0200 	mov.w	r2, #0
20002e5c:	675a      	str	r2, [r3, #116]	; 0x74
    
    this_spi->block_rx_handler = 0u;
20002e5e:	687b      	ldr	r3, [r7, #4]
20002e60:	f04f 0200 	mov.w	r2, #0
20002e64:	679a      	str	r2, [r3, #120]	; 0x78
    
    this_spi->slave_tx_buffer = 0u;
20002e66:	687b      	ldr	r3, [r7, #4]
20002e68:	f04f 0200 	mov.w	r2, #0
20002e6c:	609a      	str	r2, [r3, #8]
    this_spi->slave_tx_size = 0u;
20002e6e:	687b      	ldr	r3, [r7, #4]
20002e70:	f04f 0200 	mov.w	r2, #0
20002e74:	60da      	str	r2, [r3, #12]
    this_spi->slave_tx_idx = 0u;
20002e76:	687b      	ldr	r3, [r7, #4]
20002e78:	f04f 0200 	mov.w	r2, #0
20002e7c:	611a      	str	r2, [r3, #16]

    this_spi->resp_tx_buffer = 0u;
20002e7e:	687b      	ldr	r3, [r7, #4]
20002e80:	f04f 0200 	mov.w	r2, #0
20002e84:	615a      	str	r2, [r3, #20]
    this_spi->resp_buff_size = 0u;
20002e86:	687b      	ldr	r3, [r7, #4]
20002e88:	f04f 0200 	mov.w	r2, #0
20002e8c:	619a      	str	r2, [r3, #24]
    this_spi->resp_buff_tx_idx = 0u;
20002e8e:	687b      	ldr	r3, [r7, #4]
20002e90:	f04f 0200 	mov.w	r2, #0
20002e94:	61da      	str	r2, [r3, #28]
    
    this_spi->cmd_handler = 0;
20002e96:	687b      	ldr	r3, [r7, #4]
20002e98:	f04f 0200 	mov.w	r2, #0
20002e9c:	621a      	str	r2, [r3, #32]
    
    this_spi->slave_rx_buffer = 0;
20002e9e:	687b      	ldr	r3, [r7, #4]
20002ea0:	f04f 0200 	mov.w	r2, #0
20002ea4:	625a      	str	r2, [r3, #36]	; 0x24
    this_spi->slave_rx_size = 0u;
20002ea6:	687b      	ldr	r3, [r7, #4]
20002ea8:	f04f 0200 	mov.w	r2, #0
20002eac:	629a      	str	r2, [r3, #40]	; 0x28
    this_spi->slave_rx_idx = 0u;
20002eae:	687b      	ldr	r3, [r7, #4]
20002eb0:	f04f 0200 	mov.w	r2, #0
20002eb4:	62da      	str	r2, [r3, #44]	; 0x2c
    
    for(i = 0u; i < (uint16_t)MSS_SPI_MAX_NB_OF_SLAVES; ++i)
20002eb6:	f04f 0300 	mov.w	r3, #0
20002eba:	81fb      	strh	r3, [r7, #14]
20002ebc:	e00b      	b.n	20002ed6 <MSS_SPI_init+0x166>
    {
        this_spi->slaves_cfg[i].ctrl_reg = NOT_CONFIGURED;
20002ebe:	89fa      	ldrh	r2, [r7, #14]
20002ec0:	687b      	ldr	r3, [r7, #4]
20002ec2:	f102 0206 	add.w	r2, r2, #6
20002ec6:	f04f 31ff 	mov.w	r1, #4294967295
20002eca:	f843 1032 	str.w	r1, [r3, r2, lsl #3]
    
    this_spi->slave_rx_buffer = 0;
    this_spi->slave_rx_size = 0u;
    this_spi->slave_rx_idx = 0u;
    
    for(i = 0u; i < (uint16_t)MSS_SPI_MAX_NB_OF_SLAVES; ++i)
20002ece:	89fb      	ldrh	r3, [r7, #14]
20002ed0:	f103 0301 	add.w	r3, r3, #1
20002ed4:	81fb      	strh	r3, [r7, #14]
20002ed6:	89fb      	ldrh	r3, [r7, #14]
20002ed8:	2b07      	cmp	r3, #7
20002eda:	d9f0      	bls.n	20002ebe <MSS_SPI_init+0x14e>
    {
        this_spi->slaves_cfg[i].ctrl_reg = NOT_CONFIGURED;
    }
}
20002edc:	f107 0710 	add.w	r7, r7, #16
20002ee0:	46bd      	mov	sp, r7
20002ee2:	bd80      	pop	{r7, pc}

20002ee4 <recover_from_rx_overflow>:
 */
static void recover_from_rx_overflow
(
    mss_spi_instance_t * this_spi
)
{
20002ee4:	b580      	push	{r7, lr}
20002ee6:	b08a      	sub	sp, #40	; 0x28
20002ee8:	af00      	add	r7, sp, #0
20002eea:	6078      	str	r0, [r7, #4]
    uint32_t slave_select;
    
    /*
     * Read current SPI hardware block configuration.
     */
    control_reg = this_spi->hw_reg->CONTROL;
20002eec:	687b      	ldr	r3, [r7, #4]
20002eee:	681b      	ldr	r3, [r3, #0]
20002ef0:	681b      	ldr	r3, [r3, #0]
20002ef2:	60fb      	str	r3, [r7, #12]
    clk_gen = this_spi->hw_reg->CLK_GEN;
20002ef4:	687b      	ldr	r3, [r7, #4]
20002ef6:	681b      	ldr	r3, [r3, #0]
20002ef8:	699b      	ldr	r3, [r3, #24]
20002efa:	613b      	str	r3, [r7, #16]
    frame_size = this_spi->hw_reg->TXRXDF_SIZE;
20002efc:	687b      	ldr	r3, [r7, #4]
20002efe:	681b      	ldr	r3, [r3, #0]
20002f00:	685b      	ldr	r3, [r3, #4]
20002f02:	617b      	str	r3, [r7, #20]
    control2 = this_spi->hw_reg->CONTROL2;
20002f04:	687b      	ldr	r3, [r7, #4]
20002f06:	681b      	ldr	r3, [r3, #0]
20002f08:	6a9b      	ldr	r3, [r3, #40]	; 0x28
20002f0a:	61bb      	str	r3, [r7, #24]
    packet_size = this_spi->hw_reg->PKTSIZE;
20002f0c:	687b      	ldr	r3, [r7, #4]
20002f0e:	681b      	ldr	r3, [r3, #0]
20002f10:	6b1b      	ldr	r3, [r3, #48]	; 0x30
20002f12:	61fb      	str	r3, [r7, #28]
    cmd_size = this_spi->hw_reg->CMDSIZE;
20002f14:	687b      	ldr	r3, [r7, #4]
20002f16:	681b      	ldr	r3, [r3, #0]
20002f18:	6b5b      	ldr	r3, [r3, #52]	; 0x34
20002f1a:	623b      	str	r3, [r7, #32]
    slave_select = this_spi->hw_reg->SLAVE_SELECT;
20002f1c:	687b      	ldr	r3, [r7, #4]
20002f1e:	681b      	ldr	r3, [r3, #0]
20002f20:	69db      	ldr	r3, [r3, #28]
20002f22:	627b      	str	r3, [r7, #36]	; 0x24
     
    /*
     * Reset the SPI hardware block.
     */
    if(this_spi == &g_mss_spi0)
20002f24:	687a      	ldr	r2, [r7, #4]
20002f26:	f644 23f8 	movw	r3, #19192	; 0x4af8
20002f2a:	f2c2 0300 	movt	r3, #8192	; 0x2000
20002f2e:	429a      	cmp	r2, r3
20002f30:	d12e      	bne.n	20002f90 <recover_from_rx_overflow+0xac>
    {
        this_spi->hw_reg = ((SPI_REVB_TypeDef *) SPI0_BASE);
20002f32:	687a      	ldr	r2, [r7, #4]
20002f34:	f241 0300 	movw	r3, #4096	; 0x1000
20002f38:	f2c4 0300 	movt	r3, #16384	; 0x4000
20002f3c:	6013      	str	r3, [r2, #0]
        this_spi->irqn = SPI0_IRQn;
20002f3e:	687b      	ldr	r3, [r7, #4]
20002f40:	f04f 020c 	mov.w	r2, #12
20002f44:	809a      	strh	r2, [r3, #4]

        /* reset SPI0 */
        SYSREG->SOFT_RST_CR |= SYSREG_SPI0_SOFTRESET_MASK;
20002f46:	f242 0300 	movw	r3, #8192	; 0x2000
20002f4a:	f2ce 0304 	movt	r3, #57348	; 0xe004
20002f4e:	f242 0200 	movw	r2, #8192	; 0x2000
20002f52:	f2ce 0204 	movt	r2, #57348	; 0xe004
20002f56:	6b12      	ldr	r2, [r2, #48]	; 0x30
20002f58:	f442 7200 	orr.w	r2, r2, #512	; 0x200
20002f5c:	631a      	str	r2, [r3, #48]	; 0x30
        /* Clear any previously pended SPI0 interrupt */
        NVIC_ClearPendingIRQ(SPI0_IRQn);
20002f5e:	f04f 000c 	mov.w	r0, #12
20002f62:	f7ff fee7 	bl	20002d34 <NVIC_ClearPendingIRQ>
        /* Take SPI0 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_SPI0_SOFTRESET_MASK;
20002f66:	f242 0300 	movw	r3, #8192	; 0x2000
20002f6a:	f2ce 0304 	movt	r3, #57348	; 0xe004
20002f6e:	f242 0200 	movw	r2, #8192	; 0x2000
20002f72:	f2ce 0204 	movt	r2, #57348	; 0xe004
20002f76:	6b12      	ldr	r2, [r2, #48]	; 0x30
20002f78:	f422 7200 	bic.w	r2, r2, #512	; 0x200
20002f7c:	631a      	str	r2, [r3, #48]	; 0x30

        this_spi->hw_reg->CONTROL &= ~CTRL_REG_RESET_MASK;
20002f7e:	687b      	ldr	r3, [r7, #4]
20002f80:	681b      	ldr	r3, [r3, #0]
20002f82:	687a      	ldr	r2, [r7, #4]
20002f84:	6812      	ldr	r2, [r2, #0]
20002f86:	6812      	ldr	r2, [r2, #0]
20002f88:	f022 4200 	bic.w	r2, r2, #2147483648	; 0x80000000
20002f8c:	601a      	str	r2, [r3, #0]
20002f8e:	e02d      	b.n	20002fec <recover_from_rx_overflow+0x108>
    }
    else
    {
        this_spi->hw_reg = ((SPI_REVB_TypeDef *) SPI1_BASE);
20002f90:	687a      	ldr	r2, [r7, #4]
20002f92:	f241 0300 	movw	r3, #4096	; 0x1000
20002f96:	f2c4 0301 	movt	r3, #16385	; 0x4001
20002f9a:	6013      	str	r3, [r2, #0]
        this_spi->irqn = SPI1_IRQn;
20002f9c:	687b      	ldr	r3, [r7, #4]
20002f9e:	f04f 020d 	mov.w	r2, #13
20002fa2:	809a      	strh	r2, [r3, #4]
        
        /* reset SPI1 */
        SYSREG->SOFT_RST_CR |= SYSREG_SPI1_SOFTRESET_MASK;
20002fa4:	f242 0300 	movw	r3, #8192	; 0x2000
20002fa8:	f2ce 0304 	movt	r3, #57348	; 0xe004
20002fac:	f242 0200 	movw	r2, #8192	; 0x2000
20002fb0:	f2ce 0204 	movt	r2, #57348	; 0xe004
20002fb4:	6b12      	ldr	r2, [r2, #48]	; 0x30
20002fb6:	f442 6280 	orr.w	r2, r2, #1024	; 0x400
20002fba:	631a      	str	r2, [r3, #48]	; 0x30
        /* Clear any previously pended SPI1 interrupt */
        NVIC_ClearPendingIRQ(SPI1_IRQn);
20002fbc:	f04f 000d 	mov.w	r0, #13
20002fc0:	f7ff feb8 	bl	20002d34 <NVIC_ClearPendingIRQ>
        /* Take SPI1 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_SPI1_SOFTRESET_MASK;
20002fc4:	f242 0300 	movw	r3, #8192	; 0x2000
20002fc8:	f2ce 0304 	movt	r3, #57348	; 0xe004
20002fcc:	f242 0200 	movw	r2, #8192	; 0x2000
20002fd0:	f2ce 0204 	movt	r2, #57348	; 0xe004
20002fd4:	6b12      	ldr	r2, [r2, #48]	; 0x30
20002fd6:	f422 6280 	bic.w	r2, r2, #1024	; 0x400
20002fda:	631a      	str	r2, [r3, #48]	; 0x30
        
        this_spi->hw_reg->CONTROL &= ~CTRL_REG_RESET_MASK;
20002fdc:	687b      	ldr	r3, [r7, #4]
20002fde:	681b      	ldr	r3, [r3, #0]
20002fe0:	687a      	ldr	r2, [r7, #4]
20002fe2:	6812      	ldr	r2, [r2, #0]
20002fe4:	6812      	ldr	r2, [r2, #0]
20002fe6:	f022 4200 	bic.w	r2, r2, #2147483648	; 0x80000000
20002fea:	601a      	str	r2, [r3, #0]
    }
    
    /*
     * Restore SPI hardware block configuration.
     */
    this_spi->hw_reg->CONTROL &= ~(uint32_t)CTRL_ENABLE_MASK;
20002fec:	687b      	ldr	r3, [r7, #4]
20002fee:	681b      	ldr	r3, [r3, #0]
20002ff0:	687a      	ldr	r2, [r7, #4]
20002ff2:	6812      	ldr	r2, [r2, #0]
20002ff4:	6812      	ldr	r2, [r2, #0]
20002ff6:	f022 0201 	bic.w	r2, r2, #1
20002ffa:	601a      	str	r2, [r3, #0]
    this_spi->hw_reg->CONTROL = control_reg;
20002ffc:	687b      	ldr	r3, [r7, #4]
20002ffe:	681b      	ldr	r3, [r3, #0]
20003000:	68fa      	ldr	r2, [r7, #12]
20003002:	601a      	str	r2, [r3, #0]
    this_spi->hw_reg->CLK_GEN = clk_gen;
20003004:	687b      	ldr	r3, [r7, #4]
20003006:	681b      	ldr	r3, [r3, #0]
20003008:	693a      	ldr	r2, [r7, #16]
2000300a:	619a      	str	r2, [r3, #24]
    this_spi->hw_reg->TXRXDF_SIZE = frame_size;
2000300c:	687b      	ldr	r3, [r7, #4]
2000300e:	681b      	ldr	r3, [r3, #0]
20003010:	697a      	ldr	r2, [r7, #20]
20003012:	605a      	str	r2, [r3, #4]
    this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK;
20003014:	687b      	ldr	r3, [r7, #4]
20003016:	681b      	ldr	r3, [r3, #0]
20003018:	687a      	ldr	r2, [r7, #4]
2000301a:	6812      	ldr	r2, [r2, #0]
2000301c:	6812      	ldr	r2, [r2, #0]
2000301e:	f042 0201 	orr.w	r2, r2, #1
20003022:	601a      	str	r2, [r3, #0]
    this_spi->hw_reg->CONTROL2 = control2;
20003024:	687b      	ldr	r3, [r7, #4]
20003026:	681b      	ldr	r3, [r3, #0]
20003028:	69ba      	ldr	r2, [r7, #24]
2000302a:	629a      	str	r2, [r3, #40]	; 0x28
    this_spi->hw_reg->PKTSIZE = packet_size;
2000302c:	687b      	ldr	r3, [r7, #4]
2000302e:	681b      	ldr	r3, [r3, #0]
20003030:	69fa      	ldr	r2, [r7, #28]
20003032:	631a      	str	r2, [r3, #48]	; 0x30
    this_spi->hw_reg->CMDSIZE = cmd_size;
20003034:	687b      	ldr	r3, [r7, #4]
20003036:	681b      	ldr	r3, [r3, #0]
20003038:	6a3a      	ldr	r2, [r7, #32]
2000303a:	635a      	str	r2, [r3, #52]	; 0x34
    this_spi->hw_reg->SLAVE_SELECT = slave_select;
2000303c:	687b      	ldr	r3, [r7, #4]
2000303e:	681b      	ldr	r3, [r3, #0]
20003040:	6a7a      	ldr	r2, [r7, #36]	; 0x24
20003042:	61da      	str	r2, [r3, #28]
}
20003044:	f107 0728 	add.w	r7, r7, #40	; 0x28
20003048:	46bd      	mov	sp, r7
2000304a:	bd80      	pop	{r7, pc}

2000304c <MSS_SPI_configure_slave_mode>:
	mss_spi_instance_t * this_spi,
    mss_spi_protocol_mode_t protocol_mode,
    mss_spi_pclk_div_t clk_rate,
    uint8_t frame_bit_length
)
{
2000304c:	b480      	push	{r7}
2000304e:	b085      	sub	sp, #20
20003050:	af00      	add	r7, sp, #0
20003052:	60f8      	str	r0, [r7, #12]
20003054:	60b9      	str	r1, [r7, #8]
20003056:	71fa      	strb	r2, [r7, #7]
20003058:	71bb      	strb	r3, [r7, #6]
    ASSERT((this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1));
2000305a:	68fa      	ldr	r2, [r7, #12]
2000305c:	f644 23f8 	movw	r3, #19192	; 0x4af8
20003060:	f2c2 0300 	movt	r3, #8192	; 0x2000
20003064:	429a      	cmp	r2, r3
20003066:	d007      	beq.n	20003078 <MSS_SPI_configure_slave_mode+0x2c>
20003068:	68fa      	ldr	r2, [r7, #12]
2000306a:	f644 237c 	movw	r3, #19068	; 0x4a7c
2000306e:	f2c2 0300 	movt	r3, #8192	; 0x2000
20003072:	429a      	cmp	r2, r3
20003074:	d000      	beq.n	20003078 <MSS_SPI_configure_slave_mode+0x2c>
20003076:	be00      	bkpt	0x0000
    ASSERT(frame_bit_length <= MAX_FRAME_LENGTH);
20003078:	79bb      	ldrb	r3, [r7, #6]
2000307a:	2b20      	cmp	r3, #32
2000307c:	d900      	bls.n	20003080 <MSS_SPI_configure_slave_mode+0x34>
2000307e:	be00      	bkpt	0x0000
    ASSERT(protocol_mode != MSS_SPI_NSC_MODE);
20003080:	68bb      	ldr	r3, [r7, #8]
20003082:	2b08      	cmp	r3, #8
20003084:	d100      	bne.n	20003088 <MSS_SPI_configure_slave_mode+0x3c>
20003086:	be00      	bkpt	0x0000
    
	/* Set the mode. */
    this_spi->hw_reg->CONTROL &= ~CTRL_MASTER_MASK;
20003088:	68fb      	ldr	r3, [r7, #12]
2000308a:	681b      	ldr	r3, [r3, #0]
2000308c:	68fa      	ldr	r2, [r7, #12]
2000308e:	6812      	ldr	r2, [r2, #0]
20003090:	6812      	ldr	r2, [r2, #0]
20003092:	f022 0202 	bic.w	r2, r2, #2
20003096:	601a      	str	r2, [r3, #0]

    /* Set the clock rate. */
    this_spi->hw_reg->CONTROL &= ~CTRL_ENABLE_MASK;
20003098:	68fb      	ldr	r3, [r7, #12]
2000309a:	681b      	ldr	r3, [r3, #0]
2000309c:	68fa      	ldr	r2, [r7, #12]
2000309e:	6812      	ldr	r2, [r2, #0]
200030a0:	6812      	ldr	r2, [r2, #0]
200030a2:	f022 0201 	bic.w	r2, r2, #1
200030a6:	601a      	str	r2, [r3, #0]
    this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~PROTOCOL_MODE_MASK) |
200030a8:	68fb      	ldr	r3, [r7, #12]
200030aa:	681a      	ldr	r2, [r3, #0]
200030ac:	68fb      	ldr	r3, [r7, #12]
200030ae:	681b      	ldr	r3, [r3, #0]
200030b0:	681b      	ldr	r3, [r3, #0]
200030b2:	f023 7340 	bic.w	r3, r3, #50331648	; 0x3000000
200030b6:	f023 03c0 	bic.w	r3, r3, #192	; 0xc0
                                (uint32_t)protocol_mode | BIGFIFO_MASK;
200030ba:	68b9      	ldr	r1, [r7, #8]
200030bc:	ea43 0301 	orr.w	r3, r3, r1
	/* Set the mode. */
    this_spi->hw_reg->CONTROL &= ~CTRL_MASTER_MASK;

    /* Set the clock rate. */
    this_spi->hw_reg->CONTROL &= ~CTRL_ENABLE_MASK;
    this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~PROTOCOL_MODE_MASK) |
200030c0:	f043 5300 	orr.w	r3, r3, #536870912	; 0x20000000
200030c4:	6013      	str	r3, [r2, #0]
                                (uint32_t)protocol_mode | BIGFIFO_MASK;
                                
    this_spi->hw_reg->CLK_GEN = (uint32_t)clk_rate;
200030c6:	68fb      	ldr	r3, [r7, #12]
200030c8:	681b      	ldr	r3, [r3, #0]
200030ca:	79fa      	ldrb	r2, [r7, #7]
200030cc:	619a      	str	r2, [r3, #24]
    
    /* Set default frame size to byte size and number of data frames to 1. */
    this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK) | ((uint32_t)1 << TXRXDFCOUNT_SHIFT);
200030ce:	68fb      	ldr	r3, [r7, #12]
200030d0:	681a      	ldr	r2, [r3, #0]
200030d2:	68fb      	ldr	r3, [r7, #12]
200030d4:	681b      	ldr	r3, [r3, #0]
200030d6:	6819      	ldr	r1, [r3, #0]
200030d8:	f240 03ff 	movw	r3, #255	; 0xff
200030dc:	f6cf 7300 	movt	r3, #65280	; 0xff00
200030e0:	ea01 0303 	and.w	r3, r1, r3
200030e4:	f443 7380 	orr.w	r3, r3, #256	; 0x100
200030e8:	6013      	str	r3, [r2, #0]
    this_spi->hw_reg->TXRXDF_SIZE = frame_bit_length;
200030ea:	68fb      	ldr	r3, [r7, #12]
200030ec:	681b      	ldr	r3, [r3, #0]
200030ee:	79ba      	ldrb	r2, [r7, #6]
200030f0:	605a      	str	r2, [r3, #4]
    this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK;
200030f2:	68fb      	ldr	r3, [r7, #12]
200030f4:	681b      	ldr	r3, [r3, #0]
200030f6:	68fa      	ldr	r2, [r7, #12]
200030f8:	6812      	ldr	r2, [r2, #0]
200030fa:	6812      	ldr	r2, [r2, #0]
200030fc:	f042 0201 	orr.w	r2, r2, #1
20003100:	601a      	str	r2, [r3, #0]
}
20003102:	f107 0714 	add.w	r7, r7, #20
20003106:	46bd      	mov	sp, r7
20003108:	bc80      	pop	{r7}
2000310a:	4770      	bx	lr

2000310c <MSS_SPI_configure_master_mode>:
	mss_spi_slave_t         slave,
    mss_spi_protocol_mode_t protocol_mode,
    mss_spi_pclk_div_t      clk_rate,
    uint8_t                 frame_bit_length
)
{
2000310c:	b480      	push	{r7}
2000310e:	b085      	sub	sp, #20
20003110:	af00      	add	r7, sp, #0
20003112:	60f8      	str	r0, [r7, #12]
20003114:	607a      	str	r2, [r7, #4]
20003116:	460a      	mov	r2, r1
20003118:	72fa      	strb	r2, [r7, #11]
2000311a:	70fb      	strb	r3, [r7, #3]
    ASSERT((this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1));
2000311c:	68fa      	ldr	r2, [r7, #12]
2000311e:	f644 23f8 	movw	r3, #19192	; 0x4af8
20003122:	f2c2 0300 	movt	r3, #8192	; 0x2000
20003126:	429a      	cmp	r2, r3
20003128:	d007      	beq.n	2000313a <MSS_SPI_configure_master_mode+0x2e>
2000312a:	68fa      	ldr	r2, [r7, #12]
2000312c:	f644 237c 	movw	r3, #19068	; 0x4a7c
20003130:	f2c2 0300 	movt	r3, #8192	; 0x2000
20003134:	429a      	cmp	r2, r3
20003136:	d000      	beq.n	2000313a <MSS_SPI_configure_master_mode+0x2e>
20003138:	be00      	bkpt	0x0000
    ASSERT(slave < MSS_SPI_MAX_NB_OF_SLAVES);
2000313a:	7afb      	ldrb	r3, [r7, #11]
2000313c:	2b07      	cmp	r3, #7
2000313e:	d900      	bls.n	20003142 <MSS_SPI_configure_master_mode+0x36>
20003140:	be00      	bkpt	0x0000
    ASSERT(frame_bit_length <= MAX_FRAME_LENGTH);
20003142:	7e3b      	ldrb	r3, [r7, #24]
20003144:	2b20      	cmp	r3, #32
20003146:	d900      	bls.n	2000314a <MSS_SPI_configure_master_mode+0x3e>
20003148:	be00      	bkpt	0x0000
    
	/* Set the mode. */
    this_spi->hw_reg->CONTROL &= ~CTRL_ENABLE_MASK;
2000314a:	68fb      	ldr	r3, [r7, #12]
2000314c:	681b      	ldr	r3, [r3, #0]
2000314e:	68fa      	ldr	r2, [r7, #12]
20003150:	6812      	ldr	r2, [r2, #0]
20003152:	6812      	ldr	r2, [r2, #0]
20003154:	f022 0201 	bic.w	r2, r2, #1
20003158:	601a      	str	r2, [r3, #0]
    this_spi->hw_reg->CONTROL |= CTRL_MASTER_MASK;
2000315a:	68fb      	ldr	r3, [r7, #12]
2000315c:	681b      	ldr	r3, [r3, #0]
2000315e:	68fa      	ldr	r2, [r7, #12]
20003160:	6812      	ldr	r2, [r2, #0]
20003162:	6812      	ldr	r2, [r2, #0]
20003164:	f042 0202 	orr.w	r2, r2, #2
20003168:	601a      	str	r2, [r3, #0]
    this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK;
2000316a:	68fb      	ldr	r3, [r7, #12]
2000316c:	681b      	ldr	r3, [r3, #0]
2000316e:	68fa      	ldr	r2, [r7, #12]
20003170:	6812      	ldr	r2, [r2, #0]
20003172:	6812      	ldr	r2, [r2, #0]
20003174:	f042 0201 	orr.w	r2, r2, #1
20003178:	601a      	str	r2, [r3, #0]
    /*
     * Keep track of the required register configuration for this slave. These
     * values will be used by the MSS_SPI_set_slave_select() function to configure
     * the master to match the slave being selected.
     */
    if(slave < MSS_SPI_MAX_NB_OF_SLAVES)     
2000317a:	7afb      	ldrb	r3, [r7, #11]
2000317c:	2b07      	cmp	r3, #7
2000317e:	d81e      	bhi.n	200031be <MSS_SPI_configure_master_mode+0xb2>
    {
        this_spi->slaves_cfg[slave].ctrl_reg = MASTER_MODE_MASK |
20003180:	7af9      	ldrb	r1, [r7, #11]
20003182:	687a      	ldr	r2, [r7, #4]
20003184:	f240 1302 	movw	r3, #258	; 0x102
20003188:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000318c:	ea42 0303 	orr.w	r3, r2, r3
20003190:	68fa      	ldr	r2, [r7, #12]
20003192:	f101 0106 	add.w	r1, r1, #6
20003196:	f842 3031 	str.w	r3, [r2, r1, lsl #3]
                                               BIGFIFO_MASK |
                                               (uint32_t)protocol_mode | 
                                               ((uint32_t)1 << TXRXDFCOUNT_SHIFT);
        this_spi->slaves_cfg[slave].txrxdf_size_reg = frame_bit_length;
2000319a:	7afb      	ldrb	r3, [r7, #11]
2000319c:	68fa      	ldr	r2, [r7, #12]
2000319e:	f103 0306 	add.w	r3, r3, #6
200031a2:	ea4f 03c3 	mov.w	r3, r3, lsl #3
200031a6:	4413      	add	r3, r2
200031a8:	7e3a      	ldrb	r2, [r7, #24]
200031aa:	711a      	strb	r2, [r3, #4]
        this_spi->slaves_cfg[slave].clk_gen = (uint8_t)clk_rate;
200031ac:	7afb      	ldrb	r3, [r7, #11]
200031ae:	68fa      	ldr	r2, [r7, #12]
200031b0:	f103 0306 	add.w	r3, r3, #6
200031b4:	ea4f 03c3 	mov.w	r3, r3, lsl #3
200031b8:	4413      	add	r3, r2
200031ba:	78fa      	ldrb	r2, [r7, #3]
200031bc:	715a      	strb	r2, [r3, #5]
    }
}
200031be:	f107 0714 	add.w	r7, r7, #20
200031c2:	46bd      	mov	sp, r7
200031c4:	bc80      	pop	{r7}
200031c6:	4770      	bx	lr

200031c8 <MSS_SPI_set_slave_select>:
void MSS_SPI_set_slave_select
(
	mss_spi_instance_t * this_spi,
	mss_spi_slave_t slave
)
{
200031c8:	b580      	push	{r7, lr}
200031ca:	b084      	sub	sp, #16
200031cc:	af00      	add	r7, sp, #0
200031ce:	6078      	str	r0, [r7, #4]
200031d0:	460b      	mov	r3, r1
200031d2:	70fb      	strb	r3, [r7, #3]
    uint32_t rx_overflow;
    
    ASSERT((this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1));
200031d4:	687a      	ldr	r2, [r7, #4]
200031d6:	f644 23f8 	movw	r3, #19192	; 0x4af8
200031da:	f2c2 0300 	movt	r3, #8192	; 0x2000
200031de:	429a      	cmp	r2, r3
200031e0:	d007      	beq.n	200031f2 <MSS_SPI_set_slave_select+0x2a>
200031e2:	687a      	ldr	r2, [r7, #4]
200031e4:	f644 237c 	movw	r3, #19068	; 0x4a7c
200031e8:	f2c2 0300 	movt	r3, #8192	; 0x2000
200031ec:	429a      	cmp	r2, r3
200031ee:	d000      	beq.n	200031f2 <MSS_SPI_set_slave_select+0x2a>
200031f0:	be00      	bkpt	0x0000
    
    /* This function is only intended to be used with an SPI master. */
    ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK) == CTRL_MASTER_MASK);
200031f2:	687b      	ldr	r3, [r7, #4]
200031f4:	681b      	ldr	r3, [r3, #0]
200031f6:	681b      	ldr	r3, [r3, #0]
200031f8:	f003 0302 	and.w	r3, r3, #2
200031fc:	2b00      	cmp	r3, #0
200031fe:	d100      	bne.n	20003202 <MSS_SPI_set_slave_select+0x3a>
20003200:	be00      	bkpt	0x0000
    
    ASSERT(this_spi->slaves_cfg[slave].ctrl_reg != NOT_CONFIGURED);
20003202:	78fa      	ldrb	r2, [r7, #3]
20003204:	687b      	ldr	r3, [r7, #4]
20003206:	f102 0206 	add.w	r2, r2, #6
2000320a:	f853 3032 	ldr.w	r3, [r3, r2, lsl #3]
2000320e:	f1b3 3fff 	cmp.w	r3, #4294967295
20003212:	d100      	bne.n	20003216 <MSS_SPI_set_slave_select+0x4e>
20003214:	be00      	bkpt	0x0000

    /* Recover from receive overflow. */
    rx_overflow = this_spi->hw_reg->STATUS & RX_OVERFLOW_MASK;
20003216:	687b      	ldr	r3, [r7, #4]
20003218:	681b      	ldr	r3, [r3, #0]
2000321a:	689b      	ldr	r3, [r3, #8]
2000321c:	f003 0304 	and.w	r3, r3, #4
20003220:	60fb      	str	r3, [r7, #12]
    if(rx_overflow)
20003222:	68fb      	ldr	r3, [r7, #12]
20003224:	2b00      	cmp	r3, #0
20003226:	d002      	beq.n	2000322e <MSS_SPI_set_slave_select+0x66>
    {
         recover_from_rx_overflow(this_spi);
20003228:	6878      	ldr	r0, [r7, #4]
2000322a:	f7ff fe5b 	bl	20002ee4 <recover_from_rx_overflow>
    }
    
    /* Set the clock rate. */
    this_spi->hw_reg->CONTROL &= ~CTRL_ENABLE_MASK;
2000322e:	687b      	ldr	r3, [r7, #4]
20003230:	681b      	ldr	r3, [r3, #0]
20003232:	687a      	ldr	r2, [r7, #4]
20003234:	6812      	ldr	r2, [r2, #0]
20003236:	6812      	ldr	r2, [r2, #0]
20003238:	f022 0201 	bic.w	r2, r2, #1
2000323c:	601a      	str	r2, [r3, #0]
    this_spi->hw_reg->CONTROL = this_spi->slaves_cfg[slave].ctrl_reg;
2000323e:	687b      	ldr	r3, [r7, #4]
20003240:	681b      	ldr	r3, [r3, #0]
20003242:	78f9      	ldrb	r1, [r7, #3]
20003244:	687a      	ldr	r2, [r7, #4]
20003246:	f101 0106 	add.w	r1, r1, #6
2000324a:	f852 2031 	ldr.w	r2, [r2, r1, lsl #3]
2000324e:	601a      	str	r2, [r3, #0]
    this_spi->hw_reg->CLK_GEN = this_spi->slaves_cfg[slave].clk_gen;
20003250:	687b      	ldr	r3, [r7, #4]
20003252:	681a      	ldr	r2, [r3, #0]
20003254:	78fb      	ldrb	r3, [r7, #3]
20003256:	6879      	ldr	r1, [r7, #4]
20003258:	f103 0306 	add.w	r3, r3, #6
2000325c:	ea4f 03c3 	mov.w	r3, r3, lsl #3
20003260:	440b      	add	r3, r1
20003262:	795b      	ldrb	r3, [r3, #5]
20003264:	6193      	str	r3, [r2, #24]
    this_spi->hw_reg->TXRXDF_SIZE = this_spi->slaves_cfg[slave].txrxdf_size_reg;
20003266:	687b      	ldr	r3, [r7, #4]
20003268:	681a      	ldr	r2, [r3, #0]
2000326a:	78fb      	ldrb	r3, [r7, #3]
2000326c:	6879      	ldr	r1, [r7, #4]
2000326e:	f103 0306 	add.w	r3, r3, #6
20003272:	ea4f 03c3 	mov.w	r3, r3, lsl #3
20003276:	440b      	add	r3, r1
20003278:	791b      	ldrb	r3, [r3, #4]
2000327a:	6053      	str	r3, [r2, #4]
    this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK;
2000327c:	687b      	ldr	r3, [r7, #4]
2000327e:	681b      	ldr	r3, [r3, #0]
20003280:	687a      	ldr	r2, [r7, #4]
20003282:	6812      	ldr	r2, [r2, #0]
20003284:	6812      	ldr	r2, [r2, #0]
20003286:	f042 0201 	orr.w	r2, r2, #1
2000328a:	601a      	str	r2, [r3, #0]
    
    /* Set slave select */
    this_spi->hw_reg->SLAVE_SELECT |= ((uint32_t)1 << (uint32_t)slave);
2000328c:	687b      	ldr	r3, [r7, #4]
2000328e:	681b      	ldr	r3, [r3, #0]
20003290:	687a      	ldr	r2, [r7, #4]
20003292:	6812      	ldr	r2, [r2, #0]
20003294:	69d1      	ldr	r1, [r2, #28]
20003296:	78fa      	ldrb	r2, [r7, #3]
20003298:	f04f 0001 	mov.w	r0, #1
2000329c:	fa00 f202 	lsl.w	r2, r0, r2
200032a0:	ea41 0202 	orr.w	r2, r1, r2
200032a4:	61da      	str	r2, [r3, #28]
}
200032a6:	f107 0710 	add.w	r7, r7, #16
200032aa:	46bd      	mov	sp, r7
200032ac:	bd80      	pop	{r7, pc}
200032ae:	bf00      	nop

200032b0 <MSS_SPI_clear_slave_select>:
void MSS_SPI_clear_slave_select
(
	mss_spi_instance_t * this_spi,
	mss_spi_slave_t slave
)
{
200032b0:	b580      	push	{r7, lr}
200032b2:	b084      	sub	sp, #16
200032b4:	af00      	add	r7, sp, #0
200032b6:	6078      	str	r0, [r7, #4]
200032b8:	460b      	mov	r3, r1
200032ba:	70fb      	strb	r3, [r7, #3]
    uint32_t rx_overflow;
    
    ASSERT((this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1));
200032bc:	687a      	ldr	r2, [r7, #4]
200032be:	f644 23f8 	movw	r3, #19192	; 0x4af8
200032c2:	f2c2 0300 	movt	r3, #8192	; 0x2000
200032c6:	429a      	cmp	r2, r3
200032c8:	d007      	beq.n	200032da <MSS_SPI_clear_slave_select+0x2a>
200032ca:	687a      	ldr	r2, [r7, #4]
200032cc:	f644 237c 	movw	r3, #19068	; 0x4a7c
200032d0:	f2c2 0300 	movt	r3, #8192	; 0x2000
200032d4:	429a      	cmp	r2, r3
200032d6:	d000      	beq.n	200032da <MSS_SPI_clear_slave_select+0x2a>
200032d8:	be00      	bkpt	0x0000
    
    /* This function is only intended to be used with an SPI master. */
    ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK) == CTRL_MASTER_MASK);
200032da:	687b      	ldr	r3, [r7, #4]
200032dc:	681b      	ldr	r3, [r3, #0]
200032de:	681b      	ldr	r3, [r3, #0]
200032e0:	f003 0302 	and.w	r3, r3, #2
200032e4:	2b00      	cmp	r3, #0
200032e6:	d100      	bne.n	200032ea <MSS_SPI_clear_slave_select+0x3a>
200032e8:	be00      	bkpt	0x0000

    /* Recover from receive overflow. */
    rx_overflow = this_spi->hw_reg->STATUS & RX_OVERFLOW_MASK;
200032ea:	687b      	ldr	r3, [r7, #4]
200032ec:	681b      	ldr	r3, [r3, #0]
200032ee:	689b      	ldr	r3, [r3, #8]
200032f0:	f003 0304 	and.w	r3, r3, #4
200032f4:	60fb      	str	r3, [r7, #12]
    if(rx_overflow)
200032f6:	68fb      	ldr	r3, [r7, #12]
200032f8:	2b00      	cmp	r3, #0
200032fa:	d002      	beq.n	20003302 <MSS_SPI_clear_slave_select+0x52>
    {
         recover_from_rx_overflow(this_spi);
200032fc:	6878      	ldr	r0, [r7, #4]
200032fe:	f7ff fdf1 	bl	20002ee4 <recover_from_rx_overflow>
    }
    
    this_spi->hw_reg->SLAVE_SELECT &= ~((uint32_t)1 << (uint32_t)slave);
20003302:	687b      	ldr	r3, [r7, #4]
20003304:	681b      	ldr	r3, [r3, #0]
20003306:	687a      	ldr	r2, [r7, #4]
20003308:	6812      	ldr	r2, [r2, #0]
2000330a:	69d1      	ldr	r1, [r2, #28]
2000330c:	78fa      	ldrb	r2, [r7, #3]
2000330e:	f04f 0001 	mov.w	r0, #1
20003312:	fa00 f202 	lsl.w	r2, r0, r2
20003316:	ea6f 0202 	mvn.w	r2, r2
2000331a:	ea01 0202 	and.w	r2, r1, r2
2000331e:	61da      	str	r2, [r3, #28]
}
20003320:	f107 0710 	add.w	r7, r7, #16
20003324:	46bd      	mov	sp, r7
20003326:	bd80      	pop	{r7, pc}

20003328 <MSS_SPI_transfer_frame>:
uint32_t MSS_SPI_transfer_frame
(
    mss_spi_instance_t * this_spi,
    uint32_t tx_bits
)
{
20003328:	b480      	push	{r7}
2000332a:	b087      	sub	sp, #28
2000332c:	af00      	add	r7, sp, #0
2000332e:	6078      	str	r0, [r7, #4]
20003330:	6039      	str	r1, [r7, #0]
    volatile uint32_t dummy;
    uint32_t rx_fifo_empty;
    uint32_t rx_ready;
    uint32_t tx_done;
    
    ASSERT((this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1));
20003332:	687a      	ldr	r2, [r7, #4]
20003334:	f644 23f8 	movw	r3, #19192	; 0x4af8
20003338:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000333c:	429a      	cmp	r2, r3
2000333e:	d007      	beq.n	20003350 <MSS_SPI_transfer_frame+0x28>
20003340:	687a      	ldr	r2, [r7, #4]
20003342:	f644 237c 	movw	r3, #19068	; 0x4a7c
20003346:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000334a:	429a      	cmp	r2, r3
2000334c:	d000      	beq.n	20003350 <MSS_SPI_transfer_frame+0x28>
2000334e:	be00      	bkpt	0x0000
    
    /* This function is only intended to be used with an SPI master. */
    ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK) == CTRL_MASTER_MASK);
20003350:	687b      	ldr	r3, [r7, #4]
20003352:	681b      	ldr	r3, [r3, #0]
20003354:	681b      	ldr	r3, [r3, #0]
20003356:	f003 0302 	and.w	r3, r3, #2
2000335a:	2b00      	cmp	r3, #0
2000335c:	d100      	bne.n	20003360 <MSS_SPI_transfer_frame+0x38>
2000335e:	be00      	bkpt	0x0000
    
    /* Flush the Tx and Rx FIFOs. Please note this does not have any effect on A2F200. */
    this_spi->hw_reg->COMMAND |= (TX_FIFO_RESET_MASK | RX_FIFO_RESET_MASK);
20003360:	687b      	ldr	r3, [r7, #4]
20003362:	681b      	ldr	r3, [r3, #0]
20003364:	687a      	ldr	r2, [r7, #4]
20003366:	6812      	ldr	r2, [r2, #0]
20003368:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
2000336a:	f042 020c 	orr.w	r2, r2, #12
2000336e:	62da      	str	r2, [r3, #44]	; 0x2c
    
    /* Flush Rx FIFO in case we are executing on A2F200. */
    rx_fifo_empty = this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK;
20003370:	687b      	ldr	r3, [r7, #4]
20003372:	681b      	ldr	r3, [r3, #0]
20003374:	689b      	ldr	r3, [r3, #8]
20003376:	f003 0340 	and.w	r3, r3, #64	; 0x40
2000337a:	60fb      	str	r3, [r7, #12]
    while(!rx_fifo_empty)
2000337c:	e00b      	b.n	20003396 <MSS_SPI_transfer_frame+0x6e>
    {
        dummy = this_spi->hw_reg->RX_DATA;
2000337e:	687b      	ldr	r3, [r7, #4]
20003380:	681b      	ldr	r3, [r3, #0]
20003382:	691b      	ldr	r3, [r3, #16]
20003384:	60bb      	str	r3, [r7, #8]
        dummy = dummy;  /* Prevent Lint warning. */
20003386:	68bb      	ldr	r3, [r7, #8]
20003388:	60bb      	str	r3, [r7, #8]
        rx_fifo_empty = this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK;
2000338a:	687b      	ldr	r3, [r7, #4]
2000338c:	681b      	ldr	r3, [r3, #0]
2000338e:	689b      	ldr	r3, [r3, #8]
20003390:	f003 0340 	and.w	r3, r3, #64	; 0x40
20003394:	60fb      	str	r3, [r7, #12]
    /* Flush the Tx and Rx FIFOs. Please note this does not have any effect on A2F200. */
    this_spi->hw_reg->COMMAND |= (TX_FIFO_RESET_MASK | RX_FIFO_RESET_MASK);
    
    /* Flush Rx FIFO in case we are executing on A2F200. */
    rx_fifo_empty = this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK;
    while(!rx_fifo_empty)
20003396:	68fb      	ldr	r3, [r7, #12]
20003398:	2b00      	cmp	r3, #0
2000339a:	d0f0      	beq.n	2000337e <MSS_SPI_transfer_frame+0x56>
        dummy = dummy;  /* Prevent Lint warning. */
        rx_fifo_empty = this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK;
    }
    
    /* Send frame. */
    this_spi->hw_reg->TX_DATA = tx_bits;
2000339c:	687b      	ldr	r3, [r7, #4]
2000339e:	681b      	ldr	r3, [r3, #0]
200033a0:	683a      	ldr	r2, [r7, #0]
200033a2:	615a      	str	r2, [r3, #20]
    
    /* Wait for frame Tx to complete. */
    tx_done = this_spi->hw_reg->STATUS & TX_DONE_MASK;
200033a4:	687b      	ldr	r3, [r7, #4]
200033a6:	681b      	ldr	r3, [r3, #0]
200033a8:	689b      	ldr	r3, [r3, #8]
200033aa:	f003 0301 	and.w	r3, r3, #1
200033ae:	617b      	str	r3, [r7, #20]
    while(!tx_done)
200033b0:	e005      	b.n	200033be <MSS_SPI_transfer_frame+0x96>
    {
        tx_done = this_spi->hw_reg->STATUS & TX_DONE_MASK;
200033b2:	687b      	ldr	r3, [r7, #4]
200033b4:	681b      	ldr	r3, [r3, #0]
200033b6:	689b      	ldr	r3, [r3, #8]
200033b8:	f003 0301 	and.w	r3, r3, #1
200033bc:	617b      	str	r3, [r7, #20]
    /* Send frame. */
    this_spi->hw_reg->TX_DATA = tx_bits;
    
    /* Wait for frame Tx to complete. */
    tx_done = this_spi->hw_reg->STATUS & TX_DONE_MASK;
    while(!tx_done)
200033be:	697b      	ldr	r3, [r7, #20]
200033c0:	2b00      	cmp	r3, #0
200033c2:	d0f6      	beq.n	200033b2 <MSS_SPI_transfer_frame+0x8a>
        tx_done = this_spi->hw_reg->STATUS & TX_DONE_MASK;
    }
    
    /* Read received frame. */
    /* Wait for Rx complete. */
    rx_ready = this_spi->hw_reg->STATUS & RX_DATA_READY_MASK;
200033c4:	687b      	ldr	r3, [r7, #4]
200033c6:	681b      	ldr	r3, [r3, #0]
200033c8:	689b      	ldr	r3, [r3, #8]
200033ca:	f003 0302 	and.w	r3, r3, #2
200033ce:	613b      	str	r3, [r7, #16]
    while(!rx_ready)
200033d0:	e005      	b.n	200033de <MSS_SPI_transfer_frame+0xb6>
    {
        rx_ready = this_spi->hw_reg->STATUS & RX_DATA_READY_MASK;
200033d2:	687b      	ldr	r3, [r7, #4]
200033d4:	681b      	ldr	r3, [r3, #0]
200033d6:	689b      	ldr	r3, [r3, #8]
200033d8:	f003 0302 	and.w	r3, r3, #2
200033dc:	613b      	str	r3, [r7, #16]
    }
    
    /* Read received frame. */
    /* Wait for Rx complete. */
    rx_ready = this_spi->hw_reg->STATUS & RX_DATA_READY_MASK;
    while(!rx_ready)
200033de:	693b      	ldr	r3, [r7, #16]
200033e0:	2b00      	cmp	r3, #0
200033e2:	d0f6      	beq.n	200033d2 <MSS_SPI_transfer_frame+0xaa>
    {
        rx_ready = this_spi->hw_reg->STATUS & RX_DATA_READY_MASK;
    }
    /* Return Rx data. */
    return( this_spi->hw_reg->RX_DATA );
200033e4:	687b      	ldr	r3, [r7, #4]
200033e6:	681b      	ldr	r3, [r3, #0]
200033e8:	691b      	ldr	r3, [r3, #16]
}
200033ea:	4618      	mov	r0, r3
200033ec:	f107 071c 	add.w	r7, r7, #28
200033f0:	46bd      	mov	sp, r7
200033f2:	bc80      	pop	{r7}
200033f4:	4770      	bx	lr
200033f6:	bf00      	nop

200033f8 <MSS_SPI_transfer_block>:
    const uint8_t * cmd_buffer,
    uint16_t cmd_byte_size,
    uint8_t * rd_buffer,
    uint16_t rd_byte_size
)
{
200033f8:	b580      	push	{r7, lr}
200033fa:	b08e      	sub	sp, #56	; 0x38
200033fc:	af00      	add	r7, sp, #0
200033fe:	60f8      	str	r0, [r7, #12]
20003400:	60b9      	str	r1, [r7, #8]
20003402:	603b      	str	r3, [r7, #0]
20003404:	4613      	mov	r3, r2
20003406:	80fb      	strh	r3, [r7, #6]
    uint16_t transfer_idx = 0u;
20003408:	f04f 0300 	mov.w	r3, #0
2000340c:	837b      	strh	r3, [r7, #26]
    uint16_t tx_idx;
    uint16_t rx_idx;
    uint32_t frame_count;
    volatile uint32_t rx_raw;
    uint16_t transit = 0u;
2000340e:	f04f 0300 	mov.w	r3, #0
20003412:	84fb      	strh	r3, [r7, #38]	; 0x26
    uint32_t rx_overflow;
    uint32_t rx_fifo_empty;
    
    uint16_t transfer_size;     /* Total number of bytes transfered. */
    
    ASSERT((this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1));
20003414:	68fa      	ldr	r2, [r7, #12]
20003416:	f644 23f8 	movw	r3, #19192	; 0x4af8
2000341a:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000341e:	429a      	cmp	r2, r3
20003420:	d007      	beq.n	20003432 <MSS_SPI_transfer_block+0x3a>
20003422:	68fa      	ldr	r2, [r7, #12]
20003424:	f644 237c 	movw	r3, #19068	; 0x4a7c
20003428:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000342c:	429a      	cmp	r2, r3
2000342e:	d000      	beq.n	20003432 <MSS_SPI_transfer_block+0x3a>
20003430:	be00      	bkpt	0x0000
    
    /* This function is only intended to be used with an SPI master. */
    ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK) == CTRL_MASTER_MASK);
20003432:	68fb      	ldr	r3, [r7, #12]
20003434:	681b      	ldr	r3, [r3, #0]
20003436:	681b      	ldr	r3, [r3, #0]
20003438:	f003 0302 	and.w	r3, r3, #2
2000343c:	2b00      	cmp	r3, #0
2000343e:	d100      	bne.n	20003442 <MSS_SPI_transfer_block+0x4a>
20003440:	be00      	bkpt	0x0000
    
    /* Compute number of bytes to transfer. */
    transfer_size = cmd_byte_size + rd_byte_size;
20003442:	88fa      	ldrh	r2, [r7, #6]
20003444:	f8b7 3040 	ldrh.w	r3, [r7, #64]	; 0x40
20003448:	4413      	add	r3, r2
2000344a:	86fb      	strh	r3, [r7, #54]	; 0x36
    
    /* Adjust to 1 byte transfer to cater for DMA transfers. */
    if(transfer_size == 0u)
2000344c:	8efb      	ldrh	r3, [r7, #54]	; 0x36
2000344e:	2b00      	cmp	r3, #0
20003450:	d103      	bne.n	2000345a <MSS_SPI_transfer_block+0x62>
    {
        frame_count = 1u;
20003452:	f04f 0301 	mov.w	r3, #1
20003456:	623b      	str	r3, [r7, #32]
20003458:	e001      	b.n	2000345e <MSS_SPI_transfer_block+0x66>
    }
    else
    {
        frame_count = transfer_size;
2000345a:	8efb      	ldrh	r3, [r7, #54]	; 0x36
2000345c:	623b      	str	r3, [r7, #32]
    }

    /* Flush the Tx and Rx FIFOs. Please note this does not have any effect on A2F200. */
    this_spi->hw_reg->COMMAND |= (TX_FIFO_RESET_MASK | RX_FIFO_RESET_MASK);
2000345e:	68fb      	ldr	r3, [r7, #12]
20003460:	681b      	ldr	r3, [r3, #0]
20003462:	68fa      	ldr	r2, [r7, #12]
20003464:	6812      	ldr	r2, [r2, #0]
20003466:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
20003468:	f042 020c 	orr.w	r2, r2, #12
2000346c:	62da      	str	r2, [r3, #44]	; 0x2c
    
    /* Recover from receive overflow. */
    rx_overflow = this_spi->hw_reg->STATUS & RX_OVERFLOW_MASK;
2000346e:	68fb      	ldr	r3, [r7, #12]
20003470:	681b      	ldr	r3, [r3, #0]
20003472:	689b      	ldr	r3, [r3, #8]
20003474:	f003 0304 	and.w	r3, r3, #4
20003478:	62fb      	str	r3, [r7, #44]	; 0x2c
    if(rx_overflow)
2000347a:	6afb      	ldr	r3, [r7, #44]	; 0x2c
2000347c:	2b00      	cmp	r3, #0
2000347e:	d002      	beq.n	20003486 <MSS_SPI_transfer_block+0x8e>
    {
         recover_from_rx_overflow(this_spi);
20003480:	68f8      	ldr	r0, [r7, #12]
20003482:	f7ff fd2f 	bl	20002ee4 <recover_from_rx_overflow>
    }
    
    /* Set frame size to 8 bits and the frame count to the transfer size. */
    this_spi->hw_reg->CONTROL &= ~CTRL_ENABLE_MASK;
20003486:	68fb      	ldr	r3, [r7, #12]
20003488:	681b      	ldr	r3, [r3, #0]
2000348a:	68fa      	ldr	r2, [r7, #12]
2000348c:	6812      	ldr	r2, [r2, #0]
2000348e:	6812      	ldr	r2, [r2, #0]
20003490:	f022 0201 	bic.w	r2, r2, #1
20003494:	601a      	str	r2, [r3, #0]
    this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK) | ( (frame_count << TXRXDFCOUNT_SHIFT) & TXRXDFCOUNT_MASK);
20003496:	68fb      	ldr	r3, [r7, #12]
20003498:	6819      	ldr	r1, [r3, #0]
2000349a:	68fb      	ldr	r3, [r7, #12]
2000349c:	681b      	ldr	r3, [r3, #0]
2000349e:	681b      	ldr	r3, [r3, #0]
200034a0:	f240 02ff 	movw	r2, #255	; 0xff
200034a4:	f6cf 7200 	movt	r2, #65280	; 0xff00
200034a8:	ea03 0202 	and.w	r2, r3, r2
200034ac:	6a3b      	ldr	r3, [r7, #32]
200034ae:	ea4f 2003 	mov.w	r0, r3, lsl #8
200034b2:	f64f 7300 	movw	r3, #65280	; 0xff00
200034b6:	f2c0 03ff 	movt	r3, #255	; 0xff
200034ba:	ea00 0303 	and.w	r3, r0, r3
200034be:	ea42 0303 	orr.w	r3, r2, r3
200034c2:	600b      	str	r3, [r1, #0]
    this_spi->hw_reg->TXRXDF_SIZE = 8u;
200034c4:	68fb      	ldr	r3, [r7, #12]
200034c6:	681b      	ldr	r3, [r3, #0]
200034c8:	f04f 0208 	mov.w	r2, #8
200034cc:	605a      	str	r2, [r3, #4]
    this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK;
200034ce:	68fb      	ldr	r3, [r7, #12]
200034d0:	681b      	ldr	r3, [r3, #0]
200034d2:	68fa      	ldr	r2, [r7, #12]
200034d4:	6812      	ldr	r2, [r2, #0]
200034d6:	6812      	ldr	r2, [r2, #0]
200034d8:	f042 0201 	orr.w	r2, r2, #1
200034dc:	601a      	str	r2, [r3, #0]

    /* Flush the receive FIFO. */
    rx_fifo_empty = this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK;
200034de:	68fb      	ldr	r3, [r7, #12]
200034e0:	681b      	ldr	r3, [r3, #0]
200034e2:	689b      	ldr	r3, [r3, #8]
200034e4:	f003 0340 	and.w	r3, r3, #64	; 0x40
200034e8:	633b      	str	r3, [r7, #48]	; 0x30
    while(!rx_fifo_empty)
200034ea:	e009      	b.n	20003500 <MSS_SPI_transfer_block+0x108>
    {
        rx_raw = this_spi->hw_reg->RX_DATA;
200034ec:	68fb      	ldr	r3, [r7, #12]
200034ee:	681b      	ldr	r3, [r3, #0]
200034f0:	691b      	ldr	r3, [r3, #16]
200034f2:	617b      	str	r3, [r7, #20]
        rx_fifo_empty = this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK;
200034f4:	68fb      	ldr	r3, [r7, #12]
200034f6:	681b      	ldr	r3, [r3, #0]
200034f8:	689b      	ldr	r3, [r3, #8]
200034fa:	f003 0340 	and.w	r3, r3, #64	; 0x40
200034fe:	633b      	str	r3, [r7, #48]	; 0x30
    this_spi->hw_reg->TXRXDF_SIZE = 8u;
    this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK;

    /* Flush the receive FIFO. */
    rx_fifo_empty = this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK;
    while(!rx_fifo_empty)
20003500:	6b3b      	ldr	r3, [r7, #48]	; 0x30
20003502:	2b00      	cmp	r3, #0
20003504:	d0f2      	beq.n	200034ec <MSS_SPI_transfer_block+0xf4>
    {
        rx_raw = this_spi->hw_reg->RX_DATA;
        rx_fifo_empty = this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK;
    }
    
    tx_idx = 0u;
20003506:	f04f 0300 	mov.w	r3, #0
2000350a:	83bb      	strh	r3, [r7, #28]
    rx_idx = 0u;
2000350c:	f04f 0300 	mov.w	r3, #0
20003510:	83fb      	strh	r3, [r7, #30]
    if(tx_idx < cmd_byte_size)
20003512:	8bba      	ldrh	r2, [r7, #28]
20003514:	88fb      	ldrh	r3, [r7, #6]
20003516:	429a      	cmp	r2, r3
20003518:	d20f      	bcs.n	2000353a <MSS_SPI_transfer_block+0x142>
    {
        this_spi->hw_reg->TX_DATA = cmd_buffer[tx_idx];
2000351a:	68fb      	ldr	r3, [r7, #12]
2000351c:	681b      	ldr	r3, [r3, #0]
2000351e:	8bb9      	ldrh	r1, [r7, #28]
20003520:	68ba      	ldr	r2, [r7, #8]
20003522:	440a      	add	r2, r1
20003524:	7812      	ldrb	r2, [r2, #0]
20003526:	615a      	str	r2, [r3, #20]
        ++tx_idx;
20003528:	8bbb      	ldrh	r3, [r7, #28]
2000352a:	f103 0301 	add.w	r3, r3, #1
2000352e:	83bb      	strh	r3, [r7, #28]
        ++transit;
20003530:	8cfb      	ldrh	r3, [r7, #38]	; 0x26
20003532:	f103 0301 	add.w	r3, r3, #1
20003536:	84fb      	strh	r3, [r7, #38]	; 0x26
        }
    }
    /* Perform the remainder of the transfer by sending a byte every time a byte
     * has been received. This should ensure that no Rx overflow can happen in
     * case of an interrupt occurs during this function. */
    while(transfer_idx < transfer_size)
20003538:	e06a      	b.n	20003610 <MSS_SPI_transfer_block+0x218>
        ++tx_idx;
        ++transit;
    }
    else
    {
        if(tx_idx < transfer_size)
2000353a:	8bba      	ldrh	r2, [r7, #28]
2000353c:	8efb      	ldrh	r3, [r7, #54]	; 0x36
2000353e:	429a      	cmp	r2, r3
20003540:	d266      	bcs.n	20003610 <MSS_SPI_transfer_block+0x218>
        {
            this_spi->hw_reg->TX_DATA = 0x00u;
20003542:	68fb      	ldr	r3, [r7, #12]
20003544:	681b      	ldr	r3, [r3, #0]
20003546:	f04f 0200 	mov.w	r2, #0
2000354a:	615a      	str	r2, [r3, #20]
            ++tx_idx;
2000354c:	8bbb      	ldrh	r3, [r7, #28]
2000354e:	f103 0301 	add.w	r3, r3, #1
20003552:	83bb      	strh	r3, [r7, #28]
            ++transit;
20003554:	8cfb      	ldrh	r3, [r7, #38]	; 0x26
20003556:	f103 0301 	add.w	r3, r3, #1
2000355a:	84fb      	strh	r3, [r7, #38]	; 0x26
        }
    }
    /* Perform the remainder of the transfer by sending a byte every time a byte
     * has been received. This should ensure that no Rx overflow can happen in
     * case of an interrupt occurs during this function. */
    while(transfer_idx < transfer_size)
2000355c:	e058      	b.n	20003610 <MSS_SPI_transfer_block+0x218>
    {
        rx_fifo_empty = this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK;
2000355e:	68fb      	ldr	r3, [r7, #12]
20003560:	681b      	ldr	r3, [r3, #0]
20003562:	689b      	ldr	r3, [r3, #8]
20003564:	f003 0340 	and.w	r3, r3, #64	; 0x40
20003568:	633b      	str	r3, [r7, #48]	; 0x30
        if(!rx_fifo_empty)
2000356a:	6b3b      	ldr	r3, [r7, #48]	; 0x30
2000356c:	2b00      	cmp	r3, #0
2000356e:	d11e      	bne.n	200035ae <MSS_SPI_transfer_block+0x1b6>
        {
            /* Process received byte. */
            rx_raw = this_spi->hw_reg->RX_DATA;
20003570:	68fb      	ldr	r3, [r7, #12]
20003572:	681b      	ldr	r3, [r3, #0]
20003574:	691b      	ldr	r3, [r3, #16]
20003576:	617b      	str	r3, [r7, #20]
            if(transfer_idx >= cmd_byte_size)
20003578:	8b7a      	ldrh	r2, [r7, #26]
2000357a:	88fb      	ldrh	r3, [r7, #6]
2000357c:	429a      	cmp	r2, r3
2000357e:	d30e      	bcc.n	2000359e <MSS_SPI_transfer_block+0x1a6>
            {
                if(rx_idx < rd_byte_size)
20003580:	8bfa      	ldrh	r2, [r7, #30]
20003582:	f8b7 3040 	ldrh.w	r3, [r7, #64]	; 0x40
20003586:	429a      	cmp	r2, r3
20003588:	d205      	bcs.n	20003596 <MSS_SPI_transfer_block+0x19e>
                {
                    rd_buffer[rx_idx] = (uint8_t)rx_raw;   
2000358a:	8bfa      	ldrh	r2, [r7, #30]
2000358c:	683b      	ldr	r3, [r7, #0]
2000358e:	4413      	add	r3, r2
20003590:	697a      	ldr	r2, [r7, #20]
20003592:	b2d2      	uxtb	r2, r2
20003594:	701a      	strb	r2, [r3, #0]
                }
                ++rx_idx;
20003596:	8bfb      	ldrh	r3, [r7, #30]
20003598:	f103 0301 	add.w	r3, r3, #1
2000359c:	83fb      	strh	r3, [r7, #30]
            }
            ++transfer_idx;
2000359e:	8b7b      	ldrh	r3, [r7, #26]
200035a0:	f103 0301 	add.w	r3, r3, #1
200035a4:	837b      	strh	r3, [r7, #26]
            --transit;
200035a6:	8cfb      	ldrh	r3, [r7, #38]	; 0x26
200035a8:	f103 33ff 	add.w	r3, r3, #4294967295
200035ac:	84fb      	strh	r3, [r7, #38]	; 0x26
        }

        tx_fifo_full = this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK;
200035ae:	68fb      	ldr	r3, [r7, #12]
200035b0:	681b      	ldr	r3, [r3, #0]
200035b2:	689b      	ldr	r3, [r3, #8]
200035b4:	f403 7380 	and.w	r3, r3, #256	; 0x100
200035b8:	62bb      	str	r3, [r7, #40]	; 0x28
        if(!tx_fifo_full)
200035ba:	6abb      	ldr	r3, [r7, #40]	; 0x28
200035bc:	2b00      	cmp	r3, #0
200035be:	d127      	bne.n	20003610 <MSS_SPI_transfer_block+0x218>
        {
            if(transit < RX_FIFO_SIZE)
200035c0:	8cfb      	ldrh	r3, [r7, #38]	; 0x26
200035c2:	2b03      	cmp	r3, #3
200035c4:	d824      	bhi.n	20003610 <MSS_SPI_transfer_block+0x218>
            {
                /* Send another byte. */
                if(tx_idx < cmd_byte_size)
200035c6:	8bba      	ldrh	r2, [r7, #28]
200035c8:	88fb      	ldrh	r3, [r7, #6]
200035ca:	429a      	cmp	r2, r3
200035cc:	d20f      	bcs.n	200035ee <MSS_SPI_transfer_block+0x1f6>
                {
                    this_spi->hw_reg->TX_DATA = cmd_buffer[tx_idx];
200035ce:	68fb      	ldr	r3, [r7, #12]
200035d0:	681b      	ldr	r3, [r3, #0]
200035d2:	8bb9      	ldrh	r1, [r7, #28]
200035d4:	68ba      	ldr	r2, [r7, #8]
200035d6:	440a      	add	r2, r1
200035d8:	7812      	ldrb	r2, [r2, #0]
200035da:	615a      	str	r2, [r3, #20]
                    ++tx_idx;
200035dc:	8bbb      	ldrh	r3, [r7, #28]
200035de:	f103 0301 	add.w	r3, r3, #1
200035e2:	83bb      	strh	r3, [r7, #28]
                    ++transit;
200035e4:	8cfb      	ldrh	r3, [r7, #38]	; 0x26
200035e6:	f103 0301 	add.w	r3, r3, #1
200035ea:	84fb      	strh	r3, [r7, #38]	; 0x26
200035ec:	e010      	b.n	20003610 <MSS_SPI_transfer_block+0x218>
                }
                else
                {
                    if(tx_idx < transfer_size)
200035ee:	8bba      	ldrh	r2, [r7, #28]
200035f0:	8efb      	ldrh	r3, [r7, #54]	; 0x36
200035f2:	429a      	cmp	r2, r3
200035f4:	d20c      	bcs.n	20003610 <MSS_SPI_transfer_block+0x218>
                    {
                        this_spi->hw_reg->TX_DATA = 0x00u;
200035f6:	68fb      	ldr	r3, [r7, #12]
200035f8:	681b      	ldr	r3, [r3, #0]
200035fa:	f04f 0200 	mov.w	r2, #0
200035fe:	615a      	str	r2, [r3, #20]
                        ++tx_idx;
20003600:	8bbb      	ldrh	r3, [r7, #28]
20003602:	f103 0301 	add.w	r3, r3, #1
20003606:	83bb      	strh	r3, [r7, #28]
                        ++transit;
20003608:	8cfb      	ldrh	r3, [r7, #38]	; 0x26
2000360a:	f103 0301 	add.w	r3, r3, #1
2000360e:	84fb      	strh	r3, [r7, #38]	; 0x26
        }
    }
    /* Perform the remainder of the transfer by sending a byte every time a byte
     * has been received. This should ensure that no Rx overflow can happen in
     * case of an interrupt occurs during this function. */
    while(transfer_idx < transfer_size)
20003610:	8b7a      	ldrh	r2, [r7, #26]
20003612:	8efb      	ldrh	r3, [r7, #54]	; 0x36
20003614:	429a      	cmp	r2, r3
20003616:	d3a2      	bcc.n	2000355e <MSS_SPI_transfer_block+0x166>
                    }
                }
            }
        }
    }
}
20003618:	f107 0738 	add.w	r7, r7, #56	; 0x38
2000361c:	46bd      	mov	sp, r7
2000361e:	bd80      	pop	{r7, pc}

20003620 <MSS_SPI_set_frame_rx_handler>:
void MSS_SPI_set_frame_rx_handler
(
    mss_spi_instance_t * this_spi,
    mss_spi_frame_rx_handler_t rx_handler
)
{
20003620:	b580      	push	{r7, lr}
20003622:	b084      	sub	sp, #16
20003624:	af00      	add	r7, sp, #0
20003626:	6078      	str	r0, [r7, #4]
20003628:	6039      	str	r1, [r7, #0]
    uint32_t tx_fifo_empty;
    
    ASSERT((this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1));
2000362a:	687a      	ldr	r2, [r7, #4]
2000362c:	f644 23f8 	movw	r3, #19192	; 0x4af8
20003630:	f2c2 0300 	movt	r3, #8192	; 0x2000
20003634:	429a      	cmp	r2, r3
20003636:	d007      	beq.n	20003648 <MSS_SPI_set_frame_rx_handler+0x28>
20003638:	687a      	ldr	r2, [r7, #4]
2000363a:	f644 237c 	movw	r3, #19068	; 0x4a7c
2000363e:	f2c2 0300 	movt	r3, #8192	; 0x2000
20003642:	429a      	cmp	r2, r3
20003644:	d000      	beq.n	20003648 <MSS_SPI_set_frame_rx_handler+0x28>
20003646:	be00      	bkpt	0x0000
    
    /* This function is only intended to be used with an SPI slave. */
    ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK) != CTRL_MASTER_MASK);
20003648:	687b      	ldr	r3, [r7, #4]
2000364a:	681b      	ldr	r3, [r3, #0]
2000364c:	681b      	ldr	r3, [r3, #0]
2000364e:	f003 0302 	and.w	r3, r3, #2
20003652:	2b00      	cmp	r3, #0
20003654:	d000      	beq.n	20003658 <MSS_SPI_set_frame_rx_handler+0x38>
20003656:	be00      	bkpt	0x0000
    
    /* Disable block Rx handler as they are mutually exclusive. */
    this_spi->block_rx_handler = 0u;
20003658:	687b      	ldr	r3, [r7, #4]
2000365a:	f04f 0200 	mov.w	r2, #0
2000365e:	679a      	str	r2, [r3, #120]	; 0x78
    
    /* Keep a copy of the pointer to the rx hnadler function. */
    this_spi->frame_rx_handler = rx_handler;
20003660:	687b      	ldr	r3, [r7, #4]
20003662:	683a      	ldr	r2, [r7, #0]
20003664:	671a      	str	r2, [r3, #112]	; 0x70
    
    /* Automatically fill the TX FIFO with zeroes if no slave tx frame set.*/
    tx_fifo_empty = this_spi->hw_reg->STATUS & TX_FIFO_EMPTY_MASK;
20003666:	687b      	ldr	r3, [r7, #4]
20003668:	681b      	ldr	r3, [r3, #0]
2000366a:	689b      	ldr	r3, [r3, #8]
2000366c:	f403 6380 	and.w	r3, r3, #1024	; 0x400
20003670:	60fb      	str	r3, [r7, #12]
    if(tx_fifo_empty)
20003672:	68fb      	ldr	r3, [r7, #12]
20003674:	2b00      	cmp	r3, #0
20003676:	d007      	beq.n	20003688 <MSS_SPI_set_frame_rx_handler+0x68>
    {
        this_spi->hw_reg->COMMAND |= AUTOFILL_MASK;
20003678:	687b      	ldr	r3, [r7, #4]
2000367a:	681b      	ldr	r3, [r3, #0]
2000367c:	687a      	ldr	r2, [r7, #4]
2000367e:	6812      	ldr	r2, [r2, #0]
20003680:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
20003682:	f042 0201 	orr.w	r2, r2, #1
20003686:	62da      	str	r2, [r3, #44]	; 0x2c
    }
    
    /* Enable Rx interrupt. */
    this_spi->hw_reg->CONTROL |= CTRL_RX_IRQ_EN_MASK;
20003688:	687b      	ldr	r3, [r7, #4]
2000368a:	681b      	ldr	r3, [r3, #0]
2000368c:	687a      	ldr	r2, [r7, #4]
2000368e:	6812      	ldr	r2, [r2, #0]
20003690:	6812      	ldr	r2, [r2, #0]
20003692:	f042 0210 	orr.w	r2, r2, #16
20003696:	601a      	str	r2, [r3, #0]
    NVIC_EnableIRQ( this_spi->irqn );
20003698:	687b      	ldr	r3, [r7, #4]
2000369a:	889b      	ldrh	r3, [r3, #4]
2000369c:	b21b      	sxth	r3, r3
2000369e:	4618      	mov	r0, r3
200036a0:	f7ff fb2c 	bl	20002cfc <NVIC_EnableIRQ>
}
200036a4:	f107 0710 	add.w	r7, r7, #16
200036a8:	46bd      	mov	sp, r7
200036aa:	bd80      	pop	{r7, pc}

200036ac <MSS_SPI_set_slave_tx_frame>:
void MSS_SPI_set_slave_tx_frame
(
    mss_spi_instance_t * this_spi,
    uint32_t frame_value
)
{
200036ac:	b580      	push	{r7, lr}
200036ae:	b082      	sub	sp, #8
200036b0:	af00      	add	r7, sp, #0
200036b2:	6078      	str	r0, [r7, #4]
200036b4:	6039      	str	r1, [r7, #0]
    ASSERT((this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1));
200036b6:	687a      	ldr	r2, [r7, #4]
200036b8:	f644 23f8 	movw	r3, #19192	; 0x4af8
200036bc:	f2c2 0300 	movt	r3, #8192	; 0x2000
200036c0:	429a      	cmp	r2, r3
200036c2:	d007      	beq.n	200036d4 <MSS_SPI_set_slave_tx_frame+0x28>
200036c4:	687a      	ldr	r2, [r7, #4]
200036c6:	f644 237c 	movw	r3, #19068	; 0x4a7c
200036ca:	f2c2 0300 	movt	r3, #8192	; 0x2000
200036ce:	429a      	cmp	r2, r3
200036d0:	d000      	beq.n	200036d4 <MSS_SPI_set_slave_tx_frame+0x28>
200036d2:	be00      	bkpt	0x0000

    /* This function is only intended to be used with an SPI slave. */
    ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK) != CTRL_MASTER_MASK);
200036d4:	687b      	ldr	r3, [r7, #4]
200036d6:	681b      	ldr	r3, [r3, #0]
200036d8:	681b      	ldr	r3, [r3, #0]
200036da:	f003 0302 	and.w	r3, r3, #2
200036de:	2b00      	cmp	r3, #0
200036e0:	d000      	beq.n	200036e4 <MSS_SPI_set_slave_tx_frame+0x38>
200036e2:	be00      	bkpt	0x0000
    
    /* Disable slave block tx buffer as it is mutually exclusive with frame
     * level handling. */    
    this_spi->slave_tx_buffer = 0u;
200036e4:	687b      	ldr	r3, [r7, #4]
200036e6:	f04f 0200 	mov.w	r2, #0
200036ea:	609a      	str	r2, [r3, #8]
    this_spi->slave_tx_size = 0u;
200036ec:	687b      	ldr	r3, [r7, #4]
200036ee:	f04f 0200 	mov.w	r2, #0
200036f2:	60da      	str	r2, [r3, #12]
    this_spi->slave_tx_idx = 0u;
200036f4:	687b      	ldr	r3, [r7, #4]
200036f6:	f04f 0200 	mov.w	r2, #0
200036fa:	611a      	str	r2, [r3, #16]
    
    /* Keep a copy of the slave tx frame value. */
    this_spi->slave_tx_frame = frame_value;
200036fc:	687b      	ldr	r3, [r7, #4]
200036fe:	683a      	ldr	r2, [r7, #0]
20003700:	675a      	str	r2, [r3, #116]	; 0x74
    
    /* Disable automatic fill of the TX FIFO with zeroes.*/
    this_spi->hw_reg->COMMAND &= ~AUTOFILL_MASK;
20003702:	687b      	ldr	r3, [r7, #4]
20003704:	681b      	ldr	r3, [r3, #0]
20003706:	687a      	ldr	r2, [r7, #4]
20003708:	6812      	ldr	r2, [r2, #0]
2000370a:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
2000370c:	f022 0201 	bic.w	r2, r2, #1
20003710:	62da      	str	r2, [r3, #44]	; 0x2c
    this_spi->hw_reg->COMMAND |= TX_FIFO_RESET_MASK;
20003712:	687b      	ldr	r3, [r7, #4]
20003714:	681b      	ldr	r3, [r3, #0]
20003716:	687a      	ldr	r2, [r7, #4]
20003718:	6812      	ldr	r2, [r2, #0]
2000371a:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
2000371c:	f042 0208 	orr.w	r2, r2, #8
20003720:	62da      	str	r2, [r3, #44]	; 0x2c
    
    /* Load frame into Tx data register. */
    this_spi->hw_reg->TX_DATA = this_spi->slave_tx_frame;
20003722:	687b      	ldr	r3, [r7, #4]
20003724:	681b      	ldr	r3, [r3, #0]
20003726:	687a      	ldr	r2, [r7, #4]
20003728:	6f52      	ldr	r2, [r2, #116]	; 0x74
2000372a:	615a      	str	r2, [r3, #20]
    
    /* Enable Tx Done interrupt in order to reload the slave Tx frame after each
     * time it has been sent. */
    this_spi->hw_reg->CONTROL |= CTRL_TX_IRQ_EN_MASK;
2000372c:	687b      	ldr	r3, [r7, #4]
2000372e:	681b      	ldr	r3, [r3, #0]
20003730:	687a      	ldr	r2, [r7, #4]
20003732:	6812      	ldr	r2, [r2, #0]
20003734:	6812      	ldr	r2, [r2, #0]
20003736:	f042 0220 	orr.w	r2, r2, #32
2000373a:	601a      	str	r2, [r3, #0]
    NVIC_EnableIRQ( this_spi->irqn );
2000373c:	687b      	ldr	r3, [r7, #4]
2000373e:	889b      	ldrh	r3, [r3, #4]
20003740:	b21b      	sxth	r3, r3
20003742:	4618      	mov	r0, r3
20003744:	f7ff fada 	bl	20002cfc <NVIC_EnableIRQ>
}
20003748:	f107 0708 	add.w	r7, r7, #8
2000374c:	46bd      	mov	sp, r7
2000374e:	bd80      	pop	{r7, pc}

20003750 <MSS_SPI_set_slave_block_buffers>:
    uint32_t tx_buff_size,
    uint8_t * rx_buffer,
    uint32_t rx_buff_size,
    mss_spi_block_rx_handler_t block_rx_handler
)
{
20003750:	b580      	push	{r7, lr}
20003752:	b086      	sub	sp, #24
20003754:	af00      	add	r7, sp, #0
20003756:	60f8      	str	r0, [r7, #12]
20003758:	60b9      	str	r1, [r7, #8]
2000375a:	607a      	str	r2, [r7, #4]
2000375c:	603b      	str	r3, [r7, #0]
    uint32_t frame_count;
    uint32_t tx_fifo_full;
    
    ASSERT((this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1));
2000375e:	68fa      	ldr	r2, [r7, #12]
20003760:	f644 23f8 	movw	r3, #19192	; 0x4af8
20003764:	f2c2 0300 	movt	r3, #8192	; 0x2000
20003768:	429a      	cmp	r2, r3
2000376a:	d007      	beq.n	2000377c <MSS_SPI_set_slave_block_buffers+0x2c>
2000376c:	68fa      	ldr	r2, [r7, #12]
2000376e:	f644 237c 	movw	r3, #19068	; 0x4a7c
20003772:	f2c2 0300 	movt	r3, #8192	; 0x2000
20003776:	429a      	cmp	r2, r3
20003778:	d000      	beq.n	2000377c <MSS_SPI_set_slave_block_buffers+0x2c>
2000377a:	be00      	bkpt	0x0000
    
    /* This function is only intended to be used with an SPI slave. */
    ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK) != CTRL_MASTER_MASK);
2000377c:	68fb      	ldr	r3, [r7, #12]
2000377e:	681b      	ldr	r3, [r3, #0]
20003780:	681b      	ldr	r3, [r3, #0]
20003782:	f003 0302 	and.w	r3, r3, #2
20003786:	2b00      	cmp	r3, #0
20003788:	d000      	beq.n	2000378c <MSS_SPI_set_slave_block_buffers+0x3c>
2000378a:	be00      	bkpt	0x0000
    
    /* Disable Rx frame handler as it is mutually exclusive with block rx handler. */
    this_spi->frame_rx_handler = 0u;
2000378c:	68fb      	ldr	r3, [r7, #12]
2000378e:	f04f 0200 	mov.w	r2, #0
20003792:	671a      	str	r2, [r3, #112]	; 0x70
    
    /* Keep a copy of the pointer to the block rx handler function. */
    this_spi->block_rx_handler = block_rx_handler;
20003794:	68fb      	ldr	r3, [r7, #12]
20003796:	6a7a      	ldr	r2, [r7, #36]	; 0x24
20003798:	679a      	str	r2, [r3, #120]	; 0x78
    
    this_spi->slave_rx_buffer = rx_buffer;
2000379a:	68fb      	ldr	r3, [r7, #12]
2000379c:	683a      	ldr	r2, [r7, #0]
2000379e:	625a      	str	r2, [r3, #36]	; 0x24
    this_spi->slave_rx_size = rx_buff_size;
200037a0:	68fb      	ldr	r3, [r7, #12]
200037a2:	6a3a      	ldr	r2, [r7, #32]
200037a4:	629a      	str	r2, [r3, #40]	; 0x28
    this_spi->slave_rx_idx = 0u;
200037a6:	68fb      	ldr	r3, [r7, #12]
200037a8:	f04f 0200 	mov.w	r2, #0
200037ac:	62da      	str	r2, [r3, #44]	; 0x2c
    
    /* Initialise the transmit state data. */
    this_spi->slave_tx_buffer = tx_buffer;
200037ae:	68fb      	ldr	r3, [r7, #12]
200037b0:	68ba      	ldr	r2, [r7, #8]
200037b2:	609a      	str	r2, [r3, #8]
    this_spi->slave_tx_size = tx_buff_size;
200037b4:	68fb      	ldr	r3, [r7, #12]
200037b6:	687a      	ldr	r2, [r7, #4]
200037b8:	60da      	str	r2, [r3, #12]
    this_spi->slave_tx_idx = 0u;
200037ba:	68fb      	ldr	r3, [r7, #12]
200037bc:	f04f 0200 	mov.w	r2, #0
200037c0:	611a      	str	r2, [r3, #16]

    /* Use the frame counter to control how often receive interrupts are generated. */
    frame_count = RX_IRQ_THRESHOLD;
200037c2:	f04f 0310 	mov.w	r3, #16
200037c6:	613b      	str	r3, [r7, #16]
    
    /**/
    this_spi->hw_reg->CONTROL &= ~CTRL_ENABLE_MASK;
200037c8:	68fb      	ldr	r3, [r7, #12]
200037ca:	681b      	ldr	r3, [r3, #0]
200037cc:	68fa      	ldr	r2, [r7, #12]
200037ce:	6812      	ldr	r2, [r2, #0]
200037d0:	6812      	ldr	r2, [r2, #0]
200037d2:	f022 0201 	bic.w	r2, r2, #1
200037d6:	601a      	str	r2, [r3, #0]
    this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK) | (frame_count << TXRXDFCOUNT_SHIFT);
200037d8:	68fb      	ldr	r3, [r7, #12]
200037da:	681a      	ldr	r2, [r3, #0]
200037dc:	68fb      	ldr	r3, [r7, #12]
200037de:	681b      	ldr	r3, [r3, #0]
200037e0:	6819      	ldr	r1, [r3, #0]
200037e2:	f240 03ff 	movw	r3, #255	; 0xff
200037e6:	f6cf 7300 	movt	r3, #65280	; 0xff00
200037ea:	ea01 0303 	and.w	r3, r1, r3
200037ee:	6939      	ldr	r1, [r7, #16]
200037f0:	ea4f 2101 	mov.w	r1, r1, lsl #8
200037f4:	ea43 0301 	orr.w	r3, r3, r1
200037f8:	6013      	str	r3, [r2, #0]
    this_spi->hw_reg->TXRXDF_SIZE = 8u;
200037fa:	68fb      	ldr	r3, [r7, #12]
200037fc:	681b      	ldr	r3, [r3, #0]
200037fe:	f04f 0208 	mov.w	r2, #8
20003802:	605a      	str	r2, [r3, #4]
    this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK;
20003804:	68fb      	ldr	r3, [r7, #12]
20003806:	681b      	ldr	r3, [r3, #0]
20003808:	68fa      	ldr	r2, [r7, #12]
2000380a:	6812      	ldr	r2, [r2, #0]
2000380c:	6812      	ldr	r2, [r2, #0]
2000380e:	f042 0201 	orr.w	r2, r2, #1
20003812:	601a      	str	r2, [r3, #0]
    
    /* Load the transmit FIFO. */
    tx_fifo_full = this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK;
20003814:	68fb      	ldr	r3, [r7, #12]
20003816:	681b      	ldr	r3, [r3, #0]
20003818:	689b      	ldr	r3, [r3, #8]
2000381a:	f403 7380 	and.w	r3, r3, #256	; 0x100
2000381e:	617b      	str	r3, [r7, #20]
    while(!tx_fifo_full && (this_spi->slave_tx_idx < this_spi->slave_tx_size))
20003820:	e014      	b.n	2000384c <MSS_SPI_set_slave_block_buffers+0xfc>
    {
        this_spi->hw_reg->TX_DATA = this_spi->slave_tx_buffer[this_spi->slave_tx_idx];
20003822:	68fb      	ldr	r3, [r7, #12]
20003824:	681b      	ldr	r3, [r3, #0]
20003826:	68fa      	ldr	r2, [r7, #12]
20003828:	6891      	ldr	r1, [r2, #8]
2000382a:	68fa      	ldr	r2, [r7, #12]
2000382c:	6912      	ldr	r2, [r2, #16]
2000382e:	440a      	add	r2, r1
20003830:	7812      	ldrb	r2, [r2, #0]
20003832:	615a      	str	r2, [r3, #20]
        ++this_spi->slave_tx_idx;
20003834:	68fb      	ldr	r3, [r7, #12]
20003836:	691b      	ldr	r3, [r3, #16]
20003838:	f103 0201 	add.w	r2, r3, #1
2000383c:	68fb      	ldr	r3, [r7, #12]
2000383e:	611a      	str	r2, [r3, #16]
        tx_fifo_full = this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK;
20003840:	68fb      	ldr	r3, [r7, #12]
20003842:	681b      	ldr	r3, [r3, #0]
20003844:	689b      	ldr	r3, [r3, #8]
20003846:	f403 7380 	and.w	r3, r3, #256	; 0x100
2000384a:	617b      	str	r3, [r7, #20]
    this_spi->hw_reg->TXRXDF_SIZE = 8u;
    this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK;
    
    /* Load the transmit FIFO. */
    tx_fifo_full = this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK;
    while(!tx_fifo_full && (this_spi->slave_tx_idx < this_spi->slave_tx_size))
2000384c:	697b      	ldr	r3, [r7, #20]
2000384e:	2b00      	cmp	r3, #0
20003850:	d105      	bne.n	2000385e <MSS_SPI_set_slave_block_buffers+0x10e>
20003852:	68fb      	ldr	r3, [r7, #12]
20003854:	691a      	ldr	r2, [r3, #16]
20003856:	68fb      	ldr	r3, [r7, #12]
20003858:	68db      	ldr	r3, [r3, #12]
2000385a:	429a      	cmp	r2, r3
2000385c:	d3e1      	bcc.n	20003822 <MSS_SPI_set_slave_block_buffers+0xd2>
        ++this_spi->slave_tx_idx;
        tx_fifo_full = this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK;
    }
    
    /* Enable Rx interrupt. */
    this_spi->hw_reg->CONTROL |= CTRL_RX_IRQ_EN_MASK;
2000385e:	68fb      	ldr	r3, [r7, #12]
20003860:	681b      	ldr	r3, [r3, #0]
20003862:	68fa      	ldr	r2, [r7, #12]
20003864:	6812      	ldr	r2, [r2, #0]
20003866:	6812      	ldr	r2, [r2, #0]
20003868:	f042 0210 	orr.w	r2, r2, #16
2000386c:	601a      	str	r2, [r3, #0]
    
    
    if(tx_buff_size > 0u)
2000386e:	687b      	ldr	r3, [r7, #4]
20003870:	2b00      	cmp	r3, #0
20003872:	d010      	beq.n	20003896 <MSS_SPI_set_slave_block_buffers+0x146>
    {
        this_spi->hw_reg->COMMAND &= ~AUTOFILL_MASK;
20003874:	68fb      	ldr	r3, [r7, #12]
20003876:	681b      	ldr	r3, [r3, #0]
20003878:	68fa      	ldr	r2, [r7, #12]
2000387a:	6812      	ldr	r2, [r2, #0]
2000387c:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
2000387e:	f022 0201 	bic.w	r2, r2, #1
20003882:	62da      	str	r2, [r3, #44]	; 0x2c
        this_spi->hw_reg->CONTROL |= CTRL_TX_IRQ_EN_MASK;
20003884:	68fb      	ldr	r3, [r7, #12]
20003886:	681b      	ldr	r3, [r3, #0]
20003888:	68fa      	ldr	r2, [r7, #12]
2000388a:	6812      	ldr	r2, [r2, #0]
2000388c:	6812      	ldr	r2, [r2, #0]
2000388e:	f042 0220 	orr.w	r2, r2, #32
20003892:	601a      	str	r2, [r3, #0]
20003894:	e007      	b.n	200038a6 <MSS_SPI_set_slave_block_buffers+0x156>
    }
    else
    {
        this_spi->hw_reg->COMMAND |= AUTOFILL_MASK;
20003896:	68fb      	ldr	r3, [r7, #12]
20003898:	681b      	ldr	r3, [r3, #0]
2000389a:	68fa      	ldr	r2, [r7, #12]
2000389c:	6812      	ldr	r2, [r2, #0]
2000389e:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
200038a0:	f042 0201 	orr.w	r2, r2, #1
200038a4:	62da      	str	r2, [r3, #44]	; 0x2c
    /*
     * Enable slave select release interrupt. The SSEND interrupt is used to
     * complete reading of the recieve FIFO and prepare the transmit FIFO for
     * the next transaction.
     */
    this_spi->hw_reg->CONTROL2 |= ENABLE_SSEND_IRQ_MASK;
200038a6:	68fb      	ldr	r3, [r7, #12]
200038a8:	681b      	ldr	r3, [r3, #0]
200038aa:	68fa      	ldr	r2, [r7, #12]
200038ac:	6812      	ldr	r2, [r2, #0]
200038ae:	6a92      	ldr	r2, [r2, #40]	; 0x28
200038b0:	f042 0220 	orr.w	r2, r2, #32
200038b4:	629a      	str	r2, [r3, #40]	; 0x28
    
    NVIC_EnableIRQ(this_spi->irqn);
200038b6:	68fb      	ldr	r3, [r7, #12]
200038b8:	889b      	ldrh	r3, [r3, #4]
200038ba:	b21b      	sxth	r3, r3
200038bc:	4618      	mov	r0, r3
200038be:	f7ff fa1d 	bl	20002cfc <NVIC_EnableIRQ>
}
200038c2:	f107 0718 	add.w	r7, r7, #24
200038c6:	46bd      	mov	sp, r7
200038c8:	bd80      	pop	{r7, pc}
200038ca:	bf00      	nop

200038cc <MSS_SPI_set_cmd_handler>:
(
    mss_spi_instance_t * this_spi,
    mss_spi_block_rx_handler_t cmd_handler,
    uint32_t cmd_size
)
{
200038cc:	b480      	push	{r7}
200038ce:	b085      	sub	sp, #20
200038d0:	af00      	add	r7, sp, #0
200038d2:	60f8      	str	r0, [r7, #12]
200038d4:	60b9      	str	r1, [r7, #8]
200038d6:	607a      	str	r2, [r7, #4]
    this_spi->cmd_handler = cmd_handler;
200038d8:	68fb      	ldr	r3, [r7, #12]
200038da:	68ba      	ldr	r2, [r7, #8]
200038dc:	621a      	str	r2, [r3, #32]
    this_spi->hw_reg->CMDSIZE = cmd_size;
200038de:	68fb      	ldr	r3, [r7, #12]
200038e0:	681b      	ldr	r3, [r3, #0]
200038e2:	687a      	ldr	r2, [r7, #4]
200038e4:	635a      	str	r2, [r3, #52]	; 0x34
    this_spi->hw_reg->CONTROL2 |= ENABLE_CMD_IRQ_MASK;
200038e6:	68fb      	ldr	r3, [r7, #12]
200038e8:	681b      	ldr	r3, [r3, #0]
200038ea:	68fa      	ldr	r2, [r7, #12]
200038ec:	6812      	ldr	r2, [r2, #0]
200038ee:	6a92      	ldr	r2, [r2, #40]	; 0x28
200038f0:	f042 0210 	orr.w	r2, r2, #16
200038f4:	629a      	str	r2, [r3, #40]	; 0x28
}
200038f6:	f107 0714 	add.w	r7, r7, #20
200038fa:	46bd      	mov	sp, r7
200038fc:	bc80      	pop	{r7}
200038fe:	4770      	bx	lr

20003900 <MSS_SPI_set_cmd_response>:
(
    mss_spi_instance_t * this_spi,
    const uint8_t * resp_tx_buffer,
    uint32_t resp_buff_size
)
{
20003900:	b580      	push	{r7, lr}
20003902:	b084      	sub	sp, #16
20003904:	af00      	add	r7, sp, #0
20003906:	60f8      	str	r0, [r7, #12]
20003908:	60b9      	str	r1, [r7, #8]
2000390a:	607a      	str	r2, [r7, #4]
    this_spi->resp_tx_buffer = resp_tx_buffer;
2000390c:	68fb      	ldr	r3, [r7, #12]
2000390e:	68ba      	ldr	r2, [r7, #8]
20003910:	615a      	str	r2, [r3, #20]
    this_spi->resp_buff_size = resp_buff_size;
20003912:	68fb      	ldr	r3, [r7, #12]
20003914:	687a      	ldr	r2, [r7, #4]
20003916:	619a      	str	r2, [r3, #24]
    this_spi->resp_buff_tx_idx = 0u;
20003918:	68fb      	ldr	r3, [r7, #12]
2000391a:	f04f 0200 	mov.w	r2, #0
2000391e:	61da      	str	r2, [r3, #28]
    
    fill_slave_tx_fifo(this_spi);
20003920:	68f8      	ldr	r0, [r7, #12]
20003922:	f000 f863 	bl	200039ec <fill_slave_tx_fifo>
}
20003926:	f107 0710 	add.w	r7, r7, #16
2000392a:	46bd      	mov	sp, r7
2000392c:	bd80      	pop	{r7, pc}
2000392e:	bf00      	nop

20003930 <MSS_SPI_enable>:
 */
void MSS_SPI_enable
(
    mss_spi_instance_t * this_spi
)
{
20003930:	b480      	push	{r7}
20003932:	b083      	sub	sp, #12
20003934:	af00      	add	r7, sp, #0
20003936:	6078      	str	r0, [r7, #4]
    this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK;
20003938:	687b      	ldr	r3, [r7, #4]
2000393a:	681b      	ldr	r3, [r3, #0]
2000393c:	687a      	ldr	r2, [r7, #4]
2000393e:	6812      	ldr	r2, [r2, #0]
20003940:	6812      	ldr	r2, [r2, #0]
20003942:	f042 0201 	orr.w	r2, r2, #1
20003946:	601a      	str	r2, [r3, #0]
}
20003948:	f107 070c 	add.w	r7, r7, #12
2000394c:	46bd      	mov	sp, r7
2000394e:	bc80      	pop	{r7}
20003950:	4770      	bx	lr
20003952:	bf00      	nop

20003954 <MSS_SPI_disable>:
 */
void MSS_SPI_disable
(
    mss_spi_instance_t * this_spi
)
{
20003954:	b480      	push	{r7}
20003956:	b083      	sub	sp, #12
20003958:	af00      	add	r7, sp, #0
2000395a:	6078      	str	r0, [r7, #4]
    this_spi->hw_reg->CONTROL &= ~CTRL_ENABLE_MASK;
2000395c:	687b      	ldr	r3, [r7, #4]
2000395e:	681b      	ldr	r3, [r3, #0]
20003960:	687a      	ldr	r2, [r7, #4]
20003962:	6812      	ldr	r2, [r2, #0]
20003964:	6812      	ldr	r2, [r2, #0]
20003966:	f022 0201 	bic.w	r2, r2, #1
2000396a:	601a      	str	r2, [r3, #0]
}
2000396c:	f107 070c 	add.w	r7, r7, #12
20003970:	46bd      	mov	sp, r7
20003972:	bc80      	pop	{r7}
20003974:	4770      	bx	lr
20003976:	bf00      	nop

20003978 <MSS_SPI_set_transfer_byte_count>:
void MSS_SPI_set_transfer_byte_count
(
    mss_spi_instance_t * this_spi,
    uint16_t byte_count
)
{
20003978:	b480      	push	{r7}
2000397a:	b083      	sub	sp, #12
2000397c:	af00      	add	r7, sp, #0
2000397e:	6078      	str	r0, [r7, #4]
20003980:	460b      	mov	r3, r1
20003982:	807b      	strh	r3, [r7, #2]
    this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK)
20003984:	687b      	ldr	r3, [r7, #4]
20003986:	6819      	ldr	r1, [r3, #0]
20003988:	687b      	ldr	r3, [r7, #4]
2000398a:	681b      	ldr	r3, [r3, #0]
2000398c:	681b      	ldr	r3, [r3, #0]
2000398e:	f240 02ff 	movw	r2, #255	; 0xff
20003992:	f6cf 7200 	movt	r2, #65280	; 0xff00
20003996:	ea03 0202 	and.w	r2, r3, r2
                                | (((uint32_t)byte_count << TXRXDFCOUNT_SHIFT) & TXRXDFCOUNT_MASK);
2000399a:	887b      	ldrh	r3, [r7, #2]
2000399c:	ea4f 2003 	mov.w	r0, r3, lsl #8
200039a0:	f64f 7300 	movw	r3, #65280	; 0xff00
200039a4:	f2c0 03ff 	movt	r3, #255	; 0xff
200039a8:	ea00 0303 	and.w	r3, r0, r3
(
    mss_spi_instance_t * this_spi,
    uint16_t byte_count
)
{
    this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK)
200039ac:	ea42 0303 	orr.w	r3, r2, r3
200039b0:	600b      	str	r3, [r1, #0]
                                | (((uint32_t)byte_count << TXRXDFCOUNT_SHIFT) & TXRXDFCOUNT_MASK);
                                
    this_spi->hw_reg->TXRXDF_SIZE = MSS_SPI_BLOCK_TRANSFER_FRAME_SIZE;
200039b2:	687b      	ldr	r3, [r7, #4]
200039b4:	681b      	ldr	r3, [r3, #0]
200039b6:	f04f 0208 	mov.w	r2, #8
200039ba:	605a      	str	r2, [r3, #4]
}
200039bc:	f107 070c 	add.w	r7, r7, #12
200039c0:	46bd      	mov	sp, r7
200039c2:	bc80      	pop	{r7}
200039c4:	4770      	bx	lr
200039c6:	bf00      	nop

200039c8 <MSS_SPI_tx_done>:
 */
uint32_t MSS_SPI_tx_done
(
    mss_spi_instance_t * this_spi
)
{
200039c8:	b480      	push	{r7}
200039ca:	b085      	sub	sp, #20
200039cc:	af00      	add	r7, sp, #0
200039ce:	6078      	str	r0, [r7, #4]
    uint32_t tx_done;
    
    tx_done = this_spi->hw_reg->STATUS & TX_DONE_MASK;
200039d0:	687b      	ldr	r3, [r7, #4]
200039d2:	681b      	ldr	r3, [r3, #0]
200039d4:	689b      	ldr	r3, [r3, #8]
200039d6:	f003 0301 	and.w	r3, r3, #1
200039da:	60fb      	str	r3, [r7, #12]
    
    return tx_done;
200039dc:	68fb      	ldr	r3, [r7, #12]
}
200039de:	4618      	mov	r0, r3
200039e0:	f107 0714 	add.w	r7, r7, #20
200039e4:	46bd      	mov	sp, r7
200039e6:	bc80      	pop	{r7}
200039e8:	4770      	bx	lr
200039ea:	bf00      	nop

200039ec <fill_slave_tx_fifo>:
 */
static void fill_slave_tx_fifo
(
    mss_spi_instance_t * this_spi
)
{
200039ec:	b480      	push	{r7}
200039ee:	b085      	sub	sp, #20
200039f0:	af00      	add	r7, sp, #0
200039f2:	6078      	str	r0, [r7, #4]
    uint32_t more_data = 1u;
200039f4:	f04f 0301 	mov.w	r3, #1
200039f8:	60bb      	str	r3, [r7, #8]
    uint32_t tx_fifo_full;
    
    tx_fifo_full = this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK;
200039fa:	687b      	ldr	r3, [r7, #4]
200039fc:	681b      	ldr	r3, [r3, #0]
200039fe:	689b      	ldr	r3, [r3, #8]
20003a00:	f403 7380 	and.w	r3, r3, #256	; 0x100
20003a04:	60fb      	str	r3, [r7, #12]
    
    while(!tx_fifo_full && more_data)
20003a06:	e034      	b.n	20003a72 <fill_slave_tx_fifo+0x86>
    {
        if(this_spi->slave_tx_idx < this_spi->slave_tx_size)
20003a08:	687b      	ldr	r3, [r7, #4]
20003a0a:	691a      	ldr	r2, [r3, #16]
20003a0c:	687b      	ldr	r3, [r7, #4]
20003a0e:	68db      	ldr	r3, [r3, #12]
20003a10:	429a      	cmp	r2, r3
20003a12:	d20f      	bcs.n	20003a34 <fill_slave_tx_fifo+0x48>
        {
            this_spi->hw_reg->TX_DATA = this_spi->slave_tx_buffer[this_spi->slave_tx_idx];
20003a14:	687b      	ldr	r3, [r7, #4]
20003a16:	681b      	ldr	r3, [r3, #0]
20003a18:	687a      	ldr	r2, [r7, #4]
20003a1a:	6891      	ldr	r1, [r2, #8]
20003a1c:	687a      	ldr	r2, [r7, #4]
20003a1e:	6912      	ldr	r2, [r2, #16]
20003a20:	440a      	add	r2, r1
20003a22:	7812      	ldrb	r2, [r2, #0]
20003a24:	615a      	str	r2, [r3, #20]
            ++this_spi->slave_tx_idx;
20003a26:	687b      	ldr	r3, [r7, #4]
20003a28:	691b      	ldr	r3, [r3, #16]
20003a2a:	f103 0201 	add.w	r2, r3, #1
20003a2e:	687b      	ldr	r3, [r7, #4]
20003a30:	611a      	str	r2, [r3, #16]
20003a32:	e018      	b.n	20003a66 <fill_slave_tx_fifo+0x7a>
        }
        else if(this_spi->resp_buff_tx_idx < this_spi->resp_buff_size)
20003a34:	687b      	ldr	r3, [r7, #4]
20003a36:	69da      	ldr	r2, [r3, #28]
20003a38:	687b      	ldr	r3, [r7, #4]
20003a3a:	699b      	ldr	r3, [r3, #24]
20003a3c:	429a      	cmp	r2, r3
20003a3e:	d20f      	bcs.n	20003a60 <fill_slave_tx_fifo+0x74>
        {
            this_spi->hw_reg->TX_DATA = this_spi->resp_tx_buffer[this_spi->resp_buff_tx_idx];
20003a40:	687b      	ldr	r3, [r7, #4]
20003a42:	681b      	ldr	r3, [r3, #0]
20003a44:	687a      	ldr	r2, [r7, #4]
20003a46:	6951      	ldr	r1, [r2, #20]
20003a48:	687a      	ldr	r2, [r7, #4]
20003a4a:	69d2      	ldr	r2, [r2, #28]
20003a4c:	440a      	add	r2, r1
20003a4e:	7812      	ldrb	r2, [r2, #0]
20003a50:	615a      	str	r2, [r3, #20]
            ++this_spi->resp_buff_tx_idx;
20003a52:	687b      	ldr	r3, [r7, #4]
20003a54:	69db      	ldr	r3, [r3, #28]
20003a56:	f103 0201 	add.w	r2, r3, #1
20003a5a:	687b      	ldr	r3, [r7, #4]
20003a5c:	61da      	str	r2, [r3, #28]
20003a5e:	e002      	b.n	20003a66 <fill_slave_tx_fifo+0x7a>
        }
        else
        {
            more_data = 0u;
20003a60:	f04f 0300 	mov.w	r3, #0
20003a64:	60bb      	str	r3, [r7, #8]
        }
        tx_fifo_full = this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK;
20003a66:	687b      	ldr	r3, [r7, #4]
20003a68:	681b      	ldr	r3, [r3, #0]
20003a6a:	689b      	ldr	r3, [r3, #8]
20003a6c:	f403 7380 	and.w	r3, r3, #256	; 0x100
20003a70:	60fb      	str	r3, [r7, #12]
    uint32_t more_data = 1u;
    uint32_t tx_fifo_full;
    
    tx_fifo_full = this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK;
    
    while(!tx_fifo_full && more_data)
20003a72:	68fb      	ldr	r3, [r7, #12]
20003a74:	2b00      	cmp	r3, #0
20003a76:	d102      	bne.n	20003a7e <fill_slave_tx_fifo+0x92>
20003a78:	68bb      	ldr	r3, [r7, #8]
20003a7a:	2b00      	cmp	r3, #0
20003a7c:	d1c4      	bne.n	20003a08 <fill_slave_tx_fifo+0x1c>
        {
            more_data = 0u;
        }
        tx_fifo_full = this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK;
    }
}
20003a7e:	f107 0714 	add.w	r7, r7, #20
20003a82:	46bd      	mov	sp, r7
20003a84:	bc80      	pop	{r7}
20003a86:	4770      	bx	lr

20003a88 <read_slave_rx_fifo>:
 */
static void read_slave_rx_fifo
(
    mss_spi_instance_t * this_spi
)
{
20003a88:	b580      	push	{r7, lr}
20003a8a:	b084      	sub	sp, #16
20003a8c:	af00      	add	r7, sp, #0
20003a8e:	6078      	str	r0, [r7, #4]
    uint32_t rx_frame;
    uint32_t rx_fifo_empty;
    
    if(this_spi->frame_rx_handler != 0u)
20003a90:	687b      	ldr	r3, [r7, #4]
20003a92:	6f1b      	ldr	r3, [r3, #112]	; 0x70
20003a94:	2b00      	cmp	r3, #0
20003a96:	d018      	beq.n	20003aca <read_slave_rx_fifo+0x42>
    {
        rx_fifo_empty = this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK;
20003a98:	687b      	ldr	r3, [r7, #4]
20003a9a:	681b      	ldr	r3, [r3, #0]
20003a9c:	689b      	ldr	r3, [r3, #8]
20003a9e:	f003 0340 	and.w	r3, r3, #64	; 0x40
20003aa2:	60fb      	str	r3, [r7, #12]
        
        while(!rx_fifo_empty)
20003aa4:	e00d      	b.n	20003ac2 <read_slave_rx_fifo+0x3a>
        {
            /* Single frame handling mode. */
            rx_frame = this_spi->hw_reg->RX_DATA;
20003aa6:	687b      	ldr	r3, [r7, #4]
20003aa8:	681b      	ldr	r3, [r3, #0]
20003aaa:	691b      	ldr	r3, [r3, #16]
20003aac:	60bb      	str	r3, [r7, #8]
            this_spi->frame_rx_handler( rx_frame );
20003aae:	687b      	ldr	r3, [r7, #4]
20003ab0:	6f1b      	ldr	r3, [r3, #112]	; 0x70
20003ab2:	68b8      	ldr	r0, [r7, #8]
20003ab4:	4798      	blx	r3
            rx_fifo_empty = this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK;
20003ab6:	687b      	ldr	r3, [r7, #4]
20003ab8:	681b      	ldr	r3, [r3, #0]
20003aba:	689b      	ldr	r3, [r3, #8]
20003abc:	f003 0340 	and.w	r3, r3, #64	; 0x40
20003ac0:	60fb      	str	r3, [r7, #12]
    
    if(this_spi->frame_rx_handler != 0u)
    {
        rx_fifo_empty = this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK;
        
        while(!rx_fifo_empty)
20003ac2:	68fb      	ldr	r3, [r7, #12]
20003ac4:	2b00      	cmp	r3, #0
20003ac6:	d0ee      	beq.n	20003aa6 <read_slave_rx_fifo+0x1e>
20003ac8:	e027      	b.n	20003b1a <read_slave_rx_fifo+0x92>
        }
    }
    else 
    {
        /* Block handling mode. */
        rx_fifo_empty = this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK;
20003aca:	687b      	ldr	r3, [r7, #4]
20003acc:	681b      	ldr	r3, [r3, #0]
20003ace:	689b      	ldr	r3, [r3, #8]
20003ad0:	f003 0340 	and.w	r3, r3, #64	; 0x40
20003ad4:	60fb      	str	r3, [r7, #12]
        
        while((!rx_fifo_empty) && (this_spi->slave_rx_idx < this_spi->slave_rx_size))
20003ad6:	e017      	b.n	20003b08 <read_slave_rx_fifo+0x80>
        {
            rx_frame = this_spi->hw_reg->RX_DATA;
20003ad8:	687b      	ldr	r3, [r7, #4]
20003ada:	681b      	ldr	r3, [r3, #0]
20003adc:	691b      	ldr	r3, [r3, #16]
20003ade:	60bb      	str	r3, [r7, #8]
            this_spi->slave_rx_buffer[this_spi->slave_rx_idx] = (uint8_t)rx_frame;
20003ae0:	687b      	ldr	r3, [r7, #4]
20003ae2:	6a5a      	ldr	r2, [r3, #36]	; 0x24
20003ae4:	687b      	ldr	r3, [r7, #4]
20003ae6:	6adb      	ldr	r3, [r3, #44]	; 0x2c
20003ae8:	4413      	add	r3, r2
20003aea:	68ba      	ldr	r2, [r7, #8]
20003aec:	b2d2      	uxtb	r2, r2
20003aee:	701a      	strb	r2, [r3, #0]
            ++this_spi->slave_rx_idx;
20003af0:	687b      	ldr	r3, [r7, #4]
20003af2:	6adb      	ldr	r3, [r3, #44]	; 0x2c
20003af4:	f103 0201 	add.w	r2, r3, #1
20003af8:	687b      	ldr	r3, [r7, #4]
20003afa:	62da      	str	r2, [r3, #44]	; 0x2c
            rx_fifo_empty = this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK;
20003afc:	687b      	ldr	r3, [r7, #4]
20003afe:	681b      	ldr	r3, [r3, #0]
20003b00:	689b      	ldr	r3, [r3, #8]
20003b02:	f003 0340 	and.w	r3, r3, #64	; 0x40
20003b06:	60fb      	str	r3, [r7, #12]
    else 
    {
        /* Block handling mode. */
        rx_fifo_empty = this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK;
        
        while((!rx_fifo_empty) && (this_spi->slave_rx_idx < this_spi->slave_rx_size))
20003b08:	68fb      	ldr	r3, [r7, #12]
20003b0a:	2b00      	cmp	r3, #0
20003b0c:	d105      	bne.n	20003b1a <read_slave_rx_fifo+0x92>
20003b0e:	687b      	ldr	r3, [r7, #4]
20003b10:	6ada      	ldr	r2, [r3, #44]	; 0x2c
20003b12:	687b      	ldr	r3, [r7, #4]
20003b14:	6a9b      	ldr	r3, [r3, #40]	; 0x28
20003b16:	429a      	cmp	r2, r3
20003b18:	d3de      	bcc.n	20003ad8 <read_slave_rx_fifo+0x50>
            this_spi->slave_rx_buffer[this_spi->slave_rx_idx] = (uint8_t)rx_frame;
            ++this_spi->slave_rx_idx;
            rx_fifo_empty = this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK;
        }
    }
}
20003b1a:	f107 0710 	add.w	r7, r7, #16
20003b1e:	46bd      	mov	sp, r7
20003b20:	bd80      	pop	{r7, pc}
20003b22:	bf00      	nop

20003b24 <mss_spi_isr>:
 */
static void mss_spi_isr
(
    mss_spi_instance_t * this_spi
)
{
20003b24:	b580      	push	{r7, lr}
20003b26:	b084      	sub	sp, #16
20003b28:	af00      	add	r7, sp, #0
20003b2a:	6078      	str	r0, [r7, #4]
    uint32_t tx_done;
    
    ASSERT((this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1));
20003b2c:	687a      	ldr	r2, [r7, #4]
20003b2e:	f644 23f8 	movw	r3, #19192	; 0x4af8
20003b32:	f2c2 0300 	movt	r3, #8192	; 0x2000
20003b36:	429a      	cmp	r2, r3
20003b38:	d007      	beq.n	20003b4a <mss_spi_isr+0x26>
20003b3a:	687a      	ldr	r2, [r7, #4]
20003b3c:	f644 237c 	movw	r3, #19068	; 0x4a7c
20003b40:	f2c2 0300 	movt	r3, #8192	; 0x2000
20003b44:	429a      	cmp	r2, r3
20003b46:	d000      	beq.n	20003b4a <mss_spi_isr+0x26>
20003b48:	be00      	bkpt	0x0000
  
    /* Handle receive. */
    if(this_spi->hw_reg->MIS & RXDONE_IRQ_MASK)
20003b4a:	687b      	ldr	r3, [r7, #4]
20003b4c:	681b      	ldr	r3, [r3, #0]
20003b4e:	6a1b      	ldr	r3, [r3, #32]
20003b50:	f003 0302 	and.w	r3, r3, #2
20003b54:	2b00      	cmp	r3, #0
20003b56:	d007      	beq.n	20003b68 <mss_spi_isr+0x44>
    {
        read_slave_rx_fifo(this_spi);
20003b58:	6878      	ldr	r0, [r7, #4]
20003b5a:	f7ff ff95 	bl	20003a88 <read_slave_rx_fifo>
        this_spi->hw_reg->IRQ_CLEAR = RXDONE_IRQ_MASK;
20003b5e:	687b      	ldr	r3, [r7, #4]
20003b60:	681b      	ldr	r3, [r3, #0]
20003b62:	f04f 0202 	mov.w	r2, #2
20003b66:	60da      	str	r2, [r3, #12]
    }
    
    /* Handle transmit. */
    tx_done = this_spi->hw_reg->MIS & TXDONE_IRQ_MASK;
20003b68:	687b      	ldr	r3, [r7, #4]
20003b6a:	681b      	ldr	r3, [r3, #0]
20003b6c:	6a1b      	ldr	r3, [r3, #32]
20003b6e:	f003 0301 	and.w	r3, r3, #1
20003b72:	60bb      	str	r3, [r7, #8]
    if(tx_done)
20003b74:	68bb      	ldr	r3, [r7, #8]
20003b76:	2b00      	cmp	r3, #0
20003b78:	d00d      	beq.n	20003b96 <mss_spi_isr+0x72>
    {
        if(0u == this_spi->slave_tx_buffer)
20003b7a:	687b      	ldr	r3, [r7, #4]
20003b7c:	689b      	ldr	r3, [r3, #8]
20003b7e:	2b00      	cmp	r3, #0
20003b80:	d104      	bne.n	20003b8c <mss_spi_isr+0x68>
        {
            /* Reload slave tx frame into Tx data register. */
            this_spi->hw_reg->TX_DATA = this_spi->slave_tx_frame;
20003b82:	687b      	ldr	r3, [r7, #4]
20003b84:	681b      	ldr	r3, [r3, #0]
20003b86:	687a      	ldr	r2, [r7, #4]
20003b88:	6f52      	ldr	r2, [r2, #116]	; 0x74
20003b8a:	615a      	str	r2, [r3, #20]
        }
        this_spi->hw_reg->IRQ_CLEAR = TXDONE_IRQ_MASK;
20003b8c:	687b      	ldr	r3, [r7, #4]
20003b8e:	681b      	ldr	r3, [r3, #0]
20003b90:	f04f 0201 	mov.w	r2, #1
20003b94:	60da      	str	r2, [r3, #12]
    }
    
    /* Handle command interrupt. */
    if(this_spi->hw_reg->MIS & CMD_IRQ_MASK)
20003b96:	687b      	ldr	r3, [r7, #4]
20003b98:	681b      	ldr	r3, [r3, #0]
20003b9a:	6a1b      	ldr	r3, [r3, #32]
20003b9c:	f003 0310 	and.w	r3, r3, #16
20003ba0:	2b00      	cmp	r3, #0
20003ba2:	d014      	beq.n	20003bce <mss_spi_isr+0xaa>
    {
        read_slave_rx_fifo(this_spi);
20003ba4:	6878      	ldr	r0, [r7, #4]
20003ba6:	f7ff ff6f 	bl	20003a88 <read_slave_rx_fifo>
        
        /*
         * Call the command handler if one exists.
         */
        if(this_spi->cmd_handler != 0u)
20003baa:	687b      	ldr	r3, [r7, #4]
20003bac:	6a1b      	ldr	r3, [r3, #32]
20003bae:	2b00      	cmp	r3, #0
20003bb0:	d008      	beq.n	20003bc4 <mss_spi_isr+0xa0>
        {
            (*this_spi->cmd_handler)(this_spi->slave_rx_buffer, this_spi->slave_rx_idx);
20003bb2:	687b      	ldr	r3, [r7, #4]
20003bb4:	6a1b      	ldr	r3, [r3, #32]
20003bb6:	687a      	ldr	r2, [r7, #4]
20003bb8:	6a51      	ldr	r1, [r2, #36]	; 0x24
20003bba:	687a      	ldr	r2, [r7, #4]
20003bbc:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
20003bbe:	4608      	mov	r0, r1
20003bc0:	4611      	mov	r1, r2
20003bc2:	4798      	blx	r3
        }
        
        this_spi->hw_reg->IRQ_CLEAR = CMD_IRQ_MASK;
20003bc4:	687b      	ldr	r3, [r7, #4]
20003bc6:	681b      	ldr	r3, [r3, #0]
20003bc8:	f04f 0210 	mov.w	r2, #16
20003bcc:	60da      	str	r2, [r3, #12]
    }
    
    /* Handle slave select becoming de-asserted. */
    if(this_spi->hw_reg->MIS & SSEND_IRQ_MASK)
20003bce:	687b      	ldr	r3, [r7, #4]
20003bd0:	681b      	ldr	r3, [r3, #0]
20003bd2:	6a1b      	ldr	r3, [r3, #32]
20003bd4:	f003 0320 	and.w	r3, r3, #32
20003bd8:	2b00      	cmp	r3, #0
20003bda:	d028      	beq.n	20003c2e <mss_spi_isr+0x10a>
    {
        uint32_t rx_size;
        
        read_slave_rx_fifo(this_spi);
20003bdc:	6878      	ldr	r0, [r7, #4]
20003bde:	f7ff ff53 	bl	20003a88 <read_slave_rx_fifo>
        rx_size = this_spi->slave_rx_idx;
20003be2:	687b      	ldr	r3, [r7, #4]
20003be4:	6adb      	ldr	r3, [r3, #44]	; 0x2c
20003be6:	60fb      	str	r3, [r7, #12]
        /* 
         * Reset the transmit index to 0 to restart transmit at the start of the
         * transmit buffer in the next transaction. This also requires flushing
         * the Tx FIFO and refilling it with the start of Tx data buffer.
         */
        this_spi->slave_tx_idx = 0u;
20003be8:	687b      	ldr	r3, [r7, #4]
20003bea:	f04f 0200 	mov.w	r2, #0
20003bee:	611a      	str	r2, [r3, #16]
        this_spi->hw_reg->COMMAND |= (TX_FIFO_RESET_MASK | RX_FIFO_RESET_MASK);
20003bf0:	687b      	ldr	r3, [r7, #4]
20003bf2:	681b      	ldr	r3, [r3, #0]
20003bf4:	687a      	ldr	r2, [r7, #4]
20003bf6:	6812      	ldr	r2, [r2, #0]
20003bf8:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
20003bfa:	f042 020c 	orr.w	r2, r2, #12
20003bfe:	62da      	str	r2, [r3, #44]	; 0x2c
        fill_slave_tx_fifo(this_spi);
20003c00:	6878      	ldr	r0, [r7, #4]
20003c02:	f7ff fef3 	bl	200039ec <fill_slave_tx_fifo>
        
        /* Prepare to receive next packet. */
        this_spi->slave_rx_idx = 0u;
20003c06:	687b      	ldr	r3, [r7, #4]
20003c08:	f04f 0200 	mov.w	r2, #0
20003c0c:	62da      	str	r2, [r3, #44]	; 0x2c
        
        /*
         * Call the receive handler if one exists.
         */
        if(this_spi->block_rx_handler != 0u)
20003c0e:	687b      	ldr	r3, [r7, #4]
20003c10:	6f9b      	ldr	r3, [r3, #120]	; 0x78
20003c12:	2b00      	cmp	r3, #0
20003c14:	d006      	beq.n	20003c24 <mss_spi_isr+0x100>
        {
            (*this_spi->block_rx_handler)(this_spi->slave_rx_buffer, rx_size);
20003c16:	687b      	ldr	r3, [r7, #4]
20003c18:	6f9b      	ldr	r3, [r3, #120]	; 0x78
20003c1a:	687a      	ldr	r2, [r7, #4]
20003c1c:	6a52      	ldr	r2, [r2, #36]	; 0x24
20003c1e:	4610      	mov	r0, r2
20003c20:	68f9      	ldr	r1, [r7, #12]
20003c22:	4798      	blx	r3
        }
        
        this_spi->hw_reg->IRQ_CLEAR = SSEND_IRQ_MASK;
20003c24:	687b      	ldr	r3, [r7, #4]
20003c26:	681b      	ldr	r3, [r3, #0]
20003c28:	f04f 0220 	mov.w	r2, #32
20003c2c:	60da      	str	r2, [r3, #12]
    }
}
20003c2e:	f107 0710 	add.w	r7, r7, #16
20003c32:	46bd      	mov	sp, r7
20003c34:	bd80      	pop	{r7, pc}
20003c36:	bf00      	nop

20003c38 <SPI0_IRQHandler>:
#if defined(__GNUC__)
__attribute__((__interrupt__)) void SPI0_IRQHandler(void)
#else
void SPI0_IRQHandler( void )
#endif
{
20003c38:	4668      	mov	r0, sp
20003c3a:	f020 0107 	bic.w	r1, r0, #7
20003c3e:	468d      	mov	sp, r1
20003c40:	b589      	push	{r0, r3, r7, lr}
20003c42:	af00      	add	r7, sp, #0
    mss_spi_isr(&g_mss_spi0);
20003c44:	f644 20f8 	movw	r0, #19192	; 0x4af8
20003c48:	f2c2 0000 	movt	r0, #8192	; 0x2000
20003c4c:	f7ff ff6a 	bl	20003b24 <mss_spi_isr>
    NVIC_ClearPendingIRQ(SPI0_IRQn);
20003c50:	f04f 000c 	mov.w	r0, #12
20003c54:	f7ff f86e 	bl	20002d34 <NVIC_ClearPendingIRQ>
}
20003c58:	46bd      	mov	sp, r7
20003c5a:	e8bd 4089 	ldmia.w	sp!, {r0, r3, r7, lr}
20003c5e:	4685      	mov	sp, r0
20003c60:	4770      	bx	lr
20003c62:	bf00      	nop

20003c64 <SPI1_IRQHandler>:
#if defined(__GNUC__)
__attribute__((__interrupt__)) void SPI1_IRQHandler(void)
#else
void SPI1_IRQHandler(void)
#endif
{
20003c64:	4668      	mov	r0, sp
20003c66:	f020 0107 	bic.w	r1, r0, #7
20003c6a:	468d      	mov	sp, r1
20003c6c:	b589      	push	{r0, r3, r7, lr}
20003c6e:	af00      	add	r7, sp, #0
    mss_spi_isr(&g_mss_spi1);
20003c70:	f644 207c 	movw	r0, #19068	; 0x4a7c
20003c74:	f2c2 0000 	movt	r0, #8192	; 0x2000
20003c78:	f7ff ff54 	bl	20003b24 <mss_spi_isr>
    NVIC_ClearPendingIRQ(SPI1_IRQn);
20003c7c:	f04f 000d 	mov.w	r0, #13
20003c80:	f7ff f858 	bl	20002d34 <NVIC_ClearPendingIRQ>
}
20003c84:	46bd      	mov	sp, r7
20003c86:	e8bd 4089 	ldmia.w	sp!, {r0, r3, r7, lr}
20003c8a:	4685      	mov	sp, r0
20003c8c:	4770      	bx	lr
20003c8e:	bf00      	nop

20003c90 <NVIC_EnableIRQ>:
 *
 * Enable a device specific interupt in the NVIC interrupt controller.
 * The interrupt number cannot be a negative value.
 */
static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
20003c90:	b480      	push	{r7}
20003c92:	b083      	sub	sp, #12
20003c94:	af00      	add	r7, sp, #0
20003c96:	4603      	mov	r3, r0
20003c98:	80fb      	strh	r3, [r7, #6]
  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
20003c9a:	f24e 1300 	movw	r3, #57600	; 0xe100
20003c9e:	f2ce 0300 	movt	r3, #57344	; 0xe000
20003ca2:	f9b7 2006 	ldrsh.w	r2, [r7, #6]
20003ca6:	ea4f 1252 	mov.w	r2, r2, lsr #5
20003caa:	88f9      	ldrh	r1, [r7, #6]
20003cac:	f001 011f 	and.w	r1, r1, #31
20003cb0:	f04f 0001 	mov.w	r0, #1
20003cb4:	fa00 f101 	lsl.w	r1, r0, r1
20003cb8:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
}
20003cbc:	f107 070c 	add.w	r7, r7, #12
20003cc0:	46bd      	mov	sp, r7
20003cc2:	bc80      	pop	{r7}
20003cc4:	4770      	bx	lr
20003cc6:	bf00      	nop

20003cc8 <NVIC_ClearPendingIRQ>:
 *
 * Clear the pending bit for the specified interrupt. 
 * The interrupt number cannot be a negative value.
 */
static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
20003cc8:	b480      	push	{r7}
20003cca:	b083      	sub	sp, #12
20003ccc:	af00      	add	r7, sp, #0
20003cce:	4603      	mov	r3, r0
20003cd0:	80fb      	strh	r3, [r7, #6]
  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
20003cd2:	f24e 1300 	movw	r3, #57600	; 0xe100
20003cd6:	f2ce 0300 	movt	r3, #57344	; 0xe000
20003cda:	f9b7 2006 	ldrsh.w	r2, [r7, #6]
20003cde:	ea4f 1252 	mov.w	r2, r2, lsr #5
20003ce2:	88f9      	ldrh	r1, [r7, #6]
20003ce4:	f001 011f 	and.w	r1, r1, #31
20003ce8:	f04f 0001 	mov.w	r0, #1
20003cec:	fa00 f101 	lsl.w	r1, r0, r1
20003cf0:	f102 0260 	add.w	r2, r2, #96	; 0x60
20003cf4:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
}
20003cf8:	f107 070c 	add.w	r7, r7, #12
20003cfc:	46bd      	mov	sp, r7
20003cfe:	bc80      	pop	{r7}
20003d00:	4770      	bx	lr
20003d02:	bf00      	nop

20003d04 <PDMA_init>:

/***************************************************************************//**
 * See mss_pdma.h for description of this function.
 */
void PDMA_init( void )
{
20003d04:	b580      	push	{r7, lr}
20003d06:	b082      	sub	sp, #8
20003d08:	af00      	add	r7, sp, #0
    int32_t i;
    
    /* Enable PDMA master access to comms matrix. */
    SYSREG->AHB_MATRIX_CR |= PDMA_MASTER_ENABLE;
20003d0a:	f242 0300 	movw	r3, #8192	; 0x2000
20003d0e:	f2ce 0304 	movt	r3, #57348	; 0xe004
20003d12:	f242 0200 	movw	r2, #8192	; 0x2000
20003d16:	f2ce 0204 	movt	r2, #57348	; 0xe004
20003d1a:	6992      	ldr	r2, [r2, #24]
20003d1c:	f042 0204 	orr.w	r2, r2, #4
20003d20:	619a      	str	r2, [r3, #24]
    
    /* Reset PDMA block. */
    SYSREG->SOFT_RST_CR |= PDMA_SOFT_RESET;
20003d22:	f242 0300 	movw	r3, #8192	; 0x2000
20003d26:	f2ce 0304 	movt	r3, #57348	; 0xe004
20003d2a:	f242 0200 	movw	r2, #8192	; 0x2000
20003d2e:	f2ce 0204 	movt	r2, #57348	; 0xe004
20003d32:	6b12      	ldr	r2, [r2, #48]	; 0x30
20003d34:	f042 0220 	orr.w	r2, r2, #32
20003d38:	631a      	str	r2, [r3, #48]	; 0x30
    
    /* Clear any previously pended MSS PDMA interrupt */
    NVIC_ClearPendingIRQ( DMA_IRQn );
20003d3a:	f04f 0009 	mov.w	r0, #9
20003d3e:	f7ff ffc3 	bl	20003cc8 <NVIC_ClearPendingIRQ>
        
    /* Take PDMA controller out of reset*/
    SYSREG->SOFT_RST_CR &= ~PDMA_SOFT_RESET;
20003d42:	f242 0300 	movw	r3, #8192	; 0x2000
20003d46:	f2ce 0304 	movt	r3, #57348	; 0xe004
20003d4a:	f242 0200 	movw	r2, #8192	; 0x2000
20003d4e:	f2ce 0204 	movt	r2, #57348	; 0xe004
20003d52:	6b12      	ldr	r2, [r2, #48]	; 0x30
20003d54:	f022 0220 	bic.w	r2, r2, #32
20003d58:	631a      	str	r2, [r3, #48]	; 0x30
    
    /* Initialize channels state information. */
    for ( i = 0; i < NB_OF_PDMA_CHANNELS; ++i )
20003d5a:	f04f 0300 	mov.w	r3, #0
20003d5e:	607b      	str	r3, [r7, #4]
20003d60:	e024      	b.n	20003dac <PDMA_init+0xa8>
    {
        g_pdma_next_channel[i] = NEXT_CHANNEL_A;
20003d62:	687a      	ldr	r2, [r7, #4]
20003d64:	f644 13f4 	movw	r3, #18932	; 0x49f4
20003d68:	f2c2 0300 	movt	r3, #8192	; 0x2000
20003d6c:	f04f 0100 	mov.w	r1, #0
20003d70:	5499      	strb	r1, [r3, r2]
        g_pdma_started_a[i] = CHANNEL_STOPPED;
20003d72:	687a      	ldr	r2, [r7, #4]
20003d74:	f644 13fc 	movw	r3, #18940	; 0x49fc
20003d78:	f2c2 0300 	movt	r3, #8192	; 0x2000
20003d7c:	f04f 0100 	mov.w	r1, #0
20003d80:	5499      	strb	r1, [r3, r2]
        g_pdma_started_b[i] = CHANNEL_STOPPED;
20003d82:	687a      	ldr	r2, [r7, #4]
20003d84:	f644 2304 	movw	r3, #18948	; 0x4a04
20003d88:	f2c2 0300 	movt	r3, #8192	; 0x2000
20003d8c:	f04f 0100 	mov.w	r1, #0
20003d90:	5499      	strb	r1, [r3, r2]
        g_pdma_isr_table[i] = 0;
20003d92:	687a      	ldr	r2, [r7, #4]
20003d94:	f644 230c 	movw	r3, #18956	; 0x4a0c
20003d98:	f2c2 0300 	movt	r3, #8192	; 0x2000
20003d9c:	f04f 0100 	mov.w	r1, #0
20003da0:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
        
    /* Take PDMA controller out of reset*/
    SYSREG->SOFT_RST_CR &= ~PDMA_SOFT_RESET;
    
    /* Initialize channels state information. */
    for ( i = 0; i < NB_OF_PDMA_CHANNELS; ++i )
20003da4:	687b      	ldr	r3, [r7, #4]
20003da6:	f103 0301 	add.w	r3, r3, #1
20003daa:	607b      	str	r3, [r7, #4]
20003dac:	687b      	ldr	r3, [r7, #4]
20003dae:	2b07      	cmp	r3, #7
20003db0:	ddd7      	ble.n	20003d62 <PDMA_init+0x5e>
        g_pdma_next_channel[i] = NEXT_CHANNEL_A;
        g_pdma_started_a[i] = CHANNEL_STOPPED;
        g_pdma_started_b[i] = CHANNEL_STOPPED;
        g_pdma_isr_table[i] = 0;
    }
}
20003db2:	f107 0708 	add.w	r7, r7, #8
20003db6:	46bd      	mov	sp, r7
20003db8:	bd80      	pop	{r7, pc}
20003dba:	bf00      	nop

20003dbc <PDMA_configure>:
    pdma_channel_id_t channel_id,
    pdma_src_dest_t src_dest,
    uint32_t channel_cfg,
    uint8_t write_adjust
)
{
20003dbc:	b480      	push	{r7}
20003dbe:	b085      	sub	sp, #20
20003dc0:	af00      	add	r7, sp, #0
20003dc2:	60ba      	str	r2, [r7, #8]
20003dc4:	4602      	mov	r2, r0
20003dc6:	73fa      	strb	r2, [r7, #15]
20003dc8:	460a      	mov	r2, r1
20003dca:	73ba      	strb	r2, [r7, #14]
20003dcc:	71fb      	strb	r3, [r7, #7]
    /* Reset the channel. */
    PDMA->CHANNEL[channel_id].CRTL |= CHANNEL_RESET_MASK;
20003dce:	f244 0300 	movw	r3, #16384	; 0x4000
20003dd2:	f2c4 0300 	movt	r3, #16384	; 0x4000
20003dd6:	7bf9      	ldrb	r1, [r7, #15]
20003dd8:	f244 0200 	movw	r2, #16384	; 0x4000
20003ddc:	f2c4 0200 	movt	r2, #16384	; 0x4000
20003de0:	7bf8      	ldrb	r0, [r7, #15]
20003de2:	f100 0001 	add.w	r0, r0, #1
20003de6:	ea4f 1040 	mov.w	r0, r0, lsl #5
20003dea:	4402      	add	r2, r0
20003dec:	6812      	ldr	r2, [r2, #0]
20003dee:	f042 0220 	orr.w	r2, r2, #32
20003df2:	f101 0101 	add.w	r1, r1, #1
20003df6:	ea4f 1141 	mov.w	r1, r1, lsl #5
20003dfa:	440b      	add	r3, r1
20003dfc:	601a      	str	r2, [r3, #0]
    PDMA->CHANNEL[channel_id].CRTL &= ~CHANNEL_RESET_MASK;
20003dfe:	f244 0300 	movw	r3, #16384	; 0x4000
20003e02:	f2c4 0300 	movt	r3, #16384	; 0x4000
20003e06:	7bf9      	ldrb	r1, [r7, #15]
20003e08:	f244 0200 	movw	r2, #16384	; 0x4000
20003e0c:	f2c4 0200 	movt	r2, #16384	; 0x4000
20003e10:	7bf8      	ldrb	r0, [r7, #15]
20003e12:	f100 0001 	add.w	r0, r0, #1
20003e16:	ea4f 1040 	mov.w	r0, r0, lsl #5
20003e1a:	4402      	add	r2, r0
20003e1c:	6812      	ldr	r2, [r2, #0]
20003e1e:	f022 0220 	bic.w	r2, r2, #32
20003e22:	f101 0101 	add.w	r1, r1, #1
20003e26:	ea4f 1141 	mov.w	r1, r1, lsl #5
20003e2a:	440b      	add	r3, r1
20003e2c:	601a      	str	r2, [r3, #0]

    /* Configure PDMA channel's data source and destination. */
    if ( src_dest != PDMA_MEM_TO_MEM )
20003e2e:	7bbb      	ldrb	r3, [r7, #14]
20003e30:	2b0e      	cmp	r3, #14
20003e32:	d01f      	beq.n	20003e74 <PDMA_configure+0xb8>
    {
        PDMA->CHANNEL[channel_id].CRTL |= src_dest_to_ctrl_reg_lut[src_dest];
20003e34:	f244 0300 	movw	r3, #16384	; 0x4000
20003e38:	f2c4 0300 	movt	r3, #16384	; 0x4000
20003e3c:	7bf9      	ldrb	r1, [r7, #15]
20003e3e:	f244 0200 	movw	r2, #16384	; 0x4000
20003e42:	f2c4 0200 	movt	r2, #16384	; 0x4000
20003e46:	7bf8      	ldrb	r0, [r7, #15]
20003e48:	f100 0001 	add.w	r0, r0, #1
20003e4c:	ea4f 1040 	mov.w	r0, r0, lsl #5
20003e50:	4402      	add	r2, r0
20003e52:	6810      	ldr	r0, [r2, #0]
20003e54:	f897 c00e 	ldrb.w	ip, [r7, #14]
20003e58:	f644 024c 	movw	r2, #18508	; 0x484c
20003e5c:	f2c2 0200 	movt	r2, #8192	; 0x2000
20003e60:	f852 202c 	ldr.w	r2, [r2, ip, lsl #2]
20003e64:	ea40 0202 	orr.w	r2, r0, r2
20003e68:	f101 0101 	add.w	r1, r1, #1
20003e6c:	ea4f 1141 	mov.w	r1, r1, lsl #5
20003e70:	440b      	add	r3, r1
20003e72:	601a      	str	r2, [r3, #0]
    }
    
    /* Configure PDMA channel trnasfer size, priority, source and destination address increment. */
    PDMA->CHANNEL[channel_id].CRTL |= channel_cfg;
20003e74:	f244 0300 	movw	r3, #16384	; 0x4000
20003e78:	f2c4 0300 	movt	r3, #16384	; 0x4000
20003e7c:	7bf9      	ldrb	r1, [r7, #15]
20003e7e:	f244 0200 	movw	r2, #16384	; 0x4000
20003e82:	f2c4 0200 	movt	r2, #16384	; 0x4000
20003e86:	7bf8      	ldrb	r0, [r7, #15]
20003e88:	f100 0001 	add.w	r0, r0, #1
20003e8c:	ea4f 1040 	mov.w	r0, r0, lsl #5
20003e90:	4402      	add	r2, r0
20003e92:	6810      	ldr	r0, [r2, #0]
20003e94:	68ba      	ldr	r2, [r7, #8]
20003e96:	ea40 0202 	orr.w	r2, r0, r2
20003e9a:	f101 0101 	add.w	r1, r1, #1
20003e9e:	ea4f 1141 	mov.w	r1, r1, lsl #5
20003ea2:	440b      	add	r3, r1
20003ea4:	601a      	str	r2, [r3, #0]

    /* Posted write adjust. */
    PDMA->CHANNEL[channel_id].CRTL |= ((uint32_t)write_adjust << CHANNEL_N_POSTED_WRITE_ADJUST_SHIFT);
20003ea6:	f244 0300 	movw	r3, #16384	; 0x4000
20003eaa:	f2c4 0300 	movt	r3, #16384	; 0x4000
20003eae:	7bf9      	ldrb	r1, [r7, #15]
20003eb0:	f244 0200 	movw	r2, #16384	; 0x4000
20003eb4:	f2c4 0200 	movt	r2, #16384	; 0x4000
20003eb8:	7bf8      	ldrb	r0, [r7, #15]
20003eba:	f100 0001 	add.w	r0, r0, #1
20003ebe:	ea4f 1040 	mov.w	r0, r0, lsl #5
20003ec2:	4402      	add	r2, r0
20003ec4:	6810      	ldr	r0, [r2, #0]
20003ec6:	79fa      	ldrb	r2, [r7, #7]
20003ec8:	ea4f 3282 	mov.w	r2, r2, lsl #14
20003ecc:	ea40 0202 	orr.w	r2, r0, r2
20003ed0:	f101 0101 	add.w	r1, r1, #1
20003ed4:	ea4f 1141 	mov.w	r1, r1, lsl #5
20003ed8:	440b      	add	r3, r1
20003eda:	601a      	str	r2, [r3, #0]
}
20003edc:	f107 0714 	add.w	r7, r7, #20
20003ee0:	46bd      	mov	sp, r7
20003ee2:	bc80      	pop	{r7}
20003ee4:	4770      	bx	lr
20003ee6:	bf00      	nop

20003ee8 <PDMA_start>:
    pdma_channel_id_t channel_id,
    uint32_t src_addr,
    uint32_t dest_addr,
    uint16_t transfer_count
)
{
20003ee8:	b480      	push	{r7}
20003eea:	b085      	sub	sp, #20
20003eec:	af00      	add	r7, sp, #0
20003eee:	60b9      	str	r1, [r7, #8]
20003ef0:	607a      	str	r2, [r7, #4]
20003ef2:	4602      	mov	r2, r0
20003ef4:	73fa      	strb	r2, [r7, #15]
20003ef6:	807b      	strh	r3, [r7, #2]
    /* Pause transfer. */
    PDMA->CHANNEL[channel_id].CRTL |= PAUSE_MASK;
20003ef8:	f244 0300 	movw	r3, #16384	; 0x4000
20003efc:	f2c4 0300 	movt	r3, #16384	; 0x4000
20003f00:	7bf9      	ldrb	r1, [r7, #15]
20003f02:	f244 0200 	movw	r2, #16384	; 0x4000
20003f06:	f2c4 0200 	movt	r2, #16384	; 0x4000
20003f0a:	7bf8      	ldrb	r0, [r7, #15]
20003f0c:	f100 0001 	add.w	r0, r0, #1
20003f10:	ea4f 1040 	mov.w	r0, r0, lsl #5
20003f14:	4402      	add	r2, r0
20003f16:	6812      	ldr	r2, [r2, #0]
20003f18:	f042 0210 	orr.w	r2, r2, #16
20003f1c:	f101 0101 	add.w	r1, r1, #1
20003f20:	ea4f 1141 	mov.w	r1, r1, lsl #5
20003f24:	440b      	add	r3, r1
20003f26:	601a      	str	r2, [r3, #0]
    
    /* Clear complete transfers. */
    if ( PDMA->CHANNEL[channel_id].STATUS & PORT_A_COMPLETE_MASK )
20003f28:	f244 0300 	movw	r3, #16384	; 0x4000
20003f2c:	f2c4 0300 	movt	r3, #16384	; 0x4000
20003f30:	7bfa      	ldrb	r2, [r7, #15]
20003f32:	f102 0201 	add.w	r2, r2, #1
20003f36:	ea4f 1242 	mov.w	r2, r2, lsl #5
20003f3a:	4413      	add	r3, r2
20003f3c:	f103 0304 	add.w	r3, r3, #4
20003f40:	681b      	ldr	r3, [r3, #0]
20003f42:	f003 0301 	and.w	r3, r3, #1
20003f46:	b2db      	uxtb	r3, r3
20003f48:	2b00      	cmp	r3, #0
20003f4a:	d01f      	beq.n	20003f8c <PDMA_start+0xa4>
    {
        PDMA->CHANNEL[channel_id].CRTL |= CLEAR_PORT_A_DONE_MASK;
20003f4c:	f244 0300 	movw	r3, #16384	; 0x4000
20003f50:	f2c4 0300 	movt	r3, #16384	; 0x4000
20003f54:	7bf9      	ldrb	r1, [r7, #15]
20003f56:	f244 0200 	movw	r2, #16384	; 0x4000
20003f5a:	f2c4 0200 	movt	r2, #16384	; 0x4000
20003f5e:	7bf8      	ldrb	r0, [r7, #15]
20003f60:	f100 0001 	add.w	r0, r0, #1
20003f64:	ea4f 1040 	mov.w	r0, r0, lsl #5
20003f68:	4402      	add	r2, r0
20003f6a:	6812      	ldr	r2, [r2, #0]
20003f6c:	f042 0280 	orr.w	r2, r2, #128	; 0x80
20003f70:	f101 0101 	add.w	r1, r1, #1
20003f74:	ea4f 1141 	mov.w	r1, r1, lsl #5
20003f78:	440b      	add	r3, r1
20003f7a:	601a      	str	r2, [r3, #0]
        g_pdma_started_a[channel_id] = CHANNEL_STOPPED;
20003f7c:	7bfa      	ldrb	r2, [r7, #15]
20003f7e:	f644 13fc 	movw	r3, #18940	; 0x49fc
20003f82:	f2c2 0300 	movt	r3, #8192	; 0x2000
20003f86:	f04f 0100 	mov.w	r1, #0
20003f8a:	5499      	strb	r1, [r3, r2]
    }
    if ( PDMA->CHANNEL[channel_id].STATUS & PORT_B_COMPLETE_MASK )
20003f8c:	f244 0300 	movw	r3, #16384	; 0x4000
20003f90:	f2c4 0300 	movt	r3, #16384	; 0x4000
20003f94:	7bfa      	ldrb	r2, [r7, #15]
20003f96:	f102 0201 	add.w	r2, r2, #1
20003f9a:	ea4f 1242 	mov.w	r2, r2, lsl #5
20003f9e:	4413      	add	r3, r2
20003fa0:	f103 0304 	add.w	r3, r3, #4
20003fa4:	681b      	ldr	r3, [r3, #0]
20003fa6:	f003 0302 	and.w	r3, r3, #2
20003faa:	2b00      	cmp	r3, #0
20003fac:	d01f      	beq.n	20003fee <PDMA_start+0x106>
    {
        PDMA->CHANNEL[channel_id].CRTL |= CLEAR_PORT_B_DONE_MASK;
20003fae:	f244 0300 	movw	r3, #16384	; 0x4000
20003fb2:	f2c4 0300 	movt	r3, #16384	; 0x4000
20003fb6:	7bf9      	ldrb	r1, [r7, #15]
20003fb8:	f244 0200 	movw	r2, #16384	; 0x4000
20003fbc:	f2c4 0200 	movt	r2, #16384	; 0x4000
20003fc0:	7bf8      	ldrb	r0, [r7, #15]
20003fc2:	f100 0001 	add.w	r0, r0, #1
20003fc6:	ea4f 1040 	mov.w	r0, r0, lsl #5
20003fca:	4402      	add	r2, r0
20003fcc:	6812      	ldr	r2, [r2, #0]
20003fce:	f442 7280 	orr.w	r2, r2, #256	; 0x100
20003fd2:	f101 0101 	add.w	r1, r1, #1
20003fd6:	ea4f 1141 	mov.w	r1, r1, lsl #5
20003fda:	440b      	add	r3, r1
20003fdc:	601a      	str	r2, [r3, #0]
        g_pdma_started_b[channel_id] = CHANNEL_STOPPED;
20003fde:	7bfa      	ldrb	r2, [r7, #15]
20003fe0:	f644 2304 	movw	r3, #18948	; 0x4a04
20003fe4:	f2c2 0300 	movt	r3, #8192	; 0x2000
20003fe8:	f04f 0100 	mov.w	r1, #0
20003fec:	5499      	strb	r1, [r3, r2]
    }
    
    /* Load source, destination and transfer count. */
    if ( PDMA->CHANNEL[channel_id].STATUS & BUFFER_B_SELECT_MASK )
20003fee:	f244 0300 	movw	r3, #16384	; 0x4000
20003ff2:	f2c4 0300 	movt	r3, #16384	; 0x4000
20003ff6:	7bfa      	ldrb	r2, [r7, #15]
20003ff8:	f102 0201 	add.w	r2, r2, #1
20003ffc:	ea4f 1242 	mov.w	r2, r2, lsl #5
20004000:	4413      	add	r3, r2
20004002:	f103 0304 	add.w	r3, r3, #4
20004006:	681b      	ldr	r3, [r3, #0]
20004008:	f003 0304 	and.w	r3, r3, #4
2000400c:	2b00      	cmp	r3, #0
2000400e:	d034      	beq.n	2000407a <PDMA_start+0x192>
    {
        g_pdma_next_channel[channel_id] = NEXT_CHANNEL_A;
20004010:	7bfa      	ldrb	r2, [r7, #15]
20004012:	f644 13f4 	movw	r3, #18932	; 0x49f4
20004016:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000401a:	f04f 0100 	mov.w	r1, #0
2000401e:	5499      	strb	r1, [r3, r2]
        g_pdma_started_b[channel_id] = CHANNEL_STARTED;
20004020:	7bfa      	ldrb	r2, [r7, #15]
20004022:	f644 2304 	movw	r3, #18948	; 0x4a04
20004026:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000402a:	f04f 0101 	mov.w	r1, #1
2000402e:	5499      	strb	r1, [r3, r2]
        
        PDMA->CHANNEL[channel_id].BUFFER_B_SRC_ADDR = src_addr;
20004030:	f244 0300 	movw	r3, #16384	; 0x4000
20004034:	f2c4 0300 	movt	r3, #16384	; 0x4000
20004038:	7bfa      	ldrb	r2, [r7, #15]
2000403a:	ea4f 1242 	mov.w	r2, r2, lsl #5
2000403e:	4413      	add	r3, r2
20004040:	f103 0334 	add.w	r3, r3, #52	; 0x34
20004044:	68ba      	ldr	r2, [r7, #8]
20004046:	601a      	str	r2, [r3, #0]
        PDMA->CHANNEL[channel_id].BUFFER_B_DEST_ADDR = dest_addr;
20004048:	f244 0300 	movw	r3, #16384	; 0x4000
2000404c:	f2c4 0300 	movt	r3, #16384	; 0x4000
20004050:	7bfa      	ldrb	r2, [r7, #15]
20004052:	ea4f 1242 	mov.w	r2, r2, lsl #5
20004056:	4413      	add	r3, r2
20004058:	f103 0338 	add.w	r3, r3, #56	; 0x38
2000405c:	687a      	ldr	r2, [r7, #4]
2000405e:	601a      	str	r2, [r3, #0]
        PDMA->CHANNEL[channel_id].BUFFER_B_TRANSFER_COUNT = transfer_count;
20004060:	f244 0300 	movw	r3, #16384	; 0x4000
20004064:	f2c4 0300 	movt	r3, #16384	; 0x4000
20004068:	7bf9      	ldrb	r1, [r7, #15]
2000406a:	887a      	ldrh	r2, [r7, #2]
2000406c:	ea4f 1141 	mov.w	r1, r1, lsl #5
20004070:	440b      	add	r3, r1
20004072:	f103 033c 	add.w	r3, r3, #60	; 0x3c
20004076:	601a      	str	r2, [r3, #0]
20004078:	e033      	b.n	200040e2 <PDMA_start+0x1fa>
    }
    else
    {
        g_pdma_next_channel[channel_id] = NEXT_CHANNEL_B;
2000407a:	7bfa      	ldrb	r2, [r7, #15]
2000407c:	f644 13f4 	movw	r3, #18932	; 0x49f4
20004080:	f2c2 0300 	movt	r3, #8192	; 0x2000
20004084:	f04f 0101 	mov.w	r1, #1
20004088:	5499      	strb	r1, [r3, r2]
        g_pdma_started_a[channel_id] = CHANNEL_STARTED;
2000408a:	7bfa      	ldrb	r2, [r7, #15]
2000408c:	f644 13fc 	movw	r3, #18940	; 0x49fc
20004090:	f2c2 0300 	movt	r3, #8192	; 0x2000
20004094:	f04f 0101 	mov.w	r1, #1
20004098:	5499      	strb	r1, [r3, r2]
        
        PDMA->CHANNEL[channel_id].BUFFER_A_SRC_ADDR = src_addr;
2000409a:	f244 0300 	movw	r3, #16384	; 0x4000
2000409e:	f2c4 0300 	movt	r3, #16384	; 0x4000
200040a2:	7bfa      	ldrb	r2, [r7, #15]
200040a4:	ea4f 1242 	mov.w	r2, r2, lsl #5
200040a8:	4413      	add	r3, r2
200040aa:	f103 0328 	add.w	r3, r3, #40	; 0x28
200040ae:	68ba      	ldr	r2, [r7, #8]
200040b0:	601a      	str	r2, [r3, #0]
        PDMA->CHANNEL[channel_id].BUFFER_A_DEST_ADDR = dest_addr;
200040b2:	f244 0300 	movw	r3, #16384	; 0x4000
200040b6:	f2c4 0300 	movt	r3, #16384	; 0x4000
200040ba:	7bfa      	ldrb	r2, [r7, #15]
200040bc:	ea4f 1242 	mov.w	r2, r2, lsl #5
200040c0:	4413      	add	r3, r2
200040c2:	f103 032c 	add.w	r3, r3, #44	; 0x2c
200040c6:	687a      	ldr	r2, [r7, #4]
200040c8:	601a      	str	r2, [r3, #0]
        PDMA->CHANNEL[channel_id].BUFFER_A_TRANSFER_COUNT = transfer_count;
200040ca:	f244 0300 	movw	r3, #16384	; 0x4000
200040ce:	f2c4 0300 	movt	r3, #16384	; 0x4000
200040d2:	7bf9      	ldrb	r1, [r7, #15]
200040d4:	887a      	ldrh	r2, [r7, #2]
200040d6:	ea4f 1141 	mov.w	r1, r1, lsl #5
200040da:	440b      	add	r3, r1
200040dc:	f103 0330 	add.w	r3, r3, #48	; 0x30
200040e0:	601a      	str	r2, [r3, #0]
    }
    
    /* Start transfer */
    PDMA->CHANNEL[channel_id].CRTL &= ~PAUSE_MASK;
200040e2:	f244 0300 	movw	r3, #16384	; 0x4000
200040e6:	f2c4 0300 	movt	r3, #16384	; 0x4000
200040ea:	7bf9      	ldrb	r1, [r7, #15]
200040ec:	f244 0200 	movw	r2, #16384	; 0x4000
200040f0:	f2c4 0200 	movt	r2, #16384	; 0x4000
200040f4:	7bf8      	ldrb	r0, [r7, #15]
200040f6:	f100 0001 	add.w	r0, r0, #1
200040fa:	ea4f 1040 	mov.w	r0, r0, lsl #5
200040fe:	4402      	add	r2, r0
20004100:	6812      	ldr	r2, [r2, #0]
20004102:	f022 0210 	bic.w	r2, r2, #16
20004106:	f101 0101 	add.w	r1, r1, #1
2000410a:	ea4f 1141 	mov.w	r1, r1, lsl #5
2000410e:	440b      	add	r3, r1
20004110:	601a      	str	r2, [r3, #0]
}
20004112:	f107 0714 	add.w	r7, r7, #20
20004116:	46bd      	mov	sp, r7
20004118:	bc80      	pop	{r7}
2000411a:	4770      	bx	lr

2000411c <PDMA_load_next_buffer>:
    pdma_channel_id_t channel_id,
    uint32_t src_addr,
    uint32_t dest_addr,
    uint16_t transfer_count
)
{
2000411c:	b480      	push	{r7}
2000411e:	b089      	sub	sp, #36	; 0x24
20004120:	af00      	add	r7, sp, #0
20004122:	60b9      	str	r1, [r7, #8]
20004124:	607a      	str	r2, [r7, #4]
20004126:	4602      	mov	r2, r0
20004128:	73fa      	strb	r2, [r7, #15]
2000412a:	807b      	strh	r3, [r7, #2]
    if ( NEXT_CHANNEL_A == g_pdma_next_channel[channel_id] )
2000412c:	7bfa      	ldrb	r2, [r7, #15]
2000412e:	f644 13f4 	movw	r3, #18932	; 0x49f4
20004132:	f2c2 0300 	movt	r3, #8192	; 0x2000
20004136:	5c9b      	ldrb	r3, [r3, r2]
20004138:	2b00      	cmp	r3, #0
2000413a:	d168      	bne.n	2000420e <PDMA_load_next_buffer+0xf2>
    {
        /* Wait for channel A current transfer completion. */
        if ( CHANNEL_STARTED == g_pdma_started_a[channel_id] )
2000413c:	7bfa      	ldrb	r2, [r7, #15]
2000413e:	f644 13fc 	movw	r3, #18940	; 0x49fc
20004142:	f2c2 0300 	movt	r3, #8192	; 0x2000
20004146:	5c9b      	ldrb	r3, [r3, r2]
20004148:	2b01      	cmp	r3, #1
2000414a:	d12b      	bne.n	200041a4 <PDMA_load_next_buffer+0x88>
        {
            uint32_t completed;
            uint32_t channel_mask;
            channel_mask = (uint32_t)1 << ((uint32_t)channel_id * 2U);
2000414c:	7bfb      	ldrb	r3, [r7, #15]
2000414e:	ea4f 0343 	mov.w	r3, r3, lsl #1
20004152:	f04f 0201 	mov.w	r2, #1
20004156:	fa02 f303 	lsl.w	r3, r2, r3
2000415a:	617b      	str	r3, [r7, #20]
            do {
                completed = PDMA->BUFFER_STATUS & channel_mask;
2000415c:	f244 0300 	movw	r3, #16384	; 0x4000
20004160:	f2c4 0300 	movt	r3, #16384	; 0x4000
20004164:	685a      	ldr	r2, [r3, #4]
20004166:	697b      	ldr	r3, [r7, #20]
20004168:	ea02 0303 	and.w	r3, r2, r3
2000416c:	613b      	str	r3, [r7, #16]
            } while( !completed );
2000416e:	693b      	ldr	r3, [r7, #16]
20004170:	2b00      	cmp	r3, #0
20004172:	d0f3      	beq.n	2000415c <PDMA_load_next_buffer+0x40>
            PDMA->CHANNEL[channel_id].CRTL |= CLEAR_PORT_A_DONE_MASK;
20004174:	f244 0300 	movw	r3, #16384	; 0x4000
20004178:	f2c4 0300 	movt	r3, #16384	; 0x4000
2000417c:	7bf9      	ldrb	r1, [r7, #15]
2000417e:	f244 0200 	movw	r2, #16384	; 0x4000
20004182:	f2c4 0200 	movt	r2, #16384	; 0x4000
20004186:	7bf8      	ldrb	r0, [r7, #15]
20004188:	f100 0001 	add.w	r0, r0, #1
2000418c:	ea4f 1040 	mov.w	r0, r0, lsl #5
20004190:	4402      	add	r2, r0
20004192:	6812      	ldr	r2, [r2, #0]
20004194:	f042 0280 	orr.w	r2, r2, #128	; 0x80
20004198:	f101 0101 	add.w	r1, r1, #1
2000419c:	ea4f 1141 	mov.w	r1, r1, lsl #5
200041a0:	440b      	add	r3, r1
200041a2:	601a      	str	r2, [r3, #0]
        }
        /* Load source, destination and transfer count. */
        PDMA->CHANNEL[channel_id].BUFFER_A_SRC_ADDR = src_addr;
200041a4:	f244 0300 	movw	r3, #16384	; 0x4000
200041a8:	f2c4 0300 	movt	r3, #16384	; 0x4000
200041ac:	7bfa      	ldrb	r2, [r7, #15]
200041ae:	ea4f 1242 	mov.w	r2, r2, lsl #5
200041b2:	4413      	add	r3, r2
200041b4:	f103 0328 	add.w	r3, r3, #40	; 0x28
200041b8:	68ba      	ldr	r2, [r7, #8]
200041ba:	601a      	str	r2, [r3, #0]
        PDMA->CHANNEL[channel_id].BUFFER_A_DEST_ADDR = dest_addr;
200041bc:	f244 0300 	movw	r3, #16384	; 0x4000
200041c0:	f2c4 0300 	movt	r3, #16384	; 0x4000
200041c4:	7bfa      	ldrb	r2, [r7, #15]
200041c6:	ea4f 1242 	mov.w	r2, r2, lsl #5
200041ca:	4413      	add	r3, r2
200041cc:	f103 032c 	add.w	r3, r3, #44	; 0x2c
200041d0:	687a      	ldr	r2, [r7, #4]
200041d2:	601a      	str	r2, [r3, #0]
        PDMA->CHANNEL[channel_id].BUFFER_A_TRANSFER_COUNT = transfer_count;
200041d4:	f244 0300 	movw	r3, #16384	; 0x4000
200041d8:	f2c4 0300 	movt	r3, #16384	; 0x4000
200041dc:	7bf9      	ldrb	r1, [r7, #15]
200041de:	887a      	ldrh	r2, [r7, #2]
200041e0:	ea4f 1141 	mov.w	r1, r1, lsl #5
200041e4:	440b      	add	r3, r1
200041e6:	f103 0330 	add.w	r3, r3, #48	; 0x30
200041ea:	601a      	str	r2, [r3, #0]
        
        /* Update channel state information. */
        g_pdma_next_channel[channel_id] = NEXT_CHANNEL_B;
200041ec:	7bfa      	ldrb	r2, [r7, #15]
200041ee:	f644 13f4 	movw	r3, #18932	; 0x49f4
200041f2:	f2c2 0300 	movt	r3, #8192	; 0x2000
200041f6:	f04f 0101 	mov.w	r1, #1
200041fa:	5499      	strb	r1, [r3, r2]
        g_pdma_started_a[channel_id] = CHANNEL_STARTED;
200041fc:	7bfa      	ldrb	r2, [r7, #15]
200041fe:	f644 13fc 	movw	r3, #18940	; 0x49fc
20004202:	f2c2 0300 	movt	r3, #8192	; 0x2000
20004206:	f04f 0101 	mov.w	r1, #1
2000420a:	5499      	strb	r1, [r3, r2]
2000420c:	e069      	b.n	200042e2 <PDMA_load_next_buffer+0x1c6>
    }
    else
    {
        /* Wait for channel B current transfer completion. */
        if ( CHANNEL_STARTED == g_pdma_started_b[channel_id] )
2000420e:	7bfa      	ldrb	r2, [r7, #15]
20004210:	f644 2304 	movw	r3, #18948	; 0x4a04
20004214:	f2c2 0300 	movt	r3, #8192	; 0x2000
20004218:	5c9b      	ldrb	r3, [r3, r2]
2000421a:	2b01      	cmp	r3, #1
2000421c:	d12d      	bne.n	2000427a <PDMA_load_next_buffer+0x15e>
        {
            uint32_t completed;
            uint32_t channel_mask;
            channel_mask = (uint32_t)1 << (((uint32_t)channel_id * 2U) + 1U);
2000421e:	7bfb      	ldrb	r3, [r7, #15]
20004220:	ea4f 0343 	mov.w	r3, r3, lsl #1
20004224:	f103 0301 	add.w	r3, r3, #1
20004228:	f04f 0201 	mov.w	r2, #1
2000422c:	fa02 f303 	lsl.w	r3, r2, r3
20004230:	61fb      	str	r3, [r7, #28]
            do {
                completed = PDMA->BUFFER_STATUS & channel_mask;
20004232:	f244 0300 	movw	r3, #16384	; 0x4000
20004236:	f2c4 0300 	movt	r3, #16384	; 0x4000
2000423a:	685a      	ldr	r2, [r3, #4]
2000423c:	69fb      	ldr	r3, [r7, #28]
2000423e:	ea02 0303 	and.w	r3, r2, r3
20004242:	61bb      	str	r3, [r7, #24]
            } while( !completed );
20004244:	69bb      	ldr	r3, [r7, #24]
20004246:	2b00      	cmp	r3, #0
20004248:	d0f3      	beq.n	20004232 <PDMA_load_next_buffer+0x116>
            PDMA->CHANNEL[channel_id].CRTL |= CLEAR_PORT_B_DONE_MASK;
2000424a:	f244 0300 	movw	r3, #16384	; 0x4000
2000424e:	f2c4 0300 	movt	r3, #16384	; 0x4000
20004252:	7bf9      	ldrb	r1, [r7, #15]
20004254:	f244 0200 	movw	r2, #16384	; 0x4000
20004258:	f2c4 0200 	movt	r2, #16384	; 0x4000
2000425c:	7bf8      	ldrb	r0, [r7, #15]
2000425e:	f100 0001 	add.w	r0, r0, #1
20004262:	ea4f 1040 	mov.w	r0, r0, lsl #5
20004266:	4402      	add	r2, r0
20004268:	6812      	ldr	r2, [r2, #0]
2000426a:	f442 7280 	orr.w	r2, r2, #256	; 0x100
2000426e:	f101 0101 	add.w	r1, r1, #1
20004272:	ea4f 1141 	mov.w	r1, r1, lsl #5
20004276:	440b      	add	r3, r1
20004278:	601a      	str	r2, [r3, #0]
        }            
        /* Load source, destination and transfer count. */
        PDMA->CHANNEL[channel_id].BUFFER_B_SRC_ADDR = src_addr;
2000427a:	f244 0300 	movw	r3, #16384	; 0x4000
2000427e:	f2c4 0300 	movt	r3, #16384	; 0x4000
20004282:	7bfa      	ldrb	r2, [r7, #15]
20004284:	ea4f 1242 	mov.w	r2, r2, lsl #5
20004288:	4413      	add	r3, r2
2000428a:	f103 0334 	add.w	r3, r3, #52	; 0x34
2000428e:	68ba      	ldr	r2, [r7, #8]
20004290:	601a      	str	r2, [r3, #0]
        PDMA->CHANNEL[channel_id].BUFFER_B_DEST_ADDR = dest_addr;
20004292:	f244 0300 	movw	r3, #16384	; 0x4000
20004296:	f2c4 0300 	movt	r3, #16384	; 0x4000
2000429a:	7bfa      	ldrb	r2, [r7, #15]
2000429c:	ea4f 1242 	mov.w	r2, r2, lsl #5
200042a0:	4413      	add	r3, r2
200042a2:	f103 0338 	add.w	r3, r3, #56	; 0x38
200042a6:	687a      	ldr	r2, [r7, #4]
200042a8:	601a      	str	r2, [r3, #0]
        PDMA->CHANNEL[channel_id].BUFFER_B_TRANSFER_COUNT = transfer_count;
200042aa:	f244 0300 	movw	r3, #16384	; 0x4000
200042ae:	f2c4 0300 	movt	r3, #16384	; 0x4000
200042b2:	7bf9      	ldrb	r1, [r7, #15]
200042b4:	887a      	ldrh	r2, [r7, #2]
200042b6:	ea4f 1141 	mov.w	r1, r1, lsl #5
200042ba:	440b      	add	r3, r1
200042bc:	f103 033c 	add.w	r3, r3, #60	; 0x3c
200042c0:	601a      	str	r2, [r3, #0]
        
        /* Update channel state information. */
        g_pdma_next_channel[channel_id] = NEXT_CHANNEL_A;
200042c2:	7bfa      	ldrb	r2, [r7, #15]
200042c4:	f644 13f4 	movw	r3, #18932	; 0x49f4
200042c8:	f2c2 0300 	movt	r3, #8192	; 0x2000
200042cc:	f04f 0100 	mov.w	r1, #0
200042d0:	5499      	strb	r1, [r3, r2]
        g_pdma_started_b[channel_id] = CHANNEL_STARTED;
200042d2:	7bfa      	ldrb	r2, [r7, #15]
200042d4:	f644 2304 	movw	r3, #18948	; 0x4a04
200042d8:	f2c2 0300 	movt	r3, #8192	; 0x2000
200042dc:	f04f 0101 	mov.w	r1, #1
200042e0:	5499      	strb	r1, [r3, r2]
    }
}
200042e2:	f107 0724 	add.w	r7, r7, #36	; 0x24
200042e6:	46bd      	mov	sp, r7
200042e8:	bc80      	pop	{r7}
200042ea:	4770      	bx	lr

200042ec <PDMA_status>:
 */
uint32_t PDMA_status
(
    pdma_channel_id_t  channel_id
)
{
200042ec:	b480      	push	{r7}
200042ee:	b085      	sub	sp, #20
200042f0:	af00      	add	r7, sp, #0
200042f2:	4603      	mov	r3, r0
200042f4:	71fb      	strb	r3, [r7, #7]
    uint32_t status;
    
    status = PDMA->CHANNEL[channel_id].STATUS & (PORT_A_COMPLETE_MASK | PORT_B_COMPLETE_MASK);
200042f6:	f244 0300 	movw	r3, #16384	; 0x4000
200042fa:	f2c4 0300 	movt	r3, #16384	; 0x4000
200042fe:	79fa      	ldrb	r2, [r7, #7]
20004300:	f102 0201 	add.w	r2, r2, #1
20004304:	ea4f 1242 	mov.w	r2, r2, lsl #5
20004308:	4413      	add	r3, r2
2000430a:	f103 0304 	add.w	r3, r3, #4
2000430e:	681b      	ldr	r3, [r3, #0]
20004310:	f003 0303 	and.w	r3, r3, #3
20004314:	60fb      	str	r3, [r7, #12]
    
    return status;
20004316:	68fb      	ldr	r3, [r7, #12]
}
20004318:	4618      	mov	r0, r3
2000431a:	f107 0714 	add.w	r7, r7, #20
2000431e:	46bd      	mov	sp, r7
20004320:	bc80      	pop	{r7}
20004322:	4770      	bx	lr

20004324 <get_channel_id_from_status>:

static pdma_channel_id_t get_channel_id_from_status
(
    uint16_t status
)
{
20004324:	b480      	push	{r7}
20004326:	b085      	sub	sp, #20
20004328:	af00      	add	r7, sp, #0
2000432a:	4603      	mov	r3, r0
2000432c:	80fb      	strh	r3, [r7, #6]
    pdma_channel_id_t channel_id = PDMA_CHANNEL_0;
2000432e:	f04f 0300 	mov.w	r3, #0
20004332:	73fb      	strb	r3, [r7, #15]
    
    if ( status & CHANNEL_0_STATUS_BITS_MASK )
20004334:	88fb      	ldrh	r3, [r7, #6]
20004336:	f003 0303 	and.w	r3, r3, #3
2000433a:	2b00      	cmp	r3, #0
2000433c:	d003      	beq.n	20004346 <get_channel_id_from_status+0x22>
    {
        channel_id = PDMA_CHANNEL_0;
2000433e:	f04f 0300 	mov.w	r3, #0
20004342:	73fb      	strb	r3, [r7, #15]
20004344:	e03f      	b.n	200043c6 <get_channel_id_from_status+0xa2>
    }
    else if ( status & CHANNEL_1_STATUS_BITS_MASK )
20004346:	88fb      	ldrh	r3, [r7, #6]
20004348:	f003 030c 	and.w	r3, r3, #12
2000434c:	2b00      	cmp	r3, #0
2000434e:	d003      	beq.n	20004358 <get_channel_id_from_status+0x34>
    {
        channel_id = PDMA_CHANNEL_1;
20004350:	f04f 0301 	mov.w	r3, #1
20004354:	73fb      	strb	r3, [r7, #15]
20004356:	e036      	b.n	200043c6 <get_channel_id_from_status+0xa2>
    }
    else if ( status & CHANNEL_2_STATUS_BITS_MASK )
20004358:	88fb      	ldrh	r3, [r7, #6]
2000435a:	f003 0330 	and.w	r3, r3, #48	; 0x30
2000435e:	2b00      	cmp	r3, #0
20004360:	d003      	beq.n	2000436a <get_channel_id_from_status+0x46>
    {
        channel_id = PDMA_CHANNEL_2;
20004362:	f04f 0302 	mov.w	r3, #2
20004366:	73fb      	strb	r3, [r7, #15]
20004368:	e02d      	b.n	200043c6 <get_channel_id_from_status+0xa2>
    }
    else if ( status & CHANNEL_3_STATUS_BITS_MASK )
2000436a:	88fb      	ldrh	r3, [r7, #6]
2000436c:	f003 03c0 	and.w	r3, r3, #192	; 0xc0
20004370:	2b00      	cmp	r3, #0
20004372:	d003      	beq.n	2000437c <get_channel_id_from_status+0x58>
    {
        channel_id = PDMA_CHANNEL_3;
20004374:	f04f 0303 	mov.w	r3, #3
20004378:	73fb      	strb	r3, [r7, #15]
2000437a:	e024      	b.n	200043c6 <get_channel_id_from_status+0xa2>
    }
    else if ( status & CHANNEL_4_STATUS_BITS_MASK )
2000437c:	88fb      	ldrh	r3, [r7, #6]
2000437e:	f403 7340 	and.w	r3, r3, #768	; 0x300
20004382:	2b00      	cmp	r3, #0
20004384:	d003      	beq.n	2000438e <get_channel_id_from_status+0x6a>
    {
        channel_id = PDMA_CHANNEL_4;
20004386:	f04f 0304 	mov.w	r3, #4
2000438a:	73fb      	strb	r3, [r7, #15]
2000438c:	e01b      	b.n	200043c6 <get_channel_id_from_status+0xa2>
    }
    else if ( status & CHANNEL_5_STATUS_BITS_MASK )
2000438e:	88fb      	ldrh	r3, [r7, #6]
20004390:	f403 6340 	and.w	r3, r3, #3072	; 0xc00
20004394:	2b00      	cmp	r3, #0
20004396:	d003      	beq.n	200043a0 <get_channel_id_from_status+0x7c>
    {
        channel_id = PDMA_CHANNEL_5;
20004398:	f04f 0305 	mov.w	r3, #5
2000439c:	73fb      	strb	r3, [r7, #15]
2000439e:	e012      	b.n	200043c6 <get_channel_id_from_status+0xa2>
    }
    else if ( status & CHANNEL_6_STATUS_BITS_MASK )
200043a0:	88fb      	ldrh	r3, [r7, #6]
200043a2:	f403 5340 	and.w	r3, r3, #12288	; 0x3000
200043a6:	2b00      	cmp	r3, #0
200043a8:	d003      	beq.n	200043b2 <get_channel_id_from_status+0x8e>
    {
        channel_id = PDMA_CHANNEL_6;
200043aa:	f04f 0306 	mov.w	r3, #6
200043ae:	73fb      	strb	r3, [r7, #15]
200043b0:	e009      	b.n	200043c6 <get_channel_id_from_status+0xa2>
    }
    else if ( status & CHANNEL_7_STATUS_BITS_MASK )
200043b2:	88fb      	ldrh	r3, [r7, #6]
200043b4:	f403 4340 	and.w	r3, r3, #49152	; 0xc000
200043b8:	2b00      	cmp	r3, #0
200043ba:	d003      	beq.n	200043c4 <get_channel_id_from_status+0xa0>
    {
        channel_id = PDMA_CHANNEL_7;
200043bc:	f04f 0307 	mov.w	r3, #7
200043c0:	73fb      	strb	r3, [r7, #15]
200043c2:	e000      	b.n	200043c6 <get_channel_id_from_status+0xa2>
    }
    else
    {
        ASSERT(0);
200043c4:	be00      	bkpt	0x0000
    }
    return channel_id;
200043c6:	7bfb      	ldrb	r3, [r7, #15]
}
200043c8:	4618      	mov	r0, r3
200043ca:	f107 0714 	add.w	r7, r7, #20
200043ce:	46bd      	mov	sp, r7
200043d0:	bc80      	pop	{r7}
200043d2:	4770      	bx	lr

200043d4 <DMA_IRQHandler>:
#if defined(__GNUC__)
__attribute__((__interrupt__)) void DMA_IRQHandler( void )
#else
void DMA_IRQHandler( void )
#endif
{
200043d4:	4668      	mov	r0, sp
200043d6:	f020 0107 	bic.w	r1, r0, #7
200043da:	468d      	mov	sp, r1
200043dc:	b581      	push	{r0, r7, lr}
200043de:	b083      	sub	sp, #12
200043e0:	af00      	add	r7, sp, #0
    uint16_t status;
    pdma_channel_id_t channel_id;
    
    status = (uint16_t)PDMA->BUFFER_STATUS;
200043e2:	f244 0300 	movw	r3, #16384	; 0x4000
200043e6:	f2c4 0300 	movt	r3, #16384	; 0x4000
200043ea:	685b      	ldr	r3, [r3, #4]
200043ec:	80bb      	strh	r3, [r7, #4]
    
    do {
        channel_id = get_channel_id_from_status( status );
200043ee:	88bb      	ldrh	r3, [r7, #4]
200043f0:	4618      	mov	r0, r3
200043f2:	f7ff ff97 	bl	20004324 <get_channel_id_from_status>
200043f6:	4603      	mov	r3, r0
200043f8:	71fb      	strb	r3, [r7, #7]
        status &= (uint16_t)~g_pdma_status_mask[channel_id];
200043fa:	79fa      	ldrb	r2, [r7, #7]
200043fc:	f644 0384 	movw	r3, #18564	; 0x4884
20004400:	f2c2 0300 	movt	r3, #8192	; 0x2000
20004404:	f833 3012 	ldrh.w	r3, [r3, r2, lsl #1]
20004408:	ea6f 0303 	mvn.w	r3, r3
2000440c:	b29a      	uxth	r2, r3
2000440e:	88bb      	ldrh	r3, [r7, #4]
20004410:	ea02 0303 	and.w	r3, r2, r3
20004414:	80bb      	strh	r3, [r7, #4]
        if ( 0 != g_pdma_isr_table[channel_id])
20004416:	79fa      	ldrb	r2, [r7, #7]
20004418:	f644 230c 	movw	r3, #18956	; 0x4a0c
2000441c:	f2c2 0300 	movt	r3, #8192	; 0x2000
20004420:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
20004424:	2b00      	cmp	r3, #0
20004426:	d007      	beq.n	20004438 <DMA_IRQHandler+0x64>
        {
            g_pdma_isr_table[channel_id]();
20004428:	79fa      	ldrb	r2, [r7, #7]
2000442a:	f644 230c 	movw	r3, #18956	; 0x4a0c
2000442e:	f2c2 0300 	movt	r3, #8192	; 0x2000
20004432:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
20004436:	4798      	blx	r3
        }
    } while ( 0U != status );
20004438:	88bb      	ldrh	r3, [r7, #4]
2000443a:	2b00      	cmp	r3, #0
2000443c:	d1d7      	bne.n	200043ee <DMA_IRQHandler+0x1a>
      
    NVIC_ClearPendingIRQ( DMA_IRQn );
2000443e:	f04f 0009 	mov.w	r0, #9
20004442:	f7ff fc41 	bl	20003cc8 <NVIC_ClearPendingIRQ>
}
20004446:	f107 070c 	add.w	r7, r7, #12
2000444a:	46bd      	mov	sp, r7
2000444c:	e8bd 4081 	ldmia.w	sp!, {r0, r7, lr}
20004450:	4685      	mov	sp, r0
20004452:	4770      	bx	lr

20004454 <PDMA_set_irq_handler>:
void PDMA_set_irq_handler
(
    pdma_channel_id_t channel_id,
    pdma_channel_isr_t handler
)
{
20004454:	b580      	push	{r7, lr}
20004456:	b082      	sub	sp, #8
20004458:	af00      	add	r7, sp, #0
2000445a:	4603      	mov	r3, r0
2000445c:	6039      	str	r1, [r7, #0]
2000445e:	71fb      	strb	r3, [r7, #7]
    /* Save address of handler function in PDMA driver ISR lookup table. */
    g_pdma_isr_table[channel_id] = handler;
20004460:	79fa      	ldrb	r2, [r7, #7]
20004462:	f644 230c 	movw	r3, #18956	; 0x4a0c
20004466:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000446a:	6839      	ldr	r1, [r7, #0]
2000446c:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
    
    /* Enable PDMA channel's interrupt. */
    PDMA->CHANNEL[channel_id].CRTL |= PDMA_IRQ_ENABLE_MASK;
20004470:	f244 0300 	movw	r3, #16384	; 0x4000
20004474:	f2c4 0300 	movt	r3, #16384	; 0x4000
20004478:	79f9      	ldrb	r1, [r7, #7]
2000447a:	f244 0200 	movw	r2, #16384	; 0x4000
2000447e:	f2c4 0200 	movt	r2, #16384	; 0x4000
20004482:	79f8      	ldrb	r0, [r7, #7]
20004484:	f100 0001 	add.w	r0, r0, #1
20004488:	ea4f 1040 	mov.w	r0, r0, lsl #5
2000448c:	4402      	add	r2, r0
2000448e:	6812      	ldr	r2, [r2, #0]
20004490:	f042 0240 	orr.w	r2, r2, #64	; 0x40
20004494:	f101 0101 	add.w	r1, r1, #1
20004498:	ea4f 1141 	mov.w	r1, r1, lsl #5
2000449c:	440b      	add	r3, r1
2000449e:	601a      	str	r2, [r3, #0]
    
    /* Enable PDMA interrupt in Cortex-M3 NVIC. */
    NVIC_EnableIRQ( DMA_IRQn );
200044a0:	f04f 0009 	mov.w	r0, #9
200044a4:	f7ff fbf4 	bl	20003c90 <NVIC_EnableIRQ>
}
200044a8:	f107 0708 	add.w	r7, r7, #8
200044ac:	46bd      	mov	sp, r7
200044ae:	bd80      	pop	{r7, pc}

200044b0 <PDMA_enable_irq>:

/***************************************************************************//**
 * See mss_pdma.h for description of this function.
 */
void PDMA_enable_irq( pdma_channel_id_t channel_id )
{
200044b0:	b580      	push	{r7, lr}
200044b2:	b082      	sub	sp, #8
200044b4:	af00      	add	r7, sp, #0
200044b6:	4603      	mov	r3, r0
200044b8:	71fb      	strb	r3, [r7, #7]
    PDMA->CHANNEL[channel_id].CRTL |= PDMA_IRQ_ENABLE_MASK;
200044ba:	f244 0300 	movw	r3, #16384	; 0x4000
200044be:	f2c4 0300 	movt	r3, #16384	; 0x4000
200044c2:	79f9      	ldrb	r1, [r7, #7]
200044c4:	f244 0200 	movw	r2, #16384	; 0x4000
200044c8:	f2c4 0200 	movt	r2, #16384	; 0x4000
200044cc:	79f8      	ldrb	r0, [r7, #7]
200044ce:	f100 0001 	add.w	r0, r0, #1
200044d2:	ea4f 1040 	mov.w	r0, r0, lsl #5
200044d6:	4402      	add	r2, r0
200044d8:	6812      	ldr	r2, [r2, #0]
200044da:	f042 0240 	orr.w	r2, r2, #64	; 0x40
200044de:	f101 0101 	add.w	r1, r1, #1
200044e2:	ea4f 1141 	mov.w	r1, r1, lsl #5
200044e6:	440b      	add	r3, r1
200044e8:	601a      	str	r2, [r3, #0]
    NVIC_EnableIRQ( DMA_IRQn );
200044ea:	f04f 0009 	mov.w	r0, #9
200044ee:	f7ff fbcf 	bl	20003c90 <NVIC_EnableIRQ>
}
200044f2:	f107 0708 	add.w	r7, r7, #8
200044f6:	46bd      	mov	sp, r7
200044f8:	bd80      	pop	{r7, pc}
200044fa:	bf00      	nop

200044fc <PDMA_clear_irq>:
 */
void PDMA_clear_irq
(
    pdma_channel_id_t channel_id
)
{
200044fc:	b580      	push	{r7, lr}
200044fe:	b082      	sub	sp, #8
20004500:	af00      	add	r7, sp, #0
20004502:	4603      	mov	r3, r0
20004504:	71fb      	strb	r3, [r7, #7]
    /* Clear interrupt in PDMA controller. */
    PDMA->CHANNEL[channel_id].CRTL |= CLEAR_PORT_A_DONE_MASK;
20004506:	f244 0300 	movw	r3, #16384	; 0x4000
2000450a:	f2c4 0300 	movt	r3, #16384	; 0x4000
2000450e:	79f9      	ldrb	r1, [r7, #7]
20004510:	f244 0200 	movw	r2, #16384	; 0x4000
20004514:	f2c4 0200 	movt	r2, #16384	; 0x4000
20004518:	79f8      	ldrb	r0, [r7, #7]
2000451a:	f100 0001 	add.w	r0, r0, #1
2000451e:	ea4f 1040 	mov.w	r0, r0, lsl #5
20004522:	4402      	add	r2, r0
20004524:	6812      	ldr	r2, [r2, #0]
20004526:	f042 0280 	orr.w	r2, r2, #128	; 0x80
2000452a:	f101 0101 	add.w	r1, r1, #1
2000452e:	ea4f 1141 	mov.w	r1, r1, lsl #5
20004532:	440b      	add	r3, r1
20004534:	601a      	str	r2, [r3, #0]
    PDMA->CHANNEL[channel_id].CRTL |= CLEAR_PORT_B_DONE_MASK;
20004536:	f244 0300 	movw	r3, #16384	; 0x4000
2000453a:	f2c4 0300 	movt	r3, #16384	; 0x4000
2000453e:	79f9      	ldrb	r1, [r7, #7]
20004540:	f244 0200 	movw	r2, #16384	; 0x4000
20004544:	f2c4 0200 	movt	r2, #16384	; 0x4000
20004548:	79f8      	ldrb	r0, [r7, #7]
2000454a:	f100 0001 	add.w	r0, r0, #1
2000454e:	ea4f 1040 	mov.w	r0, r0, lsl #5
20004552:	4402      	add	r2, r0
20004554:	6812      	ldr	r2, [r2, #0]
20004556:	f442 7280 	orr.w	r2, r2, #256	; 0x100
2000455a:	f101 0101 	add.w	r1, r1, #1
2000455e:	ea4f 1141 	mov.w	r1, r1, lsl #5
20004562:	440b      	add	r3, r1
20004564:	601a      	str	r2, [r3, #0]
    
    /* Clear interrupt in Cortex-M3 NVIC. */
    NVIC_ClearPendingIRQ( DMA_IRQn );
20004566:	f04f 0009 	mov.w	r0, #9
2000456a:	f7ff fbad 	bl	20003cc8 <NVIC_ClearPendingIRQ>
}
2000456e:	f107 0708 	add.w	r7, r7, #8
20004572:	46bd      	mov	sp, r7
20004574:	bd80      	pop	{r7, pc}
20004576:	bf00      	nop

20004578 <SystemInit>:

/***************************************************************************//**
 * See system_a2fxxxm3f.h for details.
 */
void SystemInit(void)
{
20004578:	b480      	push	{r7}
2000457a:	af00      	add	r7, sp, #0
    /*
     * Do not make use of global variables or make any asumptions regarding
     * memory content if modifying this function. The memory content has not been
     * initialised by the time this function is called by the start-up code.
     */
}
2000457c:	46bd      	mov	sp, r7
2000457e:	bc80      	pop	{r7}
20004580:	4770      	bx	lr
20004582:	bf00      	nop

20004584 <SystemCoreClockUpdate>:

/***************************************************************************//**
 *
 */
void SystemCoreClockUpdate (void)
{
20004584:	b580      	push	{r7, lr}
20004586:	b08a      	sub	sp, #40	; 0x28
20004588:	af00      	add	r7, sp, #0
    uint32_t PclkDiv0;
    uint32_t PclkDiv1;
    uint32_t AceDiv;
    uint32_t FabDiv;

    const uint32_t pclk_div_lut[4] = { 1uL, 2uL, 4uL, 1uL };
2000458a:	f644 0394 	movw	r3, #18580	; 0x4894
2000458e:	f2c2 0300 	movt	r3, #8192	; 0x2000
20004592:	46bc      	mov	ip, r7
20004594:	cb0f      	ldmia	r3!, {r0, r1, r2, r3}
20004596:	e88c 000f 	stmia.w	ip, {r0, r1, r2, r3}

    /* Read PCLK dividers from system registers. Multiply the value read from
     * system register by two to get actual divider value. */
    PclkDiv0 = pclk_div_lut[((SYSREG->MSS_CLK_CR >> PCLK0_DIV_SHIFT) & PCLK_DIV_MASK)];
2000459a:	f242 0300 	movw	r3, #8192	; 0x2000
2000459e:	f2ce 0304 	movt	r3, #57348	; 0xe004
200045a2:	6c9b      	ldr	r3, [r3, #72]	; 0x48
200045a4:	ea4f 0393 	mov.w	r3, r3, lsr #2
200045a8:	f003 0303 	and.w	r3, r3, #3
200045ac:	ea4f 0383 	mov.w	r3, r3, lsl #2
200045b0:	f107 0228 	add.w	r2, r7, #40	; 0x28
200045b4:	4413      	add	r3, r2
200045b6:	f853 3c28 	ldr.w	r3, [r3, #-40]
200045ba:	613b      	str	r3, [r7, #16]
    PclkDiv1 = pclk_div_lut[((SYSREG->MSS_CLK_CR >> PCLK1_DIV_SHIFT) & PCLK_DIV_MASK)];
200045bc:	f242 0300 	movw	r3, #8192	; 0x2000
200045c0:	f2ce 0304 	movt	r3, #57348	; 0xe004
200045c4:	6c9b      	ldr	r3, [r3, #72]	; 0x48
200045c6:	ea4f 1313 	mov.w	r3, r3, lsr #4
200045ca:	f003 0303 	and.w	r3, r3, #3
200045ce:	ea4f 0383 	mov.w	r3, r3, lsl #2
200045d2:	f107 0228 	add.w	r2, r7, #40	; 0x28
200045d6:	4413      	add	r3, r2
200045d8:	f853 3c28 	ldr.w	r3, [r3, #-40]
200045dc:	617b      	str	r3, [r7, #20]
    AceDiv = pclk_div_lut[((SYSREG->MSS_CLK_CR >> ACE_DIV_SHIFT) & PCLK_DIV_MASK)];
200045de:	f242 0300 	movw	r3, #8192	; 0x2000
200045e2:	f2ce 0304 	movt	r3, #57348	; 0xe004
200045e6:	6c9b      	ldr	r3, [r3, #72]	; 0x48
200045e8:	ea4f 1393 	mov.w	r3, r3, lsr #6
200045ec:	f003 0303 	and.w	r3, r3, #3
200045f0:	ea4f 0383 	mov.w	r3, r3, lsl #2
200045f4:	f107 0228 	add.w	r2, r7, #40	; 0x28
200045f8:	4413      	add	r3, r2
200045fa:	f853 3c28 	ldr.w	r3, [r3, #-40]
200045fe:	61bb      	str	r3, [r7, #24]
    {
        /* Compute the FPGA fabric frequency divider. */
        uint32_t obdiv;
        uint32_t obdivhalf;
        
        obdiv = (SYSREG->MSS_CCC_DIV_CR >> OBDIV_SHIFT) & OBDIV_MASK;
20004600:	f242 0300 	movw	r3, #8192	; 0x2000
20004604:	f2ce 0304 	movt	r3, #57348	; 0xe004
20004608:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
2000460a:	ea4f 2313 	mov.w	r3, r3, lsr #8
2000460e:	f003 031f 	and.w	r3, r3, #31
20004612:	623b      	str	r3, [r7, #32]
        obdivhalf = (SYSREG->MSS_CCC_DIV_CR >> OBDIVHALF_SHIFT) & OBDIVHALF_MASK;
20004614:	f242 0300 	movw	r3, #8192	; 0x2000
20004618:	f2ce 0304 	movt	r3, #57348	; 0xe004
2000461c:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
2000461e:	ea4f 3353 	mov.w	r3, r3, lsr #13
20004622:	f003 0301 	and.w	r3, r3, #1
20004626:	627b      	str	r3, [r7, #36]	; 0x24
        FabDiv = obdiv + 1uL;
20004628:	6a3b      	ldr	r3, [r7, #32]
2000462a:	f103 0301 	add.w	r3, r3, #1
2000462e:	61fb      	str	r3, [r7, #28]
        if ( obdivhalf != 0uL )
20004630:	6a7b      	ldr	r3, [r7, #36]	; 0x24
20004632:	2b00      	cmp	r3, #0
20004634:	d003      	beq.n	2000463e <SystemCoreClockUpdate+0xba>
        {
            FabDiv = FabDiv * 2uL;
20004636:	69fb      	ldr	r3, [r7, #28]
20004638:	ea4f 0343 	mov.w	r3, r3, lsl #1
2000463c:	61fb      	str	r3, [r7, #28]
    }
    
    /* Retrieve FCLK from eNVM spare pages if Actel system boot programmed as part of the system. */
    
    /* Read system clock from eNVM spare pages. */
    SystemCoreClock = GetSystemClock();
2000463e:	f000 f849 	bl	200046d4 <GetSystemClock>
20004642:	4602      	mov	r2, r0
20004644:	f644 03dc 	movw	r3, #18652	; 0x48dc
20004648:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000464c:	601a      	str	r2, [r3, #0]
    g_FrequencyPCLK0 = SystemCoreClock / PclkDiv0;
2000464e:	f644 03dc 	movw	r3, #18652	; 0x48dc
20004652:	f2c2 0300 	movt	r3, #8192	; 0x2000
20004656:	681a      	ldr	r2, [r3, #0]
20004658:	693b      	ldr	r3, [r7, #16]
2000465a:	fbb2 f2f3 	udiv	r2, r2, r3
2000465e:	f644 03e0 	movw	r3, #18656	; 0x48e0
20004662:	f2c2 0300 	movt	r3, #8192	; 0x2000
20004666:	601a      	str	r2, [r3, #0]
    g_FrequencyPCLK1 = SystemCoreClock / PclkDiv1;
20004668:	f644 03dc 	movw	r3, #18652	; 0x48dc
2000466c:	f2c2 0300 	movt	r3, #8192	; 0x2000
20004670:	681a      	ldr	r2, [r3, #0]
20004672:	697b      	ldr	r3, [r7, #20]
20004674:	fbb2 f2f3 	udiv	r2, r2, r3
20004678:	f644 03e4 	movw	r3, #18660	; 0x48e4
2000467c:	f2c2 0300 	movt	r3, #8192	; 0x2000
20004680:	601a      	str	r2, [r3, #0]
    g_FrequencyACE = SystemCoreClock / AceDiv;
20004682:	f644 03dc 	movw	r3, #18652	; 0x48dc
20004686:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000468a:	681a      	ldr	r2, [r3, #0]
2000468c:	69bb      	ldr	r3, [r7, #24]
2000468e:	fbb2 f2f3 	udiv	r2, r2, r3
20004692:	f644 03e8 	movw	r3, #18664	; 0x48e8
20004696:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000469a:	601a      	str	r2, [r3, #0]
    g_FrequencyFPGA = SystemCoreClock / FabDiv;
2000469c:	f644 03dc 	movw	r3, #18652	; 0x48dc
200046a0:	f2c2 0300 	movt	r3, #8192	; 0x2000
200046a4:	681a      	ldr	r2, [r3, #0]
200046a6:	69fb      	ldr	r3, [r7, #28]
200046a8:	fbb2 f2f3 	udiv	r2, r2, r3
200046ac:	f644 03ec 	movw	r3, #18668	; 0x48ec
200046b0:	f2c2 0300 	movt	r3, #8192	; 0x2000
200046b4:	601a      	str	r2, [r3, #0]
    
    /* Keep SystemFrequency as well as SystemCoreClock for legacy reasons. */
    SystemFrequency = SystemCoreClock;
200046b6:	f644 03dc 	movw	r3, #18652	; 0x48dc
200046ba:	f2c2 0300 	movt	r3, #8192	; 0x2000
200046be:	681a      	ldr	r2, [r3, #0]
200046c0:	f644 03d8 	movw	r3, #18648	; 0x48d8
200046c4:	f2c2 0300 	movt	r3, #8192	; 0x2000
200046c8:	601a      	str	r2, [r3, #0]
}
200046ca:	f107 0728 	add.w	r7, r7, #40	; 0x28
200046ce:	46bd      	mov	sp, r7
200046d0:	bd80      	pop	{r7, pc}
200046d2:	bf00      	nop

200046d4 <GetSystemClock>:
 * retrieved from eNVM spare pages.
 * The FCLK frequency value selected in the MSS Configurator software tool is
 * stored in eNVM spare pages as part of the Actel system boot configuration data.
 */
uint32_t GetSystemClock( void )
{
200046d4:	b480      	push	{r7}
200046d6:	b08b      	sub	sp, #44	; 0x2c
200046d8:	af00      	add	r7, sp, #0
    uint32_t fclk = 0uL;
200046da:	f04f 0300 	mov.w	r3, #0
200046de:	607b      	str	r3, [r7, #4]
    
    uint32_t * p_sysboot_key = SYSBOOT_KEY_ADDR;
200046e0:	f640 031c 	movw	r3, #2076	; 0x81c
200046e4:	f2c6 0308 	movt	r3, #24584	; 0x6008
200046e8:	60bb      	str	r3, [r7, #8]
    uint32_t * p_idcode = IDCODE_LOCATION;
200046ea:	f240 2330 	movw	r3, #560	; 0x230
200046ee:	f2c6 0308 	movt	r3, #24584	; 0x6008
200046f2:	60fb      	str	r3, [r7, #12]
    uint32_t idcode;
	
    idcode = *p_idcode & ~IDCODE_DEV_REV_MASK;
200046f4:	68fb      	ldr	r3, [r7, #12]
200046f6:	681b      	ldr	r3, [r3, #0]
200046f8:	f023 4370 	bic.w	r3, r3, #4026531840	; 0xf0000000
200046fc:	613b      	str	r3, [r7, #16]
	
    if ( A2F060IFX_ID == idcode )
200046fe:	693a      	ldr	r2, [r7, #16]
20004700:	f241 13cf 	movw	r3, #4559	; 0x11cf
20004704:	f2c0 53a1 	movt	r3, #1441	; 0x5a1
20004708:	429a      	cmp	r2, r3
2000470a:	d108      	bne.n	2000471e <GetSystemClock+0x4a>
    {
        uint32_t *p_fclk = SYSBOOT_A2F060_FCLK_ADDR;
2000470c:	f64e 732c 	movw	r3, #61228	; 0xef2c
20004710:	f2c6 0301 	movt	r3, #24577	; 0x6001
20004714:	617b      	str	r3, [r7, #20]
        fclk = *p_fclk;
20004716:	697b      	ldr	r3, [r7, #20]
20004718:	681b      	ldr	r3, [r3, #0]
2000471a:	607b      	str	r3, [r7, #4]
2000471c:	e03d      	b.n	2000479a <GetSystemClock+0xc6>
    }
    else if ( SYSBOOT_KEY_VALUE == *p_sysboot_key )
2000471e:	68bb      	ldr	r3, [r7, #8]
20004720:	681a      	ldr	r2, [r3, #0]
20004722:	f244 3341 	movw	r3, #17217	; 0x4341
20004726:	f6c4 4354 	movt	r3, #19540	; 0x4c54
2000472a:	429a      	cmp	r2, r3
2000472c:	d135      	bne.n	2000479a <GetSystemClock+0xc6>
    {
        /* Actel system boot programmed, check if it has the FCLK value stored. */
        uint32_t *p_sysboot_version = SYSBOOT_VERSION_ADDR;
2000472e:	f640 0340 	movw	r3, #2112	; 0x840
20004732:	f2c6 0308 	movt	r3, #24584	; 0x6008
20004736:	61bb      	str	r3, [r7, #24]
        uint32_t sysboot_version = *p_sysboot_version;
20004738:	69bb      	ldr	r3, [r7, #24]
2000473a:	681b      	ldr	r3, [r3, #0]
2000473c:	61fb      	str	r3, [r7, #28]
        
        sysboot_version &= SYSBOOT_VERSION_MASK;
2000473e:	69fb      	ldr	r3, [r7, #28]
20004740:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
20004744:	61fb      	str	r3, [r7, #28]
        
        if ( sysboot_version >= MIN_SYSBOOT_VERSION )
20004746:	69fa      	ldr	r2, [r7, #28]
20004748:	f240 3300 	movw	r3, #768	; 0x300
2000474c:	f2c0 0301 	movt	r3, #1
20004750:	429a      	cmp	r2, r3
20004752:	d922      	bls.n	2000479a <GetSystemClock+0xc6>
        {
            /* Handle change of eNVM location of FCLK between 1.3.x and 2.x.x versions of the system boot. */
            if ( sysboot_version < SYSBOOT_VERSION_2_X )
20004754:	69fa      	ldr	r2, [r7, #28]
20004756:	f64f 73ff 	movw	r3, #65535	; 0xffff
2000475a:	f2c0 0301 	movt	r3, #1
2000475e:	429a      	cmp	r2, r3
20004760:	d808      	bhi.n	20004774 <GetSystemClock+0xa0>
            {
                /* Read FCLK value from MSS configurator generated configuration
                 * data stored in eNVM spare pages as part of system boot version 1.3.x
                 * configuration tables. */
                uint32_t *p_fclk = SYSBOOT_1_3_FCLK_ADDR;
20004762:	f241 632c 	movw	r3, #5676	; 0x162c
20004766:	f2c6 0308 	movt	r3, #24584	; 0x6008
2000476a:	623b      	str	r3, [r7, #32]
                fclk = *p_fclk;
2000476c:	6a3b      	ldr	r3, [r7, #32]
2000476e:	681b      	ldr	r3, [r3, #0]
20004770:	607b      	str	r3, [r7, #4]
20004772:	e012      	b.n	2000479a <GetSystemClock+0xc6>
            }
            else if ( sysboot_version < MAX_SYSBOOT_VERSION )
20004774:	69fa      	ldr	r2, [r7, #28]
20004776:	f64f 73ff 	movw	r3, #65535	; 0xffff
2000477a:	f2c0 0302 	movt	r3, #2
2000477e:	429a      	cmp	r2, r3
20004780:	d808      	bhi.n	20004794 <GetSystemClock+0xc0>
            {
                /* Read FCLK value from MSS configurator generated configuration
                 * data stored in eNVM spare pages as part of system boot version 2.x.x
                 * configuration tables. */
                uint32_t *p_fclk = SYSBOOT_2_x_FCLK_ADDR;
20004782:	f641 63ac 	movw	r3, #7852	; 0x1eac
20004786:	f2c6 0308 	movt	r3, #24584	; 0x6008
2000478a:	627b      	str	r3, [r7, #36]	; 0x24
                fclk = *p_fclk;
2000478c:	6a7b      	ldr	r3, [r7, #36]	; 0x24
2000478e:	681b      	ldr	r3, [r3, #0]
20004790:	607b      	str	r3, [r7, #4]
20004792:	e002      	b.n	2000479a <GetSystemClock+0xc6>
            }
            else
            {
                fclk = 0uL;
20004794:	f04f 0300 	mov.w	r3, #0
20004798:	607b      	str	r3, [r7, #4]
            }
        }
    }
    
    if ( 0uL == fclk )
2000479a:	687b      	ldr	r3, [r7, #4]
2000479c:	2b00      	cmp	r3, #0
2000479e:	d105      	bne.n	200047ac <GetSystemClock+0xd8>
        /* 
         * Could not retrieve FCLK from system boot configuration data. Fall back
         * to using SMARTFUSION_FCLK_FREQ which must then be defined as part of
         * project settings.
         */
        ASSERT( SMARTFUSION_FCLK_FREQ_DEFINED );
200047a0:	be00      	bkpt	0x0000
        fclk = SMARTFUSION_FCLK_FREQ;
200047a2:	f647 0340 	movw	r3, #30784	; 0x7840
200047a6:	f2c0 137d 	movt	r3, #381	; 0x17d
200047aa:	607b      	str	r3, [r7, #4]
    }
    
    return fclk;
200047ac:	687b      	ldr	r3, [r7, #4]
}
200047ae:	4618      	mov	r0, r3
200047b0:	f107 072c 	add.w	r7, r7, #44	; 0x2c
200047b4:	46bd      	mov	sp, r7
200047b6:	bc80      	pop	{r7}
200047b8:	4770      	bx	lr
200047ba:	bf00      	nop

200047bc <__errno>:
200047bc:	f644 03f0 	movw	r3, #18672	; 0x48f0
200047c0:	f2c2 0300 	movt	r3, #8192	; 0x2000
200047c4:	6818      	ldr	r0, [r3, #0]
200047c6:	4770      	bx	lr

200047c8 <__libc_init_array>:
200047c8:	b570      	push	{r4, r5, r6, lr}
200047ca:	f644 06c4 	movw	r6, #18628	; 0x48c4
200047ce:	f644 05c4 	movw	r5, #18628	; 0x48c4
200047d2:	f2c2 0600 	movt	r6, #8192	; 0x2000
200047d6:	f2c2 0500 	movt	r5, #8192	; 0x2000
200047da:	1b76      	subs	r6, r6, r5
200047dc:	10b6      	asrs	r6, r6, #2
200047de:	d006      	beq.n	200047ee <__libc_init_array+0x26>
200047e0:	2400      	movs	r4, #0
200047e2:	f855 3024 	ldr.w	r3, [r5, r4, lsl #2]
200047e6:	3401      	adds	r4, #1
200047e8:	4798      	blx	r3
200047ea:	42a6      	cmp	r6, r4
200047ec:	d8f9      	bhi.n	200047e2 <__libc_init_array+0x1a>
200047ee:	f644 05c4 	movw	r5, #18628	; 0x48c4
200047f2:	f644 06c8 	movw	r6, #18632	; 0x48c8
200047f6:	f2c2 0500 	movt	r5, #8192	; 0x2000
200047fa:	f2c2 0600 	movt	r6, #8192	; 0x2000
200047fe:	1b76      	subs	r6, r6, r5
20004800:	f000 f854 	bl	200048ac <_init>
20004804:	10b6      	asrs	r6, r6, #2
20004806:	d006      	beq.n	20004816 <__libc_init_array+0x4e>
20004808:	2400      	movs	r4, #0
2000480a:	f855 3024 	ldr.w	r3, [r5, r4, lsl #2]
2000480e:	3401      	adds	r4, #1
20004810:	4798      	blx	r3
20004812:	42a6      	cmp	r6, r4
20004814:	d8f9      	bhi.n	2000480a <__libc_init_array+0x42>
20004816:	bd70      	pop	{r4, r5, r6, pc}
20004818:	00000061 	.word	0x00000061
2000481c:	00000064 	.word	0x00000064
20004820:	00000068 	.word	0x00000068
20004824:	0000006b 	.word	0x0000006b
20004828:	00000079 	.word	0x00000079
2000482c:	0000007a 	.word	0x0000007a
20004830:	70616548 	.word	0x70616548
20004834:	646e6120 	.word	0x646e6120
20004838:	61747320 	.word	0x61747320
2000483c:	63206b63 	.word	0x63206b63
20004840:	696c6c6f 	.word	0x696c6c6f
20004844:	6e6f6973 	.word	0x6e6f6973
20004848:	0000000a 	.word	0x0000000a

2000484c <src_dest_to_ctrl_reg_lut>:
2000484c:	00000001 00800003 01000001 01800003     ................
2000485c:	02000001 02800003 03000001 03800003     ................
2000486c:	04000001 04000003 04800001 04800003     ................
2000487c:	05000003 05800001                       ........

20004884 <g_pdma_status_mask>:
20004884:	000c0003 00c00030 0c000300 c0003000     ....0........0..

20004894 <C.18.2576>:
20004894:	00000001 00000002 00000004 00000001     ................

200048a4 <_global_impure_ptr>:
200048a4:	200048f4 00000043                       .H. C...

200048ac <_init>:
200048ac:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
200048ae:	bf00      	nop
200048b0:	bcf8      	pop	{r3, r4, r5, r6, r7}
200048b2:	bc08      	pop	{r3}
200048b4:	469e      	mov	lr, r3
200048b6:	4770      	bx	lr

200048b8 <_fini>:
200048b8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
200048ba:	bf00      	nop
200048bc:	bcf8      	pop	{r3, r4, r5, r6, r7}
200048be:	bc08      	pop	{r3}
200048c0:	469e      	mov	lr, r3
200048c2:	4770      	bx	lr

200048c4 <__frame_dummy_init_array_entry>:
200048c4:	0479 2000                                   y.. 

200048c8 <__do_global_dtors_aux_fini_array_entry>:
200048c8:	0465 2000                                   e.. 
