`timescale 1 ns/100 ps
// Version: 10.0 10.0.9.37


module Loading_Booting_EMC(
       EMC_CLK,
       EMC_CS0_N,
       EMC_CS1_N,
       EMC_OEN0_N,
       EMC_OEN1_N,
       EMC_RW_N,
       UART_0_TXD,
       UART_0_RXD,
       SPI_1_DO,
       SPI_1_SS,
       SPI_1_CLK,
       SPI_1_DI,
       MSS_RESET_N,
       MAINXIN,
       M2F_GPO_1,
       M2F_GPO_0,
       M2F_GPO_2,
       EMC_DB,
       EMC_AB,
       EMC_BYTEN
    );
output EMC_CLK;
output EMC_CS0_N;
output EMC_CS1_N;
output EMC_OEN0_N;
output EMC_OEN1_N;
output EMC_RW_N;
output UART_0_TXD;
input  UART_0_RXD;
output SPI_1_DO;
inout  SPI_1_SS;
inout  SPI_1_CLK;
input  SPI_1_DI;
input  MSS_RESET_N;
input  MAINXIN;
output M2F_GPO_1;
output M2F_GPO_0;
output M2F_GPO_2;
inout  [15:0] EMC_DB;
output [25:0] EMC_AB;
output [1:0] EMC_BYTEN;

    wire GND_net, VCC_net;
    
    VCC VCC (.Y(VCC_net));
    GND GND (.Y(GND_net));
    emcFlashImage emcFlashImage (.EMC_CLK(EMC_CLK), .EMC_CS0_N(
        EMC_CS0_N), .EMC_CS1_N(EMC_CS1_N), .EMC_OEN0_N(EMC_OEN0_N), 
        .EMC_OEN1_N(EMC_OEN1_N), .EMC_RW_N(EMC_RW_N), .UART_0_TXD(
        UART_0_TXD), .UART_0_RXD(UART_0_RXD), .SPI_1_DI(SPI_1_DI), 
        .SPI_1_DO(SPI_1_DO), .SPI_1_CLK(SPI_1_CLK), .SPI_1_SS(SPI_1_SS)
        , .MSS_RESET_N(MSS_RESET_N), .MAINXIN(MAINXIN), .M2F_GPO_2(
        M2F_GPO_2), .M2F_GPO_1(M2F_GPO_1), .M2F_GPO_0(M2F_GPO_0), 
        .EMC_DB({EMC_DB[15], EMC_DB[14], EMC_DB[13], EMC_DB[12], 
        EMC_DB[11], EMC_DB[10], EMC_DB[9], EMC_DB[8], EMC_DB[7], 
        EMC_DB[6], EMC_DB[5], EMC_DB[4], EMC_DB[3], EMC_DB[2], 
        EMC_DB[1], EMC_DB[0]}), .EMC_AB({EMC_AB[25], EMC_AB[24], 
        EMC_AB[23], EMC_AB[22], EMC_AB[21], EMC_AB[20], EMC_AB[19], 
        EMC_AB[18], EMC_AB[17], EMC_AB[16], EMC_AB[15], EMC_AB[14], 
        EMC_AB[13], EMC_AB[12], EMC_AB[11], EMC_AB[10], EMC_AB[9], 
        EMC_AB[8], EMC_AB[7], EMC_AB[6], EMC_AB[5], EMC_AB[4], 
        EMC_AB[3], EMC_AB[2], EMC_AB[1], EMC_AB[0]}), .EMC_BYTEN({
        EMC_BYTEN[1], EMC_BYTEN[0]}));
    
endmodule
