library verilog;
use verilog.vl_types.all;
entity EMC_TOP is
    port(
        MAINXIN         : in     vl_logic;
        M2F_GPO_2       : out    vl_logic;
        M2F_GPO_1       : out    vl_logic;
        M2F_GPO_0       : out    vl_logic;
        UART_0_TXD      : out    vl_logic;
        UART_0_RXD      : in     vl_logic;
        SPI_1_DI        : in     vl_logic;
        SPI_1_DO        : out    vl_logic;
        SPI_1_CLK       : inout  vl_logic;
        SPI_1_SS        : inout  vl_logic;
        EMC_DB          : inout  vl_logic_vector(15 downto 0);
        EMC_AB          : out    vl_logic_vector(25 downto 0);
        EMC_BYTEN       : out    vl_logic_vector(1 downto 0);
        EMC_CS0_N       : out    vl_logic;
        EMC_CS1_N       : out    vl_logic;
        EMC_OEN0_N      : out    vl_logic;
        EMC_OEN1_N      : out    vl_logic;
        EMC_CLK         : out    vl_logic;
        EMC_RW_N        : out    vl_logic;
        MSS_RESET_N     : in     vl_logic
    );
end EMC_TOP;
