@W: MO111 :"c:\a2f_ac343_df\a2f200\component\work\spi_flash_read_write\mss_ccc_0\spi_flash_read_write_tmp_mss_ccc_0_mss_ccc.v":64:7:64:18|Tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module SPI_Flash_Read_Write_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"c:\a2f_ac343_df\a2f200\component\work\spi_flash_read_write\mss_ccc_0\spi_flash_read_write_tmp_mss_ccc_0_mss_ccc.v":63:7:63:20|Tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module SPI_Flash_Read_Write_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"c:\a2f_ac343_df\a2f200\component\work\spi_flash_read_write\mss_ccc_0\spi_flash_read_write_tmp_mss_ccc_0_mss_ccc.v":62:7:62:18|Tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module SPI_Flash_Read_Write_tmp_MSS_CCC_0_MSS_CCC) 
@W: MT462 :"c:\a2f_ac343_df\a2f200\component\work\spi_flash_read_write\mss_ccc_0\spi_flash_read_write_tmp_mss_ccc_0_mss_ccc.v":80:40:80:47|Net SPI_Flash_Read_Write_0.MSS_ADLIB_INST_FCLK appears to be an unidentified clock source. Assuming default frequency. 
@W: MT246 :"c:\a2f_ac343_df\a2f200\component\work\spi_flash_read_write\spi_flash_read_write.v":52:54:52:65|Blackbox TRIBUFF_MSS is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"c:\a2f_ac343_df\a2f200\component\work\spi_flash_read_write\mss_ccc_0\spi_flash_read_write_tmp_mss_ccc_0_mss_ccc.v":98:15:98:22|Blackbox MSS_XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock SPI_Flash_Read_Write|MSS_ADLIB_INST_EMCCLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:SPI_Flash_Read_Write_0.MSS_ADLIB_INST_EMCCLK"
