@N|Running in 32-bit mode
@N: CG364 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v":23:7:23:15|Synthesizing module INBUF_MSS
@N: CG364 :"C:\Microsemi\Libero_v10.0\Synopsys\synplify_F201109M\lib\proasic\smartfusion.v":1868:7:1868:9|Synthesizing module VCC
@N: CG364 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v":37:7:37:16|Synthesizing module OUTBUF_MSS
@N: CG364 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v":151:7:151:13|Synthesizing module MSS_CCC
@N: CG364 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v":1:7:1:16|Synthesizing module MSS_XTLOSC
@N: CG364 :"C:\Microsemi\Libero_v10.0\Synopsys\synplify_F201109M\lib\proasic\smartfusion.v":1141:7:1141:9|Synthesizing module GND
@N: CG364 :"C:\A2F_AC339_DF\A2F500\Verilog\component\work\MSS_top_level\MSS_CCC_0\MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v":5:7:5:41|Synthesizing module MSS_top_level_tmp_MSS_CCC_0_MSS_CCC
@N: CG364 :"C:\A2F_AC339_DF\A2F500\Verilog\component\work\MSS_top_level\mss_tshell.v":1:7:1:13|Synthesizing module MSS_APB
@N: CG364 :"C:\A2F_AC339_DF\A2F500\Verilog\component\work\MSS_top_level\MSS_top_level.v":5:7:5:19|Synthesizing module MSS_top_level
@N: CG364 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3_muxptob3.v":13:0:13:5|Synthesizing module CAPB3O
@N: CG364 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":13:0:13:7|Synthesizing module CoreAPB3
@N: CG364 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":3:0:3:12|Synthesizing module CoreInterrupt
@N: CG179 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":1243:0:1243:16|Removing redundant assignment
@N: CG179 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":1307:0:1307:16|Removing redundant assignment
@N: CG179 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":1371:0:1371:16|Removing redundant assignment
@N: CG179 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":1435:0:1435:16|Removing redundant assignment
@N: CG364 :"C:\A2F_AC339_DF\A2F500\Verilog\hdl\Interrupt_Source.v":21:7:21:22|Synthesizing module Interrupt_Source
@N: CG364 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vlog\core_obfuscated\coregpio.v":9:0:9:7|Synthesizing module CoreGPIO
@N: CG179 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vlog\core_obfuscated\coregpio.v":3305:0:3309:0|Removing redundant assignment
@N: CG364 :"C:\A2F_AC339_DF\A2F500\Verilog\component\work\Interrupt_Generator\Interrupt_Generator.v":5:7:5:25|Synthesizing module Interrupt_Generator
@N: CG364 :"C:\A2F_AC339_DF\A2F500\Verilog\component\work\top_level\top_level.v":5:7:5:15|Synthesizing module top_level

