#Build: Synplify Pro E-2010.09A-1, Build 006R, Oct 6 2010 #install: C:\Actel9.1SPB\Libero_v9.1\Synopsys\synplify_E201009A-1 #OS: Windows XP 5.1 #Hostname: VXP-SUDEEPS #Implementation: synthesis #Fri Feb 18 10:57:34 2011 $ Start of Compile #Fri Feb 18 10:57:34 2011 Synopsys VHDL Compiler, version comp520rcp1, Build 028R, built Sep 23 2010 @N: : | Running in 32-bit mode Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved @N:CD720 : std.vhd(123) | Setting time resolution to ns @N: : top_level.vhd(10) | Top entity is set to top_level. VHDL syntax check successful! Options changed - recompiling @N:CD630 : top_level.vhd(10) | Synthesizing work.top_level.def_arch @N:CD630 : smartfusion.vhd(1784) | Synthesizing smartfusion.gnd.syn_black_box Post processing for smartfusion.gnd.syn_black_box @N:CD630 : Interrupt_Generator.vhd(10) | Synthesizing work.interrupt_generator.def_arch @N:CD630 : coregpio.vhd(13) | Synthesizing coregpio_lib.coregpio.cgpioo @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @N:CD364 : coregpio.vhd(516) | Removed redundant assignment @N:CD364 : coregpio.vhd(592) | Removed redundant assignment @N:CD364 : coregpio.vhd(595) | Removed redundant assignment @W:CD434 : coregpio.vhd(909) | Signal paddr in the sensitivity list is not used in the process Post processing for coregpio_lib.coregpio.cgpioo @W:CL169 : coregpio.vhd(546) | Pruning Register CGPIOiOI.2.CGPIOI1I.CGPIOOLL_11(2) @W:CL169 : coregpio.vhd(526) | Pruning Register CGPIOiOI.2.CGPIOI1I.CGPIOlll_11(2) @W:CL169 : coregpio.vhd(546) | Pruning Register CGPIOiOI.1.CGPIOI1I.CGPIOOLL_7(1) @W:CL169 : coregpio.vhd(526) | Pruning Register CGPIOiOI.1.CGPIOI1I.CGPIOlll_7(1) @W:CL169 : coregpio.vhd(546) | Pruning Register CGPIOiOI.0.CGPIOI1I.CGPIOOLL_3(0) @W:CL169 : coregpio.vhd(526) | Pruning Register CGPIOiOI.0.CGPIOI1I.CGPIOlll_3(0) @N:CD630 : Interrupt_Source.vhd(27) | Synthesizing work.interrupt_source.behav Post processing for work.interrupt_source.behav @N:CD630 : smartfusion.vhd(2742) | Synthesizing smartfusion.vcc.syn_black_box Post processing for smartfusion.vcc.syn_black_box @N:CD630 : CoreInterrupt.vhd(4) | Synthesizing work.coreinterrupt.coreinterrupt_o Post processing for work.coreinterrupt.coreinterrupt_o @W:CL190 : CoreInterrupt.vhd(216) | Optimizing register bit CoreInTERRUPT_l0l(0) to a constant 0 @W:CL190 : CoreInterrupt.vhd(216) | Optimizing register bit CoreInTERRUPT_l0l(1) to a constant 0 @W:CL190 : CoreInterrupt.vhd(216) | Optimizing register bit CoreInTERRUPT_l0l(2) to a constant 0 @W:CL190 : CoreInterrupt.vhd(216) | Optimizing register bit CoreInTERRUPT_l0l(3) to a constant 0 @W:CL190 : CoreInterrupt.vhd(216) | Optimizing register bit CoreInTERRUPT_l0l(4) to a constant 0 @W:CL190 : CoreInterrupt.vhd(216) | Optimizing register bit CoreInTERRUPT_l0l(5) to a constant 0 @W:CL190 : CoreInterrupt.vhd(216) | Optimizing register bit CoreInTERRUPT_l0l(6) to a constant 0 @W:CL190 : CoreInterrupt.vhd(216) | Optimizing register bit CoreInTERRUPT_l0l(7) to a constant 0 @W:CL190 : CoreInterrupt.vhd(234) | Optimizing register bit CoreInterrupT_I0L(0) to a constant 0 @W:CL190 : CoreInterrupt.vhd(234) | Optimizing register bit CoreInterrupT_I0L(1) to a constant 0 @W:CL190 : CoreInterrupt.vhd(234) | Optimizing register bit CoreInterrupT_I0L(2) to a constant 0 @W:CL190 : CoreInterrupt.vhd(234) | Optimizing register bit CoreInterrupT_I0L(3) to a constant 0 @W:CL190 : CoreInterrupt.vhd(234) | Optimizing register bit CoreInterrupT_I0L(4) to a constant 0 @W:CL190 : CoreInterrupt.vhd(234) | Optimizing register bit CoreInterrupT_I0L(5) to a constant 0 @W:CL190 : CoreInterrupt.vhd(234) | Optimizing register bit CoreInterrupT_I0L(6) to a constant 0 @W:CL190 : CoreInterrupt.vhd(234) | Optimizing register bit CoreInterrupT_I0L(7) to a constant 0 @W:CL169 : CoreInterrupt.vhd(216) | Pruning Register CoreInTERRUPT_l0l(7 downto 0) @W:CL169 : CoreInterrupt.vhd(234) | Pruning Register CoreInterrupT_I0L(7 downto 0) Post processing for work.interrupt_generator.def_arch @W:CL168 : Interrupt_Generator.vhd(272) | Pruning instance VCC - not in use ... @N:CD630 : coreapb3.vhd(14) | Synthesizing coreapb3_lib.coreapb3.capb3i0l @W:CD604 : coreapb3.vhd(439) | OTHERS clause is not synthesized @N:CD630 : coreapb3_muxptob3.vhd(14) | Synthesizing coreapb3_lib.capb3o.capb3ll @W:CD604 : coreapb3_muxptob3.vhd(152) | OTHERS clause is not synthesized @W:CD604 : coreapb3_muxptob3.vhd(195) | OTHERS clause is not synthesized @W:CD604 : coreapb3_muxptob3.vhd(238) | OTHERS clause is not synthesized Post processing for coreapb3_lib.capb3o.capb3ll Post processing for coreapb3_lib.coreapb3.capb3i0l @N:CD630 : MSS_top_level.vhd(8) | Synthesizing work.mss_top_level.def_arch @N:CD630 : mss_comps.vhd(4) | Synthesizing work.inbuf_mss.def_arch Post processing for work.inbuf_mss.def_arch @N:CD630 : mss_tshell.vhd(4) | Synthesizing work.mss_apb.def_arch Post processing for work.mss_apb.def_arch @N:CD630 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.vhd(8) | Synthesizing work.mss_top_level_tmp_mss_ccc_0_mss_ccc.def_arch @N:CD630 : mss_comps.vhd(432) | Synthesizing work.mss_xtlosc.def_arch Post processing for work.mss_xtlosc.def_arch @N:CD630 : mss_comps.vhd(472) | Synthesizing work.mss_ccc.def_arch Post processing for work.mss_ccc.def_arch Post processing for work.mss_top_level_tmp_mss_ccc_0_mss_ccc.def_arch @W:CL240 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.vhd(38) | LPXIN_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible @W:CL240 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.vhd(37) | MAINXIN_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible @W:CL240 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.vhd(36) | RCOSC_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible @N:CD630 : mss_comps.vhd(24) | Synthesizing work.outbuf_mss.def_arch Post processing for work.outbuf_mss.def_arch Post processing for work.mss_top_level.def_arch Post processing for work.top_level.def_arch @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.vhd(10) | Input CLKA is unused @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.vhd(11) | Input CLKA_PAD is unused @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.vhd(12) | Input CLKA_PADP is unused @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.vhd(13) | Input CLKA_PADN is unused @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.vhd(14) | Input CLKB is unused @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.vhd(15) | Input CLKB_PAD is unused @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.vhd(16) | Input CLKB_PADP is unused @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.vhd(17) | Input CLKB_PADN is unused @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.vhd(18) | Input CLKC is unused @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.vhd(19) | Input CLKC_PAD is unused @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.vhd(20) | Input CLKC_PADP is unused @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.vhd(21) | Input CLKC_PADN is unused @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.vhd(23) | Input LPXIN is unused @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.vhd(24) | Input MAC_CLK is unused @W:CL246 : coreapb3.vhd(35) | Input port bits 23 to 12 of paddr(23 downto 0) are unused @W:CL159 : coreapb3.vhd(33) | Input presetn is unused @W:CL159 : coreapb3.vhd(34) | Input pclk is unused @W:CL159 : coreapb3.vhd(66) | Input PRDATAS2 is unused @W:CL159 : coreapb3.vhd(67) | Input PRDATAS3 is unused @W:CL159 : coreapb3.vhd(68) | Input PRDATAS4 is unused @W:CL159 : coreapb3.vhd(69) | Input PRDATAS5 is unused @W:CL159 : coreapb3.vhd(70) | Input PRDATAS6 is unused @W:CL159 : coreapb3.vhd(71) | Input PRDATAS7 is unused @W:CL159 : coreapb3.vhd(72) | Input PRDATAS8 is unused @W:CL159 : coreapb3.vhd(73) | Input PRDATAS9 is unused @W:CL159 : coreapb3.vhd(74) | Input PRDATAS10 is unused @W:CL159 : coreapb3.vhd(75) | Input PRDATAS11 is unused @W:CL159 : coreapb3.vhd(76) | Input PRDATAS12 is unused @W:CL159 : coreapb3.vhd(77) | Input PRDATAS13 is unused @W:CL159 : coreapb3.vhd(78) | Input PRDATAS14 is unused @W:CL159 : coreapb3.vhd(79) | Input PRDATAS15 is unused @W:CL159 : coreapb3.vhd(82) | Input preadys2 is unused @W:CL159 : coreapb3.vhd(83) | Input preADYS3 is unused @W:CL159 : coreapb3.vhd(84) | Input preadys4 is unused @W:CL159 : coreapb3.vhd(85) | Input PREADYs5 is unused @W:CL159 : coreapb3.vhd(86) | Input preadyS6 is unused @W:CL159 : coreapb3.vhd(87) | Input PREadys7 is unused @W:CL159 : coreapb3.vhd(88) | Input pREADYS8 is unused @W:CL159 : coreapb3.vhd(89) | Input preADYS9 is unused @W:CL159 : coreapb3.vhd(90) | Input preadys10 is unused @W:CL159 : coreapb3.vhd(91) | Input preaDYS11 is unused @W:CL159 : coreapb3.vhd(92) | Input PREADYS12 is unused @W:CL159 : coreapb3.vhd(93) | Input PREadys13 is unused @W:CL159 : coreapb3.vhd(94) | Input preADYS14 is unused @W:CL159 : coreapb3.vhd(95) | Input PREAdys15 is unused @W:CL159 : coreapb3.vhd(98) | Input pslverrs2 is unused @W:CL159 : coreapb3.vhd(99) | Input pslverrS3 is unused @W:CL159 : coreapb3.vhd(100) | Input pSLVERRS4 is unused @W:CL159 : coreapb3.vhd(101) | Input PSLVERRS5 is unused @W:CL159 : coreapb3.vhd(102) | Input PSLVERRS6 is unused @W:CL159 : coreapb3.vhd(103) | Input pslvERRS7 is unused @W:CL159 : coreapb3.vhd(104) | Input pslverrs8 is unused @W:CL159 : coreapb3.vhd(105) | Input PSLVERRS9 is unused @W:CL159 : coreapb3.vhd(106) | Input PSLVERRS10 is unused @W:CL159 : coreapb3.vhd(107) | Input pslverRS11 is unused @W:CL159 : coreapb3.vhd(108) | Input PSLverrs12 is unused @W:CL159 : coreapb3.vhd(109) | Input PSLVERRS13 is unused @W:CL159 : coreapb3.vhd(110) | Input pslverrs14 is unused @W:CL159 : coreapb3.vhd(111) | Input pSLVERRS15 is unused @W:CL159 : CoreInterrupt.vhd(16) | Input fiqSource7 is unused @W:CL159 : CoreInterrupt.vhd(17) | Input fiqSOURCE6 is unused @W:CL159 : CoreInterrupt.vhd(18) | Input fiqSource5 is unused @W:CL159 : CoreInterrupt.vhd(19) | Input FIQSource4 is unused @W:CL159 : CoreInterrupt.vhd(20) | Input FIQSOURCe3 is unused @W:CL159 : CoreInterrupt.vhd(21) | Input fiqSourcE2 is unused @W:CL159 : CoreInterrupt.vhd(22) | Input FiqSource1 is unused @W:CL159 : CoreInterrupt.vhd(23) | Input FiqSource0 is unused @W:CL246 : coregpio.vhd(154) | Input port bits 31 to 3 of pwdata(31 downto 0) are unused @END Process took 0h:00m:02s realtime, 0h:00m:01s cputime # Fri Feb 18 10:57:37 2011 ###########################################################] Synopsys Actel Technology Mapper, Version mapact, Build 023R, Built Sep 29 2010 09:29:00 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved Product Version E-2010.09A-1 @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled Available hyper_sources - for debug and ip models None Found @W: : mss_top_level_tmp_mss_ccc_0_mss_ccc.vhd(118) | Net MSS_top_level_0.MSS_ADLIB_INST_FCLK appears to be a clock source which was not identfied. Assuming default frequency. @W: : mss_top_level_tmp_mss_ccc_0_mss_ccc.vhd(118) | Net Interrupt_Generator_0/PCLK appears to be a clock source which was not identfied. Assuming default frequency. Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 60MB peak: 60MB) @N:MF238 : interrupt_source.vhd(91) | Found 32 bit incrementor, 'un4_counter1_1[31:0]' @N:MF238 : interrupt_source.vhd(110) | Found 32 bit incrementor, 'un3_counter2_1[31:0]' Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 61MB peak: 62MB) Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 61MB peak: 62MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 61MB peak: 62MB) Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 62MB peak: 62MB) Finished Early Timing Optimization (Time elapsed 0h:00m:03s; Memory used current: 62MB peak: 62MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:03s; Memory used current: 62MB peak: 62MB) Finished preparing to map (Time elapsed 0h:00m:03s; Memory used current: 62MB peak: 62MB) High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes ------------------------------------------------------------------------------------------------------------------ MSS_top_level_0.MSS_CCC_0.I_MSSCCC / LOCK 181 : 181 asynchronous set/reset MSS_top_level_0.MSS_ADLIB_INST / MSSPADDR[2] 101 MSS_top_level_0.MSS_ADLIB_INST / MSSPADDR[3] 71 CoreAPB3_0.CAPB3iool_0_a2[0] / Y 35 Interrupt_Generator_0.CoreInterrupt_0.un1_coreinterrupt_l0l13_i_a2_0_a4 / Y 32 Interrupt_Generator_0.CoreInterrupt_0.un1_coreinterrupt_l0l13_1_i_a2_0_a4 / Y 32 Interrupt_Generator_0.CoreInterrupt_0.COREINTErrupt_i1_0_i_o4[6] / Y 32 ================================================================================================================== Replicating Combinational Instance Interrupt_Generator_0.CoreInterrupt_0.COREINTErrupt_i1_0_i_o4[6], fanout 32 segments 2 Replicating Combinational Instance Interrupt_Generator_0.CoreInterrupt_0.un1_coreinterrupt_l0l13_1_i_a2_0_a4, fanout 32 segments 2 Replicating Combinational Instance Interrupt_Generator_0.CoreInterrupt_0.un1_coreinterrupt_l0l13_i_a2_0_a4, fanout 32 segments 2 Replicating Combinational Instance CoreAPB3_0.CAPB3iool_0_a2[0], fanout 35 segments 2 Finished technology mapping (Time elapsed 0h:00m:03s; Memory used current: 63MB peak: 64MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:03s; Memory used current: 63MB peak: 64MB) Added 0 Buffers Added 4 Cells via replication Added 0 Sequential Cells via replication Added 4 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:03s; Memory used current: 63MB peak: 64MB) Writing Analyst data base C:\Actelprj\App_notes_upadtes\New\SmartFusion_Using_FABINT_to_Interrupt_MSS_DF\Hardware\A2F500\VHDL\fabint_fab_controller\synthesis\top_level.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:03s; Memory used current: 62MB peak: 64MB) Writing EDIF Netlist and constraint files E-2010.09A-1 Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:04s; Memory used current: 62MB peak: 64MB) @W:MT246 : mss_top_level_tmp_mss_ccc_0_mss_ccc.vhd(156) | Blackbox MSS_XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock MSS_top_level|MSS_ADLIB_INST_EMCCLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:MSS_top_level_0.MSS_ADLIB_INST_EMCCLK" @W:MT420 : | Found inferred clock MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:MSS_top_level_0_FAB_CLK" @W:MT420 : | Found inferred clock MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:MSS_top_level_0.MSS_ADLIB_INST_FCLK" ##### START OF TIMING REPORT #####[ # Timing Report written on Fri Feb 18 10:57:43 2011 # Top view: top_level Library name: smartfusion Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree ) Requested Frequency: 100.0 MHz Wire load mode: top Wire load model: smartfusion Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: -1.853 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock 100.0 MHz 84.4 MHz 10.000 11.854 -1.853 inferred Inferred_clkgroup_1 MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock 100.0 MHz 100.9 MHz 10.000 9.910 0.090 inferred Inferred_clkgroup_2 ================================================================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock | 10.000 -1.854 | No paths - | No paths - | No paths - MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock | 10.000 0.090 | No paths - | No paths - | No paths - =============================================================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[2] Z\\CoreAPB3_0_APBmslave1_PADDR_\[2\]\\ 2.679 -1.853 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[1] Z\\CoreAPB3_0_APBmslave1_PADDR_\[1\]\\ 2.679 -0.644 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[0] Z\\CoreAPB3_0_APBmslave1_PADDR_\[0\]\\ 2.679 -0.505 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[6] Z\\CoreAPB3_0_APBmslave1_PADDR_\[6\]\\ 2.679 -0.505 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[3] Z\\CoreAPB3_0_APBmslave1_PADDR_\[3\]\\ 2.679 -0.408 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[7] Z\\CoreAPB3_0_APBmslave1_PADDR_\[7\]\\ 2.679 -0.395 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[11] Z\\MSS_top_level_0_MSS_MASTER_APB_PADDR_\[11\]\\ 2.679 0.639 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[10] Z\\MSS_top_level_0_MSS_MASTER_APB_PADDR_\[10\]\\ 2.679 0.778 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[9] Z\\MSS_top_level_0_MSS_MASTER_APB_PADDR_\[9\]\\ 2.679 0.865 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[4] Z\\CoreAPB3_0_APBmslave1_PADDR_\[4\]\\ 2.679 1.157 ================================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[2] Z\\MSS_top_level_0_MSS_MASTER_APB_PRDATA_\[2\]\\ 10.000 -1.853 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[0] Z\\MSS_top_level_0_MSS_MASTER_APB_PRDATA_\[0\]\\ 10.000 0.795 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[1] Z\\MSS_top_level_0_MSS_MASTER_APB_PRDATA_\[1\]\\ 10.000 0.865 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[20] Z\\MSS_top_level_0_MSS_MASTER_APB_PRDATA_\[20\]\\ 10.000 1.841 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[21] Z\\MSS_top_level_0_MSS_MASTER_APB_PRDATA_\[21\]\\ 10.000 1.841 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[22] Z\\MSS_top_level_0_MSS_MASTER_APB_PRDATA_\[22\]\\ 10.000 1.841 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[23] Z\\MSS_top_level_0_MSS_MASTER_APB_PRDATA_\[23\]\\ 10.000 1.841 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[24] Z\\MSS_top_level_0_MSS_MASTER_APB_PRDATA_\[24\]\\ 10.000 1.841 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[25] Z\\MSS_top_level_0_MSS_MASTER_APB_PRDATA_\[25\]\\ 10.000 1.841 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[26] Z\\MSS_top_level_0_MSS_MASTER_APB_PRDATA_\[26\]\\ 10.000 1.841 ===================================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.000 - Propagation time: 11.854 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.854 Number of logic level(s): 4 Starting point: MSS_top_level_0.MSS_ADLIB_INST / MSSPADDR[2] Ending point: MSS_top_level_0.MSS_ADLIB_INST / MSSPRDATA[2] The start point is clocked by MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK The end point is clocked by MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------ MSS_top_level_0.MSS_ADLIB_INST MSS_APB MSSPADDR[2] Out 2.679 2.679 - Z\\CoreAPB3_0_APBmslave1_PADDR_\[2\]\\ Net - - 3.843 - 101 Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_1_3[0] OR2A B In - 6.522 - Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_1_3[0] OR2A Y Out 0.646 7.168 - CGPIOL1_2_o2_1_3[0] Net - - 0.386 - 2 Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_0[0] NOR3 C In - 7.554 - Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_0[0] NOR3 Y Out 0.751 8.305 - N_21 Net - - 1.776 - 11 CoreAPB3_0.CAPB3O1II.PRDATA_a0[2] OR3C C In - 10.081 - CoreAPB3_0.CAPB3O1II.PRDATA_a0[2] OR3C Y Out 0.666 10.746 - N_1_3 Net - - 0.322 - 1 CoreAPB3_0.CAPB3O1II.PRDATA_0[2] OR3C A In - 11.068 - CoreAPB3_0.CAPB3O1II.PRDATA_0[2] OR3C Y Out 0.464 11.532 - Z\\MSS_top_level_0_MSS_MASTER_APB_PRDATA_\[2\]\\ Net - - 0.322 - 1 MSS_top_level_0.MSS_ADLIB_INST MSS_APB MSSPRDATA[2] In - 11.854 - ============================================================================================================================== Total path delay (propagation time + setup) of 11.854 is 5.206(43.9%) logic and 6.648(56.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.000 - Propagation time: 10.644 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.644 Number of logic level(s): 6 Starting point: MSS_top_level_0.MSS_ADLIB_INST / MSSPADDR[1] Ending point: MSS_top_level_0.MSS_ADLIB_INST / MSSPRDATA[2] The start point is clocked by MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK The end point is clocked by MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------- MSS_top_level_0.MSS_ADLIB_INST MSS_APB MSSPADDR[1] Out 2.679 2.679 - Z\\CoreAPB3_0_APBmslave1_PADDR_\[1\]\\ Net - - 0.322 - 1 Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_1_2_0[0] OR2 B In - 3.000 - Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_1_2_0[0] OR2 Y Out 0.646 3.647 - CGPIOL1_2_o2_1_2_0[0] Net - - 0.322 - 1 Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_1_2[0] NOR2 B In - 3.968 - Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_1_2[0] NOR2 Y Out 0.646 4.615 - CGPIOL1_2_o2_1_2[0] Net - - 0.806 - 3 Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_1_3[0] OR2A A In - 5.421 - Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_1_3[0] OR2A Y Out 0.537 5.958 - CGPIOL1_2_o2_1_3[0] Net - - 0.386 - 2 Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_0[0] NOR3 C In - 6.344 - Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_0[0] NOR3 Y Out 0.751 7.095 - N_21 Net - - 1.776 - 11 CoreAPB3_0.CAPB3O1II.PRDATA_a0[2] OR3C C In - 8.871 - CoreAPB3_0.CAPB3O1II.PRDATA_a0[2] OR3C Y Out 0.666 9.537 - N_1_3 Net - - 0.322 - 1 CoreAPB3_0.CAPB3O1II.PRDATA_0[2] OR3C A In - 9.858 - CoreAPB3_0.CAPB3O1II.PRDATA_0[2] OR3C Y Out 0.464 10.322 - Z\\MSS_top_level_0_MSS_MASTER_APB_PRDATA_\[2\]\\ Net - - 0.322 - 1 MSS_top_level_0.MSS_ADLIB_INST MSS_APB MSSPRDATA[2] In - 10.644 - ================================================================================================================================ Total path delay (propagation time + setup) of 10.644 is 6.389(60.0%) logic and 4.254(40.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.000 - Propagation time: 10.505 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.505 Number of logic level(s): 6 Starting point: MSS_top_level_0.MSS_ADLIB_INST / MSSPADDR[0] Ending point: MSS_top_level_0.MSS_ADLIB_INST / MSSPRDATA[2] The start point is clocked by MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK The end point is clocked by MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------- MSS_top_level_0.MSS_ADLIB_INST MSS_APB MSSPADDR[0] Out 2.679 2.679 - Z\\CoreAPB3_0_APBmslave1_PADDR_\[0\]\\ Net - - 0.322 - 1 Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_1_2_0[0] OR2 A In - 3.000 - Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_1_2_0[0] OR2 Y Out 0.507 3.508 - CGPIOL1_2_o2_1_2_0[0] Net - - 0.322 - 1 Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_1_2[0] NOR2 B In - 3.829 - Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_1_2[0] NOR2 Y Out 0.646 4.476 - CGPIOL1_2_o2_1_2[0] Net - - 0.806 - 3 Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_1_3[0] OR2A A In - 5.282 - Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_1_3[0] OR2A Y Out 0.537 5.819 - CGPIOL1_2_o2_1_3[0] Net - - 0.386 - 2 Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_0[0] NOR3 C In - 6.205 - Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_0[0] NOR3 Y Out 0.751 6.956 - N_21 Net - - 1.776 - 11 CoreAPB3_0.CAPB3O1II.PRDATA_a0[2] OR3C C In - 8.732 - CoreAPB3_0.CAPB3O1II.PRDATA_a0[2] OR3C Y Out 0.666 9.398 - N_1_3 Net - - 0.322 - 1 CoreAPB3_0.CAPB3O1II.PRDATA_0[2] OR3C A In - 9.719 - CoreAPB3_0.CAPB3O1II.PRDATA_0[2] OR3C Y Out 0.464 10.183 - Z\\MSS_top_level_0_MSS_MASTER_APB_PRDATA_\[2\]\\ Net - - 0.322 - 1 MSS_top_level_0.MSS_ADLIB_INST MSS_APB MSSPRDATA[2] In - 10.505 - ================================================================================================================================ Total path delay (propagation time + setup) of 10.505 is 6.250(59.5%) logic and 4.254(40.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.000 - Propagation time: 10.505 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.505 Number of logic level(s): 6 Starting point: MSS_top_level_0.MSS_ADLIB_INST / MSSPADDR[6] Ending point: MSS_top_level_0.MSS_ADLIB_INST / MSSPRDATA[2] The start point is clocked by MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK The end point is clocked by MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------- MSS_top_level_0.MSS_ADLIB_INST MSS_APB MSSPADDR[6] Out 2.679 2.679 - Z\\CoreAPB3_0_APBmslave1_PADDR_\[6\]\\ Net - - 0.322 - 1 Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_1_2_1[0] OR2A B In - 3.000 - Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_1_2_1[0] OR2A Y Out 0.646 3.647 - CGPIOL1_2_o2_1_2_1[0] Net - - 0.322 - 1 Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_1_2[0] NOR2 A In - 3.968 - Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_1_2[0] NOR2 Y Out 0.507 4.476 - CGPIOL1_2_o2_1_2[0] Net - - 0.806 - 3 Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_1_3[0] OR2A A In - 5.282 - Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_1_3[0] OR2A Y Out 0.537 5.819 - CGPIOL1_2_o2_1_3[0] Net - - 0.386 - 2 Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_0[0] NOR3 C In - 6.205 - Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_0[0] NOR3 Y Out 0.751 6.956 - N_21 Net - - 1.776 - 11 CoreAPB3_0.CAPB3O1II.PRDATA_a0[2] OR3C C In - 8.732 - CoreAPB3_0.CAPB3O1II.PRDATA_a0[2] OR3C Y Out 0.666 9.398 - N_1_3 Net - - 0.322 - 1 CoreAPB3_0.CAPB3O1II.PRDATA_0[2] OR3C A In - 9.719 - CoreAPB3_0.CAPB3O1II.PRDATA_0[2] OR3C Y Out 0.464 10.183 - Z\\MSS_top_level_0_MSS_MASTER_APB_PRDATA_\[2\]\\ Net - - 0.322 - 1 MSS_top_level_0.MSS_ADLIB_INST MSS_APB MSSPRDATA[2] In - 10.505 - ================================================================================================================================ Total path delay (propagation time + setup) of 10.505 is 6.250(59.5%) logic and 4.254(40.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.000 - Propagation time: 10.408 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.408 Number of logic level(s): 3 Starting point: MSS_top_level_0.MSS_ADLIB_INST / MSSPADDR[3] Ending point: MSS_top_level_0.MSS_ADLIB_INST / MSSPRDATA[2] The start point is clocked by MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK The end point is clocked by MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------- MSS_top_level_0.MSS_ADLIB_INST MSS_APB MSSPADDR[3] Out 2.679 2.679 - Z\\CoreAPB3_0_APBmslave1_PADDR_\[3\]\\ Net - - 3.466 - 71 Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_0[0] NOR3 B In - 6.144 - Interrupt_Generator_0.CoreGPIO_0.CGPIOL1_2_o2_0[0] NOR3 Y Out 0.714 6.859 - N_21 Net - - 1.776 - 11 CoreAPB3_0.CAPB3O1II.PRDATA_a0[2] OR3C C In - 8.635 - CoreAPB3_0.CAPB3O1II.PRDATA_a0[2] OR3C Y Out 0.666 9.301 - N_1_3 Net - - 0.322 - 1 CoreAPB3_0.CAPB3O1II.PRDATA_0[2] OR3C A In - 9.622 - CoreAPB3_0.CAPB3O1II.PRDATA_0[2] OR3C Y Out 0.464 10.086 - Z\\MSS_top_level_0_MSS_MASTER_APB_PRDATA_\[2\]\\ Net - - 0.322 - 1 MSS_top_level_0.MSS_ADLIB_INST MSS_APB MSSPRDATA[2] In - 10.408 - ============================================================================================================================ Total path delay (propagation time + setup) of 10.408 is 4.523(43.5%) logic and 5.885(56.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Interrupt_Generator_0.Interrupt_Source_0.counter1[3] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter1[3] 0.737 0.090 Interrupt_Generator_0.Interrupt_Source_0.counter2[3] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter2[3] 0.737 0.090 Interrupt_Generator_0.Interrupt_Source_0.counter1[4] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter1[4] 0.737 0.092 Interrupt_Generator_0.Interrupt_Source_0.counter2[4] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter2[4] 0.737 0.092 Interrupt_Generator_0.Interrupt_Source_0.counter1[5] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter1[5] 0.737 0.153 Interrupt_Generator_0.Interrupt_Source_0.counter2[5] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter2[5] 0.737 0.153 Interrupt_Generator_0.Interrupt_Source_0.counter2[1] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter2[1] 0.737 0.403 Interrupt_Generator_0.Interrupt_Source_0.counter2[2] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter2[2] 0.737 0.512 Interrupt_Generator_0.Interrupt_Source_0.counter2[0] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter2[0] 0.737 0.546 Interrupt_Generator_0.Interrupt_Source_0.counter1[1] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter1[1] 0.737 0.567 ============================================================================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Interrupt_Generator_0.Interrupt_Source_0.counter1[28] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D I_203_0 9.461 0.090 Interrupt_Generator_0.Interrupt_Source_0.counter1[29] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D I_210_0 9.461 0.090 Interrupt_Generator_0.Interrupt_Source_0.counter1[30] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D I_217_0 9.461 0.090 Interrupt_Generator_0.Interrupt_Source_0.counter1[31] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D I_224_0 9.461 0.090 Interrupt_Generator_0.Interrupt_Source_0.counter2[28] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D I_203 9.461 0.090 Interrupt_Generator_0.Interrupt_Source_0.counter2[29] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D I_210 9.461 0.090 Interrupt_Generator_0.Interrupt_Source_0.counter2[30] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D I_217 9.461 0.090 Interrupt_Generator_0.Interrupt_Source_0.counter2[31] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D I_224 9.461 0.090 Interrupt_Generator_0.Interrupt_Source_0.counter2[12] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D counter2_2[12] 9.427 0.403 Interrupt_Generator_0.Interrupt_Source_0.counter1[15] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D counter1_3[15] 9.427 0.567 ================================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 9.371 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 0.090 Number of logic level(s): 5 Starting point: Interrupt_Generator_0.Interrupt_Source_0.counter1[3] / Q Ending point: Interrupt_Generator_0.Interrupt_Source_0.counter1[28] / D The start point is clocked by MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------ Interrupt_Generator_0.Interrupt_Source_0.counter1[3] DFN1C0 Q Out 0.737 0.737 - counter1[3] Net - - 1.423 - 6 Interrupt_Generator_0.Interrupt_Source_0.un4_counter1_1.I_34 AND3 A In - 2.160 - Interrupt_Generator_0.Interrupt_Source_0.un4_counter1_1.I_34 AND3 Y Out 0.464 2.624 - DWACT_FINC_E_0[2] Net - - 1.423 - 6 Interrupt_Generator_0.Interrupt_Source_0.un4_counter1_1.I_152 AND3 B In - 4.048 - Interrupt_Generator_0.Interrupt_Source_0.un4_counter1_1.I_152 AND3 Y Out 0.607 4.654 - DWACT_FINC_E_0[29] Net - - 1.423 - 6 Interrupt_Generator_0.Interrupt_Source_0.un4_counter1_1.I_199 AND2 A In - 6.078 - Interrupt_Generator_0.Interrupt_Source_0.un4_counter1_1.I_199 AND2 Y Out 0.514 6.592 - DWACT_FINC_E_0[24] Net - - 1.184 - 4 Interrupt_Generator_0.Interrupt_Source_0.un4_counter1_1.I_202 AND3 A In - 7.776 - Interrupt_Generator_0.Interrupt_Source_0.un4_counter1_1.I_202 AND3 Y Out 0.464 8.240 - N_19_0 Net - - 0.322 - 1 Interrupt_Generator_0.Interrupt_Source_0.un4_counter1_1.I_203 XOR2 A In - 8.561 - Interrupt_Generator_0.Interrupt_Source_0.un4_counter1_1.I_203 XOR2 Y Out 0.488 9.049 - I_203_0 Net - - 0.322 - 1 Interrupt_Generator_0.Interrupt_Source_0.counter1[28] DFN1C0 D In - 9.371 - ============================================================================================================================== Total path delay (propagation time + setup) of 9.910 is 3.813(38.5%) logic and 6.097(61.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Target Part: A2F500M3G_FBGA256_Std Report for cell top_level.def_arch Core Cell usage: cell count area count*area AND2 24 1.0 24.0 AND3 94 1.0 94.0 AO1 5 1.0 5.0 AO1A 3 1.0 3.0 AO1B 6 1.0 6.0 AO1C 2 1.0 2.0 AO1D 1 1.0 1.0 AOI1B 11 1.0 11.0 GND 9 0.0 0.0 INV 2 1.0 2.0 MSS_CCC 1 0.0 0.0 MX2B 65 1.0 65.0 NOR2 20 1.0 20.0 NOR2A 73 1.0 73.0 NOR2B 15 1.0 15.0 NOR3 19 1.0 19.0 NOR3A 13 1.0 13.0 NOR3B 10 1.0 10.0 NOR3C 27 1.0 27.0 OA1C 46 1.0 46.0 OAI1 3 1.0 3.0 OR2 19 1.0 19.0 OR2A 5 1.0 5.0 OR2B 22 1.0 22.0 OR3 4 1.0 4.0 OR3C 4 1.0 4.0 VCC 9 0.0 0.0 XOR2 63 1.0 63.0 DFN1C0 112 1.0 112.0 DFN1E1C0 70 1.0 70.0 DFN1P0 2 1.0 2.0 MSS_APB 1 0.0 0.0 ----- ---------- TOTAL 760 740.0 IO Cell usage: cell count INBUF 1 INBUF_MSS 2 MSS_XTLOSC 1 OUTBUF_MSS 1 ----- TOTAL 5 Core Cells : 740 of 11520 (6%) IO Cells : 5 RAM/ROM Usage Summary Block Rams : 0 of 24 (0%) Mapper successful! Process took 0h:00m:05s realtime, 0h:00m:04s cputime # Fri Feb 18 10:57:43 2011 ###########################################################]