#--  Synopsys, Inc.
#--  Version F-2011.09M
#--  Project file C:\A2F_AC339_DF\A2F500\VHDL\synthesis\run_options.txt
#--  Written on Thu Dec 08 16:58:46 2011


#project files
add_file -vhdl -lib work "C:/A2F_AC339_DF/A2F500/VHDL/component/Actel/SmartFusionMSS/MSS/2.5.106/mss_comps.vhd"
add_file -vhdl -lib work "C:/A2F_AC339_DF/A2F500/VHDL/component/work/MSS_top_level/MSS_CCC_0/MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.vhd"
add_file -vhdl -lib work "C:/A2F_AC339_DF/A2F500/VHDL/component/work/MSS_top_level/mss_tshell.vhd"
add_file -vhdl -lib work "C:/A2F_AC339_DF/A2F500/VHDL/component/work/MSS_top_level/MSS_top_level.vhd"
add_file -vhdl -lib work "C:/A2F_AC339_DF/A2F500/VHDL/component/Actel/DirectCore/CoreInterrupt/1.1.101/rtl/vhdl/o/CoreInterrupt.vhd"
add_file -vhdl -lib work "C:/A2F_AC339_DF/A2F500/VHDL/hdl/Interrupt_Source.vhd"
add_file -vhdl -lib COREGPIO_LIB "C:/A2F_AC339_DF/A2F500/VHDL/component/Actel/DirectCore/CoreGPIO/3.0.120/rtl/vhdl/core_obfuscated/coregpio_pkg.vhd"
add_file -vhdl -lib COREGPIO_LIB "C:/A2F_AC339_DF/A2F500/VHDL/component/Actel/DirectCore/CoreGPIO/3.0.120/rtl/vhdl/core_obfuscated/coregpio.vhd"
add_file -vhdl -lib work "C:/A2F_AC339_DF/A2F500/VHDL/component/work/Interrupt_Generator/Interrupt_Generator.vhd"
add_file -vhdl -lib COREAPB3_LIB "C:/A2F_AC339_DF/A2F500/VHDL/component/Actel/DirectCore/CoreAPB3/3.0.103/rtl/vhdl/core_obfuscated/coreapb3_muxptob3.vhd"
add_file -vhdl -lib COREAPB3_LIB "C:/A2F_AC339_DF/A2F500/VHDL/component/Actel/DirectCore/CoreAPB3/3.0.103/rtl/vhdl/core_obfuscated/coreapb3.vhd"
add_file -vhdl -lib work "C:/A2F_AC339_DF/A2F500/VHDL/component/work/top_level/top_level.vhd"
add_file -constraint "C:/A2F_AC339_DF/A2F500/VHDL/component/work/MSS_top_level/mss_tshell_syn.sdc"


#implementation: "synthesis"
impl -add synthesis -type fpga

#device options
set_option -technology SmartFusion
set_option -part A2F500M3G
set_option -package PQFP208
set_option -speed_grade Std
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "work.top_level"

# mapper_options
set_option -frequency 100.000
set_option -write_verilog 0
set_option -write_vhdl 0

# Actel 500K
set_option -run_prop_extract 1
set_option -maxfan 24
set_option -maxfan_hard3 0
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -report_path 0
set_option -opcond COMWC
set_option -update_models_cp 0
set_option -preserve_registers 0

# Actel 500K
set_option -globalthreshold 50

# NFilter
set_option -popfeed 0
set_option -constprop 0
set_option -createhierarchy 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./top_level.edn"
impl -active "synthesis"
