Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Thu Dec 08 16:59:51 2011


Design: top_level
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                10.951
Frequency (MHz):            91.316
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                8.153
Frequency (MHz):            122.654
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.383
External Hold (ns):         1.283
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               MSS_top_level_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0]
  Delay (ns):                  12.766
  Slack (ns):
  Arrival (ns):                12.766
  Required (ns):
  Setup (ns):                  -1.815
  Minimum Period (ns):         10.951

Path 2
  From:                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[1]
  Delay (ns):                  12.387
  Slack (ns):
  Arrival (ns):                12.387
  Required (ns):
  Setup (ns):                  -1.814
  Minimum Period (ns):         10.573

Path 3
  From:                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[2]
  Delay (ns):                  12.307
  Slack (ns):
  Arrival (ns):                12.307
  Required (ns):
  Setup (ns):                  -1.816
  Minimum Period (ns):         10.491

Path 4
  From:                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[29]
  Delay (ns):                  9.016
  Slack (ns):
  Arrival (ns):                9.016
  Required (ns):
  Setup (ns):                  -1.790
  Minimum Period (ns):         7.226

Path 5
  From:                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[30]
  Delay (ns):                  8.969
  Slack (ns):
  Arrival (ns):                8.969
  Required (ns):
  Setup (ns):                  -1.791
  Minimum Period (ns):         7.178


Expanded Path 1
  From: MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB
  To: MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0]
  data required time                             N/C
  data arrival time                          -   12.766
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.464          cell: ADLIB:MSS_APB_IP
  2.464                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPADDR[1] (f)
               +     0.129          net: MSS_top_level_0/MSS_ADLIB_INST/MSSPADDR[1]INT_NET
  2.593                        MSS_top_level_0/MSS_ADLIB_INST/U_30:PIN2INT (f)
               +     0.079          cell: ADLIB:MSS_IF
  2.672                        MSS_top_level_0/MSS_ADLIB_INST/U_30:PIN2 (f)
               +     0.926          net: _CoreAPB3_0_APBmslave1_PADDR_[1]_
  3.598                        Interrupt_Generator_0/CoreGPIO_0/CGPIOL1_2_o2_1_0[0]:B (f)
               +     0.490          cell: ADLIB:NOR2
  4.088                        Interrupt_Generator_0/CoreGPIO_0/CGPIOL1_2_o2_1_0[0]:Y (r)
               +     0.264          net: Interrupt_Generator_0/CoreGPIO_0/CGPIOL1_2_o2_1_0[0]
  4.352                        Interrupt_Generator_0/CoreGPIO_0/CGPIOL1_2_o2_1_3[0]:B (r)
               +     0.473          cell: ADLIB:NOR3B
  4.825                        Interrupt_Generator_0/CoreGPIO_0/CGPIOL1_2_o2_1_3[0]:Y (r)
               +     0.245          net: Interrupt_Generator_0/CoreGPIO_0/CGPIOL1_2_o2_1_3[0]
  5.070                        Interrupt_Generator_0/CoreGPIO_0/CGPIOL1_2_o2_1[0]:A (r)
               +     0.407          cell: ADLIB:OR2A
  5.477                        Interrupt_Generator_0/CoreGPIO_0/CGPIOL1_2_o2_1[0]:Y (f)
               +     0.998          net: Interrupt_Generator_0/CoreGPIO_0/N_20
  6.475                        Interrupt_Generator_0/CoreGPIO_0/CGPIOL1_2_o2_0[0]:A (f)
               +     0.407          cell: ADLIB:OR2
  6.882                        Interrupt_Generator_0/CoreGPIO_0/CGPIOL1_2_o2_0[0]:Y (f)
               +     1.566          net: Interrupt_Generator_0/CoreGPIO_0/N_21
  8.448                        Interrupt_Generator_0/CoreGPIO_0/CGPIOiOI.0.CGPIOI1I.CGPIOii_RNIBO292[0]:C (f)
               +     0.504          cell: ADLIB:OR3A
  8.952                        Interrupt_Generator_0/CoreGPIO_0/CGPIOiOI.0.CGPIOI1I.CGPIOii_RNIBO292[0]:Y (f)
               +     0.245          net: Interrupt_Generator_0/CoreGPIO_0/N_42
  9.197                        Interrupt_Generator_0/CoreGPIO_0/CGPIOiOI.0.CGPIOI1I.CGPIOii_RNI26UR6[0]:A (f)
               +     0.273          cell: ADLIB:OR3C
  9.470                        Interrupt_Generator_0/CoreGPIO_0/CGPIOiOI.0.CGPIOI1I.CGPIOii_RNI26UR6[0]:Y (r)
               +     0.925          net: _CoreAPB3_0_APBmslave1_PRDATA_[0]_
  10.395                       CoreAPB3_0/CAPB3O1II/PRDATA_1[0]:B (r)
               +     0.421          cell: ADLIB:AO1B
  10.816                       CoreAPB3_0/CAPB3O1II/PRDATA_1[0]:Y (r)
               +     1.438          net: _MSS_top_level_0_MSS_MASTER_APB_PRDATA_[0]_
  12.254                       MSS_top_level_0/MSS_ADLIB_INST/U_36:PIN6 (r)
               +     0.158          cell: ADLIB:MSS_IF
  12.412                       MSS_top_level_0/MSS_ADLIB_INST/U_36:PIN6INT (r)
               +     0.354          net: MSS_top_level_0/MSS_ADLIB_INST/MSSPRDATA[0]INT_NET
  12.766                       MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0] (r)
                                    
  12.766                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_fabric_interface_clock
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               -    -1.815          Library setup time: ADLIB:MSS_APB_IP
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0]


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        Interrupt_Generator_0/Interrupt_Source_0/counter2[3]:CLK
  To:                          Interrupt_Generator_0/Interrupt_Source_0/counter2[31]:D
  Delay (ns):                  7.718
  Slack (ns):
  Arrival (ns):                8.274
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         8.153

Path 2
  From:                        Interrupt_Generator_0/Interrupt_Source_0/counter1[7]:CLK
  To:                          Interrupt_Generator_0/Interrupt_Source_0/COUNTER1_INTRPT:D
  Delay (ns):                  7.626
  Slack (ns):
  Arrival (ns):                8.189
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         8.035

Path 3
  From:                        Interrupt_Generator_0/Interrupt_Source_0/counter2[18]:CLK
  To:                          Interrupt_Generator_0/Interrupt_Source_0/counter2[31]:D
  Delay (ns):                  7.518
  Slack (ns):
  Arrival (ns):                8.079
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.958

Path 4
  From:                        Interrupt_Generator_0/Interrupt_Source_0/counter1[7]:CLK
  To:                          Interrupt_Generator_0/Interrupt_Source_0/counter1[10]:D
  Delay (ns):                  7.432
  Slack (ns):
  Arrival (ns):                7.995
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.867

Path 5
  From:                        Interrupt_Generator_0/Interrupt_Source_0/counter1[7]:CLK
  To:                          Interrupt_Generator_0/Interrupt_Source_0/counter1[20]:D
  Delay (ns):                  7.418
  Slack (ns):
  Arrival (ns):                7.981
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.855


Expanded Path 1
  From: Interrupt_Generator_0/Interrupt_Source_0/counter2[3]:CLK
  To: Interrupt_Generator_0/Interrupt_Source_0/counter2[31]:D
  data required time                             N/C
  data arrival time                          -   8.274
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: MSS_top_level_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  0.000                        MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.556          net: FAB_CLK
  0.556                        Interrupt_Generator_0/Interrupt_Source_0/counter2[3]:CLK (r)
               +     0.440          cell: ADLIB:DFN1C0
  0.996                        Interrupt_Generator_0/Interrupt_Source_0/counter2[3]:Q (r)
               +     1.251          net: Interrupt_Generator_0/Interrupt_Source_0/counter2[3]
  2.247                        Interrupt_Generator_0/Interrupt_Source_0/un3_counter2_1_I_18:A (r)
               +     0.398          cell: ADLIB:AND3
  2.645                        Interrupt_Generator_0/Interrupt_Source_0/un3_counter2_1_I_18:Y (r)
               +     0.985          net: Interrupt_Generator_0/Interrupt_Source_0/DWACT_FINC_E[2]
  3.630                        Interrupt_Generator_0/Interrupt_Source_0/un3_counter2_1_I_68:B (r)
               +     0.473          cell: ADLIB:AND3
  4.103                        Interrupt_Generator_0/Interrupt_Source_0/un3_counter2_1_I_68:Y (r)
               +     1.439          net: Interrupt_Generator_0/Interrupt_Source_0/DWACT_FINC_E[29]
  5.542                        Interrupt_Generator_0/Interrupt_Source_0/un3_counter2_1_I_87:A (r)
               +     0.370          cell: ADLIB:AND2
  5.912                        Interrupt_Generator_0/Interrupt_Source_0/un3_counter2_1_I_87:Y (r)
               +     0.711          net: Interrupt_Generator_0/Interrupt_Source_0/DWACT_FINC_E[24]
  6.623                        Interrupt_Generator_0/Interrupt_Source_0/un3_counter2_1_I_97:A (r)
               +     0.370          cell: ADLIB:AND3
  6.993                        Interrupt_Generator_0/Interrupt_Source_0/un3_counter2_1_I_97:Y (r)
               +     0.733          net: Interrupt_Generator_0/Interrupt_Source_0/N_2
  7.726                        Interrupt_Generator_0/Interrupt_Source_0/un3_counter2_1_I_98:A (r)
               +     0.301          cell: ADLIB:XOR2
  8.027                        Interrupt_Generator_0/Interrupt_Source_0/un3_counter2_1_I_98:Y (f)
               +     0.247          net: Interrupt_Generator_0/Interrupt_Source_0/I_98
  8.274                        Interrupt_Generator_0/Interrupt_Source_0/counter2[31]:D (f)
                                    
  8.274                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: MSS_top_level_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.556          net: FAB_CLK
  N/C                          Interrupt_Generator_0/Interrupt_Source_0/counter2[31]:CLK (r)
               -     0.435          Library setup time: ADLIB:DFN1C0
  N/C                          Interrupt_Generator_0/Interrupt_Source_0/counter2[31]:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

Path 1
  From:                        SWITCH_N
  To:                          Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp1:CLR
  Delay (ns):                  1.869
  Slack (ns):
  Arrival (ns):                1.869
  Required (ns):
  Recovery (ns):               0.225
  External Recovery (ns):      1.558

Path 2
  From:                        SWITCH_N
  To:                          Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp2:CLR
  Delay (ns):                  1.780
  Slack (ns):
  Arrival (ns):                1.780
  Required (ns):
  Recovery (ns):               0.225
  External Recovery (ns):      1.469

Path 3
  From:                        SWITCH_N
  To:                          Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp:CLR
  Delay (ns):                  1.626
  Slack (ns):
  Arrival (ns):                1.626
  Required (ns):
  Recovery (ns):               0.225
  External Recovery (ns):      1.315


Expanded Path 1
  From: SWITCH_N
  To: Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp1:CLR
  data required time                             N/C
  data arrival time                          -   1.869
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        SWITCH_N (r)
               +     0.000          net: SWITCH_N
  0.000                        SWITCH_N_pad/U0/U0:PAD (r)
               +     0.806          cell: ADLIB:IOPAD_IN
  0.806                        SWITCH_N_pad/U0/U0:Y (r)
               +     0.000          net: SWITCH_N_pad/U0/NET1
  0.806                        SWITCH_N_pad/U0/U1:YIN (r)
               +     0.033          cell: ADLIB:IOIN_IB
  0.839                        SWITCH_N_pad/U0/U1:Y (r)
               +     1.030          net: SWITCH_N_c
  1.869                        Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp1:CLR (r)
                                    
  1.869                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: MSS_top_level_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.536          net: FAB_CLK
  N/C                          Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp1:CLK (r)
               -     0.225          Library recovery time: ADLIB:DFN1C0
  N/C                          Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp1:CLR


END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_top_level_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.781
  Slack (ns):
  Arrival (ns):                0.781
  Required (ns):
  Setup (ns):                  -1.782
  External Setup (ns):         -1.383


Expanded Path 1
  From: MSS_RESET_N
  To: MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.781
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        MSS_top_level_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.781          cell: ADLIB:IOPAD_IN
  0.781                        MSS_top_level_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: MSS_top_level_0/MSS_RESET_0_MSS_RESET_N_Y
  0.781                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.781                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.382          net: MSS_top_level_0/GLA0
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -1.782          Library setup time: ADLIB:MSS_APB_IP
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MSS_top_level_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

