Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Thu Dec 08 19:27:19 2011


Design: top_level
Family: SmartFusion
Die: A2F200M3F
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                9.977
Frequency (MHz):            100.231
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                7.520
Frequency (MHz):            132.979
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.574
External Hold (ns):         1.448
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               MSS_top_level_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[2]
  Delay (ns):                  11.823
  Slack (ns):
  Arrival (ns):                11.823
  Required (ns):
  Setup (ns):                  -1.846
  Minimum Period (ns):         9.977

Path 2
  From:                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0]
  Delay (ns):                  11.723
  Slack (ns):
  Arrival (ns):                11.723
  Required (ns):
  Setup (ns):                  -1.846
  Minimum Period (ns):         9.877

Path 3
  From:                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[1]
  Delay (ns):                  10.920
  Slack (ns):
  Arrival (ns):                10.920
  Required (ns):
  Setup (ns):                  -1.853
  Minimum Period (ns):         9.067

Path 4
  From:                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[8]
  Delay (ns):                  9.912
  Slack (ns):
  Arrival (ns):                9.912
  Required (ns):
  Setup (ns):                  -1.858
  Minimum Period (ns):         8.054

Path 5
  From:                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[24]
  Delay (ns):                  9.856
  Slack (ns):
  Arrival (ns):                9.856
  Required (ns):
  Setup (ns):                  -1.856
  Minimum Period (ns):         8.000


Expanded Path 1
  From: MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB
  To: MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[2]
  data required time                             N/C
  data arrival time                          -   11.823
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.981          cell: ADLIB:MSS_APB_IP
  2.981                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPADDR[7] (r)
               +     0.101          net: MSS_top_level_0/MSS_ADLIB_INST/MSSPADDR[7]INT_NET
  3.082                        MSS_top_level_0/MSS_ADLIB_INST/U_32:PIN2INT (r)
               +     0.079          cell: ADLIB:MSS_IF
  3.161                        MSS_top_level_0/MSS_ADLIB_INST/U_32:PIN2 (r)
               +     0.285          net: _CoreAPB3_0_APBmslave1_PADDR_[7]_
  3.446                        Interrupt_Generator_0/CoreGPIO_0/CGPIOL1_2_o2_1_1[0]:A (r)
               +     0.392          cell: ADLIB:NOR2A
  3.838                        Interrupt_Generator_0/CoreGPIO_0/CGPIOL1_2_o2_1_1[0]:Y (r)
               +     0.247          net: Interrupt_Generator_0/CoreGPIO_0/CGPIOL1_2_o2_1_1[0]
  4.085                        Interrupt_Generator_0/CoreGPIO_0/CGPIOL1_2_o2_1_3[0]:A (r)
               +     0.570          cell: ADLIB:NOR3B
  4.655                        Interrupt_Generator_0/CoreGPIO_0/CGPIOL1_2_o2_1_3[0]:Y (r)
               +     0.245          net: Interrupt_Generator_0/CoreGPIO_0/CGPIOL1_2_o2_1_3[0]
  4.900                        Interrupt_Generator_0/CoreGPIO_0/CGPIOL1_2_o2_1[0]:A (r)
               +     0.407          cell: ADLIB:OR2A
  5.307                        Interrupt_Generator_0/CoreGPIO_0/CGPIOL1_2_o2_1[0]:Y (f)
               +     0.788          net: Interrupt_Generator_0/CoreGPIO_0/N_20
  6.095                        Interrupt_Generator_0/CoreGPIO_0/CGPIOL1_2_o2_0[0]:A (f)
               +     0.407          cell: ADLIB:OR2
  6.502                        Interrupt_Generator_0/CoreGPIO_0/CGPIOL1_2_o2_0[0]:Y (f)
               +     1.279          net: Interrupt_Generator_0/CoreGPIO_0/N_21
  7.781                        Interrupt_Generator_0/CoreGPIO_0/CGPIOiOI.2.CGPIOI1I.CGPIOo0_RNIS2EJ2[2]:C (f)
               +     0.505          cell: ADLIB:OR3B
  8.286                        Interrupt_Generator_0/CoreGPIO_0/CGPIOiOI.2.CGPIOI1I.CGPIOo0_RNIS2EJ2[2]:Y (f)
               +     0.255          net: Interrupt_Generator_0/CoreGPIO_0/N_46
  8.541                        Interrupt_Generator_0/CoreGPIO_0/CGPIOiOI.2.CGPIOlol_RNIU8BJ7[2]:C (f)
               +     0.517          cell: ADLIB:OR3C
  9.058                        Interrupt_Generator_0/CoreGPIO_0/CGPIOiOI.2.CGPIOlol_RNIU8BJ7[2]:Y (r)
               +     0.893          net: _CoreAPB3_0_APBmslave1_PRDATA_[2]_
  9.951                        CoreAPB3_0/CAPB3O1II/PRDATA_1[2]:B (r)
               +     0.421          cell: ADLIB:AO1B
  10.372                       CoreAPB3_0/CAPB3O1II/PRDATA_1[2]:Y (r)
               +     0.904          net: _MSS_top_level_0_MSS_MASTER_APB_PRDATA_[2]_
  11.276                       MSS_top_level_0/MSS_ADLIB_INST/U_37:PIN4 (r)
               +     0.180          cell: ADLIB:MSS_IF
  11.456                       MSS_top_level_0/MSS_ADLIB_INST/U_37:PIN4INT (r)
               +     0.367          net: MSS_top_level_0/MSS_ADLIB_INST/MSSPRDATA[2]INT_NET
  11.823                       MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[2] (r)
                                    
  11.823                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_fabric_interface_clock
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               -    -1.846          Library setup time: ADLIB:MSS_APB_IP
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[2]


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        Interrupt_Generator_0/Interrupt_Source_0/counter2[12]:CLK
  To:                          Interrupt_Generator_0/Interrupt_Source_0/counter2[15]:D
  Delay (ns):                  7.067
  Slack (ns):
  Arrival (ns):                7.588
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.520

Path 2
  From:                        Interrupt_Generator_0/Interrupt_Source_0/counter2[15]:CLK
  To:                          Interrupt_Generator_0/Interrupt_Source_0/counter2[15]:D
  Delay (ns):                  7.040
  Slack (ns):
  Arrival (ns):                7.543
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.475

Path 3
  From:                        Interrupt_Generator_0/Interrupt_Source_0/counter2[12]:CLK
  To:                          Interrupt_Generator_0/Interrupt_Source_0/counter2[19]:D
  Delay (ns):                  7.035
  Slack (ns):
  Arrival (ns):                7.556
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.466

Path 4
  From:                        Interrupt_Generator_0/Interrupt_Source_0/counter2[12]:CLK
  To:                          Interrupt_Generator_0/Interrupt_Source_0/counter2[20]:D
  Delay (ns):                  7.030
  Slack (ns):
  Arrival (ns):                7.551
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.454

Path 5
  From:                        Interrupt_Generator_0/Interrupt_Source_0/counter2[12]:CLK
  To:                          Interrupt_Generator_0/Interrupt_Source_0/counter2[0]:D
  Delay (ns):                  7.018
  Slack (ns):
  Arrival (ns):                7.539
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.442


Expanded Path 1
  From: Interrupt_Generator_0/Interrupt_Source_0/counter2[12]:CLK
  To: Interrupt_Generator_0/Interrupt_Source_0/counter2[15]:D
  data required time                             N/C
  data arrival time                          -   7.588
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: MSS_top_level_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  0.000                        MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.521          net: FAB_CLK
  0.521                        Interrupt_Generator_0/Interrupt_Source_0/counter2[12]:CLK (r)
               +     0.440          cell: ADLIB:DFN1C0
  0.961                        Interrupt_Generator_0/Interrupt_Source_0/counter2[12]:Q (r)
               +     0.879          net: Interrupt_Generator_0/Interrupt_Source_0/counter2[12]
  1.840                        Interrupt_Generator_0/Interrupt_Source_0/counter2_RNI1DFT[12]:A (r)
               +     0.370          cell: ADLIB:NOR2B
  2.210                        Interrupt_Generator_0/Interrupt_Source_0/counter2_RNI1DFT[12]:Y (r)
               +     0.247          net: Interrupt_Generator_0/Interrupt_Source_0/un1_counter2_10
  2.457                        Interrupt_Generator_0/Interrupt_Source_0/counter2_RNICCGA1[2]:C (r)
               +     0.570          cell: ADLIB:NOR3C
  3.027                        Interrupt_Generator_0/Interrupt_Source_0/counter2_RNICCGA1[2]:Y (r)
               +     0.709          net: Interrupt_Generator_0/Interrupt_Source_0/un1_counter2_20
  3.736                        Interrupt_Generator_0/Interrupt_Source_0/counter2_RNIUIF53[2]:C (r)
               +     0.505          cell: ADLIB:NOR3C
  4.241                        Interrupt_Generator_0/Interrupt_Source_0/counter2_RNIUIF53[2]:Y (r)
               +     1.320          net: Interrupt_Generator_0/Interrupt_Source_0/un1_counter2_25
  5.561                        Interrupt_Generator_0/Interrupt_Source_0/counter2_RNI04VUB[2]:B (r)
               +     0.473          cell: ADLIB:NOR3C
  6.034                        Interrupt_Generator_0/Interrupt_Source_0/counter2_RNI04VUB[2]:Y (r)
               +     1.046          net: Interrupt_Generator_0/Interrupt_Source_0/counter2_RNI04VUB[2]
  7.080                        Interrupt_Generator_0/Interrupt_Source_0/counter2_RNO[15]:C (r)
               +     0.261          cell: ADLIB:XA1B
  7.341                        Interrupt_Generator_0/Interrupt_Source_0/counter2_RNO[15]:Y (f)
               +     0.247          net: Interrupt_Generator_0/Interrupt_Source_0/counter2_2[15]
  7.588                        Interrupt_Generator_0/Interrupt_Source_0/counter2[15]:D (f)
                                    
  7.588                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: MSS_top_level_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.503          net: FAB_CLK
  N/C                          Interrupt_Generator_0/Interrupt_Source_0/counter2[15]:CLK (r)
               -     0.435          Library setup time: ADLIB:DFN1C0
  N/C                          Interrupt_Generator_0/Interrupt_Source_0/counter2[15]:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

Path 1
  From:                        SWITCH_N
  To:                          Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp1:CLR
  Delay (ns):                  2.223
  Slack (ns):
  Arrival (ns):                2.223
  Required (ns):
  Recovery (ns):               0.225
  External Recovery (ns):      1.963

Path 2
  From:                        SWITCH_N
  To:                          Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp2:CLR
  Delay (ns):                  2.042
  Slack (ns):
  Arrival (ns):                2.042
  Required (ns):
  Recovery (ns):               0.225
  External Recovery (ns):      1.782

Path 3
  From:                        SWITCH_N
  To:                          Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp:CLR
  Delay (ns):                  2.041
  Slack (ns):
  Arrival (ns):                2.041
  Required (ns):
  Recovery (ns):               0.225
  External Recovery (ns):      1.781


Expanded Path 1
  From: SWITCH_N
  To: Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp1:CLR
  data required time                             N/C
  data arrival time                          -   2.223
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        SWITCH_N (r)
               +     0.000          net: SWITCH_N
  0.000                        SWITCH_N_pad/U0/U0:PAD (r)
               +     0.779          cell: ADLIB:IOPAD_IN
  0.779                        SWITCH_N_pad/U0/U0:Y (r)
               +     0.000          net: SWITCH_N_pad/U0/NET1
  0.779                        SWITCH_N_pad/U0/U1:YIN (r)
               +     0.033          cell: ADLIB:IOIN_IB
  0.812                        SWITCH_N_pad/U0/U1:Y (r)
               +     1.411          net: SWITCH_N_c
  2.223                        Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp1:CLR (r)
                                    
  2.223                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: MSS_top_level_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.485          net: FAB_CLK
  N/C                          Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp1:CLK (r)
               -     0.225          Library recovery time: ADLIB:DFN1C0
  N/C                          Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp1:CLR


END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_top_level_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.781
  Slack (ns):
  Arrival (ns):                0.781
  Required (ns):
  Setup (ns):                  -1.830
  External Setup (ns):         -1.574


Expanded Path 1
  From: MSS_RESET_N
  To: MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.781
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        MSS_top_level_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.781          cell: ADLIB:IOPAD_IN
  0.781                        MSS_top_level_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: MSS_top_level_0/MSS_RESET_0_MSS_RESET_N_Y
  0.781                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.781                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.525          net: MSS_top_level_0/GLA0
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -1.830          Library setup time: ADLIB:MSS_APB_IP
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MSS_top_level_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

