library verilog;
use verilog.vl_types.all;
entity Interrupt_Source is
    port(
        SWITCH_N        : in     vl_logic;
        FAB_CLK         : in     vl_logic;
        FAB_LOCK        : in     vl_logic;
        SWITCH_INTRPT   : out    vl_logic;
        COUNTER1_INTRPT : out    vl_logic;
        COUNTER2_INTRPT : out    vl_logic
    );
end Interrupt_Source;
