library verilog;
use verilog.vl_types.all;
entity top_level is
    port(
        UART_0_TXD      : out    vl_logic;
        UART_0_RXD      : in     vl_logic;
        MSS_RESET_N     : in     vl_logic;
        MAINXIN         : in     vl_logic;
        SWITCH_N        : in     vl_logic
    );
end top_level;
