library verilog;
use verilog.vl_types.all;
entity Interrupt_Generator is
    port(
        PRESETn         : in     vl_logic;
        PCLK            : in     vl_logic;
        IRQ             : out    vl_logic;
        PCLK_0          : in     vl_logic;
        PRESETN_0       : in     vl_logic;
        SWITCH_N        : in     vl_logic;
        FAB_LOCK        : in     vl_logic;
        FAB_CLK         : in     vl_logic;
        PSEL            : in     vl_logic;
        PENABLE         : in     vl_logic;
        PWRITE          : in     vl_logic;
        PREADY          : out    vl_logic;
        PSLVERR         : out    vl_logic;
        PSEL_0          : in     vl_logic;
        PENABLE_0       : in     vl_logic;
        PWRITE_0        : in     vl_logic;
        PADDR           : in     vl_logic_vector(7 downto 0);
        PRDATA          : out    vl_logic_vector(31 downto 0);
        PWDATA          : in     vl_logic_vector(31 downto 0);
        PADDR_0         : in     vl_logic_vector(5 downto 2);
        PWDATA_0        : in     vl_logic_vector(31 downto 0);
        PRDATA_0        : out    vl_logic_vector(31 downto 0)
    );
end Interrupt_Generator;
