Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Thu Dec 08 19:23:47 2011


Design: top_level
Family: SmartFusion
Die: A2F200M3F
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                10.542
Frequency (MHz):            94.859
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                8.190
Frequency (MHz):            122.100
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.574
External Hold (ns):         1.448
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               MSS_top_level_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0]
  Delay (ns):                  12.388
  Slack (ns):
  Arrival (ns):                12.388
  Required (ns):
  Setup (ns):                  -1.846
  Minimum Period (ns):         10.542

Path 2
  From:                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[1]
  Delay (ns):                  12.089
  Slack (ns):
  Arrival (ns):                12.089
  Required (ns):
  Setup (ns):                  -1.853
  Minimum Period (ns):         10.236

Path 3
  From:                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[2]
  Delay (ns):                  11.096
  Slack (ns):
  Arrival (ns):                11.096
  Required (ns):
  Setup (ns):                  -1.846
  Minimum Period (ns):         9.250

Path 4
  From:                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[11]
  Delay (ns):                  9.932
  Slack (ns):
  Arrival (ns):                9.932
  Required (ns):
  Setup (ns):                  -1.873
  Minimum Period (ns):         8.059

Path 5
  From:                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[3]
  Delay (ns):                  9.900
  Slack (ns):
  Arrival (ns):                9.900
  Required (ns):
  Setup (ns):                  -1.868
  Minimum Period (ns):         8.032


Expanded Path 1
  From: MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB
  To: MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0]
  data required time                             N/C
  data arrival time                          -   12.388
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.981          cell: ADLIB:MSS_APB_IP
  2.981                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPADDR[7] (r)
               +     0.101          net: MSS_top_level_0/MSS_ADLIB_INST/MSSPADDR[7]INT_NET
  3.082                        MSS_top_level_0/MSS_ADLIB_INST/U_32:PIN2INT (r)
               +     0.079          cell: ADLIB:MSS_IF
  3.161                        MSS_top_level_0/MSS_ADLIB_INST/U_32:PIN2 (r)
               +     0.285          net: MSS_top_level_0_MSS_MASTER_APB_PADDR_[7]
  3.446                        Interrupt_Generator_0/CoreGPIO_0/CGPIOl0_0_o2_1_1[0]:A (r)
               +     0.392          cell: ADLIB:NOR2A
  3.838                        Interrupt_Generator_0/CoreGPIO_0/CGPIOl0_0_o2_1_1[0]:Y (r)
               +     0.247          net: Interrupt_Generator_0/CoreGPIO_0/CGPIOl0_0_o2_1_1[0]
  4.085                        Interrupt_Generator_0/CoreGPIO_0/CGPIOl0_0_o2_1_3[0]:A (r)
               +     0.570          cell: ADLIB:NOR3B
  4.655                        Interrupt_Generator_0/CoreGPIO_0/CGPIOl0_0_o2_1_3[0]:Y (r)
               +     0.245          net: Interrupt_Generator_0/CoreGPIO_0/CGPIOl0_0_o2_1_3[0]
  4.900                        Interrupt_Generator_0/CoreGPIO_0/CGPIOl0_0_o2_1[0]:A (r)
               +     0.407          cell: ADLIB:OR2A
  5.307                        Interrupt_Generator_0/CoreGPIO_0/CGPIOl0_0_o2_1[0]:Y (f)
               +     1.197          net: Interrupt_Generator_0/CoreGPIO_0/N_20
  6.504                        Interrupt_Generator_0/CoreGPIO_0/CGPIOl0_0_o2_0[0]:B (f)
               +     0.493          cell: ADLIB:OR2
  6.997                        Interrupt_Generator_0/CoreGPIO_0/CGPIOl0_0_o2_0[0]:Y (f)
               +     1.100          net: Interrupt_Generator_0/CoreGPIO_0/N_21
  8.097                        Interrupt_Generator_0/CoreGPIO_0/CGPIOl1I.CGPIOIOl[0].CGPIOl0l.CGPIOIl_RNIOH3J2[0]:C (f)
               +     0.505          cell: ADLIB:OR3B
  8.602                        Interrupt_Generator_0/CoreGPIO_0/CGPIOl1I.CGPIOIOl[0].CGPIOl0l.CGPIOIl_RNIOH3J2[0]:Y (f)
               +     0.255          net: Interrupt_Generator_0/CoreGPIO_0/N_40
  8.857                        Interrupt_Generator_0/CoreGPIO_0/CGPIOl1I.CGPIOIOl[0].CGPIOl1_RNIURLH7[0]:C (f)
               +     0.517          cell: ADLIB:OR3C
  9.374                        Interrupt_Generator_0/CoreGPIO_0/CGPIOl1I.CGPIOIOl[0].CGPIOl1_RNIURLH7[0]:Y (r)
               +     1.071          net: CGPIOl1I_CGPIOIOl[0]_CGPIOl1_RNIURLH7[0]
  10.445                       CoreAPB3_0/CAPB3llOI/PRDATA_1[0]:A (r)
               +     0.293          cell: ADLIB:AO1B
  10.738                       CoreAPB3_0/CAPB3llOI/PRDATA_1[0]:Y (r)
               +     1.121          net: PRDATA_1[0]
  11.859                       MSS_top_level_0/MSS_ADLIB_INST/U_36:PIN6 (r)
               +     0.158          cell: ADLIB:MSS_IF
  12.017                       MSS_top_level_0/MSS_ADLIB_INST/U_36:PIN6INT (r)
               +     0.371          net: MSS_top_level_0/MSS_ADLIB_INST/MSSPRDATA[0]INT_NET
  12.388                       MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0] (r)
                                    
  12.388                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_fabric_interface_clock
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               -    -1.846          Library setup time: ADLIB:MSS_APB_IP
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[0]


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        Interrupt_Generator_0/Interrupt_Source_0/counter2[3]:CLK
  To:                          Interrupt_Generator_0/Interrupt_Source_0/counter2[24]:D
  Delay (ns):                  7.732
  Slack (ns):
  Arrival (ns):                8.233
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         8.190

Path 2
  From:                        Interrupt_Generator_0/Interrupt_Source_0/counter2[3]:CLK
  To:                          Interrupt_Generator_0/Interrupt_Source_0/counter2[31]:D
  Delay (ns):                  7.519
  Slack (ns):
  Arrival (ns):                8.020
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.970

Path 3
  From:                        Interrupt_Generator_0/Interrupt_Source_0/counter2[30]:CLK
  To:                          Interrupt_Generator_0/Interrupt_Source_0/counter2[23]:D
  Delay (ns):                  7.496
  Slack (ns):
  Arrival (ns):                7.981
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.909

Path 4
  From:                        Interrupt_Generator_0/Interrupt_Source_0/counter2[11]:CLK
  To:                          Interrupt_Generator_0/Interrupt_Source_0/counter2[23]:D
  Delay (ns):                  7.433
  Slack (ns):
  Arrival (ns):                7.954
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.882

Path 5
  From:                        Interrupt_Generator_0/Interrupt_Source_0/counter2[3]:CLK
  To:                          Interrupt_Generator_0/Interrupt_Source_0/counter2[23]:D
  Delay (ns):                  7.435
  Slack (ns):
  Arrival (ns):                7.936
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.864


Expanded Path 1
  From: Interrupt_Generator_0/Interrupt_Source_0/counter2[3]:CLK
  To: Interrupt_Generator_0/Interrupt_Source_0/counter2[24]:D
  data required time                             N/C
  data arrival time                          -   8.233
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: MSS_top_level_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  0.000                        MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.501          net: FAB_CLK
  0.501                        Interrupt_Generator_0/Interrupt_Source_0/counter2[3]:CLK (r)
               +     0.440          cell: ADLIB:DFN1C0
  0.941                        Interrupt_Generator_0/Interrupt_Source_0/counter2[3]:Q (r)
               +     1.422          net: Interrupt_Generator_0/Interrupt_Source_0/counter2[3]
  2.363                        Interrupt_Generator_0/Interrupt_Source_0/un2_counter2_1_I_18:A (r)
               +     0.398          cell: ADLIB:AND3
  2.761                        Interrupt_Generator_0/Interrupt_Source_0/un2_counter2_1_I_18:Y (r)
               +     0.926          net: Interrupt_Generator_0/Interrupt_Source_0/DWACT_FINC_E[2]
  3.687                        Interrupt_Generator_0/Interrupt_Source_0/un2_counter2_1_I_68:B (r)
               +     0.473          cell: ADLIB:AND3
  4.160                        Interrupt_Generator_0/Interrupt_Source_0/un2_counter2_1_I_68:Y (r)
               +     1.546          net: Interrupt_Generator_0/Interrupt_Source_0/DWACT_FINC_E[29]
  5.706                        Interrupt_Generator_0/Interrupt_Source_0/un2_counter2_1_I_73:A (r)
               +     0.398          cell: ADLIB:AND3
  6.104                        Interrupt_Generator_0/Interrupt_Source_0/un2_counter2_1_I_73:Y (r)
               +     1.581          net: Interrupt_Generator_0/Interrupt_Source_0/N_9
  7.685                        Interrupt_Generator_0/Interrupt_Source_0/un2_counter2_1_I_74:A (r)
               +     0.301          cell: ADLIB:XOR2
  7.986                        Interrupt_Generator_0/Interrupt_Source_0/un2_counter2_1_I_74:Y (f)
               +     0.247          net: Interrupt_Generator_0/Interrupt_Source_0/I_74
  8.233                        Interrupt_Generator_0/Interrupt_Source_0/counter2[24]:D (f)
                                    
  8.233                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: MSS_top_level_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.478          net: FAB_CLK
  N/C                          Interrupt_Generator_0/Interrupt_Source_0/counter2[24]:CLK (r)
               -     0.435          Library setup time: ADLIB:DFN1C0
  N/C                          Interrupt_Generator_0/Interrupt_Source_0/counter2[24]:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

Path 1
  From:                        SWITCH_N
  To:                          Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp1:CLR
  Delay (ns):                  2.672
  Slack (ns):
  Arrival (ns):                2.672
  Required (ns):
  Recovery (ns):               0.225
  External Recovery (ns):      2.396

Path 2
  From:                        SWITCH_N
  To:                          Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp2:CLR
  Delay (ns):                  2.485
  Slack (ns):
  Arrival (ns):                2.485
  Required (ns):
  Recovery (ns):               0.225
  External Recovery (ns):      2.209

Path 3
  From:                        SWITCH_N
  To:                          Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp:CLR
  Delay (ns):                  2.442
  Slack (ns):
  Arrival (ns):                2.442
  Required (ns):
  Recovery (ns):               0.225
  External Recovery (ns):      2.166


Expanded Path 1
  From: SWITCH_N
  To: Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp1:CLR
  data required time                             N/C
  data arrival time                          -   2.672
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        SWITCH_N (r)
               +     0.000          net: SWITCH_N
  0.000                        SWITCH_N_pad/U0/U0:PAD (r)
               +     0.779          cell: ADLIB:IOPAD_IN
  0.779                        SWITCH_N_pad/U0/U0:Y (r)
               +     0.000          net: SWITCH_N_pad/U0/NET1
  0.779                        SWITCH_N_pad/U0/U1:YIN (r)
               +     0.033          cell: ADLIB:IOIN_IB
  0.812                        SWITCH_N_pad/U0/U1:Y (r)
               +     1.860          net: SWITCH_N_c
  2.672                        Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp1:CLR (r)
                                    
  2.672                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: MSS_top_level_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.501          net: FAB_CLK
  N/C                          Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp1:CLK (r)
               -     0.225          Library recovery time: ADLIB:DFN1C0
  N/C                          Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp1:CLR


END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_top_level_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.781
  Slack (ns):
  Arrival (ns):                0.781
  Required (ns):
  Setup (ns):                  -1.830
  External Setup (ns):         -1.574


Expanded Path 1
  From: MSS_RESET_N
  To: MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.781
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        MSS_top_level_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.781          cell: ADLIB:IOPAD_IN
  0.781                        MSS_top_level_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: MSS_top_level_0/MSS_RESET_0_MSS_RESET_N_Y
  0.781                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.781                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.525          net: MSS_top_level_0/GLA0
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -1.830          Library setup time: ADLIB:MSS_APB_IP
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MSS_top_level_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

