library verilog;
use verilog.vl_types.all;
entity MSS_top_level is
    port(
        FAB_CLK         : out    vl_logic;
        MAINXIN         : in     vl_logic;
        FAB_LOCK        : out    vl_logic;
        MSSPSEL         : out    vl_logic;
        MSSPENABLE      : out    vl_logic;
        MSSPWRITE       : out    vl_logic;
        MSSPREADY       : in     vl_logic;
        MSSPSLVERR      : in     vl_logic;
        FABINT          : in     vl_logic;
        MSSPADDR        : out    vl_logic_vector(19 downto 0);
        MSSPRDATA       : in     vl_logic_vector(31 downto 0);
        MSSPWDATA       : out    vl_logic_vector(31 downto 0);
        UART_0_TXD      : out    vl_logic;
        UART_0_RXD      : in     vl_logic;
        MSS_RESET_N     : in     vl_logic
    );
end MSS_top_level;
