`timescale 1 ns/100 ps
// Version: 9.0 SP2 9.0.3.3


module Interrupt_Generator(
       PRESETn,
       PCLK,
       IRQ,
       PCLK_0,
       PRESETN_0,
       SWITCH_N,
       FAB_LOCK,
       FAB_CLK,
       PSEL,
       PENABLE,
       PWRITE,
       PREADY,
       PSLVERR,
       PSEL_0,
       PENABLE_0,
       PWRITE_0,
       PADDR,
       PRDATA,
       PWDATA,
       PADDR_0,
       PWDATA_0,
       PRDATA_0
    );
input  PRESETn;
input  PCLK;
output IRQ;
input  PCLK_0;
input  PRESETN_0;
input  SWITCH_N;
input  FAB_LOCK;
input  FAB_CLK;
input  PSEL;
input  PENABLE;
input  PWRITE;
output PREADY;
output PSLVERR;
input  PSEL_0;
input  PENABLE_0;
input  PWRITE_0;
input  [7:0] PADDR;
output [31:0] PRDATA;
input  [31:0] PWDATA;
input  [5:2] PADDR_0;
input  [31:0] PWDATA_0;
output [31:0] PRDATA_0;

    wire CoreGPIO_0_INT0to0, CoreGPIO_0_INT1to1, CoreGPIO_0_INT2to2, 
        Interrupt_Source_0_COUNTER1_INTRPT, 
        Interrupt_Source_0_COUNTER2_INTRPT, 
        Interrupt_Source_0_SWITCH_INTRPT, GND_net, VCC_net;
    
    CoreInterrupt #( .FIQPOLARITY(1), .IRQPOLARITY(1), .NUMFIQSRC(0), .NUMIRQSRC(32)
         )  CoreInterrupt_0 (.PCLK(PCLK), .PRESETn(PRESETn), .PSEL(
        PSEL_0), .PWRITE(PWRITE_0), .PENABLE(PENABLE_0), .fiqSource0(
        GND_net), .fiqSource1(GND_net), .fiqSource2(GND_net), 
        .fiqSource3(GND_net), .fiqSource4(GND_net), .fiqSource5(
        GND_net), .fiqSource6(GND_net), .fiqSource7(GND_net), 
        .irqSource0(CoreGPIO_0_INT0to0), .irqSource1(
        CoreGPIO_0_INT1to1), .irqSource2(CoreGPIO_0_INT2to2), 
        .irqSource3(GND_net), .irqSource4(GND_net), .irqSource5(
        GND_net), .irqSource6(GND_net), .irqSource7(GND_net), 
        .irqSource8(GND_net), .irqSource9(GND_net), .irqSource10(
        GND_net), .irqSource11(GND_net), .irqSource12(GND_net), 
        .irqSource13(GND_net), .irqSource14(GND_net), .irqSource15(
        GND_net), .irqSource16(GND_net), .irqSource17(GND_net), 
        .irqSource18(GND_net), .irqSource19(GND_net), .irqSource20(
        GND_net), .irqSource21(GND_net), .irqSource22(GND_net), 
        .irqSource23(GND_net), .irqSource24(GND_net), .irqSource25(
        GND_net), .irqSource26(GND_net), .irqSource27(GND_net), 
        .irqSource28(GND_net), .irqSource29(GND_net), .irqSource30(
        GND_net), .irqSource31(GND_net), .FIQ(), .IRQ(IRQ), .PADDR({
        PADDR_0[5], PADDR_0[4], PADDR_0[3], PADDR_0[2]}), .PWDATA({
        PWDATA_0[31], PWDATA_0[30], PWDATA_0[29], PWDATA_0[28], 
        PWDATA_0[27], PWDATA_0[26], PWDATA_0[25], PWDATA_0[24], 
        PWDATA_0[23], PWDATA_0[22], PWDATA_0[21], PWDATA_0[20], 
        PWDATA_0[19], PWDATA_0[18], PWDATA_0[17], PWDATA_0[16], 
        PWDATA_0[15], PWDATA_0[14], PWDATA_0[13], PWDATA_0[12], 
        PWDATA_0[11], PWDATA_0[10], PWDATA_0[9], PWDATA_0[8], 
        PWDATA_0[7], PWDATA_0[6], PWDATA_0[5], PWDATA_0[4], 
        PWDATA_0[3], PWDATA_0[2], PWDATA_0[1], PWDATA_0[0]}), .PRDATA({
        PRDATA_0[31], PRDATA_0[30], PRDATA_0[29], PRDATA_0[28], 
        PRDATA_0[27], PRDATA_0[26], PRDATA_0[25], PRDATA_0[24], 
        PRDATA_0[23], PRDATA_0[22], PRDATA_0[21], PRDATA_0[20], 
        PRDATA_0[19], PRDATA_0[18], PRDATA_0[17], PRDATA_0[16], 
        PRDATA_0[15], PRDATA_0[14], PRDATA_0[13], PRDATA_0[12], 
        PRDATA_0[11], PRDATA_0[10], PRDATA_0[9], PRDATA_0[8], 
        PRDATA_0[7], PRDATA_0[6], PRDATA_0[5], PRDATA_0[4], 
        PRDATA_0[3], PRDATA_0[2], PRDATA_0[1], PRDATA_0[0]}));
    VCC VCC (.Y(VCC_net));
    Interrupt_Source Interrupt_Source_0 (.SWITCH_N(SWITCH_N), .FAB_CLK(
        FAB_CLK), .FAB_LOCK(FAB_LOCK), .SWITCH_INTRPT(
        Interrupt_Source_0_SWITCH_INTRPT), .COUNTER1_INTRPT(
        Interrupt_Source_0_COUNTER1_INTRPT), .COUNTER2_INTRPT(
        Interrupt_Source_0_COUNTER2_INTRPT));
    GND GND (.Y(GND_net));
    CoreGPIO #( .APB_WIDTH(32), .FAMILY(15), .FIXED_CONFIG_0(1), .FIXED_CONFIG_1(1)
        , .FIXED_CONFIG_10(0), .FIXED_CONFIG_11(0), .FIXED_CONFIG_12(0)
        , .FIXED_CONFIG_13(0), .FIXED_CONFIG_14(0), .FIXED_CONFIG_15(0)
        , .FIXED_CONFIG_16(0), .FIXED_CONFIG_17(0), .FIXED_CONFIG_18(0)
        , .FIXED_CONFIG_19(0), .FIXED_CONFIG_2(1), .FIXED_CONFIG_20(0)
        , .FIXED_CONFIG_21(0), .FIXED_CONFIG_22(0), .FIXED_CONFIG_23(0)
        , .FIXED_CONFIG_24(0), .FIXED_CONFIG_25(0), .FIXED_CONFIG_26(0)
        , .FIXED_CONFIG_27(0), .FIXED_CONFIG_28(0), .FIXED_CONFIG_29(0)
        , .FIXED_CONFIG_3(0), .FIXED_CONFIG_30(0), .FIXED_CONFIG_31(0)
        , .FIXED_CONFIG_4(0), .FIXED_CONFIG_5(0), .FIXED_CONFIG_6(0), .FIXED_CONFIG_7(0)
        , .FIXED_CONFIG_8(0), .FIXED_CONFIG_9(0), .INT_BUS(0), .IO_INT_TYPE_0(2)
        , .IO_INT_TYPE_1(2), .IO_INT_TYPE_10(7), .IO_INT_TYPE_11(7), .IO_INT_TYPE_12(7)
        , .IO_INT_TYPE_13(7), .IO_INT_TYPE_14(7), .IO_INT_TYPE_15(7), .IO_INT_TYPE_16(7)
        , .IO_INT_TYPE_17(7), .IO_INT_TYPE_18(7), .IO_INT_TYPE_19(7), .IO_INT_TYPE_2(2)
        , .IO_INT_TYPE_20(7), .IO_INT_TYPE_21(7), .IO_INT_TYPE_22(7), .IO_INT_TYPE_23(7)
        , .IO_INT_TYPE_24(7), .IO_INT_TYPE_25(7), .IO_INT_TYPE_26(7), .IO_INT_TYPE_27(7)
        , .IO_INT_TYPE_28(7), .IO_INT_TYPE_29(7), .IO_INT_TYPE_3(7), .IO_INT_TYPE_30(7)
        , .IO_INT_TYPE_31(7), .IO_INT_TYPE_4(7), .IO_INT_TYPE_5(7), .IO_INT_TYPE_6(7)
        , .IO_INT_TYPE_7(7), .IO_INT_TYPE_8(7), .IO_INT_TYPE_9(7), .IO_NUM(3)
        , .IO_TYPE_0(0), .IO_TYPE_1(0), .IO_TYPE_10(0), .IO_TYPE_11(0)
        , .IO_TYPE_12(0), .IO_TYPE_13(0), .IO_TYPE_14(0), .IO_TYPE_15(0)
        , .IO_TYPE_16(0), .IO_TYPE_17(0), .IO_TYPE_18(0), .IO_TYPE_19(0)
        , .IO_TYPE_2(0), .IO_TYPE_20(0), .IO_TYPE_21(0), .IO_TYPE_22(0)
        , .IO_TYPE_23(0), .IO_TYPE_24(0), .IO_TYPE_25(0), .IO_TYPE_26(0)
        , .IO_TYPE_27(0), .IO_TYPE_28(0), .IO_TYPE_29(0), .IO_TYPE_3(0)
        , .IO_TYPE_30(0), .IO_TYPE_31(0), .IO_TYPE_4(0), .IO_TYPE_5(0)
        , .IO_TYPE_6(0), .IO_TYPE_7(0), .IO_TYPE_8(0), .IO_TYPE_9(0), .IO_VAL_0(0)
        , .IO_VAL_1(0), .IO_VAL_10(0), .IO_VAL_11(0), .IO_VAL_12(0), .IO_VAL_13(0)
        , .IO_VAL_14(0), .IO_VAL_15(0), .IO_VAL_16(0), .IO_VAL_17(0), .IO_VAL_18(0)
        , .IO_VAL_19(0), .IO_VAL_2(0), .IO_VAL_20(0), .IO_VAL_21(0), .IO_VAL_22(0)
        , .IO_VAL_23(0), .IO_VAL_24(0), .IO_VAL_25(0), .IO_VAL_26(0), .IO_VAL_27(0)
        , .IO_VAL_28(0), .IO_VAL_29(0), .IO_VAL_3(0), .IO_VAL_30(0), .IO_VAL_31(0)
        , .IO_VAL_4(0), .IO_VAL_5(0), .IO_VAL_6(0), .IO_VAL_7(0), .IO_VAL_8(0)
        , .IO_VAL_9(0), .OE_TYPE(1) )  CoreGPIO_0 (.PRESETN(PRESETN_0), 
        .PCLK(PCLK_0), .PSEL(PSEL), .PENABLE(PENABLE), .PWRITE(PWRITE), 
        .PSLVERR(PSLVERR), .PREADY(PREADY), .INT_OR(), .PADDR({
        PADDR[7], PADDR[6], PADDR[5], PADDR[4], PADDR[3], PADDR[2], 
        PADDR[1], PADDR[0]}), .PWDATA({PWDATA[31], PWDATA[30], 
        PWDATA[29], PWDATA[28], PWDATA[27], PWDATA[26], PWDATA[25], 
        PWDATA[24], PWDATA[23], PWDATA[22], PWDATA[21], PWDATA[20], 
        PWDATA[19], PWDATA[18], PWDATA[17], PWDATA[16], PWDATA[15], 
        PWDATA[14], PWDATA[13], PWDATA[12], PWDATA[11], PWDATA[10], 
        PWDATA[9], PWDATA[8], PWDATA[7], PWDATA[6], PWDATA[5], 
        PWDATA[4], PWDATA[3], PWDATA[2], PWDATA[1], PWDATA[0]}), 
        .PRDATA({PRDATA[31], PRDATA[30], PRDATA[29], PRDATA[28], 
        PRDATA[27], PRDATA[26], PRDATA[25], PRDATA[24], PRDATA[23], 
        PRDATA[22], PRDATA[21], PRDATA[20], PRDATA[19], PRDATA[18], 
        PRDATA[17], PRDATA[16], PRDATA[15], PRDATA[14], PRDATA[13], 
        PRDATA[12], PRDATA[11], PRDATA[10], PRDATA[9], PRDATA[8], 
        PRDATA[7], PRDATA[6], PRDATA[5], PRDATA[4], PRDATA[3], 
        PRDATA[2], PRDATA[1], PRDATA[0]}), .INT({CoreGPIO_0_INT2to2, 
        CoreGPIO_0_INT1to1, CoreGPIO_0_INT0to0}), .GPIO_IN({
        Interrupt_Source_0_SWITCH_INTRPT, 
        Interrupt_Source_0_COUNTER2_INTRPT, 
        Interrupt_Source_0_COUNTER1_INTRPT}), .GPIO_OUT({nc0, nc1, nc2})
        , .GPIO_OE({nc3, nc4, nc5}));
    
endmodule
