@W: CG775 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":13:0:13:7|Found Component CoreAPB3 in library COREAPB3_LIB
@W: CL190 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":1183:0:1183:5|Optimizing register bit CoreInterrupt_O0I[0] to a constant 0
@W: CL190 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":1183:0:1183:5|Optimizing register bit CoreInterrupt_O0I[1] to a constant 0
@W: CL190 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":1183:0:1183:5|Optimizing register bit CoreInterrupt_O0I[2] to a constant 0
@W: CL190 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":1183:0:1183:5|Optimizing register bit CoreInterrupt_O0I[3] to a constant 0
@W: CL190 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":1183:0:1183:5|Optimizing register bit CoreInterrupt_O0I[4] to a constant 0
@W: CL190 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":1183:0:1183:5|Optimizing register bit CoreInterrupt_O0I[5] to a constant 0
@W: CL190 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":1183:0:1183:5|Optimizing register bit CoreInterrupt_O0I[6] to a constant 0
@W: CL190 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":1183:0:1183:5|Optimizing register bit CoreInterrupt_O0I[7] to a constant 0
@W: CL190 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":1247:0:1247:5|Optimizing register bit CoreInterrupt_I0I[0] to a constant 0
@W: CL190 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":1247:0:1247:5|Optimizing register bit CoreInterrupt_I0I[1] to a constant 0
@W: CL190 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":1247:0:1247:5|Optimizing register bit CoreInterrupt_I0I[2] to a constant 0
@W: CL190 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":1247:0:1247:5|Optimizing register bit CoreInterrupt_I0I[3] to a constant 0
@W: CL190 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":1247:0:1247:5|Optimizing register bit CoreInterrupt_I0I[4] to a constant 0
@W: CL190 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":1247:0:1247:5|Optimizing register bit CoreInterrupt_I0I[5] to a constant 0
@W: CL190 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":1247:0:1247:5|Optimizing register bit CoreInterrupt_I0I[6] to a constant 0
@W: CL190 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":1247:0:1247:5|Optimizing register bit CoreInterrupt_I0I[7] to a constant 0
@W: CL169 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":1183:0:1183:5|Pruning register CoreInterrupt_O0I[7:0] 
@W: CL169 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":1247:0:1247:5|Pruning register CoreInterrupt_I0I[7:0] 
@W: CL169 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vlog\core_obfuscated\coregpio.v":3535:0:3535:5|Pruning register CGPIOl1I.CGPIOIOl[2].CGPIOl0l.CGPIOIOI[2] 
@W: CL169 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vlog\core_obfuscated\coregpio.v":3322:0:3322:5|Pruning register CGPIOl1I.CGPIOIOl[2].CGPIOl0l.CGPIOlOI[2] 
@W: CL169 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vlog\core_obfuscated\coregpio.v":3535:0:3535:5|Pruning register CGPIOl1I.CGPIOIOl[1].CGPIOl0l.CGPIOIOI[1] 
@W: CL169 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vlog\core_obfuscated\coregpio.v":3322:0:3322:5|Pruning register CGPIOl1I.CGPIOIOl[1].CGPIOl0l.CGPIOlOI[1] 
@W: CL169 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vlog\core_obfuscated\coregpio.v":3535:0:3535:5|Pruning register CGPIOl1I.CGPIOIOl[0].CGPIOl0l.CGPIOIOI[0] 
@W: CL169 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vlog\core_obfuscated\coregpio.v":3322:0:3322:5|Pruning register CGPIOl1I.CGPIOIOl[0].CGPIOl0l.CGPIOlOI[0] 
@W: CL168 :"C:\A2F_AC339_DF\A2F500\Verilog\component\work\Interrupt_Generator\Interrupt_Generator.v":94:8:94:10|Pruning instance VCC -- not in use ...
@W: CL246 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vlog\core_obfuscated\coregpio.v":1394:0:1394:5|Input port bits 31 to 3 of PWDATA[31:0] are unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":214:0:214:9|Input fiqSource7 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":217:0:217:9|Input fiqSource6 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":220:0:220:9|Input fiqSource5 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":223:0:223:9|Input fiqSource4 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":226:0:226:9|Input fiqSource3 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":229:0:229:9|Input fiqSource2 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":232:0:232:9|Input fiqSource1 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v":235:0:235:9|Input fiqSource0 is unused
@W: CL246 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":217:0:217:4|Input port bits 23 to 12 of PADDR[23:0] are unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":208:0:208:6|Input PRESETN is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":210:0:210:3|Input PCLK is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":363:0:363:7|Input PRDATAS2 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":370:0:370:7|Input PRDATAS3 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":377:0:377:7|Input PRDATAS4 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":384:0:384:7|Input PRDATAS5 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":391:0:391:7|Input PRDATAS6 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":398:0:398:7|Input PRDATAS7 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":405:0:405:7|Input PRDATAS8 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":412:0:412:7|Input PRDATAS9 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":419:0:419:8|Input PRDATAS10 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":426:0:426:8|Input PRDATAS11 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":433:0:433:8|Input PRDATAS12 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":440:0:440:8|Input PRDATAS13 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":447:0:447:8|Input PRDATAS14 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":454:0:454:8|Input PRDATAS15 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":460:0:460:7|Input PREADYS2 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":462:0:462:7|Input PREADYS3 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":464:0:464:7|Input PREADYS4 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":466:0:466:7|Input PREADYS5 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":468:0:468:7|Input PREADYS6 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":470:0:470:7|Input PREADYS7 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":472:0:472:7|Input PREADYS8 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":474:0:474:7|Input PREADYS9 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":476:0:476:8|Input PREADYS10 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":478:0:478:8|Input PREADYS11 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":480:0:480:8|Input PREADYS12 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":482:0:482:8|Input PREADYS13 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":484:0:484:8|Input PREADYS14 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":486:0:486:8|Input PREADYS15 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":492:0:492:8|Input PSLVERRS2 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":494:0:494:8|Input PSLVERRS3 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":496:0:496:8|Input PSLVERRS4 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":498:0:498:8|Input PSLVERRS5 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":500:0:500:8|Input PSLVERRS6 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":502:0:502:8|Input PSLVERRS7 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":504:0:504:8|Input PSLVERRS8 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":506:0:506:8|Input PSLVERRS9 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":508:0:508:9|Input PSLVERRS10 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":510:0:510:9|Input PSLVERRS11 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":512:0:512:9|Input PSLVERRS12 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":514:0:514:9|Input PSLVERRS13 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":516:0:516:9|Input PSLVERRS14 is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v":518:0:518:9|Input PSLVERRS15 is unused
@W: CL157 :"C:\A2F_AC339_DF\A2F500\Verilog\component\work\MSS_top_level\MSS_CCC_0\MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v":62:7:62:18|*Output RCOSC_CLKOUT has undriven bits -- simulation mismatch possible.
@W: CL157 :"C:\A2F_AC339_DF\A2F500\Verilog\component\work\MSS_top_level\MSS_CCC_0\MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v":63:7:63:20|*Output MAINXIN_CLKOUT has undriven bits -- simulation mismatch possible.
@W: CL157 :"C:\A2F_AC339_DF\A2F500\Verilog\component\work\MSS_top_level\MSS_CCC_0\MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v":64:7:64:18|*Output LPXIN_CLKOUT has undriven bits -- simulation mismatch possible.
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\work\MSS_top_level\MSS_CCC_0\MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v":36:7:36:10|Input CLKA is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\work\MSS_top_level\MSS_CCC_0\MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v":37:7:37:14|Input CLKA_PAD is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\work\MSS_top_level\MSS_CCC_0\MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v":38:7:38:15|Input CLKA_PADP is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\work\MSS_top_level\MSS_CCC_0\MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v":39:7:39:15|Input CLKA_PADN is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\work\MSS_top_level\MSS_CCC_0\MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v":40:7:40:10|Input CLKB is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\work\MSS_top_level\MSS_CCC_0\MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v":41:7:41:14|Input CLKB_PAD is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\work\MSS_top_level\MSS_CCC_0\MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v":42:7:42:15|Input CLKB_PADP is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\work\MSS_top_level\MSS_CCC_0\MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v":43:7:43:15|Input CLKB_PADN is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\work\MSS_top_level\MSS_CCC_0\MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v":44:7:44:10|Input CLKC is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\work\MSS_top_level\MSS_CCC_0\MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v":45:7:45:14|Input CLKC_PAD is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\work\MSS_top_level\MSS_CCC_0\MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v":46:7:46:15|Input CLKC_PADP is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\work\MSS_top_level\MSS_CCC_0\MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v":47:7:47:15|Input CLKC_PADN is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\work\MSS_top_level\MSS_CCC_0\MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v":49:7:49:11|Input LPXIN is unused
@W: CL159 :"C:\A2F_AC339_DF\A2F500\Verilog\component\work\MSS_top_level\MSS_CCC_0\MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v":50:7:50:13|Input MAC_CLK is unused

