----------------------------------------------------------------------
-- Created by Actel SmartDesign Thu Dec 08 16:57:42 2011
-- Testbench Template
-- This is a basic testbench that instantiates your design with basic 
-- clock and reset pins connected.  If your design has special
-- clock/reset or testbench driver requirements then you should 
-- copy this file and modify it. 
----------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench;

architecture behavioral of testbench is

    constant SYSCLK_PERIOD : time := 100 ns;

    signal SYSCLK : std_logic := '0';
    signal NSYSRESET : std_logic := '0';

    component MSS_top_level
        -- ports
        port( 
            -- Inputs
            MAINXIN : in std_logic;
            MSSPREADY : in std_logic;
            MSSPSLVERR : in std_logic;
            FABINT : in std_logic;
            MSSPRDATA : in std_logic_vector(31 downto 0);
            UART_0_RXD : in std_logic;
            MSS_RESET_N : in std_logic;

            -- Outputs
            FAB_CLK : out std_logic;
            FAB_LOCK : out std_logic;
            MSSPSEL : out std_logic;
            MSSPENABLE : out std_logic;
            MSSPWRITE : out std_logic;
            MSSPADDR : out std_logic_vector(19 downto 0);
            MSSPWDATA : out std_logic_vector(31 downto 0);
            UART_0_TXD : out std_logic

            -- Inouts

        );
    end component;

begin

    process
        variable vhdl_initial : BOOLEAN := TRUE;

    begin
        if ( vhdl_initial ) then
            -- Assert Reset
            NSYSRESET <= '0';
            wait for ( SYSCLK_PERIOD * 10 );
            
            NSYSRESET <= '1';
            wait;
        end if;
    end process;

    -- 10MHz Clock Driver
    SYSCLK <= not SYSCLK after (SYSCLK_PERIOD / 2.0 );

    -- Instantiate Unit Under Test:  MSS_top_level
    MSS_top_level_0 : MSS_top_level
        -- port map
        port map( 
            -- Inputs
            MAINXIN => '0',
            MSSPREADY => '0',
            MSSPSLVERR => '0',
            FABINT => '0',
            MSSPRDATA => (others=> '0'),
            UART_0_RXD => '0',
            MSS_RESET_N => NSYSRESET,

            -- Outputs
            FAB_CLK =>  open,
            FAB_LOCK =>  open,
            MSSPSEL =>  open,
            MSSPENABLE =>  open,
            MSSPWRITE =>  open,
            MSSPADDR => open,
            MSSPWDATA => open,
            UART_0_TXD =>  open

            -- Inouts

        );

end behavioral;

