library verilog;
use verilog.vl_types.all;
entity CoreInterrupt is
    generic(
        NUMIRQSRC       : integer := 8;
        NUMFIQSRC       : integer := 0;
        IRQPOLARITY     : integer := 0;
        FIQPOLARITY     : integer := 0
    );
    port(
        PCLK            : in     vl_logic;
        PRESETn         : in     vl_logic;
        PENABLE         : in     vl_logic;
        PSEL            : in     vl_logic;
        PADDR           : in     vl_logic_vector(5 downto 2);
        PWRITE          : in     vl_logic;
        PWDATA          : in     vl_logic_vector(31 downto 0);
        PRDATA          : out    vl_logic_vector(31 downto 0);
        fiqSource7      : in     vl_logic;
        fiqSource6      : in     vl_logic;
        fiqSource5      : in     vl_logic;
        fiqSource4      : in     vl_logic;
        fiqSource3      : in     vl_logic;
        fiqSource2      : in     vl_logic;
        fiqSource1      : in     vl_logic;
        fiqSource0      : in     vl_logic;
        irqSource31     : in     vl_logic;
        irqSource30     : in     vl_logic;
        irqSource29     : in     vl_logic;
        irqSource28     : in     vl_logic;
        irqSource27     : in     vl_logic;
        irqSource26     : in     vl_logic;
        irqSource25     : in     vl_logic;
        irqSource24     : in     vl_logic;
        irqSource23     : in     vl_logic;
        irqSource22     : in     vl_logic;
        irqSource21     : in     vl_logic;
        irqSource20     : in     vl_logic;
        irqSource19     : in     vl_logic;
        irqSource18     : in     vl_logic;
        irqSource17     : in     vl_logic;
        irqSource16     : in     vl_logic;
        irqSource15     : in     vl_logic;
        irqSource14     : in     vl_logic;
        irqSource13     : in     vl_logic;
        irqSource12     : in     vl_logic;
        irqSource11     : in     vl_logic;
        irqSource10     : in     vl_logic;
        irqSource9      : in     vl_logic;
        irqSource8      : in     vl_logic;
        irqSource7      : in     vl_logic;
        irqSource6      : in     vl_logic;
        irqSource5      : in     vl_logic;
        irqSource4      : in     vl_logic;
        irqSource3      : in     vl_logic;
        irqSource2      : in     vl_logic;
        irqSource1      : in     vl_logic;
        irqSource0      : in     vl_logic;
        IRQ             : out    vl_logic;
        FIQ             : out    vl_logic
    );
end CoreInterrupt;
