library Ieee;
use ieee.STd_logic_1164.all;
use IEEe.NUMEric_std.all;
entity COREInterrUPT is
generic (NUMIRQSRC: integer := 8;
NUMFIQSRC: Integer := 0;
IRQPOLARITY: INTeger := 0;
FIQPOLARITY: Integer := 0); port (PCLK: in STD_logic;
PRESETN: in std_lOGIC;
PENABLE: in Std_logic;
PSEL: in STD_Logic;
PADDR: in STD_logic_vectOR(5 downto 2);
PWRITE: in STD_logic;
PWDATA: in STD_logic_vectoR(31 downto 0);
PRDATA: out STD_LOGic_vector(31 downto 0);
fiqSource7: in std_logic;
fiqSOURCE6: in std_logiC;
fiqSource5: in STd_logic;
FIQSource4: in std_logiC;
FIQSOURCe3: in std_logiC;
fiqSourcE2: in Std_logic;
FiqSource1: in STD_LOgic;
FiqSource0: in STD_LOgic;
irqSoURCE31: in std_LOGIC;
IRQSource30: in STD_LOGic;
IRQSOURCe29: in sTD_LOGIC;
IrqSource28: in sTD_LOGIC;
IRQSOUrce27: in sTD_LOGIC;
IRQSource26: in STD_LOgic;
IrqSource25: in Std_logic;
irqSource24: in STd_logic;
irqSouRCE23: in std_logic;
irqSource22: in STD_LOgic;
IRQSOURCe21: in stD_LOGIC;
IRQSOURCe20: in stD_LOGIC;
IRQSOURce19: in sTD_LOGIC;
IrqSource18: in STD_Logic;
irqSource17: in STD_logic;
IRQSource16: in STD_LOGIc;
IRQSource15: in STD_LOGIc;
IRQSOURce14: in sTD_LOGIC;
IRQSOURCe13: in std_lOGIC;
irQSOURCE12: in std_logiC;
irqSource11: in STD_logic;
IrqSource10: in STD_Logic;
IRqSource9: in sTD_LOGIC;
irqSOURCE8: in std_logic;
irqSourCE7: in STd_logic;
IRQSOURce6: in std_logIC;
irqSource5: in STD_logic;
IRQSOURCe4: in std_logiC;
irqSource3: in STD_logic;
IRQSOUrce2: in std_lOGIC;
IrqSource1: in STD_LOGic;
iRQSOURCE0: in std_loGIC;
IRQ: out STD_LOGIc;
FIQ: out Std_logic);
end CoreINTERRUPT;

architecture COREINTerrupt_o of COREINTerrupt is

constant CoreInTERRUPt_l: std_logIC_vectoR(5 downto 2) := X"0";

constant CoREINTERrupt_i: STD_logic_vectOR(5 downto 2) := X"1";

constant COREINTerrupt_ol: std_logic_VECTOR(5 downto 2) := X"2";

constant CoreINTERRUPT_ll: STD_logic_vectoR(5 downto 2) := X"3";

constant CoreInterruPT_IL: std_lOGIC_VECtor(5 downto 2) := X"4";

constant CoREINTERrupt_oi: STD_LOgic_vector(5 downto 2) := X"5";

constant CoREINTERrupt_li: STD_logic_vecTOR(5 downto 2) := X"6";

constant CoreInterRUPT_II: std_lOGIC_VECtor(5 downto 2) := X"7";

constant CoreINTERRUPT_o0: Std_logic_veCTOR(5 downto 2) := X"8";

constant CoreInterruPT_L0: std_LOGIC_Vector(5 downto 2) := X"9";

constant CorEINTERRupt_i0: STd_logic_vecTOR(5 downto 2) := X"a";

constant CoreInterRUPT_O1: std_logIC_VECTOr(5 downto 2) := X"b";

signal COREInterrupt_l1: std_loGIC;

signal COREINTErrupt_i1: Std_logic_veCTOR(31 downto 0);

signal COREInterrupt_ooL: stD_LOGIC_vector(31 downto 0);

signal COREINterrupt_loL: std_logic;

signal COREINterrupt_iol: std_logic_VECTOR(31 downto 0);

signal CoreInterrUPT_OLL: STD_logic_vectOR(7 downto 0);

signal CoreInterrUPT_LLL: STD_LOGic_vector(31 downto 0);

signal CoreInteRRUPT_Ill: STD_Logic_vector(7 downto 0);

signal CoreInTERRUPT_oil: STd_logic_vecTOR(31 downto 0);

signal COREINterrupt_liL: std_logic_VECTOR(7 downto 0);

signal CoREINTERRupt_iil: std_logIC_VECTOr(7 downto 0);

signal CoreINTERRUPT_o0l: STD_logic_vectOR(7 downto 0);

signal CoreInTERRUPT_l0l: Std_logic_veCTOR(7 downto 0);

signal CoreInterrupT_I0L: STD_LOGic_vector(7 downto 0);

signal COREINTerrupt_o1l: std_logic_vECTOR(31 downto 0);

signal CoreInterrUPT_L1L: STD_logic_vectoR(31 downto 0);

signal COreInterrupt_I1L: std_lOGIC_VECtor(31 downto 0);

signal CoreInTERRUPT_ooi: STD_logic_vectoR(31 downto 0);

signal CoreInterrUPT_LOI: STD_logic_vectOR(31 downto 0);

signal COREInterrupt_ioI: std_logiC;

signal CoREINTERRupt_oli: STD_logic;

signal COREINTerrupt_lli: std_logic_VECTOR(7 downto 0);

signal CoreInterrupT_ILI: sTD_LOGIC_vector(31 downto 0);

begin
CoreInteRRUPT_OLl <= (FIQSource7&FIQSOURce6&FIQSource5&FiqSource4&fiqSOURCE3&FIQSOurce2&fiqSource1&fiqSouRCE0);
CorEINTERRUpt_lll <= (IRqSource31&irqSource30&IrqSource29&IRQSOURce28&IRQSOurce27&irqSourcE26&IrqSource25&irQSOURCE24&IRQSOURCe23&irqSource22&iRQSOURCe21&irqSource20&IRQSource19&irqSOURCE18&irqSource17&IRQSOUrce16&irqSOURCE15&irqSource14&IRQSOUrce13&irqSource12&IRQSOURce11&IRQSource10&irqSourCE9&IRQSOUrce8&irqSOURCE7&IRQSOURCe6&irqSource5&irqSource4&irqSoURCE3&irqSouRCE2&irqSouRCE1&irqSOURCE0);
CoreInterrupT_L1 <= '1' when (PWRITE = '1' and PSEL = '1'
and PENABLE = '0') else
'0';
COREINTerrupt_oil <= X"ffffffff" when (NUMIRQSRC = 32) else
X"7fffffff" when (NUMIRQSRC = 31) else
X"3fffffff" when (NUMIRQSRC = 30) else
X"1fffffff" when (NUMIRQSRC = 29) else
X"0fffffff" when (NUMIRQSRC = 28) else
X"07ffffff" when (NUMIRQSRC = 27) else
X"03ffffff" when (NUMIRQSRC = 26) else
X"01ffffff" when (NUMIRQSRC = 25) else
X"00ffffff" when (NUMIRQSRC = 24) else
X"007fffff" when (NUMIRQSRC = 23) else
X"003fffff" when (NUMIRQSRC = 22) else
X"001fffff" when (NUMIRQSRC = 21) else
X"000fffff" when (NUMIRQSRC = 20) else
X"0007ffff" when (NUMIRQSRC = 19) else
X"0003ffff" when (NUMIRQSRC = 18) else
X"0001ffff" when (NUMIRQSRC = 17) else
X"0000ffff" when (NUMIRQSRC = 16) else
X"00007fff" when (NUMIRQSRC = 15) else
X"00003fff" when (NUMIRQSRC = 14) else
X"00001fff" when (NUMIRQSRC = 13) else
X"00000fff" when (NUMIRQSRC = 12) else
X"000007ff" when (NUMIRQSRC = 11) else
X"000003ff" when (NUMIRQSRC = 10) else
X"000001ff" when (NUMIRQSRC = 9) else
X"000000ff" when (NUMIRQSRC = 8) else
X"0000007f" when (NUMIRQSRC = 7) else
X"0000003f" when (NUMIRQSRC = 6) else
X"0000001f" when (NUMIRQSRC = 5) else
X"0000000f" when (NUMIRQSRC = 4) else
X"00000007" when (NUMIRQSRC = 3) else
X"00000003" when (NUMIRQSRC = 2) else
X"00000001" when (NUMIRQSRC = 1) else
X"00000000" when (NUMIRQSRC = 0) else
X"00000000";
CoreINTERRUPT_o1l <= COreInterrupT_LLL and CoreInterRUPT_OIL;
CoreInterRUPT_ILI <= PWDATA and CoreInterruPT_OIL;
CoreINTERRUPt_ill <= X"ff" when (NUMFIQSRC = 8) else
X"7f" when (NUMFIQSRC = 7) else
X"3f" when (NUMFIQSRC = 6) else
X"1f" when (NUMFIQSRC = 5) else
X"0f" when (NUMFIQSRC = 4) else
X"07" when (NUMFIQSRC = 3) else
X"03" when (NUMFIQSRC = 2) else
X"01" when (NUMFIQSRC = 1) else
X"00" when (NUMFIQSRC = 0) else
X"00";
CorEINTERRUpt_lil <= CoreInterruPT_OLL and CoreInterrupT_ILL;
COReInterrupt_LLI <= PWDATA(7 downto 0) and COreInterrupt_ILL;
CoreInterRUPT_IIL <= COReInterrupt_LIL or CoreINTERRUPT_l0l;
CoreInterRUPT_O0l <= CoreInteRRUPT_IIl and CoreInterrupT_I0L;
process (CoreInterrUPT_O0L)
begin
CoreInterRUPT_IOI <= '0';
for CoreInterruPT_OII in 0 to 7
loop
if (COReInterrupt_O0L(COreInterrupt_OII) = '1') then
CoreInterRUPT_IOI <= '1';
end if;
end loop;
end process;
FIQ <= CoreInterruPT_IOI when (FIQPOLARITY = 1) else
not (CoreInterrUPT_IOI);
COREINTerrupt_l1l <= CoreInterruPT_O1L or COreInterrupt_OOI;
COREINterrupt_i1l <= COREINTERrupt_l1l and CoreInterrupT_LOI;
process (CoreInterruPT_I1L)
begin
CoreINTERRUPT_oli <= '0';
for CoreInteRRUPT_OIi in 0 to 31
loop
if (COREINTERRupt_i1l(CoreInterrupt_OII) = '1') then
COREINTERrupt_oli <= '1';
end if;
end loop;
end process;
IRQ <= COREINTErrupt_oli when (IRQPOLARITY = 1) else
not (CoreInterrUPT_OLI);
process (PRESETn,PCLK)
begin
if (PRESETn = '0') then
CoreInterruPT_L0L <= ( others => '0');
elsif (PCLK'eveNT and PCLK = '1') then
if (CoreINTERRUPT_l1 = '1') then
case PADDR is
when CorEINTERRupt_l =>
CoreInTERRUPT_l0l <= (CoreInterruPT_L0L or COreInterrupt_LLI);
when CoreInterruPT_I =>
COREINTerrupt_l0l <= (CoreINTERRUPt_l0l and not (COREInterrupt_lLI));
when others =>
null
;
end case;
end if;
end if;
end process;
process (PRESETn,PCLK)
begin
if (PRESETn = '0') then
COREInterrupt_i0L <= ( others => '0');
elsif (PCLK'event and PCLK = '1') then
if (CoreINTERRUPt_l1 = '1') then
case PADDR is
when CoreInterruPT_OL =>
CoreInterruPT_I0L <= (COREInterrupt_i0L or COreInterrupT_LLI);
when CoreInterRUPT_LL =>
COreInterrupt_I0L <= (COREInterrupt_i0L and not (CoreInterrUPT_LLI));
when others =>
null
;
end case;
end if;
end if;
end process;
process (PRESETN,PCLK)
begin
if (PRESETn = '0') then
COREINTERrupt_ooi <= ( others => '0');
elsif (PCLK'evENT and PCLK = '1') then
if (COREInterrupt_l1 = '1') then
case PADDR is
when CoreInterrUPT_LI =>
COreInterrupT_OOI <= (COREInterrupt_oOI or CoreINTERRUPt_ili);
when CoreINTERRUPt_ii =>
CoreInterrUPT_OOI <= (CoreInterrUPT_OOI and not (CoreInteRRUPT_ILi));
when others =>
null
;
end case;
end if;
end if;
end process;
process (PRESETN,PCLK)
begin
if (PRESETn = '0') then
CoreInterRUPT_LOI <= ( others => '0');
elsif (PCLK'EVent and PCLK = '1') then
if (CoreInteRRUPT_L1 = '1') then
case PADDR is
when CoreInterRUPT_O0 =>
CoreInterruPT_LOI <= (CoreInterrupT_LOI or COREINTERrupt_ili);
when COreInterrupt_L0 =>
COREINTERrupt_loi <= (COReInterrupt_LOI and not (COREInterrupt_iLI));
when others =>
null
;
end case;
end if;
end if;
end process;
process (PSEL,PWRITE,PADDR,COREINterrupt_l0L,COREInterrupt_i0L,CoreInterrupT_IIL,CoreInterrUPT_O0L,COREInterrupt_oOI,COREINterrupt_loi,COReInterrupt_L1L,COReInterrupt_I1L)
begin
COreInterrupT_IOL <= ( others => '0');
if (PWRITE = '0' and PSEL = '1') then
case PADDR is
when CoreInterrupt_L =>
CoreInterrUPT_IOL(7 downto 0) <= COREINTErrupt_l0l;
when COREINTERrupt_ol =>
CoreINTERRUPt_iol(7 downto 0) <= COREInterrupt_i0L;
when COreInterrupt_IL =>
COREINterrupt_iol(7 downto 0) <= COREInterrupt_iIL;
when COreInterrupT_OI =>
CoreInterrUPT_IOL(7 downto 0) <= COREINTERrupt_o0l;
when CoreINTERRUPT_li =>
CoreINTERRUPT_iol(31 downto 0) <= CoreInterrupT_OOI;
when COReInterrupt_O0 =>
COREINterrupt_iol(31 downto 0) <= CoreInterruPT_LOI;
when COreInterrupt_I0 =>
COREINterrupt_ioL(31 downto 0) <= CoreIntERRUPT_L1l;
when CoreInterRUPT_O1 =>
CoreInterruPT_IOL(31 downto 0) <= COReInterrupt_I1L;
when others =>
CoreINTERRUPt_iol <= ( others => '0');
end case;
else
COreInterrupt_IOL <= ( others => '0');
end if;
end process;
CoreInterrUPT_LOL <= '1' when (PSEL = '1' and PWRITE = '0'
and PENABLE = '0') else
'0';
CoreInterrUPT_I1 <= CoreINTERRUPT_iol when (CoreInterruPT_LOL = '1') else
( others => '0');
CoreInteRRUPT_LIi:
process (PRESETn,PCLK)
begin
if (PRESETn = '0') then
COREINterrupt_ool <= ( others => '0');
elsif (PCLK'Event and PCLK = '1') then
CoreINTERRUPT_ool <= COreInterrupT_I1;
end if;
end process CoreInterruPT_LII;
PRDATA <= CoreIntERRUPT_Ool;
end COREINTERrupt_o;
