# Created by Actel Designer Software 10.0.9.37
# Thu Dec 08 17:22:53 2011

# (OPEN DESIGN)


# set default back-annotation base-name
set_defvar "BA_NAME" "top_level_ba"
set_defvar "KEEP_EXISTING_PHYSICAL_CONSTRAINTS" "0"
set_defvar "SDC_IMPORT_MERGE" "0"
set_defvar "IDE_DESIGNERVIEW_NAME" {Impl1}
set_defvar "IDE_DESIGNERVIEW_COUNT" "1"
set_defvar "IDE_DESIGNERVIEW_REV0" {Impl1}
set_defvar "IDE_DESIGNERVIEW_REVNUM0" "1"
set_defvar "IDE_DESIGNERVIEW_ROOTDIR" {C:\A2F_AC339_DF\A2F500\Verilog\designer}
set_defvar "IDE_DESIGNERVIEW_LASTREV" "1"
