`

    #Build: Synplify Pro E-2010.09A-1, Build 006R, Oct  6 2010
    #install: C:\Actel9.1SPB\Libero_v9.1\Synopsys\synplify_E201009A-1
    #OS: Windows XP 5.1
    #Hostname: VXP-SUDEEPS

    #Implementation: synthesis

    #Fri Feb 18 11:08:09 2011

    $ Start of Compile
    #Fri Feb 18 11:08:10 2011

    Synopsys Verilog Compiler, version comp520rcp1, Build 028R, built Sep 23 2010
    @N: :  | Running in 32-bit mode
    Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved

    @I::"C:\Actel9.1SPB\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\smartfusion.v"
    @I::"C:\Actel9.1SPB\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\vlog\hypermods.v"
    @I::"C:\Actelprj\App_notes_upadtes\New\SmartFusion_Using_FABINT_to_Interrupt_MSS_DF\Hardware\A2F200\Verilog\fabint_fab_controller\component\Actel\SmartFusionMSS\MSS\2.4.105\mss_comps.v"
    @I::"C:\Actelprj\App_notes_upadtes\New\SmartFusion_Using_FABINT_to_Interrupt_MSS_DF\Hardware\A2F200\Verilog\fabint_fab_controller\component\work\MSS_top_level\MSS_CCC_0\MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v"
    @I::"C:\Actelprj\App_notes_upadtes\New\SmartFusion_Using_FABINT_to_Interrupt_MSS_DF\Hardware\A2F200\Verilog\fabint_fab_controller\component\work\MSS_top_level\mss_tshell.v"
    @I::"C:\Actelprj\App_notes_upadtes\New\SmartFusion_Using_FABINT_to_Interrupt_MSS_DF\Hardware\A2F200\Verilog\fabint_fab_controller\component\work\MSS_top_level\MSS_top_level.v"
    @I::"C:\Actelprj\App_notes_upadtes\New\SmartFusion_Using_FABINT_to_Interrupt_MSS_DF\Hardware\A2F200\Verilog\fabint_fab_controller\component\Actel\DirectCore\CoreInterrupt\1.1.101\rtl\verilog\o\CoreInterrupt.v"
    @I::"C:\Actelprj\App_notes_upadtes\New\SmartFusion_Using_FABINT_to_Interrupt_MSS_DF\Hardware\A2F200\Verilog\fabint_fab_controller\component\Actel\DirectCore\CoreGPIO\3.0.120\rtl\vlog\core_obfuscated\coregpio.v"
    @I::"C:\Actelprj\App_notes_upadtes\New\SmartFusion_Using_FABINT_to_Interrupt_MSS_DF\Hardware\A2F200\Verilog\fabint_fab_controller\hdl\Interrupt_Source.v"
    @I::"C:\Actelprj\App_notes_upadtes\New\SmartFusion_Using_FABINT_to_Interrupt_MSS_DF\Hardware\A2F200\Verilog\fabint_fab_controller\component\work\Interrupt_Generator\Interrupt_Generator.v"
    @I::"C:\Actelprj\App_notes_upadtes\New\SmartFusion_Using_FABINT_to_Interrupt_MSS_DF\Hardware\A2F200\Verilog\fabint_fab_controller\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3_muxptob3.v"
    @I::"C:\Actelprj\App_notes_upadtes\New\SmartFusion_Using_FABINT_to_Interrupt_MSS_DF\Hardware\A2F200\Verilog\fabint_fab_controller\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v"
    @I::"C:\Actelprj\App_notes_upadtes\New\SmartFusion_Using_FABINT_to_Interrupt_MSS_DF\Hardware\A2F200\Verilog\fabint_fab_controller\component\work\top_level\top_level.v"
    Verilog syntax check successful!
    Options changed - recompiling
    Selecting top level module top_level
    @N:CG364 : mss_comps.v(23) | Synthesizing module INBUF_MSS

    @N:CG364 : smartfusion.v(1814) | Synthesizing module VCC

    @N:CG364 : mss_comps.v(37) | Synthesizing module OUTBUF_MSS

    @N:CG364 : mss_comps.v(151) | Synthesizing module MSS_CCC

    @N:CG364 : mss_comps.v(1) | Synthesizing module MSS_XTLOSC

    @N:CG364 : smartfusion.v(1133) | Synthesizing module GND

    @N:CG364 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(5) | Synthesizing module MSS_top_level_tmp_MSS_CCC_0_MSS_CCC

    @N:CG364 : mss_tshell.v(1) | Synthesizing module MSS_APB

    @N:CG364 : MSS_top_level.v(5) | Synthesizing module MSS_top_level

    @W:CG775 : coreapb3.v(13) | Found Component CoreAPB3 in library COREAPB3_LIB
    @N:CG364 : coreapb3_muxptob3.v(13) | Synthesizing module CAPB3O

    @N:CG364 : coreapb3.v(13) | Synthesizing module CoreAPB3

    	APB_DWIDTH=6'b100000
    	RANGESIZE=21'b000000000000100000000
    	IADDR_ENABLE=1'b0
    	APBSLOT0ENABLE=1'b1
    	APBSLOT1ENABLE=1'b1
    	APBSLOT2ENABLE=1'b0
    	APBSLOT3ENABLE=1'b0
    	APBSLOT4ENABLE=1'b0
    	APBSLOT5ENABLE=1'b0
    	APBSLOT6ENABLE=1'b0
    	APBSLOT7ENABLE=1'b0
    	APBSLOT8ENABLE=1'b0
    	APBSLOT9ENABLE=1'b0
    	APBSLOT10ENABLE=1'b0
    	APBSLOT11ENABLE=1'b0
    	APBSLOT12ENABLE=1'b0
    	APBSLOT13ENABLE=1'b0
    	APBSLOT14ENABLE=1'b0
    	APBSLOT15ENABLE=1'b0
    	CAPB3O1I=32'b00000000000000000000000000001000
    	CAPB3I1I=32'b00000000000000000000000000001000
    	CAPB3l1I=8'b00001100
    	CAPB3OOl=8'b00001000
    	CAPB3IOl=8'b00000100
    	CAPB3lOl=8'b00000000
    	CAPB3OIl=8'b00000100
    	CAPB3IIl=8'b00000000
    	CAPB3lIl=8'b00000000
    	CAPB3Oll=16'b0000000000000001
    	CAPB3Ill=16'b0000000000000010
    	CAPB3lll=16'b0000000000000000
    	CAPB3O0l=16'b0000000000000000
    	CAPB3I0l=16'b0000000000000000
    	CAPB3l0l=16'b0000000000000000
    	CAPB3O1l=16'b0000000000000000
    	CAPB3I1l=16'b0000000000000000
    	CAPB3l1l=16'b0000000000000000
    	CAPB3OO0=16'b0000000000000000
    	CAPB3IO0=16'b0000000000000000
    	CAPB3lO0=16'b0000000000000000
    	CAPB3OI0=16'b0000000000000000
    	CAPB3II0=16'b0000000000000000
    	CAPB3lI0=16'b0000000000000000
    	CAPB3Ol0=16'b0000000000000000
       Generated name = CoreAPB3_Z1

    @N:CG364 : CoreInterrupt.v(3) | Synthesizing module CoreInterrupt

    	NUMIRQSRC=32'b00000000000000000000000000100000
    	NUMFIQSRC=32'b00000000000000000000000000000000
    	IRQPOLARITY=32'b00000000000000000000000000000001
    	FIQPOLARITY=32'b00000000000000000000000000000001
       Generated name = CoreInterrupt_32s_0s_1s_1s

    @N:CG179 : CoreInterrupt.v(1243) | Removing redundant assignment
    @N:CG179 : CoreInterrupt.v(1307) | Removing redundant assignment
    @N:CG179 : CoreInterrupt.v(1371) | Removing redundant assignment
    @N:CG179 : CoreInterrupt.v(1435) | Removing redundant assignment
    @W:CL190 : CoreInterrupt.v(1183) | Optimizing register bit CoreInterrupt_O0I[0] to a constant 0
    @W:CL190 : CoreInterrupt.v(1183) | Optimizing register bit CoreInterrupt_O0I[1] to a constant 0
    @W:CL190 : CoreInterrupt.v(1183) | Optimizing register bit CoreInterrupt_O0I[2] to a constant 0
    @W:CL190 : CoreInterrupt.v(1183) | Optimizing register bit CoreInterrupt_O0I[3] to a constant 0
    @W:CL190 : CoreInterrupt.v(1183) | Optimizing register bit CoreInterrupt_O0I[4] to a constant 0
    @W:CL190 : CoreInterrupt.v(1183) | Optimizing register bit CoreInterrupt_O0I[5] to a constant 0
    @W:CL190 : CoreInterrupt.v(1183) | Optimizing register bit CoreInterrupt_O0I[6] to a constant 0
    @W:CL190 : CoreInterrupt.v(1183) | Optimizing register bit CoreInterrupt_O0I[7] to a constant 0
    @W:CL190 : CoreInterrupt.v(1247) | Optimizing register bit CoreInterrupt_I0I[0] to a constant 0
    @W:CL190 : CoreInterrupt.v(1247) | Optimizing register bit CoreInterrupt_I0I[1] to a constant 0
    @W:CL190 : CoreInterrupt.v(1247) | Optimizing register bit CoreInterrupt_I0I[2] to a constant 0
    @W:CL190 : CoreInterrupt.v(1247) | Optimizing register bit CoreInterrupt_I0I[3] to a constant 0
    @W:CL190 : CoreInterrupt.v(1247) | Optimizing register bit CoreInterrupt_I0I[4] to a constant 0
    @W:CL190 : CoreInterrupt.v(1247) | Optimizing register bit CoreInterrupt_I0I[5] to a constant 0
    @W:CL190 : CoreInterrupt.v(1247) | Optimizing register bit CoreInterrupt_I0I[6] to a constant 0
    @W:CL190 : CoreInterrupt.v(1247) | Optimizing register bit CoreInterrupt_I0I[7] to a constant 0
    @W:CL169 : CoreInterrupt.v(1183) | Pruning Register CoreInterrupt_O0I[7:0]

    @W:CL169 : CoreInterrupt.v(1247) | Pruning Register CoreInterrupt_I0I[7:0]

    @N:CG364 : Interrupt_Source.v(21) | Synthesizing module Interrupt_Source

    @N:CG364 : coregpio.v(9) | Synthesizing module CoreGPIO

    	FAMILY=32'b00000000000000000000000000001111
    	IO_NUM=32'b00000000000000000000000000000011
    	APB_WIDTH=32'b00000000000000000000000000100000
    	OE_TYPE=1'b1
    	INT_BUS=1'b0
    	FIXED_CONFIG_0=1'b1
    	FIXED_CONFIG_1=1'b1
    	FIXED_CONFIG_2=1'b1
    	FIXED_CONFIG_3=1'b0
    	FIXED_CONFIG_4=1'b0
    	FIXED_CONFIG_5=1'b0
    	FIXED_CONFIG_6=1'b0
    	FIXED_CONFIG_7=1'b0
    	FIXED_CONFIG_8=1'b0
    	FIXED_CONFIG_9=1'b0
    	FIXED_CONFIG_10=1'b0
    	FIXED_CONFIG_11=1'b0
    	FIXED_CONFIG_12=1'b0
    	FIXED_CONFIG_13=1'b0
    	FIXED_CONFIG_14=1'b0
    	FIXED_CONFIG_15=1'b0
    	FIXED_CONFIG_16=1'b0
    	FIXED_CONFIG_17=1'b0
    	FIXED_CONFIG_18=1'b0
    	FIXED_CONFIG_19=1'b0
    	FIXED_CONFIG_20=1'b0
    	FIXED_CONFIG_21=1'b0
    	FIXED_CONFIG_22=1'b0
    	FIXED_CONFIG_23=1'b0
    	FIXED_CONFIG_24=1'b0
    	FIXED_CONFIG_25=1'b0
    	FIXED_CONFIG_26=1'b0
    	FIXED_CONFIG_27=1'b0
    	FIXED_CONFIG_28=1'b0
    	FIXED_CONFIG_29=1'b0
    	FIXED_CONFIG_30=1'b0
    	FIXED_CONFIG_31=1'b0
    	IO_TYPE_0=2'b00
    	IO_TYPE_1=2'b00
    	IO_TYPE_2=2'b00
    	IO_TYPE_3=2'b00
    	IO_TYPE_4=2'b00
    	IO_TYPE_5=2'b00
    	IO_TYPE_6=2'b00
    	IO_TYPE_7=2'b00
    	IO_TYPE_8=2'b00
    	IO_TYPE_9=2'b00
    	IO_TYPE_10=2'b00
    	IO_TYPE_11=2'b00
    	IO_TYPE_12=2'b00
    	IO_TYPE_13=2'b00
    	IO_TYPE_14=2'b00
    	IO_TYPE_15=2'b00
    	IO_TYPE_16=2'b00
    	IO_TYPE_17=2'b00
    	IO_TYPE_18=2'b00
    	IO_TYPE_19=2'b00
    	IO_TYPE_20=2'b00
    	IO_TYPE_21=2'b00
    	IO_TYPE_22=2'b00
    	IO_TYPE_23=2'b00
    	IO_TYPE_24=2'b00
    	IO_TYPE_25=2'b00
    	IO_TYPE_26=2'b00
    	IO_TYPE_27=2'b00
    	IO_TYPE_28=2'b00
    	IO_TYPE_29=2'b00
    	IO_TYPE_30=2'b00
    	IO_TYPE_31=2'b00
    	IO_INT_TYPE_0=3'b010
    	IO_INT_TYPE_1=3'b010
    	IO_INT_TYPE_2=3'b010
    	IO_INT_TYPE_3=3'b111
    	IO_INT_TYPE_4=3'b111
    	IO_INT_TYPE_5=3'b111
    	IO_INT_TYPE_6=3'b111
    	IO_INT_TYPE_7=3'b111
    	IO_INT_TYPE_8=3'b111
    	IO_INT_TYPE_9=3'b111
    	IO_INT_TYPE_10=3'b111
    	IO_INT_TYPE_11=3'b111
    	IO_INT_TYPE_12=3'b111
    	IO_INT_TYPE_13=3'b111
    	IO_INT_TYPE_14=3'b111
    	IO_INT_TYPE_15=3'b111
    	IO_INT_TYPE_16=3'b111
    	IO_INT_TYPE_17=3'b111
    	IO_INT_TYPE_18=3'b111
    	IO_INT_TYPE_19=3'b111
    	IO_INT_TYPE_20=3'b111
    	IO_INT_TYPE_21=3'b111
    	IO_INT_TYPE_22=3'b111
    	IO_INT_TYPE_23=3'b111
    	IO_INT_TYPE_24=3'b111
    	IO_INT_TYPE_25=3'b111
    	IO_INT_TYPE_26=3'b111
    	IO_INT_TYPE_27=3'b111
    	IO_INT_TYPE_28=3'b111
    	IO_INT_TYPE_29=3'b111
    	IO_INT_TYPE_30=3'b111
    	IO_INT_TYPE_31=3'b111
    	IO_VAL_0=1'b0
    	IO_VAL_1=1'b0
    	IO_VAL_2=1'b0
    	IO_VAL_3=1'b0
    	IO_VAL_4=1'b0
    	IO_VAL_5=1'b0
    	IO_VAL_6=1'b0
    	IO_VAL_7=1'b0
    	IO_VAL_8=1'b0
    	IO_VAL_9=1'b0
    	IO_VAL_10=1'b0
    	IO_VAL_11=1'b0
    	IO_VAL_12=1'b0
    	IO_VAL_13=1'b0
    	IO_VAL_14=1'b0
    	IO_VAL_15=1'b0
    	IO_VAL_16=1'b0
    	IO_VAL_17=1'b0
    	IO_VAL_18=1'b0
    	IO_VAL_19=1'b0
    	IO_VAL_20=1'b0
    	IO_VAL_21=1'b0
    	IO_VAL_22=1'b0
    	IO_VAL_23=1'b0
    	IO_VAL_24=1'b0
    	IO_VAL_25=1'b0
    	IO_VAL_26=1'b0
    	IO_VAL_27=1'b0
    	IO_VAL_28=1'b0
    	IO_VAL_29=1'b0
    	IO_VAL_30=1'b0
    	IO_VAL_31=1'b0
    	CGPIOO=32'b11100000000000000000000000000000
    	CGPIOI=96'b010010010111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
    	CGPIOl=64'b0000000000000000000000000000000000000000000000000000000000000000
    	CGPIOOI=32'b00000000000000000000000000000000
       Generated name = CoreGPIO_Z2

    @N:CG179 : coregpio.v(3305) | Removing redundant assignment
    @W:CL169 : coregpio.v(3535) | Pruning Register CGPIOl1I.CGPIOIOl[2].CGPIOl0l.CGPIOIOI[2]

    @W:CL169 : coregpio.v(3322) | Pruning Register CGPIOl1I.CGPIOIOl[2].CGPIOl0l.CGPIOlOI[2]

    @W:CL169 : coregpio.v(3535) | Pruning Register CGPIOl1I.CGPIOIOl[1].CGPIOl0l.CGPIOIOI[1]

    @W:CL169 : coregpio.v(3322) | Pruning Register CGPIOl1I.CGPIOIOl[1].CGPIOl0l.CGPIOlOI[1]

    @W:CL169 : coregpio.v(3535) | Pruning Register CGPIOl1I.CGPIOIOl[0].CGPIOl0l.CGPIOIOI[0]

    @W:CL169 : coregpio.v(3322) | Pruning Register CGPIOl1I.CGPIOIOl[0].CGPIOl0l.CGPIOlOI[0]

    @N:CG364 : Interrupt_Generator.v(5) | Synthesizing module Interrupt_Generator

    @W:CL168 : Interrupt_Generator.v(94) | Pruning instance VCC - not in use ...

    @N:CG364 : top_level.v(5) | Synthesizing module top_level

    @W:CL246 : coregpio.v(1394) | Input port bits 31 to 3 of PWDATA[31:0] are unused

    @W:CL159 : CoreInterrupt.v(214) | Input fiqSource7 is unused
    @W:CL159 : CoreInterrupt.v(217) | Input fiqSource6 is unused
    @W:CL159 : CoreInterrupt.v(220) | Input fiqSource5 is unused
    @W:CL159 : CoreInterrupt.v(223) | Input fiqSource4 is unused
    @W:CL159 : CoreInterrupt.v(226) | Input fiqSource3 is unused
    @W:CL159 : CoreInterrupt.v(229) | Input fiqSource2 is unused
    @W:CL159 : CoreInterrupt.v(232) | Input fiqSource1 is unused
    @W:CL159 : CoreInterrupt.v(235) | Input fiqSource0 is unused
    @W:CL246 : coreapb3.v(217) | Input port bits 23 to 12 of PADDR[23:0] are unused

    @W:CL159 : coreapb3.v(208) | Input PRESETN is unused
    @W:CL159 : coreapb3.v(210) | Input PCLK is unused
    @W:CL159 : coreapb3.v(363) | Input PRDATAS2 is unused
    @W:CL159 : coreapb3.v(370) | Input PRDATAS3 is unused
    @W:CL159 : coreapb3.v(377) | Input PRDATAS4 is unused
    @W:CL159 : coreapb3.v(384) | Input PRDATAS5 is unused
    @W:CL159 : coreapb3.v(391) | Input PRDATAS6 is unused
    @W:CL159 : coreapb3.v(398) | Input PRDATAS7 is unused
    @W:CL159 : coreapb3.v(405) | Input PRDATAS8 is unused
    @W:CL159 : coreapb3.v(412) | Input PRDATAS9 is unused
    @W:CL159 : coreapb3.v(419) | Input PRDATAS10 is unused
    @W:CL159 : coreapb3.v(426) | Input PRDATAS11 is unused
    @W:CL159 : coreapb3.v(433) | Input PRDATAS12 is unused
    @W:CL159 : coreapb3.v(440) | Input PRDATAS13 is unused
    @W:CL159 : coreapb3.v(447) | Input PRDATAS14 is unused
    @W:CL159 : coreapb3.v(454) | Input PRDATAS15 is unused
    @W:CL159 : coreapb3.v(460) | Input PREADYS2 is unused
    @W:CL159 : coreapb3.v(462) | Input PREADYS3 is unused
    @W:CL159 : coreapb3.v(464) | Input PREADYS4 is unused
    @W:CL159 : coreapb3.v(466) | Input PREADYS5 is unused
    @W:CL159 : coreapb3.v(468) | Input PREADYS6 is unused
    @W:CL159 : coreapb3.v(470) | Input PREADYS7 is unused
    @W:CL159 : coreapb3.v(472) | Input PREADYS8 is unused
    @W:CL159 : coreapb3.v(474) | Input PREADYS9 is unused
    @W:CL159 : coreapb3.v(476) | Input PREADYS10 is unused
    @W:CL159 : coreapb3.v(478) | Input PREADYS11 is unused
    @W:CL159 : coreapb3.v(480) | Input PREADYS12 is unused
    @W:CL159 : coreapb3.v(482) | Input PREADYS13 is unused
    @W:CL159 : coreapb3.v(484) | Input PREADYS14 is unused
    @W:CL159 : coreapb3.v(486) | Input PREADYS15 is unused
    @W:CL159 : coreapb3.v(492) | Input PSLVERRS2 is unused
    @W:CL159 : coreapb3.v(494) | Input PSLVERRS3 is unused
    @W:CL159 : coreapb3.v(496) | Input PSLVERRS4 is unused
    @W:CL159 : coreapb3.v(498) | Input PSLVERRS5 is unused
    @W:CL159 : coreapb3.v(500) | Input PSLVERRS6 is unused
    @W:CL159 : coreapb3.v(502) | Input PSLVERRS7 is unused
    @W:CL159 : coreapb3.v(504) | Input PSLVERRS8 is unused
    @W:CL159 : coreapb3.v(506) | Input PSLVERRS9 is unused
    @W:CL159 : coreapb3.v(508) | Input PSLVERRS10 is unused
    @W:CL159 : coreapb3.v(510) | Input PSLVERRS11 is unused
    @W:CL159 : coreapb3.v(512) | Input PSLVERRS12 is unused
    @W:CL159 : coreapb3.v(514) | Input PSLVERRS13 is unused
    @W:CL159 : coreapb3.v(516) | Input PSLVERRS14 is unused
    @W:CL159 : coreapb3.v(518) | Input PSLVERRS15 is unused
    @W:CL157 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(62) | *Output RCOSC_CLKOUT has undriven bits - a simulation mismatch is possible
    @W:CL157 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(63) | *Output MAINXIN_CLKOUT has undriven bits - a simulation mismatch is possible
    @W:CL157 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(64) | *Output LPXIN_CLKOUT has undriven bits - a simulation mismatch is possible
    @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(36) | Input CLKA is unused
    @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(37) | Input CLKA_PAD is unused
    @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(38) | Input CLKA_PADP is unused
    @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(39) | Input CLKA_PADN is unused
    @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(40) | Input CLKB is unused
    @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(41) | Input CLKB_PAD is unused
    @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(42) | Input CLKB_PADP is unused
    @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(43) | Input CLKB_PADN is unused
    @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(44) | Input CLKC is unused
    @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(45) | Input CLKC_PAD is unused
    @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(46) | Input CLKC_PADP is unused
    @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(47) | Input CLKC_PADN is unused
    @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(49) | Input LPXIN is unused
    @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(50) | Input MAC_CLK is unused
    @END
    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Fri Feb 18 11:08:10 2011

    ###########################################################]

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Synopsys Actel Technology Mapper, Version mapact, Build 023R, Built Sep 29 2010 09:29:00 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved Product Version E-2010.09A-1 @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled @W:MO111 : mss_top_level_tmp_mss_ccc_0_mss_ccc.v(62) | tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module MSS_top_level_tmp_MSS_CCC_0_MSS_CCC) @W:MO111 : mss_top_level_tmp_mss_ccc_0_mss_ccc.v(63) | tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module MSS_top_level_tmp_MSS_CCC_0_MSS_CCC) @W:MO111 : mss_top_level_tmp_mss_ccc_0_mss_ccc.v(64) | tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module MSS_top_level_tmp_MSS_CCC_0_MSS_CCC) Available hyper_sources - for debug and ip models None Found @W: : mss_top_level_tmp_mss_ccc_0_mss_ccc.v(79) | Net MSS_top_level_0.MSS_ADLIB_INST_FCLK appears to be a clock source which was not identfied. Assuming default frequency. @W: : mss_top_level_tmp_mss_ccc_0_mss_ccc.v(79) | Net Interrupt_Generator_0/PCLK appears to be a clock source which was not identfied. Assuming default frequency. Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 60MB peak: 60MB) @N:MF238 : interrupt_source.v(90) | Found 32 bit incrementor, 'un3_counter1_1[31:0]' @N:MF238 : interrupt_source.v(114) | Found 32 bit incrementor, 'un2_counter2_1[31:0]' Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 61MB peak: 62MB) Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 61MB peak: 62MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 61MB peak: 62MB) Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 62MB peak: 62MB) Finished Early Timing Optimization (Time elapsed 0h:00m:02s; Memory used current: 62MB peak: 62MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:02s; Memory used current: 62MB peak: 62MB) Finished preparing to map (Time elapsed 0h:00m:03s; Memory used current: 62MB peak: 62MB) High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes ------------------------------------------------------------------------------------------------------------------ MSS_top_level_0.MSS_CCC_0.I_MSSCCC / LOCK 181 : 181 asynchronous set/reset MSS_top_level_0.MSS_ADLIB_INST / MSSPADDR[2] 101 MSS_top_level_0.MSS_ADLIB_INST / MSSPADDR[3] 71 CoreAPB3_0.CAPB3O11_0_a2[0] / Y 34 Interrupt_Generator_0.CoreInterrupt_0.un1_CoreInterrupt_O0I11_i_a2_0_a9 / Y 32 Interrupt_Generator_0.CoreInterrupt_0.un1_CoreInterrupt_O0I11_1_i_a2_1_a9 / Y 32 Interrupt_Generator_0.CoreInterrupt_0.CoreInterrupt_l1_0_i_o9[11] / Y 32 ================================================================================================================== Replicating Combinational Instance Interrupt_Generator_0.CoreInterrupt_0.CoreInterrupt_l1_0_i_o9[11], fanout 32 segments 2 Replicating Combinational Instance Interrupt_Generator_0.CoreInterrupt_0.un1_CoreInterrupt_O0I11_1_i_a2_1_a9, fanout 32 segments 2 Replicating Combinational Instance Interrupt_Generator_0.CoreInterrupt_0.un1_CoreInterrupt_O0I11_i_a2_0_a9, fanout 32 segments 2 Replicating Combinational Instance CoreAPB3_0.CAPB3O11_0_a2[0], fanout 34 segments 2 Finished technology mapping (Time elapsed 0h:00m:03s; Memory used current: 63MB peak: 64MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:03s; Memory used current: 63MB peak: 64MB) Added 0 Buffers Added 4 Cells via replication Added 0 Sequential Cells via replication Added 4 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:03s; Memory used current: 63MB peak: 64MB) Writing Analyst data base C:\Actelprj\App_notes_upadtes\New\SmartFusion_Using_FABINT_to_Interrupt_MSS_DF\Hardware\A2F200\Verilog\fabint_fab_controller\synthesis\top_level.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:03s; Memory used current: 62MB peak: 64MB) Writing EDIF Netlist and constraint files E-2010.09A-1 Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:03s; Memory used current: 62MB peak: 64MB) @W:MT246 : mss_top_level_tmp_mss_ccc_0_mss_ccc.v(97) | Blackbox MSS_XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock MSS_top_level|MSS_ADLIB_INST_EMCCLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:MSS_top_level_0.MSS_ADLIB_INST_EMCCLK" @W:MT420 : | Found inferred clock MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:MSS_top_level_0_FAB_CLK" @W:MT420 : | Found inferred clock MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:MSS_top_level_0.MSS_ADLIB_INST_FCLK" ##### START OF TIMING REPORT #####[ # Timing Report written on Fri Feb 18 11:08:16 2011 # Top view: top_level Library name: smartfusion Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree ) Requested Frequency: 100.0 MHz Wire load mode: top Wire load model: smartfusion Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: -0.884 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock 100.0 MHz 91.9 MHz 10.000 10.884 -0.884 inferred Inferred_clkgroup_1 MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock 100.0 MHz 100.9 MHz 10.000 9.910 0.090 inferred Inferred_clkgroup_2 ================================================================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock | 10.000 -0.884 | No paths - | No paths - | No paths - MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock | 10.000 0.090 | No paths - | No paths - | No paths - =============================================================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[2] MSS_top_level_0_MSS_MASTER_APB_PADDR_\[2\] 2.679 -0.884 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[3] MSS_top_level_0_MSS_MASTER_APB_PADDR_\[3\] 2.679 0.124 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[1] MSS_top_level_0_MSS_MASTER_APB_PADDR_\[1\] 2.679 0.326 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[0] MSS_top_level_0_MSS_MASTER_APB_PADDR_\[0\] 2.679 0.465 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[6] MSS_top_level_0_MSS_MASTER_APB_PADDR_\[6\] 2.679 0.465 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[7] MSS_top_level_0_MSS_MASTER_APB_PADDR_\[7\] 2.679 0.575 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[11] MSS_top_level_0_MSS_MASTER_APB_PADDR_\[11\] 2.679 0.684 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[10] MSS_top_level_0_MSS_MASTER_APB_PADDR_\[10\] 2.679 0.823 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[9] MSS_top_level_0_MSS_MASTER_APB_PADDR_\[9\] 2.679 0.910 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPSEL MSS_top_level_0_MSS_MASTER_APB_PSELx 2.490 1.208 ============================================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[2] PRDATA_0[2] 10.000 -0.884 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[0] PRDATA_1[0] 10.000 0.795 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[1] PRDATA_1[1] 10.000 0.910 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[3] PRDATA_3_0_a3 10.000 1.887 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[4] PRDATA_4_0_a3 10.000 1.887 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[5] PRDATA_5_0_a3 10.000 1.887 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[6] PRDATA_6_0_a3 10.000 1.887 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[7] PRDATA_7_0_a3 10.000 1.887 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[8] PRDATA_8_0_a3 10.000 1.887 MSS_top_level_0.MSS_ADLIB_INST MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[9] PRDATA_9_0_a3 10.000 1.887 ================================================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.000 - Propagation time: 10.884 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.884 Number of logic level(s): 4 Starting point: MSS_top_level_0.MSS_ADLIB_INST / MSSPADDR[2] Ending point: MSS_top_level_0.MSS_ADLIB_INST / MSSPRDATA[2] The start point is clocked by MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK The end point is clocked by MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------ MSS_top_level_0.MSS_ADLIB_INST MSS_APB MSSPADDR[2] Out 2.679 2.679 - MSS_top_level_0_MSS_MASTER_APB_PADDR_\[2\] Net - - 3.843 - 101 Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_1_3[0] OR2A B In - 6.522 - Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_1_3[0] OR2A Y Out 0.646 7.168 - CGPIOl0_0_o2_1_3[0] Net - - 0.386 - 2 Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_0[0] NOR3 C In - 7.554 - Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_0[0] NOR3 Y Out 0.751 8.305 - N_21 Net - - 0.806 - 3 CoreAPB3_0.CAPB3llOI.PRDATA_a0[2] OR3C C In - 9.111 - CoreAPB3_0.CAPB3llOI.PRDATA_a0[2] OR3C Y Out 0.666 9.777 - N_1_3 Net - - 0.322 - 1 CoreAPB3_0.CAPB3llOI.PRDATA_0[2] OR3C A In - 10.098 - CoreAPB3_0.CAPB3llOI.PRDATA_0[2] OR3C Y Out 0.464 10.562 - PRDATA_0[2] Net - - 0.322 - 1 MSS_top_level_0.MSS_ADLIB_INST MSS_APB MSSPRDATA[2] In - 10.884 - ============================================================================================================================== Total path delay (propagation time + setup) of 10.884 is 5.206(47.8%) logic and 5.678(52.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.000 - Propagation time: 9.876 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 0.124 Number of logic level(s): 4 Starting point: MSS_top_level_0.MSS_ADLIB_INST / MSSPADDR[3] Ending point: MSS_top_level_0.MSS_ADLIB_INST / MSSPRDATA[2] The start point is clocked by MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK The end point is clocked by MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------- MSS_top_level_0.MSS_ADLIB_INST MSS_APB MSSPADDR[3] Out 2.679 2.679 - MSS_top_level_0_MSS_MASTER_APB_PADDR_\[3\] Net - - 3.466 - 71 CoreAPB3_0.CAPB3llOI.PRDATA_1_a1_0_0[2] NOR2 A In - 6.144 - CoreAPB3_0.CAPB3llOI.PRDATA_1_a1_0_0[2] NOR2 Y Out 0.507 6.652 - PRDATA_1_a1_0_0[2] Net - - 0.322 - 1 CoreAPB3_0.CAPB3llOI.PRDATA_1_a1_0_3[2] NOR3B A In - 6.973 - CoreAPB3_0.CAPB3llOI.PRDATA_1_a1_0_3[2] NOR3B Y Out 0.666 7.639 - PRDATA_1_a1_0_3[2] Net - - 0.322 - 1 CoreAPB3_0.CAPB3llOI.PRDATA_1_a1_0[2] OR3C C In - 7.960 - CoreAPB3_0.CAPB3llOI.PRDATA_1_a1_0[2] OR3C Y Out 0.666 8.626 - N_2_i Net - - 0.322 - 1 CoreAPB3_0.CAPB3llOI.PRDATA_0[2] OR3C B In - 8.948 - CoreAPB3_0.CAPB3llOI.PRDATA_0[2] OR3C Y Out 0.607 9.554 - PRDATA_0[2] Net - - 0.322 - 1 MSS_top_level_0.MSS_ADLIB_INST MSS_APB MSSPRDATA[2] In - 9.876 - ==================================================================================================================== Total path delay (propagation time + setup) of 9.876 is 5.124(51.9%) logic and 4.752(48.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.000 - Propagation time: 9.674 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 0.326 Number of logic level(s): 6 Starting point: MSS_top_level_0.MSS_ADLIB_INST / MSSPADDR[1] Ending point: MSS_top_level_0.MSS_ADLIB_INST / MSSPRDATA[2] The start point is clocked by MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK The end point is clocked by MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------- MSS_top_level_0.MSS_ADLIB_INST MSS_APB MSSPADDR[1] Out 2.679 2.679 - MSS_top_level_0_MSS_MASTER_APB_PADDR_\[1\] Net - - 0.322 - 1 Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_1_2_0[0] OR2 B In - 3.000 - Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_1_2_0[0] OR2 Y Out 0.646 3.647 - CGPIOl0_0_o2_1_2_0[0] Net - - 0.322 - 1 Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_1_2[0] NOR2 B In - 3.968 - Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_1_2[0] NOR2 Y Out 0.646 4.615 - CGPIOl0_0_o2_1_2[0] Net - - 0.806 - 3 Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_1_3[0] OR2A A In - 5.421 - Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_1_3[0] OR2A Y Out 0.537 5.958 - CGPIOl0_0_o2_1_3[0] Net - - 0.386 - 2 Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_0[0] NOR3 C In - 6.344 - Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_0[0] NOR3 Y Out 0.751 7.095 - N_21 Net - - 0.806 - 3 CoreAPB3_0.CAPB3llOI.PRDATA_a0[2] OR3C C In - 7.901 - CoreAPB3_0.CAPB3llOI.PRDATA_a0[2] OR3C Y Out 0.666 8.567 - N_1_3 Net - - 0.322 - 1 CoreAPB3_0.CAPB3llOI.PRDATA_0[2] OR3C A In - 8.888 - CoreAPB3_0.CAPB3llOI.PRDATA_0[2] OR3C Y Out 0.464 9.352 - PRDATA_0[2] Net - - 0.322 - 1 MSS_top_level_0.MSS_ADLIB_INST MSS_APB MSSPRDATA[2] In - 9.674 - ================================================================================================================================ Total path delay (propagation time + setup) of 9.674 is 6.389(66.0%) logic and 3.285(34.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.000 - Propagation time: 9.535 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 0.465 Number of logic level(s): 6 Starting point: MSS_top_level_0.MSS_ADLIB_INST / MSSPADDR[0] Ending point: MSS_top_level_0.MSS_ADLIB_INST / MSSPRDATA[2] The start point is clocked by MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK The end point is clocked by MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------- MSS_top_level_0.MSS_ADLIB_INST MSS_APB MSSPADDR[0] Out 2.679 2.679 - MSS_top_level_0_MSS_MASTER_APB_PADDR_\[0\] Net - - 0.322 - 1 Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_1_2_0[0] OR2 A In - 3.000 - Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_1_2_0[0] OR2 Y Out 0.507 3.508 - CGPIOl0_0_o2_1_2_0[0] Net - - 0.322 - 1 Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_1_2[0] NOR2 B In - 3.829 - Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_1_2[0] NOR2 Y Out 0.646 4.476 - CGPIOl0_0_o2_1_2[0] Net - - 0.806 - 3 Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_1_3[0] OR2A A In - 5.282 - Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_1_3[0] OR2A Y Out 0.537 5.819 - CGPIOl0_0_o2_1_3[0] Net - - 0.386 - 2 Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_0[0] NOR3 C In - 6.205 - Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_0[0] NOR3 Y Out 0.751 6.956 - N_21 Net - - 0.806 - 3 CoreAPB3_0.CAPB3llOI.PRDATA_a0[2] OR3C C In - 7.762 - CoreAPB3_0.CAPB3llOI.PRDATA_a0[2] OR3C Y Out 0.666 8.428 - N_1_3 Net - - 0.322 - 1 CoreAPB3_0.CAPB3llOI.PRDATA_0[2] OR3C A In - 8.749 - CoreAPB3_0.CAPB3llOI.PRDATA_0[2] OR3C Y Out 0.464 9.213 - PRDATA_0[2] Net - - 0.322 - 1 MSS_top_level_0.MSS_ADLIB_INST MSS_APB MSSPRDATA[2] In - 9.535 - ================================================================================================================================ Total path delay (propagation time + setup) of 9.535 is 6.250(65.6%) logic and 3.285(34.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.000 - Propagation time: 9.535 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 0.465 Number of logic level(s): 6 Starting point: MSS_top_level_0.MSS_ADLIB_INST / MSSPADDR[6] Ending point: MSS_top_level_0.MSS_ADLIB_INST / MSSPRDATA[2] The start point is clocked by MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK The end point is clocked by MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------- MSS_top_level_0.MSS_ADLIB_INST MSS_APB MSSPADDR[6] Out 2.679 2.679 - MSS_top_level_0_MSS_MASTER_APB_PADDR_\[6\] Net - - 0.322 - 1 Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_1_2_1[0] OR2A B In - 3.000 - Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_1_2_1[0] OR2A Y Out 0.646 3.647 - CGPIOl0_0_o2_1_2_1[0] Net - - 0.322 - 1 Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_1_2[0] NOR2 A In - 3.968 - Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_1_2[0] NOR2 Y Out 0.507 4.476 - CGPIOl0_0_o2_1_2[0] Net - - 0.806 - 3 Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_1_3[0] OR2A A In - 5.282 - Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_1_3[0] OR2A Y Out 0.537 5.819 - CGPIOl0_0_o2_1_3[0] Net - - 0.386 - 2 Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_0[0] NOR3 C In - 6.205 - Interrupt_Generator_0.CoreGPIO_0.CGPIOl0_0_o2_0[0] NOR3 Y Out 0.751 6.956 - N_21 Net - - 0.806 - 3 CoreAPB3_0.CAPB3llOI.PRDATA_a0[2] OR3C C In - 7.762 - CoreAPB3_0.CAPB3llOI.PRDATA_a0[2] OR3C Y Out 0.666 8.428 - N_1_3 Net - - 0.322 - 1 CoreAPB3_0.CAPB3llOI.PRDATA_0[2] OR3C A In - 8.749 - CoreAPB3_0.CAPB3llOI.PRDATA_0[2] OR3C Y Out 0.464 9.213 - PRDATA_0[2] Net - - 0.322 - 1 MSS_top_level_0.MSS_ADLIB_INST MSS_APB MSSPRDATA[2] In - 9.535 - ================================================================================================================================ Total path delay (propagation time + setup) of 9.535 is 6.250(65.6%) logic and 3.285(34.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Interrupt_Generator_0.Interrupt_Source_0.counter1[3] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter1[3] 0.737 0.090 Interrupt_Generator_0.Interrupt_Source_0.counter2[3] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter2[3] 0.737 0.090 Interrupt_Generator_0.Interrupt_Source_0.counter1[4] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter1[4] 0.737 0.092 Interrupt_Generator_0.Interrupt_Source_0.counter2[4] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter2[4] 0.737 0.092 Interrupt_Generator_0.Interrupt_Source_0.counter1[5] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter1[5] 0.737 0.153 Interrupt_Generator_0.Interrupt_Source_0.counter2[5] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter2[5] 0.737 0.153 Interrupt_Generator_0.Interrupt_Source_0.counter2[1] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter2[1] 0.737 0.403 Interrupt_Generator_0.Interrupt_Source_0.counter2[2] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter2[2] 0.737 0.512 Interrupt_Generator_0.Interrupt_Source_0.counter2[0] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter2[0] 0.737 0.546 Interrupt_Generator_0.Interrupt_Source_0.counter1[1] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter1[1] 0.737 0.567 ============================================================================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Interrupt_Generator_0.Interrupt_Source_0.counter1[28] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D I_203_0 9.461 0.090 Interrupt_Generator_0.Interrupt_Source_0.counter1[29] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D I_210_0 9.461 0.090 Interrupt_Generator_0.Interrupt_Source_0.counter1[30] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D I_217_0 9.461 0.090 Interrupt_Generator_0.Interrupt_Source_0.counter1[31] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D I_224_0 9.461 0.090 Interrupt_Generator_0.Interrupt_Source_0.counter2[28] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D I_203 9.461 0.090 Interrupt_Generator_0.Interrupt_Source_0.counter2[29] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D I_210 9.461 0.090 Interrupt_Generator_0.Interrupt_Source_0.counter2[30] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D I_217 9.461 0.090 Interrupt_Generator_0.Interrupt_Source_0.counter2[31] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D I_224 9.461 0.090 Interrupt_Generator_0.Interrupt_Source_0.counter2[12] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D counter2_3[12] 9.427 0.403 Interrupt_Generator_0.Interrupt_Source_0.counter1[15] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D counter1_3[15] 9.427 0.567 ================================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 9.371 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 0.090 Number of logic level(s): 5 Starting point: Interrupt_Generator_0.Interrupt_Source_0.counter1[3] / Q Ending point: Interrupt_Generator_0.Interrupt_Source_0.counter1[28] / D The start point is clocked by MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------ Interrupt_Generator_0.Interrupt_Source_0.counter1[3] DFN1C0 Q Out 0.737 0.737 - counter1[3] Net - - 1.423 - 6 Interrupt_Generator_0.Interrupt_Source_0.un3_counter1_1.I_34 AND3 A In - 2.160 - Interrupt_Generator_0.Interrupt_Source_0.un3_counter1_1.I_34 AND3 Y Out 0.464 2.624 - DWACT_FINC_E_0[2] Net - - 1.423 - 6 Interrupt_Generator_0.Interrupt_Source_0.un3_counter1_1.I_152 AND3 B In - 4.048 - Interrupt_Generator_0.Interrupt_Source_0.un3_counter1_1.I_152 AND3 Y Out 0.607 4.654 - DWACT_FINC_E_0[29] Net - - 1.423 - 6 Interrupt_Generator_0.Interrupt_Source_0.un3_counter1_1.I_199 AND2 A In - 6.078 - Interrupt_Generator_0.Interrupt_Source_0.un3_counter1_1.I_199 AND2 Y Out 0.514 6.592 - DWACT_FINC_E_0[24] Net - - 1.184 - 4 Interrupt_Generator_0.Interrupt_Source_0.un3_counter1_1.I_202 AND3 A In - 7.776 - Interrupt_Generator_0.Interrupt_Source_0.un3_counter1_1.I_202 AND3 Y Out 0.464 8.240 - N_19_0 Net - - 0.322 - 1 Interrupt_Generator_0.Interrupt_Source_0.un3_counter1_1.I_203 XOR2 A In - 8.561 - Interrupt_Generator_0.Interrupt_Source_0.un3_counter1_1.I_203 XOR2 Y Out 0.488 9.049 - I_203_0 Net - - 0.322 - 1 Interrupt_Generator_0.Interrupt_Source_0.counter1[28] DFN1C0 D In - 9.371 - ============================================================================================================================== Total path delay (propagation time + setup) of 9.910 is 3.813(38.5%) logic and 6.097(61.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Target Part: A2F200M3F_FBGA484_Std Report for cell top_level.verilog Core Cell usage: cell count area count*area AND2 24 1.0 24.0 AND3 94 1.0 94.0 AO1 2 1.0 2.0 AO1A 3 1.0 3.0 AO1B 3 1.0 3.0 AO1C 2 1.0 2.0 AO1D 1 1.0 1.0 AOI1B 11 1.0 11.0 GND 9 0.0 0.0 INV 2 1.0 2.0 MSS_CCC 1 0.0 0.0 MX2B 65 1.0 65.0 NOR2 20 1.0 20.0 NOR2A 65 1.0 65.0 NOR2B 13 1.0 13.0 NOR3 12 1.0 12.0 NOR3A 12 1.0 12.0 NOR3B 7 1.0 7.0 NOR3C 28 1.0 28.0 OA1C 53 1.0 53.0 OAI1 3 1.0 3.0 OR2 26 1.0 26.0 OR2A 8 1.0 8.0 OR2B 22 1.0 22.0 OR3 4 1.0 4.0 OR3A 3 1.0 3.0 OR3B 1 1.0 1.0 OR3C 4 1.0 4.0 VCC 9 0.0 0.0 XOR2 63 1.0 63.0 DFN1C0 112 1.0 112.0 DFN1E1C0 70 1.0 70.0 DFN1P0 2 1.0 2.0 MSS_APB 1 0.0 0.0 ----- ---------- TOTAL 755 735.0 IO Cell usage: cell count INBUF 1 INBUF_MSS 2 MSS_XTLOSC 1 OUTBUF_MSS 1 ----- TOTAL 5 Core Cells : 735 of 4608 (16%) IO Cells : 5 RAM/ROM Usage Summary Block Rams : 0 of 8 (0%) Mapper successful! Process took 0h:00m:05s realtime, 0h:00m:04s cputime # Fri Feb 18 11:08:16 2011 ###########################################################]