Timing Report Min Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Thu Dec 08 16:59:51 2011


Design: top_level
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                10.951
Frequency (MHz):            91.316
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                8.153
Frequency (MHz):            122.654
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.383
External Hold (ns):         1.283
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               MSS_top_level_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[27]
  Delay (ns):                  3.889
  Slack (ns):
  Arrival (ns):                3.889
  Required (ns):
  Hold (ns):                   1.292

Path 2
  From:                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[26]
  Delay (ns):                  3.952
  Slack (ns):
  Arrival (ns):                3.952
  Required (ns):
  Hold (ns):                   1.314

Path 3
  From:                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[9]
  Delay (ns):                  3.996
  Slack (ns):
  Arrival (ns):                3.996
  Required (ns):
  Hold (ns):                   1.332

Path 4
  From:                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[22]
  Delay (ns):                  4.125
  Slack (ns):
  Arrival (ns):                4.125
  Required (ns):
  Hold (ns):                   1.301

Path 5
  From:                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[8]
  Delay (ns):                  4.153
  Slack (ns):
  Arrival (ns):                4.153
  Required (ns):
  Hold (ns):                   1.311


Expanded Path 1
  From: MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB
  To: MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[27]
  data arrival time                              3.889
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     1.334          cell: ADLIB:MSS_APB_IP
  1.334                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPADDR[8] (r)
               +     0.059          net: MSS_top_level_0/MSS_ADLIB_INST/MSSPADDR[8]INT_NET
  1.393                        MSS_top_level_0/MSS_ADLIB_INST/U_32:PIN3INT (r)
               +     0.040          cell: ADLIB:MSS_IF
  1.433                        MSS_top_level_0/MSS_ADLIB_INST/U_32:PIN3 (r)
               +     0.606          net: _MSS_top_level_0_MSS_MASTER_APB_PADDR_[8]_
  2.039                        CoreAPB3_0/CAPB3iool_0_a2_0[0]:C (r)
               +     0.292          cell: ADLIB:OR3
  2.331                        CoreAPB3_0/CAPB3iool_0_a2_0[0]:Y (r)
               +     0.553          net: CoreAPB3_0_APBmslave0_PSELx_0
  2.884                        CoreAPB3_0/CAPB3O1II/PRDATA_27_0_a3:B (r)
               +     0.223          cell: ADLIB:NOR2A
  3.107                        CoreAPB3_0/CAPB3O1II/PRDATA_27_0_a3:Y (f)
               +     0.455          net: _MSS_top_level_0_MSS_MASTER_APB_PRDATA_[27]_
  3.562                        MSS_top_level_0/MSS_ADLIB_INST/U_56:PIN6 (f)
               +     0.083          cell: ADLIB:MSS_IF
  3.645                        MSS_top_level_0/MSS_ADLIB_INST/U_56:PIN6INT (f)
               +     0.244          net: MSS_top_level_0/MSS_ADLIB_INST/MSSPRDATA[27]INT_NET
  3.889                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[27] (f)
                                    
  3.889                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_fabric_interface_clock
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     1.292          Library hold time: ADLIB:MSS_APB_IP
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[27]


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        Interrupt_Generator_0/Interrupt_Source_0/COUNTER1_INTRPT:CLK
  To:                          Interrupt_Generator_0/CoreGPIO_0/CGPIOiOI.0.CGPIOI1[0]:D
  Delay (ns):                  0.397
  Slack (ns):
  Arrival (ns):                0.727
  Required (ns):
  Hold (ns):                   0.000

Path 2
  From:                        Interrupt_Generator_0/CoreGPIO_0/CGPIOiOI.0.CGPIOI1[0]:CLK
  To:                          Interrupt_Generator_0/CoreGPIO_0/CGPIOiOI.0.CGPIOOOL[0]:D
  Delay (ns):                  0.397
  Slack (ns):
  Arrival (ns):                0.731
  Required (ns):
  Hold (ns):                   0.000

Path 3
  From:                        Interrupt_Generator_0/Interrupt_Source_0/SWITCH_INTRPT:CLK
  To:                          Interrupt_Generator_0/CoreGPIO_0/CGPIOiOI.2.CGPIOI1[2]:D
  Delay (ns):                  0.397
  Slack (ns):
  Arrival (ns):                0.708
  Required (ns):
  Hold (ns):                   0.000

Path 4
  From:                        Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp:CLK
  To:                          Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp1:D
  Delay (ns):                  0.397
  Slack (ns):
  Arrival (ns):                0.711
  Required (ns):
  Hold (ns):                   0.000

Path 5
  From:                        Interrupt_Generator_0/Interrupt_Source_0/COUNTER2_INTRPT:CLK
  To:                          Interrupt_Generator_0/CoreGPIO_0/CGPIOiOI.1.CGPIOI1[1]:D
  Delay (ns):                  0.397
  Slack (ns):
  Arrival (ns):                0.720
  Required (ns):
  Hold (ns):                   0.000


Expanded Path 1
  From: Interrupt_Generator_0/Interrupt_Source_0/COUNTER1_INTRPT:CLK
  To: Interrupt_Generator_0/CoreGPIO_0/CGPIOiOI.0.CGPIOI1[0]:D
  data arrival time                              0.727
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: MSS_top_level_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  0.000                        MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.330          net: FAB_CLK
  0.330                        Interrupt_Generator_0/Interrupt_Source_0/COUNTER1_INTRPT:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  0.578                        Interrupt_Generator_0/Interrupt_Source_0/COUNTER1_INTRPT:Q (r)
               +     0.149          net: Interrupt_Generator_0/Interrupt_Source_0_COUNTER1_INTRPT
  0.727                        Interrupt_Generator_0/CoreGPIO_0/CGPIOiOI.0.CGPIOI1[0]:D (r)
                                    
  0.727                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: MSS_top_level_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.351          net: FAB_CLK
  N/C                          Interrupt_Generator_0/CoreGPIO_0/CGPIOiOI.0.CGPIOI1[0]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          Interrupt_Generator_0/CoreGPIO_0/CGPIOiOI.0.CGPIOI1[0]:D


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

Path 1
  From:                        SWITCH_N
  To:                          Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp:CLR
  Delay (ns):                  0.884
  Slack (ns):
  Arrival (ns):                0.884
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       -0.506

Path 2
  From:                        SWITCH_N
  To:                          Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp2:CLR
  Delay (ns):                  0.973
  Slack (ns):
  Arrival (ns):                0.973
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       -0.595

Path 3
  From:                        SWITCH_N
  To:                          Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp1:CLR
  Delay (ns):                  1.026
  Slack (ns):
  Arrival (ns):                1.026
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       -0.648


Expanded Path 1
  From: SWITCH_N
  To: Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp:CLR
  data arrival time                              0.884
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        SWITCH_N (r)
               +     0.000          net: SWITCH_N
  0.000                        SWITCH_N_pad/U0/U0:PAD (r)
               +     0.403          cell: ADLIB:IOPAD_IN
  0.403                        SWITCH_N_pad/U0/U0:Y (r)
               +     0.000          net: SWITCH_N_pad/U0/NET1
  0.403                        SWITCH_N_pad/U0/U1:YIN (r)
               +     0.018          cell: ADLIB:IOIN_IB
  0.421                        SWITCH_N_pad/U0/U1:Y (r)
               +     0.463          net: SWITCH_N_c
  0.884                        Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp:CLR (r)
                                    
  0.884                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     0.000          net: MSS_top_level_0/MSS_CCC_0/I_MSSCCC/GLA_INT
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.378          net: FAB_CLK
  N/C                          Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1C0
  N/C                          Interrupt_Generator_0/Interrupt_Source_0/switch_intrpt_temp:CLR


END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_top_level_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.276
  Slack (ns):
  Arrival (ns):                0.276
  Required (ns):
  Hold (ns):                   1.289
  External Hold (ns):          1.283


Expanded Path 1
  From: MSS_RESET_N
  To: MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.276
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        MSS_top_level_0/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.276          cell: ADLIB:IOPAD_IN
  0.276                        MSS_top_level_0/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: MSS_top_level_0/MSS_RESET_0_MSS_RESET_N_Y
  0.276                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.276                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.270          net: MSS_top_level_0/GLA0
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.289          Library hold time: ADLIB:MSS_APB_IP
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MSS_top_level_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

