----------------------------------------------------------------------
-- Created by Actel SmartDesign Thu Aug 12 18:35:16 2010
-- Testbench Template
-- This is a basic testbench that instantiates your design with basic 
-- clock and reset pins connected.  If your design has special
-- clock/reset or testbench driver requirements then you should 
-- copy this file and modify it. 
----------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench;

architecture behavioral of testbench is

    constant SYSCLK_PERIOD : time := 100 ns;

    signal SYSCLK : std_logic := '0';
    signal NSYSRESET : std_logic := '0';

    component Interrupt_Generator
        -- ports
        port( 
            -- Inputs
            PCLK : in std_logic;
            PRESETn : in std_logic;
            PSEL : in std_logic;
            PENABLE : in std_logic;
            PWRITE : in std_logic;
            PCLK_0 : in std_logic;
            PRESETN_0 : in std_logic;
            SWITCH_N : in std_logic;
            FAB_CLK : in std_logic;
            FAB_LOCK : in std_logic;
            PSEL_0 : in std_logic;
            PENABLE_0 : in std_logic;
            PWRITE_0 : in std_logic;
            PADDR : in std_logic_vector(5 downto 2);
            PWDATA : in std_logic_vector(31 downto 0);
            PADDR_0 : in std_logic_vector(7 downto 0);
            PWDATA_0 : in std_logic_vector(31 downto 0);

            -- Outputs
            IRQ : out std_logic;
            PREADY : out std_logic;
            PSLVERR : out std_logic;
            PRDATA : out std_logic_vector(31 downto 0);
            PRDATA_0 : out std_logic_vector(31 downto 0)

            -- Inouts

        );
    end component;

begin

    process
        variable vhdl_initial : BOOLEAN := TRUE;

    begin
        if ( vhdl_initial ) then
            -- Assert Reset
            NSYSRESET <= '0';
            wait for ( SYSCLK_PERIOD * 10 );
            
            NSYSRESET <= '1';
            wait;
        end if;
    end process;

    -- 10MHz Clock Driver
    SYSCLK <= not SYSCLK after (SYSCLK_PERIOD / 2.0 );

    -- Instantiate Unit Under Test:  Interrupt_Generator
    Interrupt_Generator_0 : Interrupt_Generator
        -- port map
        port map( 
            -- Inputs
            PCLK => SYSCLK,
            PRESETn => NSYSRESET,
            PSEL => '0',
            PENABLE => '0',
            PWRITE => '0',
            PCLK_0 => SYSCLK,
            PRESETN_0 => NSYSRESET,
            SWITCH_N => '0',
            FAB_CLK => SYSCLK,
            FAB_LOCK => '0',
            PSEL_0 => '0',
            PENABLE_0 => '0',
            PWRITE_0 => '0',
            PADDR => (others=> '0'),
            PWDATA => (others=> '0'),
            PADDR_0 => (others=> '0'),
            PWDATA_0 => (others=> '0'),

            -- Outputs
            IRQ =>  open,
            PREADY =>  open,
            PSLVERR =>  open,
            PRDATA => open,
            PRDATA_0 => open

            -- Inouts

        );

end behavioral;

