#Build: Synplify Pro E-2010.09A-1, Build 006R, Oct 6 2010 #install: C:\Actel9.1SPB\Libero_v9.1\Synopsys\synplify_E201009A-1 #OS: Windows XP 5.1 #Hostname: VXP-SUDEEPS #Implementation: synthesis #Mon Feb 07 17:45:09 2011 $ Start of Compile #Mon Feb 07 17:45:09 2011 Synopsys Verilog Compiler, version comp520rcp1, Build 028R, built Sep 23 2010 @N: : | Running in 32-bit mode Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved @I::"C:\Actel9.1SPB\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\smartfusion.v" @I::"C:\Actel9.1SPB\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\vlog\hypermods.v" @I::"C:\Actelprj\App_notes_upadtes\SmartFusion_Using_GPIO_to_Interrupt_MSS_DF\Hardware\A2F500\Verilog\Interrupt_MSS_GPIO\component\Actel\SmartFusionMSS\MSS\2.4.105\mss_comps.v" @I::"C:\Actelprj\App_notes_upadtes\SmartFusion_Using_GPIO_to_Interrupt_MSS_DF\Hardware\A2F500\Verilog\Interrupt_MSS_GPIO\component\work\MSS_top_level\MSS_CCC_0\MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v" @I::"C:\Actelprj\App_notes_upadtes\SmartFusion_Using_GPIO_to_Interrupt_MSS_DF\Hardware\A2F500\Verilog\Interrupt_MSS_GPIO\component\work\MSS_top_level\mss_tshell.v" @I::"C:\Actelprj\App_notes_upadtes\SmartFusion_Using_GPIO_to_Interrupt_MSS_DF\Hardware\A2F500\Verilog\Interrupt_MSS_GPIO\component\work\MSS_top_level\MSS_top_level.v" @I::"C:\Actelprj\App_notes_upadtes\SmartFusion_Using_GPIO_to_Interrupt_MSS_DF\Hardware\A2F500\Verilog\Interrupt_MSS_GPIO\hdl\Interrupt_Generator.v" @I::"C:\Actelprj\App_notes_upadtes\SmartFusion_Using_GPIO_to_Interrupt_MSS_DF\Hardware\A2F500\Verilog\Interrupt_MSS_GPIO\component\work\top_level\top_level.v" Verilog syntax check successful! Options changed - recompiling Selecting top level module top_level @N:CG364 : mss_comps.v(23) | Synthesizing module INBUF_MSS @N:CG364 : smartfusion.v(1814) | Synthesizing module VCC @N:CG364 : mss_comps.v(37) | Synthesizing module OUTBUF_MSS @N:CG364 : mss_comps.v(151) | Synthesizing module MSS_CCC @N:CG364 : mss_comps.v(1) | Synthesizing module MSS_XTLOSC @N:CG364 : smartfusion.v(1133) | Synthesizing module GND @N:CG364 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(5) | Synthesizing module MSS_top_level_tmp_MSS_CCC_0_MSS_CCC @N:CG364 : mss_tshell.v(1) | Synthesizing module MSS_APB @N:CG364 : mss_comps.v(145) | Synthesizing module MSSINT @N:CG364 : MSS_top_level.v(5) | Synthesizing module MSS_top_level @N:CG364 : Interrupt_Generator.v(23) | Synthesizing module Interrupt_Generator @N:CG364 : top_level.v(5) | Synthesizing module top_level @W:CL168 : top_level.v(33) | Pruning instance GND - not in use ... @W:CL168 : top_level.v(28) | Pruning instance VCC - not in use ... @W:CL157 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(62) | *Output RCOSC_CLKOUT has undriven bits - a simulation mismatch is possible @W:CL157 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(63) | *Output MAINXIN_CLKOUT has undriven bits - a simulation mismatch is possible @W:CL157 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(64) | *Output LPXIN_CLKOUT has undriven bits - a simulation mismatch is possible @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(36) | Input CLKA is unused @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(37) | Input CLKA_PAD is unused @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(38) | Input CLKA_PADP is unused @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(39) | Input CLKA_PADN is unused @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(40) | Input CLKB is unused @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(41) | Input CLKB_PAD is unused @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(42) | Input CLKB_PADP is unused @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(43) | Input CLKB_PADN is unused @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(44) | Input CLKC is unused @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(45) | Input CLKC_PAD is unused @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(46) | Input CLKC_PADP is unused @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(47) | Input CLKC_PADN is unused @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(49) | Input LPXIN is unused @W:CL159 : MSS_top_level_tmp_MSS_CCC_0_MSS_CCC.v(50) | Input MAC_CLK is unused @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon Feb 07 17:45:10 2011 ###########################################################] Synopsys Actel Technology Mapper, Version mapact, Build 023R, Built Sep 29 2010 09:29:00 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved Product Version E-2010.09A-1 @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled @W:MO111 : mss_top_level_tmp_mss_ccc_0_mss_ccc.v(62) | tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module MSS_top_level_tmp_MSS_CCC_0_MSS_CCC) @W:MO111 : mss_top_level_tmp_mss_ccc_0_mss_ccc.v(63) | tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module MSS_top_level_tmp_MSS_CCC_0_MSS_CCC) @W:MO111 : mss_top_level_tmp_mss_ccc_0_mss_ccc.v(64) | tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module MSS_top_level_tmp_MSS_CCC_0_MSS_CCC) Available hyper_sources - for debug and ip models None Found @W: : mss_top_level_tmp_mss_ccc_0_mss_ccc.v(79) | Net MSS_top_level_0.MSS_ADLIB_INST_FCLK appears to be a clock source which was not identfied. Assuming default frequency. @W: : mss_top_level_tmp_mss_ccc_0_mss_ccc.v(79) | Net Interrupt_Generator_0/FAB_CLK appears to be a clock source which was not identfied. Assuming default frequency. Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 56MB) @N:MF238 : interrupt_generator.v(49) | Found 32 bit incrementor, 'un3_counter1_1[31:0]' @N:MF238 : interrupt_generator.v(73) | Found 32 bit incrementor, 'un2_counter2_1[31:0]' Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 56MB) Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 56MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 56MB) High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes ---------------------------------------------------------------------------- MSS_top_level_0.MSS_CCC_0.I_MSSCCC / LOCK 66 : 66 asynchronous set/reset ============================================================================ Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 56MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 56MB) Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 56MB) Writing Analyst data base C:\Actelprj\App_notes_upadtes\SmartFusion_Using_GPIO_to_Interrupt_MSS_DF\Hardware\A2F500\Verilog\Interrupt_MSS_GPIO\synthesis\top_level.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 56MB) Writing EDIF Netlist and constraint files E-2010.09A-1 Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) @W:MT246 : mss_top_level.v(161) | Blackbox MSSINT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : mss_top_level_tmp_mss_ccc_0_mss_ccc.v(97) | Blackbox MSS_XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock MSS_top_level|MSS_ADLIB_INST_EMCCLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:MSS_top_level_0.MSS_ADLIB_INST_EMCCLK" @W:MT420 : | Found inferred clock MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:MSS_top_level_0_FAB_CLK" @W:MT420 : | Found inferred clock MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:MSS_top_level_0.MSS_ADLIB_INST_FCLK" ##### START OF TIMING REPORT #####[ # Timing Report written on Mon Feb 07 17:45:12 2011 # Top view: top_level Library name: smartfusion Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree ) Requested Frequency: 100.0 MHz Wire load mode: top Wire load model: smartfusion Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: 0.090 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_1 MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock 100.0 MHz 100.9 MHz 10.000 9.910 0.090 inferred Inferred_clkgroup_2 System 100.0 MHz 1194.2 MHz 10.000 0.837 9.163 system system_clkgroup ================================================================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock | 10.000 9.163 | No paths - | No paths - | No paths - MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock System | 10.000 8.942 | No paths - | No paths - | No paths - MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock | 10.000 0.090 | No paths - | No paths - | No paths - ============================================================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Interrupt_Generator_0.counter1[3] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter1[3] 0.737 0.090 Interrupt_Generator_0.counter2[3] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter2[3] 0.737 0.090 Interrupt_Generator_0.counter1[4] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter1[4] 0.737 0.092 Interrupt_Generator_0.counter2[4] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter2[4] 0.737 0.092 Interrupt_Generator_0.counter1[5] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter1[5] 0.737 0.153 Interrupt_Generator_0.counter2[5] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter2[5] 0.737 0.153 Interrupt_Generator_0.counter1[1] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter1[1] 0.737 0.403 Interrupt_Generator_0.counter1[2] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter1[2] 0.737 0.512 Interrupt_Generator_0.counter1[0] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter1[0] 0.737 0.546 Interrupt_Generator_0.counter2[1] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 Q counter2[1] 0.737 0.567 ========================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ Interrupt_Generator_0.counter1[28] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D I_203_0 9.461 0.090 Interrupt_Generator_0.counter1[29] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D I_210_0 9.461 0.090 Interrupt_Generator_0.counter1[30] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D I_217_0 9.461 0.090 Interrupt_Generator_0.counter1[31] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D I_224_0 9.461 0.090 Interrupt_Generator_0.counter2[28] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D I_203 9.461 0.090 Interrupt_Generator_0.counter2[29] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D I_210 9.461 0.090 Interrupt_Generator_0.counter2[30] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D I_217 9.461 0.090 Interrupt_Generator_0.counter2[31] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D I_224 9.461 0.090 Interrupt_Generator_0.counter1[12] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D counter1_3[12] 9.427 0.403 Interrupt_Generator_0.counter1[11] MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock DFN1C0 D counter1_3[11] 9.427 0.567 ============================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 9.371 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 0.090 Number of logic level(s): 5 Starting point: Interrupt_Generator_0.counter1[3] / Q Ending point: Interrupt_Generator_0.counter1[28] / D The start point is clocked by MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_top_level_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------- Interrupt_Generator_0.counter1[3] DFN1C0 Q Out 0.737 0.737 - counter1[3] Net - - 1.423 - 6 Interrupt_Generator_0.un3_counter1_1.I_34 AND3 A In - 2.160 - Interrupt_Generator_0.un3_counter1_1.I_34 AND3 Y Out 0.464 2.624 - DWACT_FINC_E_0[2] Net - - 1.423 - 6 Interrupt_Generator_0.un3_counter1_1.I_152 AND3 B In - 4.048 - Interrupt_Generator_0.un3_counter1_1.I_152 AND3 Y Out 0.607 4.654 - DWACT_FINC_E_0[29] Net - - 1.423 - 6 Interrupt_Generator_0.un3_counter1_1.I_199 AND2 A In - 6.078 - Interrupt_Generator_0.un3_counter1_1.I_199 AND2 Y Out 0.514 6.592 - DWACT_FINC_E_0[24] Net - - 1.184 - 4 Interrupt_Generator_0.un3_counter1_1.I_202 AND3 A In - 7.776 - Interrupt_Generator_0.un3_counter1_1.I_202 AND3 Y Out 0.464 8.240 - N_19_0 Net - - 0.322 - 1 Interrupt_Generator_0.un3_counter1_1.I_203 XOR2 A In - 8.561 - Interrupt_Generator_0.un3_counter1_1.I_203 XOR2 Y Out 0.488 9.049 - I_203_0 Net - - 0.322 - 1 Interrupt_Generator_0.counter1[28] DFN1C0 D In - 9.371 - =========================================================================================================== Total path delay (propagation time + setup) of 9.910 is 3.813(38.5%) logic and 6.097(61.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------ MSS_top_level_0.MSSINT_GPI_0 System MSSINT Y MSSINT_GPI_0_Y 0.000 9.163 MSS_top_level_0.MSSINT_GPI_1 System MSSINT Y MSSINT_GPI_1_Y 0.000 9.163 ====================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------- MSS_top_level_0.MSS_ADLIB_INST System MSS_APB GPI[0] MSSINT_GPI_0_Y 9.484 9.163 MSS_top_level_0.MSS_ADLIB_INST System MSS_APB GPI[1] MSSINT_GPI_1_Y 9.484 9.163 ============================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.516 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.484 - Propagation time: 0.322 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 9.163 Number of logic level(s): 0 Starting point: MSS_top_level_0.MSSINT_GPI_0 / Y Ending point: MSS_top_level_0.MSS_ADLIB_INST / GPI[0] The start point is clocked by System [rising] The end point is clocked by MSS_top_level_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------- MSS_top_level_0.MSSINT_GPI_0 MSSINT Y Out 0.000 0.000 - MSSINT_GPI_0_Y Net - - 0.322 - 1 MSS_top_level_0.MSS_ADLIB_INST MSS_APB GPI[0] In - 0.322 - ================================================================================================== Total path delay (propagation time + setup) of 0.837 is 0.516(61.6%) logic and 0.322(38.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Target Part: A2F500M3G_FBGA256_Std Report for cell top_level.verilog Core Cell usage: cell count area count*area AND2 24 1.0 24.0 AND3 94 1.0 94.0 GND 4 0.0 0.0 MSSINT 2 0.0 0.0 MSS_CCC 1 0.0 0.0 NOR2 14 1.0 14.0 NOR2A 25 1.0 25.0 NOR2B 13 1.0 13.0 NOR3 1 1.0 1.0 NOR3A 5 1.0 5.0 NOR3C 14 1.0 14.0 VCC 4 0.0 0.0 XOR2 62 1.0 62.0 DFN1C0 66 1.0 66.0 MSS_APB 1 0.0 0.0 ----- ---------- TOTAL 330 318.0 IO Cell usage: cell count INBUF 1 INBUF_MSS 2 MSS_XTLOSC 1 OUTBUF_MSS 1 ----- TOTAL 5 Core Cells : 318 of 11520 (3%) IO Cells : 5 RAM/ROM Usage Summary Block Rams : 0 of 24 (0%) Mapper successful! Process took 0h:00m:02s realtime, 0h:00m:01s cputime # Mon Feb 07 17:45:12 2011 ###########################################################]