@W: MT246 :"c:\a2f_ac338_df\a2f500\vhdl\component\work\mss_top_level\mss_top_level.vhd":623:4:623:15|Blackbox MSSINT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"c:\a2f_ac338_df\a2f500\vhdl\component\work\mss_top_level\mss_ccc_0\mss_top_level_tmp_mss_ccc_0_mss_ccc.vhd":156:4:156:11|Blackbox MSS_XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock MSS_top_level|MSS_ADLIB_INST_EMCCLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:MSS_top_level_0.MSS_ADLIB_INST_EMCCLK"
