Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Thu Dec 08 13:48:23 2011


Design: top_level
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        1.090
External Hold (ns):         -0.239
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.383
External Hold (ns):         1.283
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_glb
Period (ns):                7.481
Frequency (MHz):            133.672
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               MSS_top_level_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        F2M_GPI_1
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GPI[1]
  Delay (ns):                  2.073
  Slack (ns):
  Arrival (ns):                2.073
  Required (ns):
  Setup (ns):                  -0.983
  External Setup (ns):         1.090


Expanded Path 1
  From: F2M_GPI_1
  To: MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GPI[1]
  data required time                             N/C
  data arrival time                          -   2.073
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        F2M_GPI_1 (r)
               +     0.000          net: F2M_GPI_1
  0.000                        F2M_GPI_1_pad/U0/U0:PAD (r)
               +     0.806          cell: ADLIB:IOPAD_IN
  0.806                        F2M_GPI_1_pad/U0/U0:Y (r)
               +     0.000          net: F2M_GPI_1_pad/U0/NET1
  0.806                        F2M_GPI_1_pad/U0/U1:YIN (r)
               +     0.033          cell: ADLIB:IOIN_IB
  0.839                        F2M_GPI_1_pad/U0/U1:Y (r)
               +     1.054          net: F2M_GPI_1_c
  1.893                        MSS_top_level_0/MSS_ADLIB_INST/U_21:PIN5 (r)
               +     0.180          cell: ADLIB:MSS_IF
  2.073                        MSS_top_level_0/MSS_ADLIB_INST/U_21:PIN5INT (r)
               +     0.000          net: MSS_top_level_0/MSS_ADLIB_INST/GPI[1]INT_NET
  2.073                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GPI[1] (r)
                                    
  2.073                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_pclk1
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               -    -0.983          Library setup time: ADLIB:MSS_APB_IP
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GPI[1]


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_top_level_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.781
  Slack (ns):
  Arrival (ns):                0.781
  Required (ns):
  Setup (ns):                  -1.782
  External Setup (ns):         -1.383


Expanded Path 1
  From: MSS_RESET_N
  To: MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.781
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        MSS_top_level_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.781          cell: ADLIB:IOPAD_IN
  0.781                        MSS_top_level_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: MSS_top_level_0/MSS_RESET_0_MSS_RESET_N_Y
  0.781                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.781                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.382          net: MSS_top_level_0/GLA0
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -1.782          Library setup time: ADLIB:MSS_APB_IP
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glb

SET Register to Register

Path 1
  From:                        Interrupt_Generation_0/counter2[7]:CLK
  To:                          Interrupt_Generation_0/counter2[18]:D
  Delay (ns):                  7.049
  Slack (ns):
  Arrival (ns):                7.598
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.481

Path 2
  From:                        Interrupt_Generation_0/counter2[7]:CLK
  To:                          Interrupt_Generation_0/counter2[30]:D
  Delay (ns):                  6.840
  Slack (ns):
  Arrival (ns):                7.389
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.262

Path 3
  From:                        Interrupt_Generation_0/counter2[3]:CLK
  To:                          Interrupt_Generation_0/counter2[18]:D
  Delay (ns):                  6.725
  Slack (ns):
  Arrival (ns):                7.287
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.170

Path 4
  From:                        Interrupt_Generation_0/counter2[7]:CLK
  To:                          Interrupt_Generation_0/counter2[20]:D
  Delay (ns):                  6.737
  Slack (ns):
  Arrival (ns):                7.286
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.161

Path 5
  From:                        Interrupt_Generation_0/counter1[1]:CLK
  To:                          Interrupt_Generation_0/counter1[6]:D
  Delay (ns):                  6.618
  Slack (ns):
  Arrival (ns):                7.193
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.058


Expanded Path 1
  From: Interrupt_Generation_0/counter2[7]:CLK
  To: Interrupt_Generation_0/counter2[18]:D
  data required time                             N/C
  data arrival time                          -   7.598
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_top_level_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.549          net: FAB_CLK
  0.549                        Interrupt_Generation_0/counter2[7]:CLK (r)
               +     0.440          cell: ADLIB:DFN1C0
  0.989                        Interrupt_Generation_0/counter2[7]:Q (r)
               +     1.459          net: Interrupt_Generation_0/counter2[7]
  2.448                        Interrupt_Generation_0/un3_counter2_1_I_29:B (r)
               +     0.473          cell: ADLIB:AND3
  2.921                        Interrupt_Generation_0/un3_counter2_1_I_29:Y (r)
               +     1.210          net: Interrupt_Generation_0/DWACT_FINC_E[5]
  4.131                        Interrupt_Generation_0/un3_counter2_1_I_51:C (r)
               +     0.505          cell: ADLIB:AND3
  4.636                        Interrupt_Generation_0/un3_counter2_1_I_51:Y (r)
               +     1.464          net: Interrupt_Generation_0/DWACT_FINC_E[28]
  6.100                        Interrupt_Generation_0/un3_counter2_1_I_52:A (r)
               +     0.398          cell: ADLIB:AND3
  6.498                        Interrupt_Generation_0/un3_counter2_1_I_52:Y (r)
               +     0.255          net: Interrupt_Generation_0/N_15
  6.753                        Interrupt_Generation_0/counter2_RNO[18]:A (r)
               +     0.600          cell: ADLIB:XA1B
  7.353                        Interrupt_Generation_0/counter2_RNO[18]:Y (f)
               +     0.245          net: Interrupt_Generation_0/counter2_2[18]
  7.598                        Interrupt_Generation_0/counter2[18]:D (f)
                                    
  7.598                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_top_level_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.552          net: FAB_CLK
  N/C                          Interrupt_Generation_0/counter2[18]:CLK (r)
               -     0.435          Library setup time: ADLIB:DFN1C0
  N/C                          Interrupt_Generation_0/counter2[18]:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MSS_top_level_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

