library verilog;
use verilog.vl_types.all;
entity Interrupt_Generator is
    port(
        FAB_CLK         : in     vl_logic;
        RESET_N         : in     vl_logic;
        FABINT          : out    vl_logic;
        GPI_0           : out    vl_logic
    );
end Interrupt_Generator;
