library verilog;
use verilog.vl_types.all;
entity MSS_top_level_tmp_MSS_CCC_0_MSS_CCC is
    port(
        MSS_top_level_tmp_MSS_CCC_0_MSS_CCC_VCC: in     vl_logic;
        MSS_top_level_tmp_MSS_CCC_0_MSS_CCC_GND: in     vl_logic;
        MSS_ADLIB_INST_PLLLOCK: out    vl_logic;
        MSS_top_level_0_FAB_CLK_i: out    vl_logic;
        MSS_ADLIB_INST_FCLK: out    vl_logic;
        MAINXIN         : in     vl_logic;
        MSS_top_level_0_FAB_LOCK_0: out    vl_logic;
        MSS_top_level_0_FAB_LOCK: out    vl_logic;
        MSS_top_level_0_FAB_LOCK_1: out    vl_logic
    );
end MSS_top_level_tmp_MSS_CCC_0_MSS_CCC;
