library verilog;
use verilog.vl_types.all;
entity MSS_top_level is
    port(
        FAB_CLK         : out    vl_logic;
        MAINXIN         : in     vl_logic;
        FAB_LOCK        : out    vl_logic;
        F2M_GPI_1       : in     vl_logic;
        F2M_GPI_0       : in     vl_logic;
        FABINT          : in     vl_logic;
        UART_0_TXD      : out    vl_logic;
        UART_0_RXD      : in     vl_logic;
        MSS_RESET_N     : in     vl_logic
    );
end MSS_top_level;
