-- Version: 10.0 10.0.9.37

library ieee;
use ieee.std_logic_1164.all;
library smartfusion;
use smartfusion.all;

entity top_level is

    port( UART_0_TXD  : out   std_logic;
          UART_0_RXD  : in    std_logic;
          MSS_RESET_N : in    std_logic;
          MAINXIN     : in    std_logic;
          F2M_GPI_1   : in    std_logic
        );

end top_level;

architecture DEF_ARCH of top_level is 

  component MSS_top_level
    port( UART_0_TXD  : out   std_logic;
          UART_0_RXD  : in    std_logic := 'U';
          MSS_RESET_N : in    std_logic := 'U';
          FAB_CLK     : out   std_logic;
          MAINXIN     : in    std_logic := 'U';
          FAB_LOCK    : out   std_logic;
          F2M_GPI_1   : in    std_logic := 'U';
          F2M_GPI_0   : in    std_logic := 'U';
          FABINT      : in    std_logic := 'U'
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

    signal Interrupt_Generation_0_FABINT, 
        Interrupt_Generation_0_GPI_0, MSS_top_level_0_FAB_CLK, 
        MSS_top_level_0_FAB_LOCK, GND_net, VCC_net : std_logic;

begin 


    MSS_top_level_0 : MSS_top_level
      port map(UART_0_TXD => UART_0_TXD, UART_0_RXD => UART_0_RXD, 
        MSS_RESET_N => MSS_RESET_N, FAB_CLK => 
        MSS_top_level_0_FAB_CLK, MAINXIN => MAINXIN, FAB_LOCK => 
        MSS_top_level_0_FAB_LOCK, F2M_GPI_1 => F2M_GPI_1, 
        F2M_GPI_0 => Interrupt_Generation_0_GPI_0, FABINT => 
        Interrupt_Generation_0_FABINT);
    
    \VCC\ : VCC
      port map(Y => VCC_net);
    
    Interrupt_Generation_0 : entity work.Interrupt_Generation
      port map(RESET_N => MSS_top_level_0_FAB_LOCK, FAB_CLK => 
        MSS_top_level_0_FAB_CLK, FABINT => 
        Interrupt_Generation_0_FABINT, GPI_0 => 
        Interrupt_Generation_0_GPI_0);
    
    \GND\ : GND
      port map(Y => GND_net);
    

end DEF_ARCH; 
