library verilog;
use verilog.vl_types.all;
entity Interrupt_Generator is
    port(
        MSS_top_level_0_FAB_LOCK: in     vl_logic;
        MSS_top_level_0_FAB_CLK: in     vl_logic;
        MSS_top_level_0_FAB_LOCK_1: in     vl_logic;
        MSS_top_level_0_FAB_CLK_1: in     vl_logic;
        Interrupt_Generator_0_GPI_0: out    vl_logic;
        MSS_top_level_0_FAB_LOCK_0: in     vl_logic;
        MSS_top_level_0_FAB_CLK_0: in     vl_logic;
        Interrupt_Generator_0_FABINT: out    vl_logic
    );
end Interrupt_Generator;
