Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Wed Dec 07 18:02:21 2011


Design: top_level
Family: SmartFusion
Die: A2F200M3F
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        1.971
External Hold (ns):         -0.047
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.574
External Hold (ns):         1.448
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_glb
Period (ns):                7.264
Frequency (MHz):            137.665
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               MSS_top_level_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        F2M_GPI_1
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GPI[1]
  Delay (ns):                  2.028
  Slack (ns):
  Arrival (ns):                2.028
  Required (ns):
  Setup (ns):                  -0.057
  External Setup (ns):         1.971


Expanded Path 1
  From: F2M_GPI_1
  To: MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GPI[1]
  data required time                             N/C
  data arrival time                          -   2.028
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        F2M_GPI_1 (r)
               +     0.000          net: F2M_GPI_1
  0.000                        F2M_GPI_1_pad/U0/U0:PAD (r)
               +     0.806          cell: ADLIB:IOPAD_IN
  0.806                        F2M_GPI_1_pad/U0/U0:Y (r)
               +     0.000          net: F2M_GPI_1_pad/U0/NET1
  0.806                        F2M_GPI_1_pad/U0/U1:YIN (r)
               +     0.033          cell: ADLIB:IOIN_IB
  0.839                        F2M_GPI_1_pad/U0/U1:Y (r)
               +     1.009          net: F2M_GPI_1_c
  1.848                        MSS_top_level_0/MSS_ADLIB_INST/U_21:PIN5 (r)
               +     0.180          cell: ADLIB:MSS_IF
  2.028                        MSS_top_level_0/MSS_ADLIB_INST/U_21:PIN5INT (r)
               +     0.000          net: MSS_top_level_0/MSS_ADLIB_INST/GPI[1]INT_NET
  2.028                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GPI[1] (r)
                                    
  2.028                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_pclk1
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               -    -0.057          Library setup time: ADLIB:MSS_APB_IP
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GPI[1]


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_top_level_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.781
  Slack (ns):
  Arrival (ns):                0.781
  Required (ns):
  Setup (ns):                  -1.830
  External Setup (ns):         -1.574


Expanded Path 1
  From: MSS_RESET_N
  To: MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.781
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        MSS_top_level_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.781          cell: ADLIB:IOPAD_IN
  0.781                        MSS_top_level_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: MSS_top_level_0/MSS_RESET_0_MSS_RESET_N_Y
  0.781                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.781                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.525          net: MSS_top_level_0/GLA0
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -1.830          Library setup time: ADLIB:MSS_APB_IP
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glb

SET Register to Register

Path 1
  From:                        Interrupt_Generation_0/counter1[12]:CLK
  To:                          Interrupt_Generation_0/counter1[19]:D
  Delay (ns):                  6.824
  Slack (ns):
  Arrival (ns):                7.362
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         7.264

Path 2
  From:                        Interrupt_Generation_0/counter2[3]:CLK
  To:                          Interrupt_Generation_0/counter2[21]:D
  Delay (ns):                  6.796
  Slack (ns):
  Arrival (ns):                7.324
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.231

Path 3
  From:                        Interrupt_Generation_0/counter2[3]:CLK
  To:                          Interrupt_Generation_0/counter2[4]:D
  Delay (ns):                  6.801
  Slack (ns):
  Arrival (ns):                7.329
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         7.218

Path 4
  From:                        Interrupt_Generation_0/counter1[3]:CLK
  To:                          Interrupt_Generation_0/counter1[19]:D
  Delay (ns):                  6.742
  Slack (ns):
  Arrival (ns):                7.252
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.180

Path 5
  From:                        Interrupt_Generation_0/counter1[7]:CLK
  To:                          Interrupt_Generation_0/counter1[31]:D
  Delay (ns):                  6.728
  Slack (ns):
  Arrival (ns):                7.238
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         7.166


Expanded Path 1
  From: Interrupt_Generation_0/counter1[12]:CLK
  To: Interrupt_Generation_0/counter1[19]:D
  data required time                             N/C
  data arrival time                          -   7.362
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_top_level_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.538          net: FAB_CLK
  0.538                        Interrupt_Generation_0/counter1[12]:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  1.097                        Interrupt_Generation_0/counter1[12]:Q (f)
               +     0.353          net: Interrupt_Generation_0/counter1[12]
  1.450                        Interrupt_Generation_0/counter1_RNIEV8F[12]:B (f)
               +     0.476          cell: ADLIB:NOR2B
  1.926                        Interrupt_Generation_0/counter1_RNIEV8F[12]:Y (f)
               +     0.255          net: Interrupt_Generation_0/un2_counter1_10
  2.181                        Interrupt_Generation_0/counter1_RNIC8PD1[4]:C (f)
               +     0.517          cell: ADLIB:NOR3C
  2.698                        Interrupt_Generation_0/counter1_RNIC8PD1[4]:Y (f)
               +     0.861          net: Interrupt_Generation_0/un2_counter1_20
  3.559                        Interrupt_Generation_0/counter1_RNIE0RD1[16]:C (f)
               +     0.486          cell: ADLIB:NOR3C
  4.045                        Interrupt_Generation_0/counter1_RNIE0RD1[16]:Y (f)
               +     0.792          net: Interrupt_Generation_0/un2_counter1_25
  4.837                        Interrupt_Generation_0/counter1_RNIIHI94[10]:B (f)
               +     0.460          cell: ADLIB:NOR3C
  5.297                        Interrupt_Generation_0/counter1_RNIIHI94[10]:Y (f)
               +     1.438          net: Interrupt_Generation_0/counter1_RNIIHI94[10]
  6.735                        Interrupt_Generation_0/counter1_RNO[19]:C (f)
               +     0.372          cell: ADLIB:XA1B
  7.107                        Interrupt_Generation_0/counter1_RNO[19]:Y (r)
               +     0.255          net: Interrupt_Generation_0/counter1_3[19]
  7.362                        Interrupt_Generation_0/counter1[19]:D (r)
                                    
  7.362                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_top_level_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.507          net: FAB_CLK
  N/C                          Interrupt_Generation_0/counter1[19]:CLK (r)
               -     0.409          Library setup time: ADLIB:DFN1C0
  N/C                          Interrupt_Generation_0/counter1[19]:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MSS_top_level_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

