@W: MO111 :"c:\a2f_ac338_df\a2f200\verilog\component\work\mss_top_level\mss_ccc_0\mss_top_level_tmp_mss_ccc_0_mss_ccc.v":64:7:64:18|Tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module MSS_top_level_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"c:\a2f_ac338_df\a2f200\verilog\component\work\mss_top_level\mss_ccc_0\mss_top_level_tmp_mss_ccc_0_mss_ccc.v":63:7:63:20|Tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module MSS_top_level_tmp_MSS_CCC_0_MSS_CCC) 
@W: MO111 :"c:\a2f_ac338_df\a2f200\verilog\component\work\mss_top_level\mss_ccc_0\mss_top_level_tmp_mss_ccc_0_mss_ccc.v":62:7:62:18|Tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module MSS_top_level_tmp_MSS_CCC_0_MSS_CCC) 
@W: MT246 :"c:\a2f_ac338_df\a2f200\verilog\component\work\mss_top_level\mss_top_level.v":161:11:161:22|Blackbox MSSINT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"c:\a2f_ac338_df\a2f200\verilog\component\work\mss_top_level\mss_ccc_0\mss_top_level_tmp_mss_ccc_0_mss_ccc.v":97:15:97:22|Blackbox MSS_XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock MSS_top_level|MSS_ADLIB_INST_EMCCLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:MSS_top_level_0.MSS_ADLIB_INST_EMCCLK"
