`timescale 1 ns/100 ps
// Version: 10.0 10.0.9.37


module top_level(
       UART_0_TXD,
       UART_0_RXD,
       MSS_RESET_N,
       MAINXIN,
       F2M_GPI_1
    );
output UART_0_TXD;
input  UART_0_RXD;
input  MSS_RESET_N;
input  MAINXIN;
input  F2M_GPI_1;

    wire Interrupt_Generator_0_FABINT, Interrupt_Generator_0_GPI_0, 
        MSS_top_level_0_FAB_CLK, MSS_top_level_0_FAB_LOCK, GND_net, 
        VCC_net;
    
    MSS_top_level MSS_top_level_0 (.UART_0_TXD(UART_0_TXD), 
        .UART_0_RXD(UART_0_RXD), .MSS_RESET_N(MSS_RESET_N), .FAB_CLK(
        MSS_top_level_0_FAB_CLK), .MAINXIN(MAINXIN), .FAB_LOCK(
        MSS_top_level_0_FAB_LOCK), .F2M_GPI_1(F2M_GPI_1), .F2M_GPI_0(
        Interrupt_Generator_0_GPI_0), .FABINT(
        Interrupt_Generator_0_FABINT));
    VCC VCC (.Y(VCC_net));
    Interrupt_Generator Interrupt_Generator_0 (.FAB_CLK(
        MSS_top_level_0_FAB_CLK), .RESET_N(MSS_top_level_0_FAB_LOCK), 
        .FABINT(Interrupt_Generator_0_FABINT), .GPI_0(
        Interrupt_Generator_0_GPI_0));
    GND GND (.Y(GND_net));
    
endmodule
