library verilog;
use verilog.vl_types.all;
entity MSS_top_level is
    port(
        MSS_top_level_0_FAB_LOCK_1: out    vl_logic;
        MSS_top_level_0_FAB_LOCK: out    vl_logic;
        MSS_top_level_0_FAB_LOCK_0: out    vl_logic;
        MAINXIN         : in     vl_logic;
        MSS_top_level_0_FAB_CLK_i: out    vl_logic;
        MSS_RESET_N     : in     vl_logic;
        UART_0_TXD      : out    vl_logic;
        Interrupt_Generator_0_FABINT: in     vl_logic;
        MSS_top_level_VCC: in     vl_logic;
        MSS_top_level_GND: in     vl_logic;
        Interrupt_Generator_0_GPI_0: in     vl_logic;
        F2M_GPI_1_c     : in     vl_logic;
        UART_0_RXD      : in     vl_logic
    );
end MSS_top_level;
