`timescale  1 ns /  100 ps
/*-------------------------------------------------------------------------------
-- Title      : Interrupts Generation
-------------------------------------------------------------------------------
-- File       : Interrupt_Generator.v
-- Author     : Pavan Marisetti
--              pavan.marisetti@microsemi.com
-- Company    : Microsemi Corporation
-- Device     : SmartFusion 
-- Standard   : Verilog
-------------------------------------------------------------------------------
-- Description: This code creates two timers Timer1 and Timer2. Timer 1 generates
--              interrupt for every 950000 clock cycles of FAB_CLK, which is  
--              mapped to the MSS FAB_INT.Timer 2 generates interrupt for every 
--              2950000 clock cycles, which is mapped to the MSS GPIO_0
-------------------------------------------------------------------------------
-- Copyright (c) 2011   Microsemi Corporation
--                      All rights reserved.
-------------------------------------------------------------------------------
-- Revisions  : V1.0 
-------------------------------------------------------------------------------*/

module Interrupt_Generator (FAB_CLK,RESET_N,FABINT,GPI_0);

input          FAB_CLK, RESET_N;
output reg     FABINT, GPI_0;

reg  [31:0]   counter1;
reg  [31:0]   counter2;

/* Timer  implemetation and generation of Fabric intrrupt upon the expiry of 
   timer value. The timer value is 950000 clock cycles of FAB_CLK */

always@(posedge FAB_CLK or negedge RESET_N)
if(~RESET_N)
  begin
    counter1 <= 32'h00000000;
    FABINT   <= 1'b0; 
  end
else
  begin
    if(counter1 == 32'h000E7EF0)
      begin
        counter1 <= 32'h00000000;
        FABINT   <= 1'b1;
      end
    else
      begin
        counter1 <= counter1 + 1;
        FABINT   <= 1'b0;
      end
  end


/* Timer  implemetation and generation of Fabric intrrupt upon the expiry of 
   timer value. The timer value is 2950000 clock cycles of FAB_CLK */

always@(posedge FAB_CLK or negedge RESET_N)
if(~RESET_N)
  begin
    counter2 <= 32'h00000000;
    GPI_0   <= 1'b0; 
  end
else
  begin
    if(counter2 == 32'h002D0370)
      begin
        counter2 <= 32'h00000000;
        GPI_0   <= 1'b1;
      end
    else
      begin
        counter2 <= counter2 + 1;
        GPI_0   <= 1'b0;
      end
  end
endmodule
/* End of the module */