# (OPEN DESIGN)

open_design "C:/A2F_AC338_DF/A2F500/Verilog/designer/impl1/top_level.adb"
export -format "FDB" {C:/A2F_AC338_DF/A2F500/Verilog/designer/impl1/top_level.fdb}

save_design "C:/A2F_AC338_DF/A2F500/Verilog/designer/impl1/top_level.adb"

