Timing Report Min Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Thu Dec 08 13:47:59 2011


Design: top_level
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        1.090
External Hold (ns):         -0.239
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.383
External Hold (ns):         1.283
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_glb
Period (ns):                7.309
Frequency (MHz):            136.818
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               MSS_top_level_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        F2M_GPI_1
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GPI[1]
  Delay (ns):                  1.049
  Slack (ns):
  Arrival (ns):                1.049
  Required (ns):
  Hold (ns):                   0.810
  External Hold (ns):          -0.239


Expanded Path 1
  From: F2M_GPI_1
  To: MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GPI[1]
  data arrival time                              1.049
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        F2M_GPI_1 (f)
               +     0.000          net: F2M_GPI_1
  0.000                        F2M_GPI_1_pad/U0/U0:PAD (f)
               +     0.292          cell: ADLIB:IOPAD_IN
  0.292                        F2M_GPI_1_pad/U0/U0:Y (f)
               +     0.000          net: F2M_GPI_1_pad/U0/NET1
  0.292                        F2M_GPI_1_pad/U0/U1:YIN (f)
               +     0.018          cell: ADLIB:IOIN_IB
  0.310                        F2M_GPI_1_pad/U0/U1:Y (f)
               +     0.649          net: F2M_GPI_1_c
  0.959                        MSS_top_level_0/MSS_ADLIB_INST/U_21:PIN5 (f)
               +     0.090          cell: ADLIB:MSS_IF
  1.049                        MSS_top_level_0/MSS_ADLIB_INST/U_21:PIN5INT (f)
               +     0.000          net: MSS_top_level_0/MSS_ADLIB_INST/GPI[1]INT_NET
  1.049                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GPI[1] (f)
                                    
  1.049                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_pclk1
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     0.810          Library hold time: ADLIB:MSS_APB_IP
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GPI[1]


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_top_level_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.276
  Slack (ns):
  Arrival (ns):                0.276
  Required (ns):
  Hold (ns):                   1.289
  External Hold (ns):          1.283


Expanded Path 1
  From: MSS_RESET_N
  To: MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.276
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        MSS_top_level_0/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.276          cell: ADLIB:IOPAD_IN
  0.276                        MSS_top_level_0/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: MSS_top_level_0/MSS_RESET_0_MSS_RESET_N_Y
  0.276                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.276                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.270          net: MSS_top_level_0/GLA0
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.289          Library hold time: ADLIB:MSS_APB_IP
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glb

SET Register to Register

Path 1
  From:                        Interrupt_Generator_0/counter2[2]:CLK
  To:                          Interrupt_Generator_0/counter2[2]:D
  Delay (ns):                  0.750
  Slack (ns):
  Arrival (ns):                1.083
  Required (ns):
  Hold (ns):                   0.000

Path 2
  From:                        Interrupt_Generator_0/counter1[18]:CLK
  To:                          Interrupt_Generator_0/counter1[18]:D
  Delay (ns):                  0.767
  Slack (ns):
  Arrival (ns):                1.104
  Required (ns):
  Hold (ns):                   0.000

Path 3
  From:                        Interrupt_Generator_0/counter1[10]:CLK
  To:                          Interrupt_Generator_0/counter1[10]:D
  Delay (ns):                  0.767
  Slack (ns):
  Arrival (ns):                1.104
  Required (ns):
  Hold (ns):                   0.000

Path 4
  From:                        Interrupt_Generator_0/counter1[17]:CLK
  To:                          Interrupt_Generator_0/counter1[17]:D
  Delay (ns):                  0.779
  Slack (ns):
  Arrival (ns):                1.113
  Required (ns):
  Hold (ns):                   0.000

Path 5
  From:                        Interrupt_Generator_0/counter1[2]:CLK
  To:                          Interrupt_Generator_0/counter1[2]:D
  Delay (ns):                  0.780
  Slack (ns):
  Arrival (ns):                1.112
  Required (ns):
  Hold (ns):                   0.000


Expanded Path 1
  From: Interrupt_Generator_0/counter2[2]:CLK
  To: Interrupt_Generator_0/counter2[2]:D
  data arrival time                              1.083
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_top_level_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.333          net: FAB_CLK
  0.333                        Interrupt_Generator_0/counter2[2]:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  0.581                        Interrupt_Generator_0/counter2[2]:Q (r)
               +     0.206          net: Interrupt_Generator_0/counter2[2]
  0.787                        Interrupt_Generator_0/un2_counter2_1_I_7:C (r)
               +     0.147          cell: ADLIB:AX1C
  0.934                        Interrupt_Generator_0/un2_counter2_1_I_7:Y (r)
               +     0.149          net: Interrupt_Generator_0/I_7
  1.083                        Interrupt_Generator_0/counter2[2]:D (r)
                                    
  1.083                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_top_level_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.350          net: FAB_CLK
  N/C                          Interrupt_Generator_0/counter2[2]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          Interrupt_Generator_0/counter2[2]:D


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MSS_top_level_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

