Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Wed Dec 07 16:06:04 2011


Design: top_level
Family: SmartFusion
Die: A2F200M3F
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        1.779
External Hold (ns):         0.052
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.574
External Hold (ns):         1.448
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_glb
Period (ns):                7.136
Frequency (MHz):            140.135
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               MSS_top_level_0/MSS_CCC_0/I_XTLOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             N/A
Max Delay (ns):             N/A

END SUMMARY
-----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        F2M_GPI_1
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GPI[1]
  Delay (ns):                  1.836
  Slack (ns):
  Arrival (ns):                1.836
  Required (ns):
  Setup (ns):                  -0.057
  External Setup (ns):         1.779


Expanded Path 1
  From: F2M_GPI_1
  To: MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GPI[1]
  data required time                             N/C
  data arrival time                          -   1.836
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        F2M_GPI_1 (r)
               +     0.000          net: F2M_GPI_1
  0.000                        F2M_GPI_1_pad/U0/U0:PAD (r)
               +     0.806          cell: ADLIB:IOPAD_IN
  0.806                        F2M_GPI_1_pad/U0/U0:Y (r)
               +     0.000          net: F2M_GPI_1_pad/U0/NET1
  0.806                        F2M_GPI_1_pad/U0/U1:YIN (r)
               +     0.033          cell: ADLIB:IOIN_IB
  0.839                        F2M_GPI_1_pad/U0/U1:Y (r)
               +     0.817          net: F2M_GPI_1_c
  1.656                        MSS_top_level_0/MSS_ADLIB_INST/U_21:PIN5 (r)
               +     0.180          cell: ADLIB:MSS_IF
  1.836                        MSS_top_level_0/MSS_ADLIB_INST/U_21:PIN5INT (r)
               +     0.000          net: MSS_top_level_0/MSS_ADLIB_INST/GPI[1]INT_NET
  1.836                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GPI[1] (r)
                                    
  1.836                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_pclk1
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               -    -0.057          Library setup time: ADLIB:MSS_APB_IP
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:GPI[1]


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin MSS_top_level_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.781
  Slack (ns):
  Arrival (ns):                0.781
  Required (ns):
  Setup (ns):                  -1.830
  External Setup (ns):         -1.574


Expanded Path 1
  From: MSS_RESET_N
  To: MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.781
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        MSS_top_level_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.781          cell: ADLIB:IOPAD_IN
  0.781                        MSS_top_level_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: MSS_top_level_0/MSS_RESET_0_MSS_RESET_N_Y
  0.781                        MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.781                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.525          net: MSS_top_level_0/GLA0
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -1.830          Library setup time: ADLIB:MSS_APB_IP
  N/C                          MSS_top_level_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glb

SET Register to Register

Path 1
  From:                        Interrupt_Generator_0/counter2[5]:CLK
  To:                          Interrupt_Generator_0/counter2[4]:D
  Delay (ns):                  6.714
  Slack (ns):
  Arrival (ns):                7.247
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         7.136

Path 2
  From:                        Interrupt_Generator_0/counter2[5]:CLK
  To:                          Interrupt_Generator_0/counter2[9]:D
  Delay (ns):                  6.593
  Slack (ns):
  Arrival (ns):                7.126
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         7.015

Path 3
  From:                        Interrupt_Generator_0/counter1[3]:CLK
  To:                          Interrupt_Generator_0/FABINT:D
  Delay (ns):                  6.544
  Slack (ns):
  Arrival (ns):                7.048
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         6.964

Path 4
  From:                        Interrupt_Generator_0/counter2[5]:CLK
  To:                          Interrupt_Generator_0/counter2[19]:D
  Delay (ns):                  6.477
  Slack (ns):
  Arrival (ns):                7.010
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         6.952

Path 5
  From:                        Interrupt_Generator_0/counter2[5]:CLK
  To:                          Interrupt_Generator_0/counter2[16]:D
  Delay (ns):                  6.497
  Slack (ns):
  Arrival (ns):                7.030
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         6.906


Expanded Path 1
  From: Interrupt_Generator_0/counter2[5]:CLK
  To: Interrupt_Generator_0/counter2[4]:D
  data required time                             N/C
  data arrival time                          -   7.247
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_top_level_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.533          net: FAB_CLK
  0.533                        Interrupt_Generator_0/counter2[5]:CLK (r)
               +     0.440          cell: ADLIB:DFN1C0
  0.973                        Interrupt_Generator_0/counter2[5]:Q (r)
               +     0.919          net: Interrupt_Generator_0/counter2[5]
  1.892                        Interrupt_Generator_0/counter2_RNIK85F[30]:A (r)
               +     0.392          cell: ADLIB:NOR2A
  2.284                        Interrupt_Generator_0/counter2_RNIK85F[30]:Y (r)
               +     0.247          net: Interrupt_Generator_0/counter26_4
  2.531                        Interrupt_Generator_0/counter2_RNI3N891[26]:A (r)
               +     0.570          cell: ADLIB:NOR3A
  3.101                        Interrupt_Generator_0/counter2_RNI3N891[26]:Y (r)
               +     0.798          net: Interrupt_Generator_0/counter26_17
  3.899                        Interrupt_Generator_0/counter2_RNI3KS25[16]:B (r)
               +     0.473          cell: ADLIB:NOR3C
  4.372                        Interrupt_Generator_0/counter2_RNI3KS25[16]:Y (r)
               +     0.538          net: Interrupt_Generator_0/counter26_27
  4.910                        Interrupt_Generator_0/counter2_RNIU05I9[2]:C (r)
               +     0.505          cell: ADLIB:NOR3C
  5.415                        Interrupt_Generator_0/counter2_RNIU05I9[2]:Y (r)
               +     1.284          net: Interrupt_Generator_0/counter26
  6.699                        Interrupt_Generator_0/counter2_RNO[4]:B (r)
               +     0.293          cell: ADLIB:NOR2A
  6.992                        Interrupt_Generator_0/counter2_RNO[4]:Y (f)
               +     0.255          net: Interrupt_Generator_0/counter2_3[4]
  7.247                        Interrupt_Generator_0/counter2[4]:D (f)
                                    
  7.247                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: MSS_top_level_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          MSS_top_level_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.520          net: FAB_CLK
  N/C                          Interrupt_Generator_0/counter2[4]:CLK (r)
               -     0.409          Library setup time: ADLIB:DFN1C0
  N/C                          Interrupt_Generator_0/counter2[4]:D


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain MSS_top_level_0/MSS_CCC_0/I_XTLOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path

END SET Input to Output

----------------------------------------------------

Path set User Sets

