#-- Synopsys, Inc.
#-- Version E-2010.09A-1
#-- Project file C:\A2F_AC336_DF\A2F500\VHDL\highspeed_timerv2\synthesis\run_options.txt
#-- Written on Mon Dec 12 14:39:54 2011


#project files
add_file -vhdl -lib work "C:/A2F_AC336_DF/A2F500/VHDL/highspeed_timerv2/hdl/Decrementor24.vhd"
add_file -vhdl -lib work "C:/A2F_AC336_DF/A2F500/VHDL/highspeed_timerv2/hdl/count_zero_blk.vhd"
add_file -vhdl -lib work "C:/A2F_AC336_DF/A2F500/VHDL/highspeed_timerv2/hdl/AHB_timer.vhd"
add_file -vhdl -lib work "C:/A2F_AC336_DF/A2F500/VHDL/highspeed_timerv2/component/Actel/SmartFusionMSS/MSS/2.5.106/mss_comps.vhd"
add_file -vhdl -lib work "C:/A2F_AC336_DF/A2F500/VHDL/highspeed_timerv2/component/work/Timerv2/MSS_CCC_0/Timerv2_tmp_MSS_CCC_0_MSS_CCC.vhd"
add_file -vhdl -lib work "C:/A2F_AC336_DF/A2F500/VHDL/highspeed_timerv2/component/work/Timerv2/mss_tshell.vhd"
add_file -vhdl -lib work "C:/A2F_AC336_DF/A2F500/VHDL/highspeed_timerv2/component/work/Timerv2/Timerv2.vhd"
add_file -vhdl -lib COREAHBLITE_LIB "C:/A2F_AC336_DF/A2F500/VHDL/highspeed_timerv2/component/Actel/DirectCore/CoreAHBLite/3.1.102/rtl/vhdl/core/coreahblite_addrdec.vhd"
add_file -vhdl -lib COREAHBLITE_LIB "C:/A2F_AC336_DF/A2F500/VHDL/highspeed_timerv2/component/Actel/DirectCore/CoreAHBLite/3.1.102/rtl/vhdl/core/coreahblite_defaultslavesm.vhd"
add_file -vhdl -lib COREAHBLITE_LIB "C:/A2F_AC336_DF/A2F500/VHDL/highspeed_timerv2/component/Actel/DirectCore/CoreAHBLite/3.1.102/rtl/vhdl/core/coreahblite_masterstage.vhd"
add_file -vhdl -lib COREAHBLITE_LIB "C:/A2F_AC336_DF/A2F500/VHDL/highspeed_timerv2/component/Actel/DirectCore/CoreAHBLite/3.1.102/rtl/vhdl/core/coreahblite_slavearbiter.vhd"
add_file -vhdl -lib COREAHBLITE_LIB "C:/A2F_AC336_DF/A2F500/VHDL/highspeed_timerv2/component/Actel/DirectCore/CoreAHBLite/3.1.102/rtl/vhdl/core/coreahblite_slavestage.vhd"
add_file -vhdl -lib COREAHBLITE_LIB "C:/A2F_AC336_DF/A2F500/VHDL/highspeed_timerv2/component/Actel/DirectCore/CoreAHBLite/3.1.102/rtl/vhdl/core/coreahblite_initcfg_awrap.vhd"
add_file -vhdl -lib COREAHBLITE_LIB "C:/A2F_AC336_DF/A2F500/VHDL/highspeed_timerv2/component/Actel/DirectCore/CoreAHBLite/3.1.102/rtl/vhdl/core/coreahblite_initcfg.vhd"
add_file -vhdl -lib COREAHBLITE_LIB "C:/A2F_AC336_DF/A2F500/VHDL/highspeed_timerv2/component/Actel/DirectCore/CoreAHBLite/3.1.102/rtl/vhdl/core/coreahblite_matrix2x16.vhd"
add_file -vhdl -lib COREAHBLITE_LIB "C:/A2F_AC336_DF/A2F500/VHDL/highspeed_timerv2/component/Actel/DirectCore/CoreAHBLite/3.1.102/rtl/vhdl/core/coreahblite.vhd"
add_file -vhdl -lib work "C:/A2F_AC336_DF/A2F500/VHDL/highspeed_timerv2/component/work/top_timer/top_timer.vhd"
add_file -constraint "C:/A2F_AC336_DF/A2F500/VHDL/highspeed_timerv2/component/work/Timerv2/mss_tshell_syn.sdc"


#implementation: "synthesis"
impl -add synthesis -type fpga

#device options
set_option -technology SmartFusion
set_option -part A2F500M3G
set_option -package FBGA484
set_option -speed_grade STD
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "work.top_timer"

# mapper_options
set_option -frequency 100.000
set_option -write_verilog 0
set_option -write_vhdl 0

# Actel 500K
set_option -run_prop_extract 1
set_option -maxfan 24
set_option -maxfan_hard3 0
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -report_path 0
set_option -opcond COMWC
set_option -update_models_cp 0
set_option -preserve_registers 0

# Actel 500K
set_option -globalthreshold 50

# NFilter
set_option -popfeed 0
set_option -constprop 0
set_option -createhierarchy 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./top_timer.edn"
impl -active "synthesis"
