Timing Violation Report Min Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Mon Dec 12 14:41:19 2011


Design: top_timer
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


Path 1
  From:                        AHB_timer_0/reg_load_ack0/U1:CLK
  To:                          AHB_timer_0/reg_load_ack1:D
  Delay (ns):                  0.429
  Slack (ns):                  -2.662
  Arrival (ns):                1.712
  Required (ns):               4.374

Path 2
  From:                        AHB_timer_0/DataOut[22]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[22]:D
  Delay (ns):                  0.430
  Slack (ns):                  -2.650
  Arrival (ns):                1.722
  Required (ns):               4.372

Path 3
  From:                        AHB_timer_0/DataOut[6]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[6]:D
  Delay (ns):                  0.430
  Slack (ns):                  -2.645
  Arrival (ns):                1.727
  Required (ns):               4.372

Path 4
  From:                        AHB_timer_0/p_strecth_TIMINT_pulse.TIMINT_pulse_int[3]:CLK
  To:                          AHB_timer_0/TIMINT_int_hclk:D
  Delay (ns):                  0.790
  Slack (ns):                  -2.304
  Arrival (ns):                2.056
  Required (ns):               4.360

Path 5
  From:                        AHB_timer_0/DataOut[3]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[3]:D
  Delay (ns):                  0.811
  Slack (ns):                  -2.297
  Arrival (ns):                2.094
  Required (ns):               4.391

Path 6
  From:                        AHB_timer_0/DataOut[5]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[5]:D
  Delay (ns):                  0.811
  Slack (ns):                  -2.297
  Arrival (ns):                2.094
  Required (ns):               4.391

Path 7
  From:                        AHB_timer_0/DataOut[13]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[13]:D
  Delay (ns):                  0.832
  Slack (ns):                  -2.253
  Arrival (ns):                2.138
  Required (ns):               4.391

Path 8
  From:                        AHB_timer_0/DataOut[17]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[17]:D
  Delay (ns):                  0.847
  Slack (ns):                  -2.240
  Arrival (ns):                2.138
  Required (ns):               4.378

Path 9
  From:                        AHB_timer_0/DataOut[9]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[9]:D
  Delay (ns):                  0.886
  Slack (ns):                  -2.199
  Arrival (ns):                2.192
  Required (ns):               4.391

Path 10
  From:                        AHB_timer_0/DataOut[16]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[16]:D
  Delay (ns):                  0.900
  Slack (ns):                  -2.185
  Arrival (ns):                2.187
  Required (ns):               4.372

Path 11
  From:                        AHB_timer_0/DataOut[11]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[11]:D
  Delay (ns):                  0.914
  Slack (ns):                  -2.156
  Arrival (ns):                2.225
  Required (ns):               4.381

Path 12
  From:                        AHB_timer_0/DataOut[12]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[12]:D
  Delay (ns):                  0.959
  Slack (ns):                  -2.149
  Arrival (ns):                2.242
  Required (ns):               4.391

Path 13
  From:                        AHB_timer_0/DataOut[1]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[1]:D
  Delay (ns):                  0.953
  Slack (ns):                  -2.146
  Arrival (ns):                2.245
  Required (ns):               4.391

Path 14
  From:                        AHB_timer_0/DataOut[2]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[2]:D
  Delay (ns):                  0.953
  Slack (ns):                  -2.127
  Arrival (ns):                2.250
  Required (ns):               4.377

Path 15
  From:                        AHB_timer_0/DataOut[8]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[8]:D
  Delay (ns):                  0.946
  Slack (ns):                  -2.126
  Arrival (ns):                2.249
  Required (ns):               4.375

Path 16
  From:                        AHB_timer_0/DataOut[18]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[18]:D
  Delay (ns):                  0.951
  Slack (ns):                  -2.118
  Arrival (ns):                2.269
  Required (ns):               4.387

Path 17
  From:                        AHB_timer_0/DataOut[20]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[20]:D
  Delay (ns):                  0.979
  Slack (ns):                  -2.110
  Arrival (ns):                2.271
  Required (ns):               4.381

Path 18
  From:                        AHB_timer_0/DataOut[14]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[14]:D
  Delay (ns):                  0.992
  Slack (ns):                  -2.084
  Arrival (ns):                2.303
  Required (ns):               4.387

Path 19
  From:                        AHB_timer_0/DataOut[23]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[23]:D
  Delay (ns):                  1.006
  Slack (ns):                  -2.080
  Arrival (ns):                2.298
  Required (ns):               4.378

Path 20
  From:                        AHB_timer_0/DataOut[4]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[4]:D
  Delay (ns):                  1.072
  Slack (ns):                  -2.013
  Arrival (ns):                2.383
  Required (ns):               4.396

Path 21
  From:                        AHB_timer_0/DataOut[7]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[7]:D
  Delay (ns):                  1.100
  Slack (ns):                  -1.999
  Arrival (ns):                2.392
  Required (ns):               4.391

Path 22
  From:                        AHB_timer_0/DataOut[10]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[10]:D
  Delay (ns):                  1.112
  Slack (ns):                  -1.997
  Arrival (ns):                2.399
  Required (ns):               4.396

Path 23
  From:                        AHB_timer_0/DataOut[0]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[0]:D
  Delay (ns):                  1.129
  Slack (ns):                  -1.955
  Arrival (ns):                2.426
  Required (ns):               4.381

Path 24
  From:                        AHB_timer_0/DataOut[19]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[19]:D
  Delay (ns):                  1.135
  Slack (ns):                  -1.933
  Arrival (ns):                2.441
  Required (ns):               4.374

Path 25
  From:                        AHB_timer_0/p_strecth_TIMINT_pulse.TIMINT_pulse_int[1]:CLK
  To:                          AHB_timer_0/TIMINT_int_hclk:D
  Delay (ns):                  1.163
  Slack (ns):                  -1.928
  Arrival (ns):                2.432
  Required (ns):               4.360

Path 26
  From:                        AHB_timer_0/DataOut[15]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[15]:D
  Delay (ns):                  1.197
  Slack (ns):                  -1.874
  Arrival (ns):                2.503
  Required (ns):               4.377

Path 27
  From:                        AHB_timer_0/DataOut[21]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[21]:D
  Delay (ns):                  1.216
  Slack (ns):                  -1.850
  Arrival (ns):                2.534
  Required (ns):               4.384

Path 28
  From:                        AHB_timer_0/p_strecth_TIMINT_pulse.TIMINT_pulse_int[2]:CLK
  To:                          AHB_timer_0/TIMINT_int_hclk:D
  Delay (ns):                  1.307
  Slack (ns):                  -1.784
  Arrival (ns):                2.576
  Required (ns):               4.360

Path 29
  From:                        AHB_timer_0/IntEnable/U1:CLK
  To:                          AHB_timer_0/TIMINT_int_hclk:D
  Delay (ns):                  2.182
  Slack (ns):                  -0.891
  Arrival (ns):                3.469
  Required (ns):               4.360

Path 30
  From:                        AHB_timer_0/count_zero_blk_instance/count23_3_zero:CLK
  To:                          AHB_timer_0/TIMINT_int_hclk:D
  Delay (ns):                  2.814
  Slack (ns):                  -0.258
  Arrival (ns):                4.102
  Required (ns):               4.360

