Timing Report Min Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Mon Dec 12 14:41:18 2011


Design: top_timer
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               AHB_timer_0/TIMINT_int_hclk:Q
Period (ns):                0.860
Frequency (MHz):            1162.791
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                15.526
Frequency (MHz):            64.408
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      8.262
Max Clock-To-Out (ns):      15.072

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        -5.206
External Hold (ns):         4.012
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_glc
Period (ns):                11.294
Frequency (MHz):            88.543
Required Period (ns):       8.333
Required Frequency (MHz):   120.005
External Setup (ns):        8.824
External Hold (ns):         -0.959
Min Clock-To-Out (ns):      5.301
Max Clock-To-Out (ns):      13.968

Clock Domain:               \\Timerv2\\/MSS_CCC_0/I_RCOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             2.549
Max Delay (ns):             6.189

END SUMMARY
-----------------------------------------------------

Clock Domain AHB_timer_0/TIMINT_int_hclk:Q

Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin AHB_timer_0/TIMINT_pending_int:CLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        AHB_timer_0/reg_load_ack1:CLK
  To:                          AHB_timer_0/reg_load_ack2:D
  Delay (ns):                  0.397
  Slack (ns):                  0.382
  Arrival (ns):                4.756
  Required (ns):               4.374
  Hold (ns):                   0.000

Path 2
  From:                        AHB_timer_0/HREADYOUT/U1:CLK
  To:                          CoreAHBLite_0/matrix2x16/slavestage_5/masterDataInProg[0]/U1:D
  Delay (ns):                  0.775
  Slack (ns):                  0.758
  Arrival (ns):                5.139
  Required (ns):               4.381
  Hold (ns):                   0.000

Path 3
  From:                        AHB_timer_0/HWRITE_int/U1:CLK
  To:                          AHB_timer_0/HWRITE_int/U1:D
  Delay (ns):                  0.792
  Slack (ns):                  0.777
  Arrival (ns):                5.149
  Required (ns):               4.372
  Hold (ns):                   0.000

Path 4
  From:                        CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState[0]:CLK
  To:                          CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState[0]:D
  Delay (ns):                  0.797
  Slack (ns):                  0.781
  Arrival (ns):                5.162
  Required (ns):               4.381
  Hold (ns):                   0.000

Path 5
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[10]/U1:CLK
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[10]/U1:D
  Delay (ns):                  0.800
  Slack (ns):                  0.783
  Arrival (ns):                5.170
  Required (ns):               4.387
  Hold (ns):                   0.000


Expanded Path 1
  From: AHB_timer_0/reg_load_ack1:CLK
  To: AHB_timer_0/reg_load_ack2:D
  data arrival time                              4.756
  data required time                         -   4.374
  slack                                          0.382
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.324          net: mss_highspeed_timerv2_0_FAB_CLK
  4.359                        AHB_timer_0/reg_load_ack1:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  4.608                        AHB_timer_0/reg_load_ack1:Q (r)
               +     0.148          net: AHB_timer_0/reg_load_ack1
  4.756                        AHB_timer_0/reg_load_ack2:D (r)
                                    
  4.756                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.339          net: mss_highspeed_timerv2_0_FAB_CLK
  4.374                        AHB_timer_0/reg_load_ack2:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  4.374                        AHB_timer_0/reg_load_ack2:D
                                    
  4.374                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        AHB_timer_0/TIMINT_int_hclk:CLK
  To:                          TIMINT
  Delay (ns):                  3.917
  Slack (ns):
  Arrival (ns):                8.262
  Required (ns):
  Clock to Out (ns):           8.262


Expanded Path 1
  From: AHB_timer_0/TIMINT_int_hclk:CLK
  To: TIMINT
  data arrival time                              8.262
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.310          net: mss_highspeed_timerv2_0_FAB_CLK
  4.345                        AHB_timer_0/TIMINT_int_hclk:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  4.594                        AHB_timer_0/TIMINT_int_hclk:Q (r)
               +     1.586          net: AHB_timer_0/TIMINT_int_hclk_i
  6.180                        AHB_timer_0/TIMINT_int_hclk_RNI4603/U_CLKSRC:A (r)
               +     0.329          cell: ADLIB:CLKSRC
  6.509                        AHB_timer_0/TIMINT_int_hclk_RNI4603/U_CLKSRC:Y (r)
               +     0.355          net: TIMINT_c
  6.864                        TIMINT_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  7.143                        TIMINT_pad/U0/U1:DOUT (r)
               +     0.000          net: TIMINT_pad/U0/NET1
  7.143                        TIMINT_pad/U0/U0:D (r)
               +     1.119          cell: ADLIB:IOPAD_TRI
  8.262                        TIMINT_pad/U0/U0:PAD (r)
               +     0.000          net: TIMINT
  8.262                        TIMINT (r)
                                    
  8.262                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  N/C
                                    
  N/C                          TIMINT (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla0 to mss_ccc_gla1

Path 1
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[13]/U1:CLR
  Delay (ns):                  2.309
  Slack (ns):                  0.862
  Arrival (ns):                5.258
  Required (ns):               4.396
  Hold (ns):

Path 2
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHMASTLOCK/U1:CLR
  Delay (ns):                  2.309
  Slack (ns):                  0.862
  Arrival (ns):                5.258
  Required (ns):               4.396
  Hold (ns):

Path 3
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHWRITE/U1:CLR
  Delay (ns):                  2.309
  Slack (ns):                  0.862
  Arrival (ns):                5.258
  Required (ns):               4.396
  Hold (ns):

Path 4
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[19]/U1:CLR
  Delay (ns):                  2.309
  Slack (ns):                  0.862
  Arrival (ns):                5.258
  Required (ns):               4.396
  Hold (ns):

Path 5
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[15]/U1:CLR
  Delay (ns):                  2.309
  Slack (ns):                  0.862
  Arrival (ns):                5.258
  Required (ns):               4.396
  Hold (ns):


Expanded Path 1
  From: _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To: CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[13]/U1:CLR
  data arrival time                              5.258
  data required time                         -   4.396
  slack                                          0.862
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  2.724
               +     0.225          net: _Timerv2_/MSS_ADLIB_INST_FCLK
  2.949                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.569          cell: ADLIB:MSS_AHB_IP
  4.518                        _Timerv2_/MSS_ADLIB_INST/U_CORE:M2FRESETn (r)
               +     0.059          net: _Timerv2_/MSS_ADLIB_INST/M2FRESETnINT_NET
  4.577                        _Timerv2_/MSS_ADLIB_INST/U_46:PIN2INT (r)
               +     0.045          cell: ADLIB:MSS_IF
  4.622                        _Timerv2_/MSS_ADLIB_INST/U_46:PIN2 (r)
               +     0.636          net: mss_highspeed_timerv2_0_M2F_RESET_N
  5.258                        CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[13]/U1:CLR (r)
                                    
  5.258                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.361          net: mss_highspeed_timerv2_0_FAB_CLK
  4.396                        CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[13]/U1:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1C0
  4.396                        CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[13]/U1:CLR
                                    
  4.396                        data required time


END SET mss_ccc_gla0 to mss_ccc_gla1

----------------------------------------------------

SET mss_ccc_glc to mss_ccc_gla1

Path 1
  From:                        AHB_timer_0/reg_load_ack0/U1:CLK
  To:                          AHB_timer_0/reg_load_ack1:D
  Delay (ns):                  0.429
  Slack (ns):                  -2.662
  Arrival (ns):                1.712
  Required (ns):               4.374
  Hold (ns):                   0.000

Path 2
  From:                        AHB_timer_0/DataOut[22]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[22]:D
  Delay (ns):                  0.430
  Slack (ns):                  -2.650
  Arrival (ns):                1.722
  Required (ns):               4.372
  Hold (ns):                   0.000

Path 3
  From:                        AHB_timer_0/DataOut[6]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[6]:D
  Delay (ns):                  0.430
  Slack (ns):                  -2.645
  Arrival (ns):                1.727
  Required (ns):               4.372
  Hold (ns):                   0.000

Path 4
  From:                        AHB_timer_0/p_strecth_TIMINT_pulse.TIMINT_pulse_int[3]:CLK
  To:                          AHB_timer_0/TIMINT_int_hclk:D
  Delay (ns):                  0.790
  Slack (ns):                  -2.304
  Arrival (ns):                2.056
  Required (ns):               4.360
  Hold (ns):                   0.000

Path 5
  From:                        AHB_timer_0/DataOut[3]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[3]:D
  Delay (ns):                  0.811
  Slack (ns):                  -2.297
  Arrival (ns):                2.094
  Required (ns):               4.391
  Hold (ns):                   0.000


Expanded Path 1
  From: AHB_timer_0/reg_load_ack0/U1:CLK
  To: AHB_timer_0/reg_load_ack1:D
  data arrival time                              1.712
  data required time                         -   4.374
  slack                                          -2.662
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.957          Clock generation
  0.957
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.326          net: Timerv2_GLC
  1.283                        AHB_timer_0/reg_load_ack0/U1:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  1.532                        AHB_timer_0/reg_load_ack0/U1:Q (r)
               +     0.180          net: AHB_timer_0/reg_load_ack0
  1.712                        AHB_timer_0/reg_load_ack1:D (r)
                                    
  1.712                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.339          net: mss_highspeed_timerv2_0_FAB_CLK
  4.374                        AHB_timer_0/reg_load_ack1:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  4.374                        AHB_timer_0/reg_load_ack1:D
                                    
  4.374                        data required time


END SET mss_ccc_glc to mss_ccc_gla1

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_gla1

Path 1
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[4]/U1:D
  Delay (ns):                  2.375
  Slack (ns):                  0.952
  Arrival (ns):                5.324
  Required (ns):               4.372
  Hold (ns):                   0.000

Path 2
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[12]/U1:D
  Delay (ns):                  2.417
  Slack (ns):                  0.970
  Arrival (ns):                5.366
  Required (ns):               4.396
  Hold (ns):                   0.000

Path 3
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[13]/U1:D
  Delay (ns):                  2.511
  Slack (ns):                  1.064
  Arrival (ns):                5.460
  Required (ns):               4.396
  Hold (ns):                   0.000

Path 4
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[2]/U1:D
  Delay (ns):                  2.528
  Slack (ns):                  1.105
  Arrival (ns):                5.477
  Required (ns):               4.372
  Hold (ns):                   0.000

Path 5
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHMASTLOCK/U1:D
  Delay (ns):                  2.559
  Slack (ns):                  1.112
  Arrival (ns):                5.508
  Required (ns):               4.396
  Hold (ns):                   0.000


Expanded Path 1
  From: _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To: CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[4]/U1:D
  data arrival time                              5.324
  data required time                         -   4.372
  slack                                          0.952
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.949          Clock generation
  2.949
               +     1.348          cell: ADLIB:MSS_AHB_IP
  4.297                        _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHADDR[4] (r)
               +     0.059          net: _Timerv2_/MSS_ADLIB_INST/MSSHADDR[4]INT_NET
  4.356                        _Timerv2_/MSS_ADLIB_INST/U_31:PIN2INT (r)
               +     0.045          cell: ADLIB:MSS_IF
  4.401                        _Timerv2_/MSS_ADLIB_INST/U_31:PIN2 (r)
               +     0.522          net: _mss_highspeed_timerv2_0_MSS_MASTER_AHB_LITE_HADDR_[4]_
  4.923                        CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[4]/U0:B (r)
               +     0.251          cell: ADLIB:MX2
  5.174                        CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[4]/U0:Y (r)
               +     0.150          net: CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[4]/Y
  5.324                        CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[4]/U1:D (r)
                                    
  5.324                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.337          net: mss_highspeed_timerv2_0_FAB_CLK
  4.372                        CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[4]/U1:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  4.372                        CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[4]/U1:D
                                    
  4.372                        data required time


END SET mss_fabric_interface_clock to mss_ccc_gla1

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.277
  Slack (ns):
  Arrival (ns):                0.277
  Required (ns):
  Hold (ns):                   1.294
  External Hold (ns):          4.012


Expanded Path 1
  From: MSS_RESET_N
  To: _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.277
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        \\Timerv2\\/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.277          cell: ADLIB:IOPAD_IN
  0.277                        \\Timerv2\\/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: _Timerv2_/MSS_RESET_0_MSS_RESET_N_Y
  0.277                        _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.277                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  N/C
               +     0.271          net: _Timerv2_/MSS_ADLIB_INST_FCLK
  N/C                          _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.294          Library hold time: ADLIB:MSS_AHB_IP
  N/C                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glc

SET Register to Register

Path 1
  From:                        AHB_timer_0/reg_load_en1:CLK
  To:                          AHB_timer_0/reg_load_en2:D
  Delay (ns):                  0.397
  Slack (ns):                  0.378
  Arrival (ns):                1.698
  Required (ns):               1.320
  Hold (ns):                   0.000

Path 2
  From:                        AHB_timer_0/reg_load_en2:CLK
  To:                          AHB_timer_0/FCLKSTATE[0]:D
  Delay (ns):                  0.399
  Slack (ns):                  0.379
  Arrival (ns):                1.700
  Required (ns):               1.321
  Hold (ns):                   0.000

Path 3
  From:                        AHB_timer_0/p_strecth_TIMINT_pulse.TIMINT_pulse_int[1]:CLK
  To:                          AHB_timer_0/p_strecth_TIMINT_pulse.TIMINT_pulse_int[2]:D
  Delay (ns):                  0.430
  Slack (ns):                  0.415
  Arrival (ns):                1.699
  Required (ns):               1.284
  Hold (ns):                   0.000

Path 4
  From:                        AHB_timer_0/p_strecth_TIMINT_pulse.TIMINT_pulse_int[2]:CLK
  To:                          AHB_timer_0/p_strecth_TIMINT_pulse.TIMINT_pulse_int[3]:D
  Delay (ns):                  0.430
  Slack (ns):                  0.418
  Arrival (ns):                1.699
  Required (ns):               1.281
  Hold (ns):                   0.000

Path 5
  From:                        AHB_timer_0/Sample[0]:CLK
  To:                          AHB_timer_0/Sample[1]:D
  Delay (ns):                  0.680
  Slack (ns):                  0.643
  Arrival (ns):                1.959
  Required (ns):               1.316
  Hold (ns):                   0.000


Expanded Path 1
  From: AHB_timer_0/reg_load_en1:CLK
  To: AHB_timer_0/reg_load_en2:D
  data arrival time                              1.698
  data required time                         -   1.320
  slack                                          0.378
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.957          Clock generation
  0.957
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.344          net: Timerv2_GLC
  1.301                        AHB_timer_0/reg_load_en1:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  1.550                        AHB_timer_0/reg_load_en1:Q (r)
               +     0.148          net: AHB_timer_0/reg_load_en1
  1.698                        AHB_timer_0/reg_load_en2:D (r)
                                    
  1.698                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.957          Clock generation
  0.957
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.363          net: Timerv2_GLC
  1.320                        AHB_timer_0/reg_load_en2:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  1.320                        AHB_timer_0/reg_load_en2:D
                                    
  1.320                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        Pulse_in
  To:                          AHB_timer_0/Sample[0]:D
  Delay (ns):                  2.302
  Slack (ns):
  Arrival (ns):                2.302
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -0.959

Path 2
  From:                        Pulse_in
  To:                          AHB_timer_0/Count[7]/U1:D
  Delay (ns):                  4.040
  Slack (ns):
  Arrival (ns):                4.040
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -2.682

Path 3
  From:                        Pulse_in
  To:                          AHB_timer_0/Count[6]/U1:D
  Delay (ns):                  4.042
  Slack (ns):
  Arrival (ns):                4.042
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -2.685

Path 4
  From:                        Pulse_in
  To:                          AHB_timer_0/Count[1]/U1:D
  Delay (ns):                  4.312
  Slack (ns):
  Arrival (ns):                4.312
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -2.947

Path 5
  From:                        Pulse_in
  To:                          AHB_timer_0/Count[9]/U1:D
  Delay (ns):                  4.332
  Slack (ns):
  Arrival (ns):                4.332
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -2.974


Expanded Path 1
  From: Pulse_in
  To: AHB_timer_0/Sample[0]:D
  data arrival time                              2.302
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        Pulse_in (f)
               +     0.000          net: Pulse_in
  0.000                        Pulse_in_pad/U0/U0:PAD (f)
               +     0.277          cell: ADLIB:IOPAD_IN
  0.277                        Pulse_in_pad/U0/U0:Y (f)
               +     0.000          net: Pulse_in_pad/U0/NET1
  0.277                        Pulse_in_pad/U0/U1:YIN (f)
               +     0.017          cell: ADLIB:IOIN_IB
  0.294                        Pulse_in_pad/U0/U1:Y (f)
               +     2.008          net: Pulse_in_c_c
  2.302                        AHB_timer_0/Sample[0]:D (f)
                                    
  2.302                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glc
               +     0.000          Clock source
  N/C                          \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.957          Clock generation
  N/C
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  N/C                          \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.386          net: Timerv2_GLC
  N/C                          AHB_timer_0/Sample[0]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          AHB_timer_0/Sample[0]:D


END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        AHB_timer_0/Count[23]/U1:CLK
  To:                          Test_port[2]
  Delay (ns):                  3.995
  Slack (ns):
  Arrival (ns):                5.301
  Required (ns):
  Clock to Out (ns):           5.301

Path 2
  From:                        AHB_timer_0/count_zero_blk_instance/count23_3_zero:CLK
  To:                          Test_port[3]
  Delay (ns):                  4.378
  Slack (ns):
  Arrival (ns):                5.666
  Required (ns):
  Clock to Out (ns):           5.666

Path 3
  From:                        AHB_timer_0/TimerEn/U1:CLK
  To:                          Test_port[1]
  Delay (ns):                  4.872
  Slack (ns):
  Arrival (ns):                6.183
  Required (ns):
  Clock to Out (ns):           6.183

Path 4
  From:                        AHB_timer_0/Count[2]/U1:CLK
  To:                          Test_port[3]
  Delay (ns):                  5.059
  Slack (ns):
  Arrival (ns):                6.350
  Required (ns):
  Clock to Out (ns):           6.350

Path 5
  From:                        AHB_timer_0/Count[0]/U1:CLK
  To:                          Test_port[3]
  Delay (ns):                  5.257
  Slack (ns):
  Arrival (ns):                6.536
  Required (ns):
  Clock to Out (ns):           6.536


Expanded Path 1
  From: AHB_timer_0/Count[23]/U1:CLK
  To: Test_port[2]
  data arrival time                              5.301
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.957          Clock generation
  0.957
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.349          net: Timerv2_GLC
  1.306                        AHB_timer_0/Count[23]/U1:CLK (r)
               +     0.249          cell: ADLIB:DFN1P0
  1.555                        AHB_timer_0/Count[23]/U1:Q (r)
               +     2.370          net: Test_port_c[2]
  3.925                        Test_port_pad[2]/U0/U1:D (r)
               +     0.257          cell: ADLIB:IOTRI_OB_EB
  4.182                        Test_port_pad[2]/U0/U1:DOUT (r)
               +     0.000          net: Test_port_pad[2]/U0/NET1
  4.182                        Test_port_pad[2]/U0/U0:D (r)
               +     1.119          cell: ADLIB:IOPAD_TRI
  5.301                        Test_port_pad[2]/U0/U0:PAD (r)
               +     0.000          net: Test_port[2]
  5.301                        Test_port[2] (r)
                                    
  5.301                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glc
               +     0.000          Clock source
  N/C                          \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.957          Clock generation
  N/C
                                    
  N/C                          Test_port[2] (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_ccc_glc

Path 1
  From:                        AHB_timer_0/reg_load_en0/U1:CLK
  To:                          AHB_timer_0/reg_load_en1:D
  Delay (ns):                  0.428
  Slack (ns):                  3.472
  Arrival (ns):                4.792
  Required (ns):               1.320
  Hold (ns):                   0.000

Path 2
  From:                        CoreAHBLite_0/matrix2x16/slavestage_5/masterDataInProg[1]/U1:CLK
  To:                          AHB_timer_0/Load[18]/U1:D
  Delay (ns):                  1.311
  Slack (ns):                  4.359
  Arrival (ns):                5.681
  Required (ns):               1.322
  Hold (ns):                   0.000

Path 3
  From:                        CoreAHBLite_0/matrix2x16/slavestage_5/masterDataInProg_0[0]/U1:CLK
  To:                          AHB_timer_0/Load[5]/U1:D
  Delay (ns):                  1.397
  Slack (ns):                  4.445
  Arrival (ns):                5.767
  Required (ns):               1.322
  Hold (ns):                   0.000

Path 4
  From:                        CoreAHBLite_0/matrix2x16/slavestage_5/masterDataInProg_0[0]/U1:CLK
  To:                          AHB_timer_0/Load[4]/U1:D
  Delay (ns):                  1.395
  Slack (ns):                  4.445
  Arrival (ns):                5.765
  Required (ns):               1.320
  Hold (ns):                   0.000

Path 5
  From:                        CoreAHBLite_0/matrix2x16/slavestage_5/masterDataInProg_0[0]/U1:CLK
  To:                          AHB_timer_0/Load[8]/U1:D
  Delay (ns):                  1.397
  Slack (ns):                  4.445
  Arrival (ns):                5.767
  Required (ns):               1.322
  Hold (ns):                   0.000


Expanded Path 1
  From: AHB_timer_0/reg_load_en0/U1:CLK
  To: AHB_timer_0/reg_load_en1:D
  data arrival time                              4.792
  data required time                         -   1.320
  slack                                          3.472
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.329          net: mss_highspeed_timerv2_0_FAB_CLK
  4.364                        AHB_timer_0/reg_load_en0/U1:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  4.613                        AHB_timer_0/reg_load_en0/U1:Q (r)
               +     0.179          net: AHB_timer_0/reg_load_en0
  4.792                        AHB_timer_0/reg_load_en1:D (r)
                                    
  4.792                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.957          Clock generation
  0.957
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.363          net: Timerv2_GLC
  1.320                        AHB_timer_0/reg_load_en1:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  1.320                        AHB_timer_0/reg_load_en1:D
                                    
  1.320                        data required time


END SET mss_ccc_gla1 to mss_ccc_glc

----------------------------------------------------

SET mss_ccc_gla0 to mss_ccc_glc

Path 1
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          AHB_timer_0/TIMINT1[17]/U1:PRE
  Delay (ns):                  2.308
  Slack (ns):                  3.936
  Arrival (ns):                5.257
  Required (ns):               1.321
  Hold (ns):

Path 2
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          AHB_timer_0/FCLKSTATE[0]:CLR
  Delay (ns):                  2.308
  Slack (ns):                  3.936
  Arrival (ns):                5.257
  Required (ns):               1.321
  Hold (ns):

Path 3
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          AHB_timer_0/TIMINT1[12]/U1:PRE
  Delay (ns):                  2.475
  Slack (ns):                  4.100
  Arrival (ns):                5.424
  Required (ns):               1.324
  Hold (ns):

Path 4
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          AHB_timer_0/TIMINT2[14]/U1:PRE
  Delay (ns):                  2.475
  Slack (ns):                  4.100
  Arrival (ns):                5.424
  Required (ns):               1.324
  Hold (ns):

Path 5
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          AHB_timer_0/TIMINT2[10]/U1:PRE
  Delay (ns):                  2.475
  Slack (ns):                  4.106
  Arrival (ns):                5.424
  Required (ns):               1.318
  Hold (ns):


Expanded Path 1
  From: _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To: AHB_timer_0/TIMINT1[17]/U1:PRE
  data arrival time                              5.257
  data required time                         -   1.321
  slack                                          3.936
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  2.724
               +     0.225          net: _Timerv2_/MSS_ADLIB_INST_FCLK
  2.949                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.569          cell: ADLIB:MSS_AHB_IP
  4.518                        _Timerv2_/MSS_ADLIB_INST/U_CORE:M2FRESETn (r)
               +     0.059          net: _Timerv2_/MSS_ADLIB_INST/M2FRESETnINT_NET
  4.577                        _Timerv2_/MSS_ADLIB_INST/U_46:PIN2INT (r)
               +     0.045          cell: ADLIB:MSS_IF
  4.622                        _Timerv2_/MSS_ADLIB_INST/U_46:PIN2 (r)
               +     0.635          net: mss_highspeed_timerv2_0_M2F_RESET_N
  5.257                        AHB_timer_0/TIMINT1[17]/U1:PRE (r)
                                    
  5.257                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.957          Clock generation
  0.957
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.364          net: Timerv2_GLC
  1.321                        AHB_timer_0/TIMINT1[17]/U1:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1P0
  1.321                        AHB_timer_0/TIMINT1[17]/U1:PRE
                                    
  1.321                        data required time


END SET mss_ccc_gla0 to mss_ccc_glc

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_glc

Path 1
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          AHB_timer_0/Load[15]/U1:D
  Delay (ns):                  2.970
  Slack (ns):                  4.601
  Arrival (ns):                5.919
  Required (ns):               1.318
  Hold (ns):                   0.000

Path 2
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          AHB_timer_0/Load[13]/U1:D
  Delay (ns):                  3.020
  Slack (ns):                  4.651
  Arrival (ns):                5.969
  Required (ns):               1.318
  Hold (ns):                   0.000

Path 3
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          AHB_timer_0/Load[2]/U1:D
  Delay (ns):                  3.039
  Slack (ns):                  4.666
  Arrival (ns):                5.988
  Required (ns):               1.322
  Hold (ns):                   0.000

Path 4
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          AHB_timer_0/Load[17]/U1:D
  Delay (ns):                  3.162
  Slack (ns):                  4.789
  Arrival (ns):                6.111
  Required (ns):               1.322
  Hold (ns):                   0.000

Path 5
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          AHB_timer_0/Load[0]/U1:D
  Delay (ns):                  3.165
  Slack (ns):                  4.790
  Arrival (ns):                6.114
  Required (ns):               1.324
  Hold (ns):                   0.000


Expanded Path 1
  From: _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To: AHB_timer_0/Load[15]/U1:D
  data arrival time                              5.919
  data required time                         -   1.318
  slack                                          4.601
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.949          Clock generation
  2.949
               +     1.348          cell: ADLIB:MSS_AHB_IP
  4.297                        _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHWDATA[15] (r)
               +     0.060          net: _Timerv2_/MSS_ADLIB_INST/MSSHWDATA[15]INT_NET
  4.357                        _Timerv2_/MSS_ADLIB_INST/U_41:PIN3INT (r)
               +     0.040          cell: ADLIB:MSS_IF
  4.397                        _Timerv2_/MSS_ADLIB_INST/U_41:PIN3 (r)
               +     0.704          net: _mss_highspeed_timerv2_0_MSS_MASTER_AHB_LITE_HWDATA_[15]_
  5.101                        CoreAHBLite_0/matrix2x16/slavestage_5/masterDataInProg_RNIRE3E_9[0]:B (r)
               +     0.267          cell: ADLIB:NOR3B
  5.368                        CoreAHBLite_0/matrix2x16/slavestage_5/masterDataInProg_RNIRE3E_9[0]:Y (r)
               +     0.150          net: _CoreAHBLite_0_AHBmslave5_HWDATA_[15]_
  5.518                        AHB_timer_0/Load[15]/U0:B (r)
               +     0.251          cell: ADLIB:MX2
  5.769                        AHB_timer_0/Load[15]/U0:Y (r)
               +     0.150          net: AHB_timer_0/Load[15]/Y
  5.919                        AHB_timer_0/Load[15]/U1:D (r)
                                    
  5.919                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.957          Clock generation
  0.957
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.361          net: Timerv2_GLC
  1.318                        AHB_timer_0/Load[15]/U1:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  1.318                        AHB_timer_0/Load[15]/U1:D
                                    
  1.318                        data required time


END SET mss_fabric_interface_clock to mss_ccc_glc

----------------------------------------------------

Clock Domain \\Timerv2\\/MSS_CCC_0/I_RCOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_fabric_interface_clock

Path 1
  From:                        AHB_timer_0/DataOut_int[15]:CLK
  To:                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHRDATA[15]
  Delay (ns):                  1.370
  Slack (ns):                  1.446
  Arrival (ns):                5.731
  Required (ns):               4.285
  Hold (ns):                   1.336

Path 2
  From:                        AHB_timer_0/DataOut_int[0]:CLK
  To:                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHRDATA[0]
  Delay (ns):                  1.475
  Slack (ns):                  1.556
  Arrival (ns):                5.840
  Required (ns):               4.284
  Hold (ns):                   1.335

Path 3
  From:                        AHB_timer_0/DataOut_int[10]:CLK
  To:                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHRDATA[10]
  Delay (ns):                  1.512
  Slack (ns):                  1.604
  Arrival (ns):                5.889
  Required (ns):               4.285
  Hold (ns):                   1.336

Path 4
  From:                        AHB_timer_0/DataOut_int[11]:CLK
  To:                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHRDATA[11]
  Delay (ns):                  1.546
  Slack (ns):                  1.627
  Arrival (ns):                5.911
  Required (ns):               4.284
  Hold (ns):                   1.335

Path 5
  From:                        AHB_timer_0/DataOut_int[21]:CLK
  To:                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHRDATA[21]
  Delay (ns):                  1.581
  Slack (ns):                  1.672
  Arrival (ns):                5.948
  Required (ns):               4.276
  Hold (ns):                   1.327


Expanded Path 1
  From: AHB_timer_0/DataOut_int[15]:CLK
  To: _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHRDATA[15]
  data arrival time                              5.731
  data required time                         -   4.285
  slack                                          1.446
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.326          net: mss_highspeed_timerv2_0_FAB_CLK
  4.361                        AHB_timer_0/DataOut_int[15]:CLK (r)
               +     0.249          cell: ADLIB:DFN1C0
  4.610                        AHB_timer_0/DataOut_int[15]:Q (r)
               +     0.150          net: _CoreAHBLite_0_AHBmslave5_HRDATA_[15]_
  4.760                        CoreAHBLite_0/matrix2x16/masterstage_0/HRDATA[15]:A (r)
               +     0.221          cell: ADLIB:NOR2A
  4.981                        CoreAHBLite_0/matrix2x16/masterstage_0/HRDATA[15]:Y (r)
               +     0.450          net: _mss_highspeed_timerv2_0_MSS_MASTER_AHB_LITE_HRDATA_[15]_
  5.431                        _Timerv2_/MSS_ADLIB_INST/U_41:PIN6 (r)
               +     0.090          cell: ADLIB:MSS_IF
  5.521                        _Timerv2_/MSS_ADLIB_INST/U_41:PIN6INT (r)
               +     0.210          net: _Timerv2_/MSS_ADLIB_INST/MSSHRDATA[15]INT_NET
  5.731                        _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHRDATA[15] (r)
                                    
  5.731                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     2.949          Clock generation
  2.949
               +     1.336          Library hold time: ADLIB:MSS_AHB_IP
  4.285                        _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHRDATA[15]
                                    
  4.285                        data required time


END SET mss_ccc_gla1 to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

Path 1
  From:                        Pulse_in
  To:                          Test_port[0]
  Delay (ns):                  2.549
  Slack (ns):
  Arrival (ns):                2.549
  Required (ns):


Expanded Path 1
  From: Pulse_in
  To: Test_port[0]
  data arrival time                              2.549
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        Pulse_in (r)
               +     0.000          net: Pulse_in
  0.000                        Pulse_in_pad/U0/U0:PAD (r)
               +     0.391          cell: ADLIB:IOPAD_IN
  0.391                        Pulse_in_pad/U0/U0:Y (r)
               +     0.000          net: Pulse_in_pad/U0/NET1
  0.391                        Pulse_in_pad/U0/U1:YIN (r)
               +     0.018          cell: ADLIB:IOIN_IB
  0.409                        Pulse_in_pad/U0/U1:Y (r)
               +     0.764          net: Pulse_in_c_c
  1.173                        Test_port_pad[0]/U0/U1:D (r)
               +     0.257          cell: ADLIB:IOTRI_OB_EB
  1.430                        Test_port_pad[0]/U0/U1:DOUT (r)
               +     0.000          net: Test_port_pad[0]/U0/NET1
  1.430                        Test_port_pad[0]/U0/U0:D (r)
               +     1.119          cell: ADLIB:IOPAD_TRI
  2.549                        Test_port_pad[0]/U0/U0:PAD (r)
               +     0.000          net: Test_port[0]
  2.549                        Test_port[0] (r)
                                    
  2.549                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          Pulse_in (r)
                                    
  N/C                          Test_port[0] (r)
                                    
  N/C                          data required time


END SET Input to Output

----------------------------------------------------

Path set User Sets

