Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Mon Dec 12 14:41:18 2011


Design: top_timer
Family: SmartFusion
Die: A2F500M3G
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: STD
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               AHB_timer_0/TIMINT_int_hclk:Q
Period (ns):                0.860
Frequency (MHz):            1162.791
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                15.526
Frequency (MHz):            64.408
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      8.262
Max Clock-To-Out (ns):      15.072

Clock Domain:               mss_ccc_gla0
Period (ns):                12.500
Frequency (MHz):            80.000
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        -5.206
External Hold (ns):         4.012
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_glc
Period (ns):                11.294
Frequency (MHz):            88.543
Required Period (ns):       8.333
Required Frequency (MHz):   120.005
External Setup (ns):        8.824
External Hold (ns):         -0.959
Min Clock-To-Out (ns):      5.301
Max Clock-To-Out (ns):      13.968

Clock Domain:               \\Timerv2\\/MSS_CCC_0/I_RCOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             2.549
Max Delay (ns):             6.189

END SUMMARY
-----------------------------------------------------

Clock Domain AHB_timer_0/TIMINT_int_hclk:Q

Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin AHB_timer_0/TIMINT_pending_int:CLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/CLDATASELInt[7]/U1:CLK
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHSIZE[0]/U1:D
  Delay (ns):                  15.012
  Slack (ns):                  -3.026
  Arrival (ns):                20.951
  Required (ns):               17.925
  Setup (ns):                  0.522
  Minimum Period (ns):         15.526

Path 2
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/CLDATASELInt[6]/U1:CLK
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHSIZE[0]/U1:D
  Delay (ns):                  14.869
  Slack (ns):                  -2.883
  Arrival (ns):                20.808
  Required (ns):               17.925
  Setup (ns):                  0.522
  Minimum Period (ns):         15.383

Path 3
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/CLDATASELInt[7]/U1:CLK
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[2]/U1:D
  Delay (ns):                  14.483
  Slack (ns):                  -2.538
  Arrival (ns):                20.422
  Required (ns):               17.884
  Setup (ns):                  0.522
  Minimum Period (ns):         15.038

Path 4
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/CLDATASELInt[6]/U1:CLK
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[2]/U1:D
  Delay (ns):                  14.340
  Slack (ns):                  -2.395
  Arrival (ns):                20.279
  Required (ns):               17.884
  Setup (ns):                  0.522
  Minimum Period (ns):         14.895

Path 5
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/CLDATASELInt[7]/U1:CLK
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/CLDATASELInt[8]/U1:D
  Delay (ns):                  14.212
  Slack (ns):                  -2.246
  Arrival (ns):                20.151
  Required (ns):               17.905
  Setup (ns):                  0.522
  Minimum Period (ns):         14.746


Expanded Path 1
  From: CoreAHBLite_0/matrix2x16/masterstage_0/CLDATASELInt[7]/U1:CLK
  To: CoreAHBLite_0/matrix2x16/masterstage_0/regHSIZE[0]/U1:D
  data required time                             17.925
  data arrival time                          -   20.951
  slack                                          -3.026
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.690          net: mss_highspeed_timerv2_0_FAB_CLK
  5.939                        CoreAHBLite_0/matrix2x16/masterstage_0/CLDATASELInt[7]/U1:CLK (r)
               +     0.671          cell: ADLIB:DFN1C0
  6.610                        CoreAHBLite_0/matrix2x16/masterstage_0/CLDATASELInt[7]/U1:Q (f)
               +     0.351          net: CoreAHBLite_0/matrix2x16/masterstage_0/CLDATASELInt[7]
  6.961                        CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_o2_0_14_3:B (f)
               +     0.588          cell: ADLIB:NOR2
  7.549                        CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_o2_0_14_3:Y (r)
               +     0.306          net: CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_o2_0_14_3
  7.855                        CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_o2_0_14_9:A (r)
               +     0.604          cell: ADLIB:NOR3A
  8.459                        CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_o2_0_14_9:Y (r)
               +     1.083          net: CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_o2_0_14_9
  9.542                        CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_o2_0_14_12:C (r)
               +     0.606          cell: ADLIB:NOR3C
  10.148                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_o2_0_14_12:Y (r)
               +     0.306          net: CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_o2_0_14_12
  10.454                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_o2_0_14:C (r)
               +     0.606          cell: ADLIB:NOR3C
  11.060                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_o2_0_14:Y (r)
               +     1.463          net: CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_o2_0_14_i_0
  12.523                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_m_0_a2_2_m9_0_o5:A (r)
               +     0.478          cell: ADLIB:OR3C
  13.001                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_m_0_a2_2_m9_0_o5:Y (f)
               +     0.306          net: CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_m_0_a2_2_N_10
  13.307                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_m_0_a2_2_m9_0:B (f)
               +     0.554          cell: ADLIB:AO1B
  13.861                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_m_0_a2_2_m9_0:Y (f)
               +     0.309          net: CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_m_0_a2_2_m9_0
  14.170                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_m_0_a2_1:S (f)
               +     0.473          cell: ADLIB:MX2
  14.643                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_m_0_a2_1:Y (f)
               +     0.367          net: CoreAHBLite_0_matrix2x16_masterstage_0_N_1064_2
  15.010                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState_RNI28NOO:A (f)
               +     0.848          cell: ADLIB:OA1C
  15.858                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState_RNI28NOO:Y (r)
               +     1.236          net: CoreAHBLite_0_matrix2x16_masterstage_0_HREADY_M_iv
  17.094                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState_RNIOU4UT:B (r)
               +     0.568          cell: ADLIB:NOR3C
  17.662                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState_RNIOU4UT:Y (r)
               +     2.654          net: CoreAHBLite_0/matrix2x16/masterstage_0/masterAddrClockEnable
  20.316                       CoreAHBLite_0/matrix2x16/masterstage_0/regHSIZE[0]/U0:S (r)
               +     0.339          cell: ADLIB:MX2
  20.655                       CoreAHBLite_0/matrix2x16/masterstage_0/regHSIZE[0]/U0:Y (f)
               +     0.296          net: CoreAHBLite_0/matrix2x16/masterstage_0/regHSIZE[0]/Y
  20.951                       CoreAHBLite_0/matrix2x16/masterstage_0/regHSIZE[0]/U1:D (f)
                                    
  20.951                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_gla1
               +     0.000          Clock source
  12.500                       \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  17.749
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  17.749                       \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  17.749                       \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.698          net: mss_highspeed_timerv2_0_FAB_CLK
  18.447                       CoreAHBLite_0/matrix2x16/masterstage_0/regHSIZE[0]/U1:CLK (r)
               -     0.522          Library setup time: ADLIB:DFN1C0
  17.925                       CoreAHBLite_0/matrix2x16/masterstage_0/regHSIZE[0]/U1:D
                                    
  17.925                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        AHB_timer_0/TIMINT_int_hclk:CLK
  To:                          TIMINT
  Delay (ns):                  9.191
  Slack (ns):
  Arrival (ns):                15.072
  Required (ns):
  Clock to Out (ns):           15.072


Expanded Path 1
  From: AHB_timer_0/TIMINT_int_hclk:CLK
  To: TIMINT
  data required time                             N/C
  data arrival time                          -   15.072
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.632          net: mss_highspeed_timerv2_0_FAB_CLK
  5.881                        AHB_timer_0/TIMINT_int_hclk:CLK (r)
               +     0.671          cell: ADLIB:DFN1C0
  6.552                        AHB_timer_0/TIMINT_int_hclk:Q (f)
               +     3.102          net: AHB_timer_0/TIMINT_int_hclk_i
  9.654                        AHB_timer_0/TIMINT_int_hclk_RNI4603/U_CLKSRC:A (f)
               +     0.719          cell: ADLIB:CLKSRC
  10.373                       AHB_timer_0/TIMINT_int_hclk_RNI4603/U_CLKSRC:Y (f)
               +     0.730          net: TIMINT_c
  11.103                       TIMINT_pad/U0/U1:D (f)
               +     0.600          cell: ADLIB:IOTRI_OB_EB
  11.703                       TIMINT_pad/U0/U1:DOUT (f)
               +     0.000          net: TIMINT_pad/U0/NET1
  11.703                       TIMINT_pad/U0/U0:D (f)
               +     3.369          cell: ADLIB:IOPAD_TRI
  15.072                       TIMINT_pad/U0/U0:PAD (f)
               +     0.000          net: TIMINT
  15.072                       TIMINT (f)
                                    
  15.072                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  N/C
                                    
  N/C                          TIMINT (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla0 to mss_ccc_gla1

Path 1
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          AHB_timer_0/HADDR_int[1]/U1:CLR
  Delay (ns):                  8.414
  Slack (ns):                  5.717
  Arrival (ns):                12.418
  Required (ns):               18.135
  Setup (ns):

Path 2
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          AHB_timer_0/HADDR_int[2]/U1:CLR
  Delay (ns):                  8.414
  Slack (ns):                  5.733
  Arrival (ns):                12.418
  Required (ns):               18.151
  Setup (ns):

Path 3
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          AHB_timer_0/HADDR_int[0]/U1:CLR
  Delay (ns):                  8.414
  Slack (ns):                  5.733
  Arrival (ns):                12.418
  Required (ns):               18.151
  Setup (ns):

Path 4
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          AHB_timer_0/HADDR_int[3]/U1:CLR
  Delay (ns):                  8.414
  Slack (ns):                  5.733
  Arrival (ns):                12.418
  Required (ns):               18.151
  Setup (ns):

Path 5
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          AHB_timer_0/DataOut_int[22]:CLR
  Delay (ns):                  8.376
  Slack (ns):                  5.755
  Arrival (ns):                12.380
  Required (ns):               18.135
  Setup (ns):


Expanded Path 1
  From: _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To: AHB_timer_0/HADDR_int[1]/U1:CLR
  data required time                             18.135
  data arrival time                          -   12.418
  slack                                          5.717
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  3.545
               +     0.459          net: _Timerv2_/MSS_ADLIB_INST_FCLK
  4.004                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     3.331          cell: ADLIB:MSS_AHB_IP
  7.335                        _Timerv2_/MSS_ADLIB_INST/U_CORE:M2FRESETn (r)
               +     0.121          net: _Timerv2_/MSS_ADLIB_INST/M2FRESETnINT_NET
  7.456                        _Timerv2_/MSS_ADLIB_INST/U_46:PIN2INT (r)
               +     0.095          cell: ADLIB:MSS_IF
  7.551                        _Timerv2_/MSS_ADLIB_INST/U_46:PIN2 (r)
               +     4.867          net: mss_highspeed_timerv2_0_M2F_RESET_N
  12.418                       AHB_timer_0/HADDR_int[1]/U1:CLR (r)
                                    
  12.418                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_gla1
               +     0.000          Clock source
  12.500                       \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  17.749
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  17.749                       \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  17.749                       \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.657          net: mss_highspeed_timerv2_0_FAB_CLK
  18.406                       AHB_timer_0/HADDR_int[1]/U1:CLK (r)
               -     0.271          Library recovery time: ADLIB:DFN1C0
  18.135                       AHB_timer_0/HADDR_int[1]/U1:CLR
                                    
  18.135                       data required time


END SET mss_ccc_gla0 to mss_ccc_gla1

----------------------------------------------------

SET mss_ccc_glc to mss_ccc_gla1

Path 1
  From:                        AHB_timer_0/Count[1]/U1:CLK
  To:                          AHB_timer_0/TIMINT_int_hclk:D
  Delay (ns):                  7.953
  Slack (ns):                  -0.332
  Arrival (ns):                9.890
  Required (ns):               9.558
  Setup (ns):                  0.490

Path 2
  From:                        AHB_timer_0/Count[0]/U1:CLK
  To:                          AHB_timer_0/TIMINT_int_hclk:D
  Delay (ns):                  7.654
  Slack (ns):                  0.004
  Arrival (ns):                9.554
  Required (ns):               9.558
  Setup (ns):                  0.490

Path 3
  From:                        AHB_timer_0/Count[2]/U1:CLK
  To:                          AHB_timer_0/TIMINT_int_hclk:D
  Delay (ns):                  7.261
  Slack (ns):                  0.372
  Arrival (ns):                9.186
  Required (ns):               9.558
  Setup (ns):                  0.490

Path 4
  From:                        AHB_timer_0/count_zero_blk_instance/count23_3_zero:CLK
  To:                          AHB_timer_0/TIMINT_int_hclk:D
  Delay (ns):                  6.177
  Slack (ns):                  1.431
  Arrival (ns):                8.095
  Required (ns):               9.526
  Setup (ns):                  0.522

Path 5
  From:                        AHB_timer_0/IntEnable/U1:CLK
  To:                          AHB_timer_0/TIMINT_int_hclk:D
  Delay (ns):                  4.781
  Slack (ns):                  2.829
  Arrival (ns):                6.697
  Required (ns):               9.526
  Setup (ns):                  0.522


Expanded Path 1
  From: AHB_timer_0/Count[1]/U1:CLK
  To: AHB_timer_0/TIMINT_int_hclk:D
  data required time                             9.558
  data arrival time                          -   9.890
  slack                                          -0.332
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     1.246          Clock generation
  1.246
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  1.246                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  1.246                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.691          net: Timerv2_GLC
  1.937                        AHB_timer_0/Count[1]/U1:CLK (r)
               +     0.671          cell: ADLIB:DFN1P0
  2.608                        AHB_timer_0/Count[1]/U1:Q (f)
               +     1.967          net: AHB_timer_0/Count[1]
  4.575                        AHB_timer_0/count_zero_blk_instance/NOR3_0:B (f)
               +     0.568          cell: ADLIB:NOR3
  5.143                        AHB_timer_0/count_zero_blk_instance/NOR3_0:Y (r)
               +     0.369          net: AHB_timer_0/count_zero_blk_instance/count2_0_zero
  5.512                        AHB_timer_0/count_zero_blk_instance/count23_3_zero_RNI8HR1:B (r)
               +     0.470          cell: ADLIB:NOR2B
  5.982                        AHB_timer_0/count_zero_blk_instance/count23_3_zero_RNI8HR1:Y (r)
               +     1.697          net: Test_port_c[3]
  7.679                        AHB_timer_0/IntEnable_RNICLK5:A (r)
               +     0.370          cell: ADLIB:NOR2B
  8.049                        AHB_timer_0/IntEnable_RNICLK5:Y (r)
               +     1.056          net: AHB_timer_0/un1_timint_pulse_int_0
  9.105                        AHB_timer_0/TIMINT_int_hclk_RNO:A (r)
               +     0.479          cell: ADLIB:XOR3
  9.584                        AHB_timer_0/TIMINT_int_hclk_RNO:Y (r)
               +     0.306          net: AHB_timer_0/TIMINT_int_0
  9.890                        AHB_timer_0/TIMINT_int_hclk:D (r)
                                    
  9.890                        data arrival time
  ________________________________________________________
  Data required time calculation
  4.167                        mss_ccc_gla1
               +     0.000          Clock source
  4.167                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  9.416
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  9.416                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  9.416                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.632          net: mss_highspeed_timerv2_0_FAB_CLK
  10.048                       AHB_timer_0/TIMINT_int_hclk:CLK (r)
               -     0.490          Library setup time: ADLIB:DFN1C0
  9.558                        AHB_timer_0/TIMINT_int_hclk:D
                                    
  9.558                        data required time


END SET mss_ccc_glc to mss_ccc_gla1

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_gla1

Path 1
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHSIZE[0]/U1:D
  Delay (ns):                  16.007
  Slack (ns):                  -2.086
  Arrival (ns):                20.011
  Required (ns):               17.925
  Setup (ns):                  0.522

Path 2
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[2]/U1:D
  Delay (ns):                  15.478
  Slack (ns):                  -1.598
  Arrival (ns):                19.482
  Required (ns):               17.884
  Setup (ns):                  0.522

Path 3
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[14]/U1:D
  Delay (ns):                  15.155
  Slack (ns):                  -1.233
  Arrival (ns):                19.159
  Required (ns):               17.926
  Setup (ns):                  0.522

Path 4
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[17]/U1:D
  Delay (ns):                  15.118
  Slack (ns):                  -1.196
  Arrival (ns):                19.122
  Required (ns):               17.926
  Setup (ns):                  0.522

Path 5
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[0]/U1:D
  Delay (ns):                  14.962
  Slack (ns):                  -1.067
  Arrival (ns):                18.966
  Required (ns):               17.899
  Setup (ns):                  0.522


Expanded Path 1
  From: _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To: CoreAHBLite_0/matrix2x16/masterstage_0/regHSIZE[0]/U1:D
  data required time                             17.925
  data arrival time                          -   20.011
  slack                                          -2.086
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.004          Clock generation
  4.004
               +     2.820          cell: ADLIB:MSS_AHB_IP
  6.824                        _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHLOCK (f)
               +     0.157          net: _Timerv2_/MSS_ADLIB_INST/MSSHLOCKINT_NET
  6.981                        _Timerv2_/MSS_ADLIB_INST/U_59:PIN1INT (f)
               +     0.088          cell: ADLIB:MSS_IF
  7.069                        _Timerv2_/MSS_ADLIB_INST/U_59:PIN1 (f)
               +     1.401          net: mss_highspeed_timerv2_0_MSS_MASTER_AHB_LITE_HLOCK
  8.470                        CoreAHBLite_0/matrix2x16/masterstage_0/regHMASTLOCK_RNIHBIA:A (f)
               +     0.527          cell: ADLIB:MX2
  8.997                        CoreAHBLite_0/matrix2x16/masterstage_0/regHMASTLOCK_RNIHBIA:Y (f)
               +     1.278          net: CoreAHBLite_0/matrix2x16/M0GATEDHMASTLOCK
  10.275                       CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState_RNI063F[3]:B (f)
               +     0.571          cell: ADLIB:OR2B
  10.846                       CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState_RNI063F[3]:Y (r)
               +     0.930          net: CoreAHBLite_0/matrix2x16/N_93
  11.776                       CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState_RNI03841[3]:A (r)
               +     0.331          cell: ADLIB:NOR2
  12.107                       CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState_RNI03841[3]:Y (f)
               +     0.336          net: CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState_ns_i_o5_6_m1_e_0
  12.443                       CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState_RNIHR282[3]:A (f)
               +     0.424          cell: ADLIB:OR2A
  12.867                       CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState_RNIHR282[3]:Y (r)
               +     0.403          net: CoreAHBLite_0/matrix2x16/arbRegSMCurrentState_RNIHR282[3]
  13.270                       CoreAHBLite_0/matrix2x16/masterstage_0/masterAddrClockEnable_0tt_m3_0_a3:A (r)
               +     0.538          cell: ADLIB:NOR2A
  13.808                       CoreAHBLite_0/matrix2x16/masterstage_0/masterAddrClockEnable_0tt_m3_0_a3:Y (r)
               +     0.296          net: CoreAHBLite_0/matrix2x16/masterstage_0/masterAddrClockEnable_0tt_N_4
  14.104                       CoreAHBLite_0/matrix2x16/masterstage_0/masterRegAddrSel_RNI2T835:B (r)
               +     0.829          cell: ADLIB:OA1A
  14.933                       CoreAHBLite_0/matrix2x16/masterstage_0/masterRegAddrSel_RNI2T835:Y (r)
               +     1.183          net: CoreAHBLite_0/matrix2x16/masterstage_0/masterAddrClockEnable_0_m2_e_3
  16.116                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState_RNIOU4UT:C (r)
               +     0.606          cell: ADLIB:NOR3C
  16.722                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState_RNIOU4UT:Y (r)
               +     2.654          net: CoreAHBLite_0/matrix2x16/masterstage_0/masterAddrClockEnable
  19.376                       CoreAHBLite_0/matrix2x16/masterstage_0/regHSIZE[0]/U0:S (r)
               +     0.339          cell: ADLIB:MX2
  19.715                       CoreAHBLite_0/matrix2x16/masterstage_0/regHSIZE[0]/U0:Y (f)
               +     0.296          net: CoreAHBLite_0/matrix2x16/masterstage_0/regHSIZE[0]/Y
  20.011                       CoreAHBLite_0/matrix2x16/masterstage_0/regHSIZE[0]/U1:D (f)
                                    
  20.011                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_gla1
               +     0.000          Clock source
  12.500                       \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  17.749
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  17.749                       \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  17.749                       \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.698          net: mss_highspeed_timerv2_0_FAB_CLK
  18.447                       CoreAHBLite_0/matrix2x16/masterstage_0/regHSIZE[0]/U1:CLK (r)
               -     0.522          Library setup time: ADLIB:DFN1C0
  17.925                       CoreAHBLite_0/matrix2x16/masterstage_0/regHSIZE[0]/U1:D
                                    
  17.925                       data required time


END SET mss_fabric_interface_clock to mss_ccc_gla1

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.937
  Slack (ns):
  Arrival (ns):                0.937
  Required (ns):
  Setup (ns):                  -2.139
  External Setup (ns):         -5.206


Expanded Path 1
  From: MSS_RESET_N
  To: _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.937
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        \\Timerv2\\/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.937          cell: ADLIB:IOPAD_IN
  0.937                        \\Timerv2\\/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: _Timerv2_/MSS_RESET_0_MSS_RESET_N_Y
  0.937                        _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.937                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  N/C
               +     0.459          net: _Timerv2_/MSS_ADLIB_INST_FCLK
  N/C                          _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -2.139          Library setup time: ADLIB:MSS_AHB_IP
  N/C                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glc

SET Register to Register

Path 1
  From:                        AHB_timer_0/prescl_cnt[0]:CLK
  To:                          AHB_timer_0/new_count_pulse:D
  Delay (ns):                  10.781
  Slack (ns):                  -2.961
  Arrival (ns):                12.656
  Required (ns):               9.695
  Setup (ns):                  0.522
  Minimum Period (ns):         11.294

Path 2
  From:                        AHB_timer_0/prescl_cnt[1]:CLK
  To:                          AHB_timer_0/new_count_pulse:D
  Delay (ns):                  10.608
  Slack (ns):                  -2.788
  Arrival (ns):                12.483
  Required (ns):               9.695
  Setup (ns):                  0.522
  Minimum Period (ns):         11.121

Path 3
  From:                        AHB_timer_0/Count[1]/U1:CLK
  To:                          AHB_timer_0/Count[17]/U1:D
  Delay (ns):                  9.466
  Slack (ns):                  -1.637
  Arrival (ns):                11.403
  Required (ns):               9.766
  Setup (ns):                  0.522
  Minimum Period (ns):         9.970

Path 4
  From:                        AHB_timer_0/Count[8]/U1:CLK
  To:                          AHB_timer_0/Count[17]/U1:D
  Delay (ns):                  9.408
  Slack (ns):                  -1.588
  Arrival (ns):                11.354
  Required (ns):               9.766
  Setup (ns):                  0.522
  Minimum Period (ns):         9.921

Path 5
  From:                        AHB_timer_0/Count[1]/U1:CLK
  To:                          AHB_timer_0/Count[14]/U1:D
  Delay (ns):                  9.297
  Slack (ns):                  -1.516
  Arrival (ns):                11.234
  Required (ns):               9.718
  Setup (ns):                  0.522
  Minimum Period (ns):         9.849


Expanded Path 1
  From: AHB_timer_0/prescl_cnt[0]:CLK
  To: AHB_timer_0/new_count_pulse:D
  data required time                             9.695
  data arrival time                          -   12.656
  slack                                          -2.961
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     1.246          Clock generation
  1.246
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  1.246                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  1.246                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.629          net: Timerv2_GLC
  1.875                        AHB_timer_0/prescl_cnt[0]:CLK (r)
               +     0.528          cell: ADLIB:DFN1C0
  2.403                        AHB_timer_0/prescl_cnt[0]:Q (r)
               +     0.503          net: AHB_timer_0/prescl_cnt[0]
  2.906                        AHB_timer_0/prescl_cnt_RNI3BT2[1]:B (r)
               +     0.470          cell: ADLIB:NOR2B
  3.376                        AHB_timer_0/prescl_cnt_RNI3BT2[1]:Y (r)
               +     1.056          net: AHB_timer_0/prescl_cnt_c1
  4.432                        AHB_timer_0/prescl_cnt_RNIM0C4[2]:A (r)
               +     0.370          cell: ADLIB:OR2B
  4.802                        AHB_timer_0/prescl_cnt_RNIM0C4[2]:Y (f)
               +     0.351          net: AHB_timer_0/prescl_cnt_c2
  5.153                        AHB_timer_0/prescl_cnt_RNIAMQ5[3]:B (f)
               +     0.588          cell: ADLIB:OR2A
  5.741                        AHB_timer_0/prescl_cnt_RNIAMQ5[3]:Y (f)
               +     1.815          net: AHB_timer_0/prescl_cnt_c3
  7.556                        AHB_timer_0/prescl_cnt_RNIL1O8[5]:B (f)
               +     0.592          cell: ADLIB:OR2A
  8.148                        AHB_timer_0/prescl_cnt_RNIL1O8[5]:Y (f)
               +     1.127          net: AHB_timer_0/un27_prescl_cnt
  9.275                        AHB_timer_0/new_count_pulse_RNO_3:C (f)
               +     0.620          cell: ADLIB:OR3C
  9.895                        AHB_timer_0/new_count_pulse_RNO_3:Y (r)
               +     0.296          net: AHB_timer_0/Count_Pulse_1_sqmuxa_5_3
  10.191                       AHB_timer_0/new_count_pulse_RNO_0:B (r)
               +     0.652          cell: ADLIB:OR3C
  10.843                       AHB_timer_0/new_count_pulse_RNO_0:Y (f)
               +     0.306          net: AHB_timer_0/un1_TimerPre_1
  11.149                       AHB_timer_0/new_count_pulse_RNO:A (f)
               +     0.563          cell: ADLIB:MX2C
  11.712                       AHB_timer_0/new_count_pulse_RNO:Y (r)
               +     0.944          net: AHB_timer_0/Count_Pulse
  12.656                       AHB_timer_0/new_count_pulse:D (r)
                                    
  12.656                       data arrival time
  ________________________________________________________
  Data required time calculation
  8.333                        mss_ccc_glc
               +     0.000          Clock source
  8.333                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     1.246          Clock generation
  9.579
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  9.579                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  9.579                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.638          net: Timerv2_GLC
  10.217                       AHB_timer_0/new_count_pulse:CLK (r)
               -     0.522          Library setup time: ADLIB:DFN1C0
  9.695                        AHB_timer_0/new_count_pulse:D
                                    
  9.695                        data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        Pulse_in
  To:                          AHB_timer_0/Count[14]/U1:D
  Delay (ns):                  10.209
  Slack (ns):
  Arrival (ns):                10.209
  Required (ns):
  Setup (ns):                  0.522
  External Setup (ns):         8.824

Path 2
  From:                        Pulse_in
  To:                          AHB_timer_0/Count[2]/U1:D
  Delay (ns):                  10.156
  Slack (ns):
  Arrival (ns):                10.156
  Required (ns):
  Setup (ns):                  0.522
  External Setup (ns):         8.753

Path 3
  From:                        Pulse_in
  To:                          AHB_timer_0/Count[12]/U1:D
  Delay (ns):                  9.935
  Slack (ns):
  Arrival (ns):                9.935
  Required (ns):
  Setup (ns):                  0.522
  External Setup (ns):         8.539

Path 4
  From:                        Pulse_in
  To:                          AHB_timer_0/Count[16]/U1:D
  Delay (ns):                  9.906
  Slack (ns):
  Arrival (ns):                9.906
  Required (ns):
  Setup (ns):                  0.522
  External Setup (ns):         8.512

Path 5
  From:                        Pulse_in
  To:                          AHB_timer_0/Count[18]/U1:D
  Delay (ns):                  9.790
  Slack (ns):
  Arrival (ns):                9.790
  Required (ns):
  Setup (ns):                  0.522
  External Setup (ns):         8.333


Expanded Path 1
  From: Pulse_in
  To: AHB_timer_0/Count[14]/U1:D
  data required time                             N/C
  data arrival time                          -   10.209
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        Pulse_in (f)
               +     0.000          net: Pulse_in
  0.000                        Pulse_in_pad/U0/U0:PAD (f)
               +     0.634          cell: ADLIB:IOPAD_IN
  0.634                        Pulse_in_pad/U0/U0:Y (f)
               +     0.000          net: Pulse_in_pad/U0/NET1
  0.634                        Pulse_in_pad/U0/U1:YIN (f)
               +     0.036          cell: ADLIB:IOIN_IB
  0.670                        Pulse_in_pad/U0/U1:Y (f)
               +     3.953          net: Pulse_in_c_c
  4.623                        AHB_timer_0/new_count_pulse_RNIJB8H:C (f)
               +     0.443          cell: ADLIB:AOI1B
  5.066                        AHB_timer_0/new_count_pulse_RNIJB8H:Y (f)
               +     1.637          net: AHB_timer_0/Count_0_sqmuxa_a1_0
  6.703                        AHB_timer_0/LoadEnReg_RNI19HT:B (f)
               +     0.543          cell: ADLIB:AO1C
  7.246                        AHB_timer_0/LoadEnReg_RNI19HT:Y (f)
               +     2.179          net: AHB_timer_0/Count_0_sqmuxa
  9.425                        AHB_timer_0/Count[14]/U0:S (f)
               +     0.473          cell: ADLIB:MX2
  9.898                        AHB_timer_0/Count[14]/U0:Y (f)
               +     0.311          net: AHB_timer_0/Count[14]/Y
  10.209                       AHB_timer_0/Count[14]/U1:D (f)
                                    
  10.209                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glc
               +     0.000          Clock source
  N/C                          \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     1.246          Clock generation
  N/C
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  N/C                          \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.661          net: Timerv2_GLC
  N/C                          AHB_timer_0/Count[14]/U1:CLK (r)
               -     0.522          Library setup time: ADLIB:DFN1P0
  N/C                          AHB_timer_0/Count[14]/U1:D


END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        AHB_timer_0/Count[1]/U1:CLK
  To:                          Test_port[3]
  Delay (ns):                  12.031
  Slack (ns):
  Arrival (ns):                13.968
  Required (ns):
  Clock to Out (ns):           13.968

Path 2
  From:                        AHB_timer_0/Count[0]/U1:CLK
  To:                          Test_port[3]
  Delay (ns):                  11.734
  Slack (ns):
  Arrival (ns):                13.634
  Required (ns):
  Clock to Out (ns):           13.634

Path 3
  From:                        AHB_timer_0/Count[2]/U1:CLK
  To:                          Test_port[3]
  Delay (ns):                  11.431
  Slack (ns):
  Arrival (ns):                13.356
  Required (ns):
  Clock to Out (ns):           13.356

Path 4
  From:                        AHB_timer_0/TimerEn/U1:CLK
  To:                          Test_port[1]
  Delay (ns):                  10.859
  Slack (ns):
  Arrival (ns):                12.823
  Required (ns):
  Clock to Out (ns):           12.823

Path 5
  From:                        AHB_timer_0/count_zero_blk_instance/count23_3_zero:CLK
  To:                          Test_port[3]
  Delay (ns):                  10.381
  Slack (ns):
  Arrival (ns):                12.299
  Required (ns):
  Clock to Out (ns):           12.299


Expanded Path 1
  From: AHB_timer_0/Count[1]/U1:CLK
  To: Test_port[3]
  data required time                             N/C
  data arrival time                          -   13.968
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     1.246          Clock generation
  1.246
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  1.246                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  1.246                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.691          net: Timerv2_GLC
  1.937                        AHB_timer_0/Count[1]/U1:CLK (r)
               +     0.528          cell: ADLIB:DFN1P0
  2.465                        AHB_timer_0/Count[1]/U1:Q (r)
               +     1.818          net: AHB_timer_0/Count[1]
  4.283                        AHB_timer_0/count_zero_blk_instance/NOR3_0:B (r)
               +     0.552          cell: ADLIB:NOR3
  4.835                        AHB_timer_0/count_zero_blk_instance/NOR3_0:Y (f)
               +     0.351          net: AHB_timer_0/count_zero_blk_instance/count2_0_zero
  5.186                        AHB_timer_0/count_zero_blk_instance/count23_3_zero_RNI8HR1:B (f)
               +     0.571          cell: ADLIB:NOR2B
  5.757                        AHB_timer_0/count_zero_blk_instance/count23_3_zero_RNI8HR1:Y (f)
               +     4.430          net: Test_port_c[3]
  10.187                       Test_port_pad[3]/U0/U1:D (f)
               +     0.530          cell: ADLIB:IOTRI_OB_EB
  10.717                       Test_port_pad[3]/U0/U1:DOUT (f)
               +     0.000          net: Test_port_pad[3]/U0/NET1
  10.717                       Test_port_pad[3]/U0/U0:D (f)
               +     3.251          cell: ADLIB:IOPAD_TRI
  13.968                       Test_port_pad[3]/U0/U0:PAD (f)
               +     0.000          net: Test_port[3]
  13.968                       Test_port[3] (f)
                                    
  13.968                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glc
               +     0.000          Clock source
  N/C                          \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     1.246          Clock generation
  N/C
                                    
  N/C                          Test_port[3] (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_ccc_glc

Path 1
  From:                        AHB_timer_0/HADDR_int[0]/U1:CLK
  To:                          AHB_timer_0/DataOut[1]/U1:D
  Delay (ns):                  9.246
  Slack (ns):                  -5.399
  Arrival (ns):                15.168
  Required (ns):               9.769
  Setup (ns):                  0.490

Path 2
  From:                        AHB_timer_0/HADDR_int[0]/U1:CLK
  To:                          AHB_timer_0/Load[9]/U1:D
  Delay (ns):                  9.172
  Slack (ns):                  -5.340
  Arrival (ns):                15.094
  Required (ns):               9.754
  Setup (ns):                  0.490

Path 3
  From:                        AHB_timer_0/HADDR_int[0]/U1:CLK
  To:                          AHB_timer_0/DataOut[0]/U1:D
  Delay (ns):                  9.152
  Slack (ns):                  -5.294
  Arrival (ns):                15.074
  Required (ns):               9.780
  Setup (ns):                  0.490

Path 4
  From:                        AHB_timer_0/HADDR_int[0]/U1:CLK
  To:                          AHB_timer_0/Load[20]/U1:D
  Delay (ns):                  9.151
  Slack (ns):                  -5.284
  Arrival (ns):                15.073
  Required (ns):               9.789
  Setup (ns):                  0.490

Path 5
  From:                        AHB_timer_0/HADDR_int[1]/U1:CLK
  To:                          AHB_timer_0/DataOut[1]/U1:D
  Delay (ns):                  9.100
  Slack (ns):                  -5.237
  Arrival (ns):                15.006
  Required (ns):               9.769
  Setup (ns):                  0.490


Expanded Path 1
  From: AHB_timer_0/HADDR_int[0]/U1:CLK
  To: AHB_timer_0/DataOut[1]/U1:D
  data required time                             9.769
  data arrival time                          -   15.168
  slack                                          -5.399
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.673          net: mss_highspeed_timerv2_0_FAB_CLK
  5.922                        AHB_timer_0/HADDR_int[0]/U1:CLK (r)
               +     0.671          cell: ADLIB:DFN1C0
  6.593                        AHB_timer_0/HADDR_int[0]/U1:Q (f)
               +     0.351          net: AHB_timer_0/HADDR_int[0]
  6.944                        AHB_timer_0/HADDR_int_RNIFLSD[0]:B (f)
               +     0.588          cell: ADLIB:NOR2
  7.532                        AHB_timer_0/HADDR_int_RNIFLSD[0]:Y (r)
               +     0.344          net: AHB_timer_0/N_42
  7.876                        AHB_timer_0/HADDR_int_RNI86RK_0[2]:A (r)
               +     0.445          cell: ADLIB:OR2B
  8.321                        AHB_timer_0/HADDR_int_RNI86RK_0[2]:Y (f)
               +     0.296          net: AHB_timer_0/N_48_0
  8.617                        AHB_timer_0/HADDR_int_RNITJO21_2[4]:B (f)
               +     0.652          cell: ADLIB:AND3B
  9.269                        AHB_timer_0/HADDR_int_RNITJO21_2[4]:Y (r)
               +     2.658          net: AHB_timer_0/un19_reg_load_en2
  11.927                       AHB_timer_0/DataOut_RNO_4[1]:B (r)
               +     0.470          cell: ADLIB:OR2B
  12.397                       AHB_timer_0/DataOut_RNO_4[1]:Y (f)
               +     0.296          net: AHB_timer_0/TIMINT1_m_i[1]
  12.693                       AHB_timer_0/DataOut_RNO_0[1]:B (f)
               +     0.552          cell: ADLIB:NOR3C
  13.245                       AHB_timer_0/DataOut_RNO_0[1]:Y (f)
               +     0.282          net: AHB_timer_0/DataOut_12_0_iv_1[1]
  13.527                       AHB_timer_0/DataOut_RNO[1]:A (f)
               +     0.422          cell: ADLIB:OR3C
  13.949                       AHB_timer_0/DataOut_RNO[1]:Y (r)
               +     0.296          net: AHB_timer_0/DataOut_12[1]
  14.245                       AHB_timer_0/DataOut[1]/U0:B (r)
               +     0.617          cell: ADLIB:MX2
  14.862                       AHB_timer_0/DataOut[1]/U0:Y (r)
               +     0.306          net: AHB_timer_0/DataOut[1]/Y
  15.168                       AHB_timer_0/DataOut[1]/U1:D (r)
                                    
  15.168                       data arrival time
  ________________________________________________________
  Data required time calculation
  8.333                        mss_ccc_glc
               +     0.000          Clock source
  8.333                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     1.246          Clock generation
  9.579
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  9.579                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  9.579                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.680          net: Timerv2_GLC
  10.259                       AHB_timer_0/DataOut[1]/U1:CLK (r)
               -     0.490          Library setup time: ADLIB:DFN1C0
  9.769                        AHB_timer_0/DataOut[1]/U1:D
                                    
  9.769                        data required time


END SET mss_ccc_gla1 to mss_ccc_glc

----------------------------------------------------

SET mss_ccc_gla0 to mss_ccc_glc

Path 1
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          AHB_timer_0/Count[5]/U1:PRE
  Delay (ns):                  8.428
  Slack (ns):                  -2.463
  Arrival (ns):                12.432
  Required (ns):               9.969
  Setup (ns):

Path 2
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          AHB_timer_0/Count[19]/U1:PRE
  Delay (ns):                  8.414
  Slack (ns):                  -2.430
  Arrival (ns):                12.418
  Required (ns):               9.988
  Setup (ns):

Path 3
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          AHB_timer_0/Count[4]/U1:PRE
  Delay (ns):                  8.414
  Slack (ns):                  -2.430
  Arrival (ns):                12.418
  Required (ns):               9.988
  Setup (ns):

Path 4
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          AHB_timer_0/Count[3]/U1:PRE
  Delay (ns):                  8.414
  Slack (ns):                  -2.430
  Arrival (ns):                12.418
  Required (ns):               9.988
  Setup (ns):

Path 5
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          AHB_timer_0/TIMINT2[7]/U1:PRE
  Delay (ns):                  8.376
  Slack (ns):                  -2.392
  Arrival (ns):                12.380
  Required (ns):               9.988
  Setup (ns):


Expanded Path 1
  From: _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To: AHB_timer_0/Count[5]/U1:PRE
  data required time                             9.969
  data arrival time                          -   12.432
  slack                                          -2.463
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  3.545
               +     0.459          net: _Timerv2_/MSS_ADLIB_INST_FCLK
  4.004                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     3.331          cell: ADLIB:MSS_AHB_IP
  7.335                        _Timerv2_/MSS_ADLIB_INST/U_CORE:M2FRESETn (r)
               +     0.121          net: _Timerv2_/MSS_ADLIB_INST/M2FRESETnINT_NET
  7.456                        _Timerv2_/MSS_ADLIB_INST/U_46:PIN2INT (r)
               +     0.095          cell: ADLIB:MSS_IF
  7.551                        _Timerv2_/MSS_ADLIB_INST/U_46:PIN2 (r)
               +     4.881          net: mss_highspeed_timerv2_0_M2F_RESET_N
  12.432                       AHB_timer_0/Count[5]/U1:PRE (r)
                                    
  12.432                       data arrival time
  ________________________________________________________
  Data required time calculation
  8.333                        mss_ccc_glc
               +     0.000          Clock source
  8.333                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     1.246          Clock generation
  9.579
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  9.579                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  9.579                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.661          net: Timerv2_GLC
  10.240                       AHB_timer_0/Count[5]/U1:CLK (r)
               -     0.271          Library recovery time: ADLIB:DFN1P0
  9.969                        AHB_timer_0/Count[5]/U1:PRE
                                    
  9.969                        data required time


END SET mss_ccc_gla0 to mss_ccc_glc

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_glc

Path 1
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          AHB_timer_0/IntClrEn/U1:D
  Delay (ns):                  8.132
  Slack (ns):                  -2.377
  Arrival (ns):                12.136
  Required (ns):               9.759
  Setup (ns):                  0.490

Path 2
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          AHB_timer_0/Load[14]/U1:D
  Delay (ns):                  7.980
  Slack (ns):                  -2.199
  Arrival (ns):                11.984
  Required (ns):               9.785
  Setup (ns):                  0.490

Path 3
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          AHB_timer_0/Load[21]/U1:D
  Delay (ns):                  7.872
  Slack (ns):                  -2.085
  Arrival (ns):                11.876
  Required (ns):               9.791
  Setup (ns):                  0.490

Path 4
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          AHB_timer_0/Load[23]/U1:D
  Delay (ns):                  7.766
  Slack (ns):                  -2.016
  Arrival (ns):                11.770
  Required (ns):               9.754
  Setup (ns):                  0.490

Path 5
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          AHB_timer_0/TimerPre[3]/U1:D
  Delay (ns):                  7.781
  Slack (ns):                  -2.005
  Arrival (ns):                11.785
  Required (ns):               9.780
  Setup (ns):                  0.490


Expanded Path 1
  From: _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To: AHB_timer_0/IntClrEn/U1:D
  data required time                             9.759
  data arrival time                          -   12.136
  slack                                          -2.377
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.004          Clock generation
  4.004
               +     2.919          cell: ADLIB:MSS_AHB_IP
  6.923                        _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHWDATA[0] (r)
               +     0.124          net: _Timerv2_/MSS_ADLIB_INST/MSSHWDATA[0]INT_NET
  7.047                        _Timerv2_/MSS_ADLIB_INST/U_36:PIN3INT (r)
               +     0.086          cell: ADLIB:MSS_IF
  7.133                        _Timerv2_/MSS_ADLIB_INST/U_36:PIN3 (r)
               +     1.716          net: _mss_highspeed_timerv2_0_MSS_MASTER_AHB_LITE_HWDATA_[0]_
  8.849                        CoreAHBLite_0/matrix2x16/slavestage_5/masterDataInProg_0_RNI6H2C[0]:B (r)
               +     0.568          cell: ADLIB:NOR3B
  9.417                        CoreAHBLite_0/matrix2x16/slavestage_5/masterDataInProg_0_RNI6H2C[0]:Y (r)
               +     0.970          net: _CoreAHBLite_0_AHBmslave5_HWDATA_[0]_
  10.387                       AHB_timer_0/IntClrEn_RNO:A (r)
               +     0.604          cell: ADLIB:NOR3A
  10.991                       AHB_timer_0/IntClrEn_RNO:Y (r)
               +     0.306          net: AHB_timer_0/IntClrEn_6
  11.297                       AHB_timer_0/IntClrEn/U0:B (r)
               +     0.533          cell: ADLIB:MX2
  11.830                       AHB_timer_0/IntClrEn/U0:Y (r)
               +     0.306          net: AHB_timer_0/IntClrEn/Y
  12.136                       AHB_timer_0/IntClrEn/U1:D (r)
                                    
  12.136                       data arrival time
  ________________________________________________________
  Data required time calculation
  8.333                        mss_ccc_glc
               +     0.000          Clock source
  8.333                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     1.246          Clock generation
  9.579
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  9.579                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  9.579                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.670          net: Timerv2_GLC
  10.249                       AHB_timer_0/IntClrEn/U1:CLK (r)
               -     0.490          Library setup time: ADLIB:DFN1C0
  9.759                        AHB_timer_0/IntClrEn/U1:D
                                    
  9.759                        data required time


END SET mss_fabric_interface_clock to mss_ccc_glc

----------------------------------------------------

Clock Domain \\Timerv2\\/MSS_CCC_0/I_RCOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_fabric_interface_clock

Path 1
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/CLDATASELInt[7]/U1:CLK
  To:                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHREADY
  Delay (ns):                  12.660
  Slack (ns):                  -0.473
  Arrival (ns):                18.599
  Required (ns):               18.126
  Setup (ns):                  -1.622

Path 2
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/CLDATASELInt[6]/U1:CLK
  To:                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHREADY
  Delay (ns):                  12.517
  Slack (ns):                  -0.330
  Arrival (ns):                18.456
  Required (ns):               18.126
  Setup (ns):                  -1.622

Path 3
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/CLDATASELInt[7]/U1:CLK
  To:                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHRESP
  Delay (ns):                  12.589
  Slack (ns):                  -0.131
  Arrival (ns):                18.528
  Required (ns):               18.397
  Setup (ns):                  -1.893

Path 4
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/CLDATASELInt[6]/U1:CLK
  To:                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHRESP
  Delay (ns):                  12.446
  Slack (ns):                  0.012
  Arrival (ns):                18.385
  Required (ns):               18.397
  Setup (ns):                  -1.893

Path 5
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[12]/U1:CLK
  To:                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHREADY
  Delay (ns):                  11.898
  Slack (ns):                  0.317
  Arrival (ns):                17.809
  Required (ns):               18.126
  Setup (ns):                  -1.622


Expanded Path 1
  From: CoreAHBLite_0/matrix2x16/masterstage_0/CLDATASELInt[7]/U1:CLK
  To: _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHREADY
  data required time                             18.126
  data arrival time                          -   18.599
  slack                                          -0.473
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.690          net: mss_highspeed_timerv2_0_FAB_CLK
  5.939                        CoreAHBLite_0/matrix2x16/masterstage_0/CLDATASELInt[7]/U1:CLK (r)
               +     0.671          cell: ADLIB:DFN1C0
  6.610                        CoreAHBLite_0/matrix2x16/masterstage_0/CLDATASELInt[7]/U1:Q (f)
               +     0.351          net: CoreAHBLite_0/matrix2x16/masterstage_0/CLDATASELInt[7]
  6.961                        CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_o2_0_14_3:B (f)
               +     0.588          cell: ADLIB:NOR2
  7.549                        CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_o2_0_14_3:Y (r)
               +     0.306          net: CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_o2_0_14_3
  7.855                        CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_o2_0_14_9:A (r)
               +     0.604          cell: ADLIB:NOR3A
  8.459                        CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_o2_0_14_9:Y (r)
               +     1.083          net: CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_o2_0_14_9
  9.542                        CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_o2_0_14_12:C (r)
               +     0.606          cell: ADLIB:NOR3C
  10.148                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_o2_0_14_12:Y (r)
               +     0.306          net: CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_o2_0_14_12
  10.454                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_o2_0_14:C (r)
               +     0.606          cell: ADLIB:NOR3C
  11.060                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_o2_0_14:Y (r)
               +     1.463          net: CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_o2_0_14_i_0
  12.523                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_m_0_a2_2_m9_0_o5:A (r)
               +     0.478          cell: ADLIB:OR3C
  13.001                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_m_0_a2_2_m9_0_o5:Y (f)
               +     0.306          net: CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_m_0_a2_2_N_10
  13.307                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_m_0_a2_2_m9_0:B (f)
               +     0.554          cell: ADLIB:AO1B
  13.861                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_m_0_a2_2_m9_0:Y (f)
               +     0.309          net: CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_m_0_a2_2_m9_0
  14.170                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_m_0_a2_1:S (f)
               +     0.473          cell: ADLIB:MX2
  14.643                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_m_0_a2_1:Y (f)
               +     0.367          net: CoreAHBLite_0_matrix2x16_masterstage_0_N_1064_2
  15.010                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState_RNI28NOO:A (f)
               +     0.848          cell: ADLIB:OA1C
  15.858                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState_RNI28NOO:Y (r)
               +     2.246          net: CoreAHBLite_0_matrix2x16_masterstage_0_HREADY_M_iv
  18.104                       _Timerv2_/MSS_ADLIB_INST/U_58:PIN4 (r)
               +     0.079          cell: ADLIB:MSS_IF
  18.183                       _Timerv2_/MSS_ADLIB_INST/U_58:PIN4INT (r)
               +     0.416          net: _Timerv2_/MSS_ADLIB_INST/MSSHREADYINT_NET
  18.599                       _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHREADY (r)
                                    
  18.599                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_fabric_interface_clock
               +     0.000          Clock source
  12.500                       _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.004          Clock generation
  16.504
               -    -1.622          Library setup time: ADLIB:MSS_AHB_IP
  18.126                       _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHREADY
                                    
  18.126                       data required time


END SET mss_ccc_gla1 to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

Path 1
  From:                        Pulse_in
  To:                          Test_port[0]
  Delay (ns):                  6.189
  Slack (ns):
  Arrival (ns):                6.189
  Required (ns):


Expanded Path 1
  From: Pulse_in
  To: Test_port[0]
  data required time                             N/C
  data arrival time                          -   6.189
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        Pulse_in (f)
               +     0.000          net: Pulse_in
  0.000                        Pulse_in_pad/U0/U0:PAD (f)
               +     0.634          cell: ADLIB:IOPAD_IN
  0.634                        Pulse_in_pad/U0/U0:Y (f)
               +     0.000          net: Pulse_in_pad/U0/NET1
  0.634                        Pulse_in_pad/U0/U1:YIN (f)
               +     0.036          cell: ADLIB:IOIN_IB
  0.670                        Pulse_in_pad/U0/U1:Y (f)
               +     1.620          net: Pulse_in_c_c
  2.290                        Test_port_pad[0]/U0/U1:D (f)
               +     0.530          cell: ADLIB:IOTRI_OB_EB
  2.820                        Test_port_pad[0]/U0/U1:DOUT (f)
               +     0.000          net: Test_port_pad[0]/U0/NET1
  2.820                        Test_port_pad[0]/U0/U0:D (f)
               +     3.369          cell: ADLIB:IOPAD_TRI
  6.189                        Test_port_pad[0]/U0/U0:PAD (f)
               +     0.000          net: Test_port[0]
  6.189                        Test_port[0] (f)
                                    
  6.189                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          Pulse_in (f)
                                    
  N/C                          Test_port[0] (f)
                                    
  N/C                          data required time


END SET Input to Output

----------------------------------------------------

Path set User Sets

