#Build: Synplify Pro E-2010.09A-1, Build 006R, Oct 6 2010 #install: C:\Actel9.1SPB\Libero_v9.1\Synopsys\synplify_E201009A-1 #OS: Windows XP 5.1 #Hostname: VXP-SUDEEPS #Implementation: synthesis #Fri Feb 18 11:47:35 2011 $ Start of Compile #Fri Feb 18 11:47:35 2011 Synopsys VHDL Compiler, version comp520rcp1, Build 028R, built Sep 23 2010 @N: : | Running in 32-bit mode Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved @N:CD720 : std.vhd(123) | Setting time resolution to ns @N: : top_timer.vhd(10) | Top entity is set to top_timer. VHDL syntax check successful! File C:\Actelprj\App_notes_upadtes\SmartFusion_Timer_DF\Hardware\A2F200\VHDL\highspeed_timerv2\hdl\Decrementor24.vhd changed - recompiling File C:\Actelprj\App_notes_upadtes\SmartFusion_Timer_DF\Hardware\A2F200\VHDL\highspeed_timerv2\hdl\count_zero_blk.vhd changed - recompiling File C:\Actelprj\App_notes_upadtes\SmartFusion_Timer_DF\Hardware\A2F200\VHDL\highspeed_timerv2\component\Actel\SmartFusionMSS\MSS\2.4.105\mss_comps.vhd changed - recompiling File C:\Actelprj\App_notes_upadtes\SmartFusion_Timer_DF\Hardware\A2F200\VHDL\highspeed_timerv2\component\work\mss_highspeed_timerv2\mss_tshell.vhd changed - recompiling File C:\Actelprj\App_notes_upadtes\SmartFusion_Timer_DF\Hardware\A2F200\VHDL\highspeed_timerv2\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_addrdec.vhd changed - recompiling File C:\Actelprj\App_notes_upadtes\SmartFusion_Timer_DF\Hardware\A2F200\VHDL\highspeed_timerv2\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_defaultslavesm.vhd changed - recompiling File C:\Actelprj\App_notes_upadtes\SmartFusion_Timer_DF\Hardware\A2F200\VHDL\highspeed_timerv2\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_slavearbiter.vhd changed - recompiling File C:\Actelprj\App_notes_upadtes\SmartFusion_Timer_DF\Hardware\A2F200\VHDL\highspeed_timerv2\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_initcfg_awrap.vhd changed - recompiling File C:\Actelprj\App_notes_upadtes\SmartFusion_Timer_DF\Hardware\A2F200\VHDL\highspeed_timerv2\hdl\AHB_timer.vhd changed - recompiling File C:\Actelprj\App_notes_upadtes\SmartFusion_Timer_DF\Hardware\A2F200\VHDL\highspeed_timerv2\component\work\mss_highspeed_timerv2\MSS_CCC_0\mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC.vhd changed - recompiling File C:\Actelprj\App_notes_upadtes\SmartFusion_Timer_DF\Hardware\A2F200\VHDL\highspeed_timerv2\component\work\mss_highspeed_timerv2\mss_highspeed_timerv2.vhd changed - recompiling File C:\Actelprj\App_notes_upadtes\SmartFusion_Timer_DF\Hardware\A2F200\VHDL\highspeed_timerv2\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_masterstage.vhd changed - recompiling File C:\Actelprj\App_notes_upadtes\SmartFusion_Timer_DF\Hardware\A2F200\VHDL\highspeed_timerv2\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_slavestage.vhd changed - recompiling File C:\Actelprj\App_notes_upadtes\SmartFusion_Timer_DF\Hardware\A2F200\VHDL\highspeed_timerv2\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_initcfg.vhd changed - recompiling File C:\Actelprj\App_notes_upadtes\SmartFusion_Timer_DF\Hardware\A2F200\VHDL\highspeed_timerv2\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite_matrix2x16.vhd changed - recompiling File C:\Actelprj\App_notes_upadtes\SmartFusion_Timer_DF\Hardware\A2F200\VHDL\highspeed_timerv2\component\Actel\DirectCore\CoreAHBLite\3.1.102\rtl\vhdl\core\coreahblite.vhd changed - recompiling File C:\Actelprj\App_notes_upadtes\SmartFusion_Timer_DF\Hardware\A2F200\VHDL\highspeed_timerv2\component\work\top_timer\top_timer.vhd changed - recompiling @N:CD630 : top_timer.vhd(10) | Synthesizing work.top_timer.def_arch @N:CD630 : mss_highspeed_timerv2.vhd(8) | Synthesizing work.mss_highspeed_timerv2.def_arch @N:CD630 : mss_comps.vhd(4) | Synthesizing work.inbuf_mss.def_arch Post processing for work.inbuf_mss.def_arch @N:CD630 : smartfusion.vhd(1784) | Synthesizing smartfusion.gnd.syn_black_box Post processing for smartfusion.gnd.syn_black_box @N:CD630 : mss_tshell.vhd(4) | Synthesizing work.mss_ahb.def_arch Post processing for work.mss_ahb.def_arch @N:CD630 : mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC.vhd(8) | Synthesizing work.mss_highspeed_timerv2_tmp_mss_ccc_0_mss_ccc.def_arch @N:CD630 : smartfusion.vhd(2742) | Synthesizing smartfusion.vcc.syn_black_box Post processing for smartfusion.vcc.syn_black_box @N:CD630 : smartfusion.vhd(3703) | Synthesizing smartfusion.rcosc.syn_black_box Post processing for smartfusion.rcosc.syn_black_box @N:CD630 : mss_comps.vhd(472) | Synthesizing work.mss_ccc.def_arch Post processing for work.mss_ccc.def_arch Post processing for work.mss_highspeed_timerv2_tmp_mss_ccc_0_mss_ccc.def_arch @W:CL240 : mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC.vhd(38) | LPXIN_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible @W:CL240 : mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC.vhd(37) | MAINXIN_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible @W:CL240 : mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC.vhd(36) | RCOSC_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible @N:CD630 : mss_comps.vhd(24) | Synthesizing work.outbuf_mss.def_arch Post processing for work.outbuf_mss.def_arch Post processing for work.mss_highspeed_timerv2.def_arch @N:CD630 : AHB_timer.vhd(24) | Synthesizing work.ahb_timer.synth @N:CD233 : AHB_timer.vhd(117) | Using sequential encoding for type hclk_req_st_type @N:CD233 : AHB_timer.vhd(120) | Using sequential encoding for type fclk_ack_st_type @N:CD364 : AHB_timer.vhd(418) | Removed redundant assignment @W:CD638 : AHB_timer.vhd(98) | Signal zerocount is undriven @N:CD630 : count_zero_blk.vhd(6) | Synthesizing work.count_zero_blk.def_arch @N:CD630 : smartfusion.vhd(37) | Synthesizing smartfusion.and3.syn_black_box Post processing for smartfusion.and3.syn_black_box @N:CD630 : smartfusion.vhd(2128) | Synthesizing smartfusion.nor3.syn_black_box Post processing for smartfusion.nor3.syn_black_box Post processing for work.count_zero_blk.def_arch @N:CD630 : Decrementor24.vhd(8) | Synthesizing work.decrementor24.def_arch @N:CD630 : smartfusion.vhd(2837) | Synthesizing smartfusion.xor2.syn_black_box Post processing for smartfusion.xor2.syn_black_box @N:CD630 : smartfusion.vhd(2104) | Synthesizing smartfusion.nor2.syn_black_box Post processing for smartfusion.nor2.syn_black_box @N:CD630 : smartfusion.vhd(1945) | Synthesizing smartfusion.inv.syn_black_box Post processing for smartfusion.inv.syn_black_box @N:CD630 : smartfusion.vhd(21) | Synthesizing smartfusion.and2a.syn_black_box Post processing for smartfusion.and2a.syn_black_box @N:CD630 : smartfusion.vhd(46) | Synthesizing smartfusion.and3a.syn_black_box Post processing for smartfusion.and3a.syn_black_box @N:CD630 : smartfusion.vhd(55) | Synthesizing smartfusion.and3b.syn_black_box Post processing for smartfusion.and3b.syn_black_box @N:CD630 : smartfusion.vhd(13) | Synthesizing smartfusion.and2.syn_black_box Post processing for smartfusion.and2.syn_black_box @N:CD630 : smartfusion.vhd(2802) | Synthesizing smartfusion.xnor2.syn_black_box Post processing for smartfusion.xnor2.syn_black_box Post processing for work.decrementor24.def_arch Post processing for work.ahb_timer.synth @W:CL190 : AHB_timer.vhd(250) | Optimizing register bit DataOut(24) to a constant 0 @W:CL190 : AHB_timer.vhd(250) | Optimizing register bit DataOut(25) to a constant 0 @W:CL190 : AHB_timer.vhd(250) | Optimizing register bit DataOut(26) to a constant 0 @W:CL190 : AHB_timer.vhd(250) | Optimizing register bit DataOut(27) to a constant 0 @W:CL190 : AHB_timer.vhd(250) | Optimizing register bit DataOut(28) to a constant 0 @W:CL190 : AHB_timer.vhd(250) | Optimizing register bit DataOut(29) to a constant 0 @W:CL190 : AHB_timer.vhd(250) | Optimizing register bit DataOut(30) to a constant 0 @W:CL190 : AHB_timer.vhd(250) | Optimizing register bit DataOut(31) to a constant 0 @W:CL260 : AHB_timer.vhd(250) | Pruning Register bit 31 of DataOut(31 downto 0) @W:CL260 : AHB_timer.vhd(250) | Pruning Register bit 30 of DataOut(31 downto 0) @W:CL260 : AHB_timer.vhd(250) | Pruning Register bit 29 of DataOut(31 downto 0) @W:CL260 : AHB_timer.vhd(250) | Pruning Register bit 28 of DataOut(31 downto 0) @W:CL260 : AHB_timer.vhd(250) | Pruning Register bit 27 of DataOut(31 downto 0) @W:CL260 : AHB_timer.vhd(250) | Pruning Register bit 26 of DataOut(31 downto 0) @W:CL260 : AHB_timer.vhd(250) | Pruning Register bit 25 of DataOut(31 downto 0) @W:CL260 : AHB_timer.vhd(250) | Pruning Register bit 24 of DataOut(31 downto 0) @N:CD630 : coreahblite.vhd(34) | Synthesizing coreahblite_lib.coreahblite.coreahblite_arch @N:CD630 : coreahblite_matrix2x16.vhd(34) | Synthesizing coreahblite_lib.coreahblite_matrix2x16.coreahblite_matrix2x16_arch @N:CD630 : coreahblite_initcfg.vhd(37) | Synthesizing coreahblite_lib.coreahblite_initcfg.coreahblite_initcfg_arch @N:CD630 : coreahblite_initcfg_awrap.vhd(36) | Synthesizing coreahblite_lib.coreahblite_initcfg_awrap.coreahblite_initcfg_awrap_arch Post processing for coreahblite_lib.coreahblite_initcfg_awrap.coreahblite_initcfg_awrap_arch @W:CL169 : coreahblite_initcfg_awrap.vhd(123) | Pruning Register HREADYOUT_int_s1 @N:CD630 : coreahblite_slavearbiter.vhd(31) | Synthesizing coreahblite_lib.coreahblite_slavearbiter.coreahblite_slavearbiter_arch @W:CD604 : coreahblite_slavearbiter.vhd(177) | OTHERS clause is not synthesized Post processing for coreahblite_lib.coreahblite_slavearbiter.coreahblite_slavearbiter_arch Post processing for coreahblite_lib.coreahblite_initcfg.coreahblite_initcfg_arch @N:CD630 : coreahblite_slavestage.vhd(33) | Synthesizing coreahblite_lib.coreahblite_slavestage.trans Post processing for coreahblite_lib.coreahblite_slavestage.trans @N:CD630 : coreahblite_masterstage.vhd(33) | Synthesizing coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch @W:CD434 : coreahblite_masterstage.vhd(372) | Signal sdataready in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal shresp in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s0 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s0 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s1 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s1 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s2 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s2 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s3 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s3 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s4 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s4 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s5 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s5 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s6 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s6 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s7 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s7 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s8 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s8 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s9 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s9 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s10 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s10 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s11 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s11 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s12 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s12 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s13 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s13 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s14 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s14 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s15 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s15 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_shg in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_shg in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal cldataready in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal clhresp in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_cl in the sensitivity list is not used in the process @W:CD604 : coreahblite_masterstage.vhd(821) | OTHERS clause is not synthesized @N:CD630 : coreahblite_defaultslavesm.vhd(31) | Synthesizing coreahblite_lib.coreahblite_defaultslavesm.coreahblite_defaultslavesm_arch @W:CD604 : coreahblite_defaultslavesm.vhd(65) | OTHERS clause is not synthesized Post processing for coreahblite_lib.coreahblite_defaultslavesm.coreahblite_defaultslavesm_arch @N:CD630 : coreahblite_addrdec.vhd(31) | Synthesizing coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch Post processing for coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch Post processing for coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch @N:CL177 : coreahblite_masterstage.vhd(828) | Sharing sequential element addrRegSMCurrentState. @N:CD630 : coreahblite_masterstage.vhd(33) | Synthesizing coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s1 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s1 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s2 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s2 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s3 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s3 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s4 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s4 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s5 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s5 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s6 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s6 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s7 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s7 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s8 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s8 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s9 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s9 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s10 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s10 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s11 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s11 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s12 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s12 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s13 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s13 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s14 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s14 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_s15 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_s15 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hrdata_shg in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_shg in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal cldataready in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal clhresp in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(372) | Signal hreadyout_cl in the sensitivity list is not used in the process @W:CD604 : coreahblite_masterstage.vhd(821) | OTHERS clause is not synthesized @N:CD630 : coreahblite_addrdec.vhd(31) | Synthesizing coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch Post processing for coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch Post processing for coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch @N:CL177 : coreahblite_masterstage.vhd(828) | Sharing sequential element addrRegSMCurrentState. Post processing for coreahblite_lib.coreahblite_matrix2x16.coreahblite_matrix2x16_arch Post processing for coreahblite_lib.coreahblite.coreahblite_arch Post processing for work.top_timer.def_arch @W:CL246 : coreahblite_masterstage.vhd(52) | Input port bits 16 to 1 of sdataready(16 downto 0) are unused @W:CL246 : coreahblite_masterstage.vhd(53) | Input port bits 16 to 1 of shresp(16 downto 0) are unused @W:CL159 : coreahblite_masterstage.vhd(55) | Input CLDATAREADY is unused @W:CL159 : coreahblite_masterstage.vhd(56) | Input CLHRESP is unused @W:CL159 : coreahblite_masterstage.vhd(70) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_masterstage.vhd(71) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_masterstage.vhd(72) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.vhd(73) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.vhd(74) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_masterstage.vhd(75) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_masterstage.vhd(76) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.vhd(77) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.vhd(78) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.vhd(79) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.vhd(80) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.vhd(81) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.vhd(82) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.vhd(83) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.vhd(84) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.vhd(85) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.vhd(86) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.vhd(87) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.vhd(88) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.vhd(89) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.vhd(90) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.vhd(91) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.vhd(92) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.vhd(93) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.vhd(94) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.vhd(95) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.vhd(96) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.vhd(97) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.vhd(98) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.vhd(99) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_masterstage.vhd(100) | Input HRDATA_SHG is unused @W:CL159 : coreahblite_masterstage.vhd(101) | Input HREADYOUT_SHG is unused @W:CL159 : coreahblite_masterstage.vhd(102) | Input HREADYOUT_CL is unused @W:CL159 : coreahblite_masterstage.vhd(52) | Input SDATAREADY is unused @W:CL159 : coreahblite_masterstage.vhd(53) | Input SHRESP is unused @W:CL159 : coreahblite_masterstage.vhd(55) | Input CLDATAREADY is unused @W:CL159 : coreahblite_masterstage.vhd(56) | Input CLHRESP is unused @W:CL159 : coreahblite_masterstage.vhd(68) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_masterstage.vhd(69) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_masterstage.vhd(70) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_masterstage.vhd(71) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_masterstage.vhd(72) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.vhd(73) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.vhd(74) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_masterstage.vhd(75) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_masterstage.vhd(76) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.vhd(77) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.vhd(78) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.vhd(79) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.vhd(80) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.vhd(81) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.vhd(82) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.vhd(83) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.vhd(84) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.vhd(85) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.vhd(86) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.vhd(87) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.vhd(88) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.vhd(89) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.vhd(90) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.vhd(91) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.vhd(92) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.vhd(93) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.vhd(94) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.vhd(95) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.vhd(96) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.vhd(97) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.vhd(98) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.vhd(99) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_masterstage.vhd(100) | Input HRDATA_SHG is unused @W:CL159 : coreahblite_masterstage.vhd(101) | Input HREADYOUT_SHG is unused @W:CL159 : coreahblite_masterstage.vhd(102) | Input HREADYOUT_CL is unused @N:CL201 : coreahblite_slavearbiter.vhd(184) | Trying to extract state machine for register arbRegSMCurrentState Extracted state machine for register arbRegSMCurrentState State machine has 8 reachable states with original encodings of: 000 001 010 011 100 101 110 111 @W:CL246 : coreahblite_initcfg_awrap.vhd(43) | Input port bits 31 to 12 of haddr(31 downto 0) are unused @W:CL247 : coreahblite_initcfg_awrap.vhd(47) | Input port bit 0 of htrans(1 downto 0) is unused @W:CL159 : coreahblite_initcfg.vhd(47) | Input CLADDRSEL_M0 is unused @W:CL159 : coreahblite_initcfg.vhd(48) | Input CLADDRSEL_M1 is unused @W:CL159 : coreahblite_matrix2x16.vhd(60) | Input HWDATA_M1 is unused @W:CL159 : coreahblite_matrix2x16.vhd(75) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_matrix2x16.vhd(76) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_matrix2x16.vhd(77) | Input HRESP_S1 is unused @W:CL159 : coreahblite_matrix2x16.vhd(86) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_matrix2x16.vhd(87) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_matrix2x16.vhd(88) | Input HRESP_S2 is unused @W:CL159 : coreahblite_matrix2x16.vhd(97) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_matrix2x16.vhd(98) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_matrix2x16.vhd(99) | Input HRESP_S3 is unused @W:CL159 : coreahblite_matrix2x16.vhd(108) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_matrix2x16.vhd(109) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_matrix2x16.vhd(110) | Input HRESP_S4 is unused @W:CL159 : coreahblite_matrix2x16.vhd(119) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_matrix2x16.vhd(120) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_matrix2x16.vhd(121) | Input HRESP_S5 is unused @W:CL159 : coreahblite_matrix2x16.vhd(130) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_matrix2x16.vhd(131) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_matrix2x16.vhd(132) | Input HRESP_S6 is unused @W:CL159 : coreahblite_matrix2x16.vhd(141) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_matrix2x16.vhd(142) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_matrix2x16.vhd(143) | Input HRESP_S7 is unused @W:CL159 : coreahblite_matrix2x16.vhd(152) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_matrix2x16.vhd(153) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_matrix2x16.vhd(154) | Input HRESP_S8 is unused @W:CL159 : coreahblite_matrix2x16.vhd(163) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_matrix2x16.vhd(164) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_matrix2x16.vhd(165) | Input HRESP_S9 is unused @W:CL159 : coreahblite_matrix2x16.vhd(174) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_matrix2x16.vhd(175) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_matrix2x16.vhd(176) | Input HRESP_S10 is unused @W:CL159 : coreahblite_matrix2x16.vhd(185) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_matrix2x16.vhd(186) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_matrix2x16.vhd(187) | Input HRESP_S11 is unused @W:CL159 : coreahblite_matrix2x16.vhd(196) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_matrix2x16.vhd(197) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_matrix2x16.vhd(198) | Input HRESP_S12 is unused @W:CL159 : coreahblite_matrix2x16.vhd(207) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_matrix2x16.vhd(208) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_matrix2x16.vhd(209) | Input HRESP_S13 is unused @W:CL159 : coreahblite_matrix2x16.vhd(218) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_matrix2x16.vhd(219) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_matrix2x16.vhd(220) | Input HRESP_S14 is unused @W:CL159 : coreahblite_matrix2x16.vhd(229) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_matrix2x16.vhd(230) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_matrix2x16.vhd(231) | Input HRESP_S15 is unused @W:CL159 : coreahblite_matrix2x16.vhd(240) | Input HRDATA_SHG is unused @W:CL159 : coreahblite_matrix2x16.vhd(241) | Input HREADYOUT_SHG is unused @W:CL159 : coreahblite_matrix2x16.vhd(242) | Input HRESP_SHG is unused @W:CL247 : coreahblite.vhd(113) | Input port bit 0 of htrans_m0(1 downto 0) is unused @W:CL247 : coreahblite.vhd(124) | Input port bit 0 of htrans_m1(1 downto 0) is unused @W:CL247 : coreahblite.vhd(134) | Input port bit 1 of hresp_s0(1 downto 0) is unused @W:CL247 : coreahblite.vhd(147) | Input port bit 1 of hresp_s1(1 downto 0) is unused @W:CL247 : coreahblite.vhd(160) | Input port bit 1 of hresp_s2(1 downto 0) is unused @W:CL247 : coreahblite.vhd(173) | Input port bit 1 of hresp_s3(1 downto 0) is unused @W:CL247 : coreahblite.vhd(186) | Input port bit 1 of hresp_s4(1 downto 0) is unused @W:CL247 : coreahblite.vhd(199) | Input port bit 1 of hresp_s5(1 downto 0) is unused @W:CL247 : coreahblite.vhd(212) | Input port bit 1 of hresp_s6(1 downto 0) is unused @W:CL247 : coreahblite.vhd(225) | Input port bit 1 of hresp_s7(1 downto 0) is unused @W:CL247 : coreahblite.vhd(238) | Input port bit 1 of hresp_s8(1 downto 0) is unused @W:CL247 : coreahblite.vhd(251) | Input port bit 1 of hresp_s9(1 downto 0) is unused @W:CL247 : coreahblite.vhd(264) | Input port bit 1 of hresp_s10(1 downto 0) is unused @W:CL247 : coreahblite.vhd(277) | Input port bit 1 of hresp_s11(1 downto 0) is unused @W:CL247 : coreahblite.vhd(290) | Input port bit 1 of hresp_s12(1 downto 0) is unused @W:CL247 : coreahblite.vhd(303) | Input port bit 1 of hresp_s13(1 downto 0) is unused @W:CL247 : coreahblite.vhd(316) | Input port bit 1 of hresp_s14(1 downto 0) is unused @W:CL247 : coreahblite.vhd(329) | Input port bit 1 of hresp_s15(1 downto 0) is unused @W:CL247 : coreahblite.vhd(342) | Input port bit 1 of hresp_shg(1 downto 0) is unused @W:CL159 : coreahblite.vhd(116) | Input HBURST_M0 is unused @W:CL159 : coreahblite.vhd(117) | Input HPROT_M0 is unused @W:CL159 : coreahblite.vhd(127) | Input HBURST_M1 is unused @W:CL159 : coreahblite.vhd(128) | Input HPROT_M1 is unused @W:CL260 : AHB_timer.vhd(492) | Pruning Register bit 31 of DataOut_int(31 downto 0) @W:CL260 : AHB_timer.vhd(492) | Pruning Register bit 30 of DataOut_int(31 downto 0) @W:CL260 : AHB_timer.vhd(492) | Pruning Register bit 29 of DataOut_int(31 downto 0) @W:CL260 : AHB_timer.vhd(492) | Pruning Register bit 28 of DataOut_int(31 downto 0) @W:CL260 : AHB_timer.vhd(492) | Pruning Register bit 27 of DataOut_int(31 downto 0) @W:CL260 : AHB_timer.vhd(492) | Pruning Register bit 26 of DataOut_int(31 downto 0) @W:CL260 : AHB_timer.vhd(492) | Pruning Register bit 25 of DataOut_int(31 downto 0) @W:CL189 : AHB_timer.vhd(492) | Register bit DataOut_int(24) is always 0, optimizing ... @W:CL260 : AHB_timer.vhd(492) | Pruning Register bit 24 of DataOut_int(24 downto 0) @N:CL201 : AHB_timer.vhd(210) | Trying to extract state machine for register HCLKSTATE Extracted state machine for register HCLKSTATE State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL246 : AHB_timer.vhd(29) | Input port bits 19 to 5 of haddr(19 downto 0) are unused @W:CL247 : AHB_timer.vhd(31) | Input port bit 0 of htrans(1 downto 0) is unused @W:CL246 : AHB_timer.vhd(35) | Input port bits 31 to 24 of hwdata(31 downto 0) are unused @W:CL159 : mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC.vhd(10) | Input CLKA is unused @W:CL159 : mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC.vhd(11) | Input CLKA_PAD is unused @W:CL159 : mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC.vhd(12) | Input CLKA_PADP is unused @W:CL159 : mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC.vhd(13) | Input CLKA_PADN is unused @W:CL159 : mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC.vhd(14) | Input CLKB is unused @W:CL159 : mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC.vhd(15) | Input CLKB_PAD is unused @W:CL159 : mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC.vhd(16) | Input CLKB_PADP is unused @W:CL159 : mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC.vhd(17) | Input CLKB_PADN is unused @W:CL159 : mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC.vhd(18) | Input CLKC is unused @W:CL159 : mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC.vhd(19) | Input CLKC_PAD is unused @W:CL159 : mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC.vhd(20) | Input CLKC_PADP is unused @W:CL159 : mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC.vhd(21) | Input CLKC_PADN is unused @W:CL159 : mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC.vhd(22) | Input MAINXIN is unused @W:CL159 : mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC.vhd(23) | Input LPXIN is unused @W:CL159 : mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC.vhd(24) | Input MAC_CLK is unused @END Process took 0h:00m:04s realtime, 0h:00m:03s cputime # Fri Feb 18 11:47:39 2011 ###########################################################] Synopsys Actel Technology Mapper, Version mapact, Build 023R, Built Sep 29 2010 09:29:00 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved Product Version E-2010.09A-1 @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled @W:MO161 : coreahblite_masterstage.vhd(828) | Register bit masterRegAddrSel is always 0, optimizing ... @N:BN116 : coreahblite_masterstage.vhd(356) | Removing sequential instance GATEDHWRITE_save of view:PrimLib.dffre(prim) because there are no references to its outputs @N:BN116 : coreahblite_masterstage.vhd(276) | Removing sequential instance regHTRANS of view:PrimLib.dffre(prim) because there are no references to its outputs @N:BN116 : coreahblite_initcfg.vhd(231) | Removing sequential instance masterDataInProg[1:0] of view:PrimLib.dffre(prim) because there are no references to its outputs @N:BN115 : coreahblite_initcfg.vhd(163) | Removing instance init_cfg_client_arbiter of view:coreahblite_lib.COREAHBLITE_SLAVEARBITER_init_cfg_client_arbiter(coreahblite_slavearbiter_arch) because there are no references to its outputs @N:BN116 : coreahblite_initcfg_awrap.vhd(123) | Removing sequential instance CoreAHBLite_0.matrix2x16.initcfg_slavestage.init_cfg_awrap.INITDONE_r[15:0] of view:PrimLib.dffre(prim) because there are no references to its outputs @N:BN115 : coreahblite_matrix2x16.vhd(5600) | Removing instance CoreAHBLite_0.matrix2x16.slavestage_16 of view:coreahblite_lib.COREAHBLITE_SLAVESTAGE_slavestage_1(trans) because there are no references to its outputs @N:BN115 : coreahblite_matrix2x16.vhd(5559) | Removing instance CoreAHBLite_0.matrix2x16.slavestage_15 of view:coreahblite_lib.COREAHBLITE_SLAVESTAGE_slavestage_1(trans) because there are no references to its outputs @N:BN115 : coreahblite_matrix2x16.vhd(5518) | Removing instance CoreAHBLite_0.matrix2x16.slavestage_14 of view:coreahblite_lib.COREAHBLITE_SLAVESTAGE_slavestage_1(trans) because there are no references to its outputs @N:BN115 : coreahblite_matrix2x16.vhd(5477) | Removing instance CoreAHBLite_0.matrix2x16.slavestage_13 of view:coreahblite_lib.COREAHBLITE_SLAVESTAGE_slavestage_1(trans) because there are no references to its outputs @N:BN115 : coreahblite_matrix2x16.vhd(5436) | Removing instance CoreAHBLite_0.matrix2x16.slavestage_12 of view:coreahblite_lib.COREAHBLITE_SLAVESTAGE_slavestage_1(trans) because there are no references to its outputs @N:BN115 : coreahblite_matrix2x16.vhd(5395) | Removing instance CoreAHBLite_0.matrix2x16.slavestage_11 of view:coreahblite_lib.COREAHBLITE_SLAVESTAGE_slavestage_1(trans) because there are no references to its outputs @N:BN115 : coreahblite_matrix2x16.vhd(5354) | Removing instance CoreAHBLite_0.matrix2x16.slavestage_10 of view:coreahblite_lib.COREAHBLITE_SLAVESTAGE_slavestage_1(trans) because there are no references to its outputs @N:BN115 : coreahblite_matrix2x16.vhd(5313) | Removing instance CoreAHBLite_0.matrix2x16.slavestage_9 of view:coreahblite_lib.COREAHBLITE_SLAVESTAGE_slavestage_1(trans) because there are no references to its outputs @N:BN115 : coreahblite_matrix2x16.vhd(5272) | Removing instance CoreAHBLite_0.matrix2x16.slavestage_8 of view:coreahblite_lib.COREAHBLITE_SLAVESTAGE_slavestage_1(trans) because there are no references to its outputs @N:BN115 : coreahblite_matrix2x16.vhd(5231) | Removing instance CoreAHBLite_0.matrix2x16.slavestage_7 of view:coreahblite_lib.COREAHBLITE_SLAVESTAGE_slavestage_1(trans) because there are no references to its outputs @N:BN115 : coreahblite_matrix2x16.vhd(5190) | Removing instance CoreAHBLite_0.matrix2x16.slavestage_6 of view:coreahblite_lib.COREAHBLITE_SLAVESTAGE_slavestage_1(trans) because there are no references to its outputs @N:BN115 : coreahblite_matrix2x16.vhd(5149) | Removing instance CoreAHBLite_0.matrix2x16.slavestage_5 of view:coreahblite_lib.COREAHBLITE_SLAVESTAGE_slavestage_1(trans) because there are no references to its outputs @N:BN115 : coreahblite_matrix2x16.vhd(5108) | Removing instance CoreAHBLite_0.matrix2x16.slavestage_4 of view:coreahblite_lib.COREAHBLITE_SLAVESTAGE_slavestage_1(trans) because there are no references to its outputs @N:BN115 : coreahblite_matrix2x16.vhd(5067) | Removing instance CoreAHBLite_0.matrix2x16.slavestage_3 of view:coreahblite_lib.COREAHBLITE_SLAVESTAGE_slavestage_1(trans) because there are no references to its outputs @N:BN115 : coreahblite_matrix2x16.vhd(5026) | Removing instance CoreAHBLite_0.matrix2x16.slavestage_2 of view:coreahblite_lib.COREAHBLITE_SLAVESTAGE_slavestage_1(trans) because there are no references to its outputs @N:BN115 : coreahblite_matrix2x16.vhd(4985) | Removing instance CoreAHBLite_0.matrix2x16.slavestage_1 of view:coreahblite_lib.COREAHBLITE_SLAVESTAGE_slavestage_1(trans) because there are no references to its outputs Available hyper_sources - for debug and ip models None Found @W: : mss_highspeed_timerv2_tmp_mss_ccc_0_mss_ccc.vhd(117) | Net AHB_timer_0/HCLK appears to be a clock source which was not identfied. Assuming default frequency. @W: : mss_highspeed_timerv2_tmp_mss_ccc_0_mss_ccc.vhd(117) | Net mss_highspeed_timerv2_0.MSS_ADLIB_INST_FCLK appears to be a clock source which was not identfied. Assuming default frequency. @W: : mss_highspeed_timerv2_tmp_mss_ccc_0_mss_ccc.vhd(117) | Net AHB_timer_0/FABTIMER_CLK appears to be a clock source which was not identfied. Assuming default frequency. Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 59MB peak: 61MB) @W:MO161 : coreahblite_masterstage.vhd(345) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[16] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.regHSIZE[2] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[31] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[30] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[29] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[28] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[27] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[26] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[25] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[24] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[23] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[22] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[21] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(276) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[20] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(345) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[15] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(345) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[14] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(345) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[13] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(345) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[12] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(345) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[11] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(345) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[10] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(345) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[9] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(345) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[8] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(345) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[7] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(345) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[6] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(345) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[5] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(345) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[4] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(345) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[3] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(345) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[2] is always 0, optimizing ... @W:MO161 : coreahblite_masterstage.vhd(345) | Register bit CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[1] is always 0, optimizing ... Encoding state machine coreahblite_lib.COREAHBLITE_SLAVEARBITER(coreahblite_slavearbiter_arch)-arbRegSMCurrentState[0:7] original code -> new code 000 -> 00000001 001 -> 00000010 010 -> 00000100 011 -> 00001000 100 -> 00010000 101 -> 00100000 110 -> 01000000 111 -> 10000000 @W:MO161 : coreahblite_slavearbiter.vhd(125) | Register bit arbRegSMCurrentState[5] is always 0, optimizing ... @N: : ahb_timer.vhd(346) | Found counter in view:work.AHB_timer(synth) inst prescl_cnt[7:0] Encoding state machine work.AHB_timer(synth)-HCLKSTATE[0:3] original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 60MB peak: 61MB) @N:BN116 : coreahblite_masterstage.vhd(276) | Removing sequential instance CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[19] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_masterstage.vhd(276) | Boundary register CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[19] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_masterstage.vhd(276) | Removing sequential instance CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[18] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_masterstage.vhd(276) | Boundary register CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[18] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_masterstage.vhd(276) | Removing sequential instance CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[17] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_masterstage.vhd(276) | Boundary register CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[17] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_masterstage.vhd(276) | Removing sequential instance CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[16] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_masterstage.vhd(276) | Boundary register CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[16] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_masterstage.vhd(276) | Removing sequential instance CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[15] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_masterstage.vhd(276) | Boundary register CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[15] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_masterstage.vhd(276) | Removing sequential instance CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[14] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_masterstage.vhd(276) | Boundary register CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[14] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_masterstage.vhd(276) | Removing sequential instance CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[13] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_masterstage.vhd(276) | Boundary register CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[13] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_masterstage.vhd(276) | Removing sequential instance CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[12] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_masterstage.vhd(276) | Boundary register CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[12] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_masterstage.vhd(276) | Removing sequential instance CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[11] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_masterstage.vhd(276) | Boundary register CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[11] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_masterstage.vhd(276) | Removing sequential instance CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[10] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_masterstage.vhd(276) | Boundary register CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[10] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_masterstage.vhd(276) | Removing sequential instance CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[9] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_masterstage.vhd(276) | Boundary register CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[9] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_masterstage.vhd(276) | Removing sequential instance CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[8] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_masterstage.vhd(276) | Boundary register CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[8] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_masterstage.vhd(276) | Removing sequential instance CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[7] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_masterstage.vhd(276) | Boundary register CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[7] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_masterstage.vhd(276) | Removing sequential instance CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[6] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_masterstage.vhd(276) | Boundary register CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[6] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : coreahblite_masterstage.vhd(276) | Removing sequential instance CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[5] of view:PrimLib.dffr(prim) because there are no references to its outputs @A:BN291 : coreahblite_masterstage.vhd(276) | Boundary register CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[5] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 60MB peak: 61MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 60MB peak: 61MB) Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 60MB peak: 61MB) Finished Early Timing Optimization (Time elapsed 0h:00m:02s; Memory used current: 60MB peak: 61MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:02s; Memory used current: 60MB peak: 61MB) Finished preparing to map (Time elapsed 0h:00m:02s; Memory used current: 60MB peak: 61MB) High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes -------------------------------------------------------------------------------------------------- mss_highspeed_timerv2_0.MSS_ADLIB_INST / M2FRESETn 206 : 205 asynchronous set/reset CoreAHBLite_0.matrix2x16.slavestage_0.masterDataInProg[0] / Q 25 CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[0] / Q 26 AHB_timer_0.FAB_rcvr_state_seq.un8_reg_load_en2_0_a2 / Y 25 AHB_timer_0.LoadEnReg_1_sqmuxa_0_a2 / Y 25 AHB_timer_0.FAB_rcvr_state_seq.un20_reg_load_en2_0_a2_0 / Y 31 AHB_timer_0.FAB_rcvr_state_seq.un19_reg_load_en2_0_a2_0 / Y 30 ================================================================================================== @N:FP130 : | Promoting Net TIMINT_c on CLKINT AHB_timer_0.TIMINT_int_hclk_inferred_clock Replicating Combinational Instance AHB_timer_0.FAB_rcvr_state_seq.un19_reg_load_en2_0_a2_0, fanout 30 segments 2 Replicating Combinational Instance AHB_timer_0.FAB_rcvr_state_seq.un20_reg_load_en2_0_a2_0, fanout 31 segments 2 Replicating Combinational Instance AHB_timer_0.LoadEnReg_1_sqmuxa_0_a2, fanout 25 segments 2 Replicating Combinational Instance AHB_timer_0.FAB_rcvr_state_seq.un8_reg_load_en2_0_a2, fanout 26 segments 2 Replicating Sequential Instance CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[0], fanout 26 segments 2 Replicating Sequential Instance CoreAHBLite_0.matrix2x16.slavestage_0.masterDataInProg[0], fanout 25 segments 2 Finished technology mapping (Time elapsed 0h:00m:02s; Memory used current: 61MB peak: 61MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:02s; Memory used current: 61MB peak: 61MB) Added 0 Buffers Added 6 Cells via replication Added 2 Sequential Cells via replication Added 4 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:02s; Memory used current: 61MB peak: 61MB) Writing Analyst data base C:\Actelprj\App_notes_upadtes\New\SmartFusion_Timer_DF\Hardware\A2F200\VHDL\highspeed_timerv2\synthesis\top_timer.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:02s; Memory used current: 60MB peak: 61MB) Writing EDIF Netlist and constraint files E-2010.09A-1 Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:03s; Memory used current: 60MB peak: 61MB) @W:MT420 : | Found inferred clock mss_highspeed_timerv2|MSS_ADLIB_INST_EMCCLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:mss_highspeed_timerv2_0.MSS_ADLIB_INST_EMCCLK" @W:MT420 : | Found inferred clock mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:mss_highspeed_timerv2_0_GLC" @W:MT420 : | Found inferred clock mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:mss_highspeed_timerv2_0.MSS_ADLIB_INST_FCLK" @W:MT420 : | Found inferred clock mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:mss_highspeed_timerv2_0_FAB_CLK" @W:MT420 : | Found inferred clock AHB_timer|TIMINT_int_hclk_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:AHB_timer_0.TIMINT_int_hclk" ##### START OF TIMING REPORT #####[ # Timing Report written on Fri Feb 18 11:47:44 2011 # Top view: top_timer Library name: smartfusion Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree ) Requested Frequency: 100.0 MHz Wire load mode: top Wire load model: smartfusion Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: -2.866 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- AHB_timer|TIMINT_int_hclk_inferred_clock 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_1 mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_3 mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock 100.0 MHz 77.7 MHz 10.000 12.866 -2.866 inferred Inferred_clkgroup_2 mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock 100.0 MHz 86.7 MHz 10.000 11.538 -1.538 inferred Inferred_clkgroup_4 ================================================================================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- AHB_timer|TIMINT_int_hclk_inferred_clock mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock | 10.000 -2.866 | No paths - | No paths - | No paths - mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock | Diff grp - | No paths - | No paths - | No paths - mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock | Diff grp - | No paths - | No paths - | No paths - mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock | 10.000 -1.538 | No paths - | No paths - | No paths - =============================================================================================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreAHBLite_0.matrix2x16.masterstage_0.masterRegAddrSel mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock DFN1C0 Q masterRegAddrSel 0.737 -2.866 CoreAHBLite_0.matrix2x16.masterstage_0.regHTRANS mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock DFN1E0C0 Q regHTRANS 0.737 -1.390 CoreAHBLite_0.matrix2x16.masterstage_0.regHMASTLOCK mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock DFN1E0C0 Q regHMASTLOCK 0.737 -1.126 CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[4] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock DFN1C0 Q arbRegSMCurrentState[4] 0.737 -0.881 CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[7] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock DFN1P0 Q arbRegSMCurrentState[7] 0.737 -0.742 CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[3] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock DFN1C0 Q arbRegSMCurrentState[3] 0.737 0.365 AHB_timer_0.HREADYOUT mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock DFN1E1P0 Q CoreAHBLite_0_AHBmslave0_HREADY 0.737 1.217 CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[6] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock DFN1C0 Q arbRegSMCurrentState[6] 0.737 1.262 CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[1] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock DFN1C0 Q arbRegSMCurrentState[1] 0.737 1.290 CoreAHBLite_0.matrix2x16.masterstage_0.SDATASELInt[0] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock DFN1E0C0 Q xhdl1222[0] 0.737 1.870 ========================================================================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- AHB_timer_0.HCLKSTATE[0] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock DFN1C0 D HCLKSTATE_ns[0] 9.427 -2.866 AHB_timer_0.HREADYOUT mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock DFN1E1P0 E N_15 9.392 -1.933 CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[0] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock DFN1E0C0 E N_80 9.392 -1.650 CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[1] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock DFN1E0C0 E N_80 9.392 -1.650 CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[2] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock DFN1E0C0 E N_80 9.392 -1.650 CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[3] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock DFN1E0C0 E N_80 9.392 -1.650 CoreAHBLite_0.matrix2x16.masterstage_0.regHADDR[4] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock DFN1E0C0 E N_80 9.392 -1.650 CoreAHBLite_0.matrix2x16.masterstage_0.regHMASTLOCK mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock DFN1E0C0 E N_80 9.392 -1.650 CoreAHBLite_0.matrix2x16.masterstage_0.regHSIZE[0] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock DFN1E0C0 E N_80 9.392 -1.650 CoreAHBLite_0.matrix2x16.masterstage_0.regHSIZE[1] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock DFN1E0C0 E N_80 9.392 -1.650 =================================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.573 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.427 - Propagation time: 12.292 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -2.866 Number of logic level(s): 8 Starting point: CoreAHBLite_0.matrix2x16.masterstage_0.masterRegAddrSel / Q Ending point: AHB_timer_0.HCLKSTATE[0] / D The start point is clocked by mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------- CoreAHBLite_0.matrix2x16.masterstage_0.masterRegAddrSel DFN1C0 Q Out 0.737 0.737 - masterRegAddrSel Net - - 2.037 - 13 CoreAHBLite_0.matrix2x16.masterstage_0.regHTRANS_RNIGJ8F MX2 S In - 2.774 - CoreAHBLite_0.matrix2x16.masterstage_0.regHTRANS_RNIGJ8F MX2 Y Out 0.396 3.170 - N_171 Net - - 1.776 - 11 CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNINF5A1[4] NOR3B A In - 4.946 - CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNINF5A1[4] NOR3B Y Out 0.641 5.588 - N_95 Net - - 0.322 - 1 CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNI2C1I1[6] NOR2 B In - 5.909 - CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNI2C1I1[6] NOR2 Y Out 0.646 6.556 - N_100 Net - - 0.386 - 2 CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNIIR6S2[1] OR2B B In - 6.941 - CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNIIR6S2[1] OR2B Y Out 0.516 7.457 - masterAddrInProg[0] Net - - 1.279 - 5 AHB_timer_0.HREADYOUT_RNIHE1H4 OR2B B In - 8.737 - AHB_timer_0.HREADYOUT_RNIHE1H4 OR2B Y Out 0.627 9.364 - un6_hsel Net - - 0.322 - 1 AHB_timer_0.reg_load_ack2_RNI4MPN4 MX2 A In - 9.685 - AHB_timer_0.reg_load_ack2_RNI4MPN4 MX2 Y Out 0.568 10.254 - N_11 Net - - 0.322 - 1 AHB_timer_0.HCLKSTATE_RNIDJTN4[0] NOR2 A In - 10.575 - AHB_timer_0.HCLKSTATE_RNIDJTN4[0] NOR2 Y Out 0.363 10.938 - N_15 Net - - 0.386 - 2 AHB_timer_0.HCLKSTATE_RNO[0] OR2 B In - 11.324 - AHB_timer_0.HCLKSTATE_RNO[0] OR2 Y Out 0.646 11.971 - HCLKSTATE_ns[0] Net - - 0.322 - 1 AHB_timer_0.HCLKSTATE[0] DFN1C0 D In - 12.292 - ===================================================================================================================================================== Total path delay (propagation time + setup) of 12.866 is 5.716(44.4%) logic and 7.150(55.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 0.573 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.427 - Propagation time: 12.265 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -2.838 Number of logic level(s): 8 Starting point: CoreAHBLite_0.matrix2x16.masterstage_0.masterRegAddrSel / Q Ending point: AHB_timer_0.HCLKSTATE[0] / D The start point is clocked by mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------- CoreAHBLite_0.matrix2x16.masterstage_0.masterRegAddrSel DFN1C0 Q Out 0.737 0.737 - masterRegAddrSel Net - - 2.037 - 13 CoreAHBLite_0.matrix2x16.masterstage_0.regHTRANS_RNIGJ8F MX2 S In - 2.774 - CoreAHBLite_0.matrix2x16.masterstage_0.regHTRANS_RNIGJ8F MX2 Y Out 0.396 3.170 - N_171 Net - - 1.776 - 11 CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNIAJ921[3] NOR3C C In - 4.946 - CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNIAJ921[3] NOR3C Y Out 0.641 5.588 - N_96 Net - - 0.322 - 1 CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNIGF5A1[1] NOR2 B In - 5.909 - CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNIGF5A1[1] NOR2 Y Out 0.646 6.556 - N_110 Net - - 0.386 - 2 CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNIIR6S2[1] OR2B A In - 6.941 - CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNIIR6S2[1] OR2B Y Out 0.488 7.430 - masterAddrInProg[0] Net - - 1.279 - 5 AHB_timer_0.HREADYOUT_RNIHE1H4 OR2B B In - 8.709 - AHB_timer_0.HREADYOUT_RNIHE1H4 OR2B Y Out 0.627 9.336 - un6_hsel Net - - 0.322 - 1 AHB_timer_0.reg_load_ack2_RNI4MPN4 MX2 A In - 9.658 - AHB_timer_0.reg_load_ack2_RNI4MPN4 MX2 Y Out 0.568 10.226 - N_11 Net - - 0.322 - 1 AHB_timer_0.HCLKSTATE_RNIDJTN4[0] NOR2 A In - 10.547 - AHB_timer_0.HCLKSTATE_RNIDJTN4[0] NOR2 Y Out 0.363 10.911 - N_15 Net - - 0.386 - 2 AHB_timer_0.HCLKSTATE_RNO[0] OR2 B In - 11.297 - AHB_timer_0.HCLKSTATE_RNO[0] OR2 Y Out 0.646 11.943 - HCLKSTATE_ns[0] Net - - 0.322 - 1 AHB_timer_0.HCLKSTATE[0] DFN1C0 D In - 12.265 - ===================================================================================================================================================== Total path delay (propagation time + setup) of 12.838 is 5.688(44.3%) logic and 7.150(55.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 0.573 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.427 - Propagation time: 12.092 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -2.666 Number of logic level(s): 8 Starting point: CoreAHBLite_0.matrix2x16.masterstage_0.masterRegAddrSel / Q Ending point: AHB_timer_0.HCLKSTATE[0] / D The start point is clocked by mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------- CoreAHBLite_0.matrix2x16.masterstage_0.masterRegAddrSel DFN1C0 Q Out 0.737 0.737 - masterRegAddrSel Net - - 2.037 - 13 CoreAHBLite_0.matrix2x16.masterstage_0.regHMASTLOCK_RNII35B MX2 S In - 2.774 - CoreAHBLite_0.matrix2x16.masterstage_0.regHMASTLOCK_RNII35B MX2 Y Out 0.396 3.170 - N_174 Net - - 1.639 - 8 CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNIAJ921[3] NOR3C B In - 4.809 - CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNIAJ921[3] NOR3C Y Out 0.607 5.415 - N_96 Net - - 0.322 - 1 CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNIGF5A1[1] NOR2 B In - 5.737 - CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNIGF5A1[1] NOR2 Y Out 0.646 6.383 - N_110 Net - - 0.386 - 2 CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNIIR6S2[1] OR2B A In - 6.769 - CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNIIR6S2[1] OR2B Y Out 0.488 7.258 - masterAddrInProg[0] Net - - 1.279 - 5 AHB_timer_0.HREADYOUT_RNIHE1H4 OR2B B In - 8.537 - AHB_timer_0.HREADYOUT_RNIHE1H4 OR2B Y Out 0.627 9.164 - un6_hsel Net - - 0.322 - 1 AHB_timer_0.reg_load_ack2_RNI4MPN4 MX2 A In - 9.486 - AHB_timer_0.reg_load_ack2_RNI4MPN4 MX2 Y Out 0.568 10.054 - N_11 Net - - 0.322 - 1 AHB_timer_0.HCLKSTATE_RNIDJTN4[0] NOR2 A In - 10.375 - AHB_timer_0.HCLKSTATE_RNIDJTN4[0] NOR2 Y Out 0.363 10.739 - N_15 Net - - 0.386 - 2 AHB_timer_0.HCLKSTATE_RNO[0] OR2 B In - 11.124 - AHB_timer_0.HCLKSTATE_RNO[0] OR2 Y Out 0.646 11.771 - HCLKSTATE_ns[0] Net - - 0.322 - 1 AHB_timer_0.HCLKSTATE[0] DFN1C0 D In - 12.092 - ===================================================================================================================================================== Total path delay (propagation time + setup) of 12.666 is 5.653(44.6%) logic and 7.013(55.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 11.892 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -2.431 Number of logic level(s): 8 Starting point: CoreAHBLite_0.matrix2x16.masterstage_0.masterRegAddrSel / Q Ending point: AHB_timer_0.HCLKSTATE[0] / D The start point is clocked by mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------- CoreAHBLite_0.matrix2x16.masterstage_0.masterRegAddrSel DFN1C0 Q Out 0.737 0.737 - masterRegAddrSel Net - - 2.037 - 13 CoreAHBLite_0.matrix2x16.masterstage_0.regHMASTLOCK_RNII35B MX2 S In - 2.774 - CoreAHBLite_0.matrix2x16.masterstage_0.regHMASTLOCK_RNII35B MX2 Y Out 0.396 3.170 - N_174 Net - - 1.639 - 8 CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNINF5A1[4] NOR3B C In - 4.809 - CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNINF5A1[4] NOR3B Y Out 0.488 5.297 - N_95 Net - - 0.322 - 1 CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNI2C1I1[6] NOR2 B In - 5.619 - CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNI2C1I1[6] NOR2 Y Out 0.514 6.133 - N_100 Net - - 0.386 - 2 CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNIIR6S2[1] OR2B B In - 6.519 - CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNIIR6S2[1] OR2B Y Out 0.627 7.146 - masterAddrInProg[0] Net - - 1.279 - 5 AHB_timer_0.HREADYOUT_RNIHE1H4 OR2B B In - 8.425 - AHB_timer_0.HREADYOUT_RNIHE1H4 OR2B Y Out 0.516 8.942 - un6_hsel Net - - 0.322 - 1 AHB_timer_0.reg_load_ack2_RNI4MPN4 MX2 A In - 9.263 - AHB_timer_0.reg_load_ack2_RNI4MPN4 MX2 Y Out 0.579 9.842 - N_11 Net - - 0.322 - 1 AHB_timer_0.HCLKSTATE_RNIDJTN4[0] NOR2 A In - 10.163 - AHB_timer_0.HCLKSTATE_RNIDJTN4[0] NOR2 Y Out 0.507 10.671 - N_15 Net - - 0.386 - 2 AHB_timer_0.HCLKSTATE_RNO[0] OR2 B In - 11.057 - AHB_timer_0.HCLKSTATE_RNO[0] OR2 Y Out 0.514 11.571 - HCLKSTATE_ns[0] Net - - 0.322 - 1 AHB_timer_0.HCLKSTATE[0] DFN1C0 D In - 11.892 - ===================================================================================================================================================== Total path delay (propagation time + setup) of 12.431 is 5.418(43.6%) logic and 7.013(56.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 0.608 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.392 - Propagation time: 11.324 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.933 Number of logic level(s): 7 Starting point: CoreAHBLite_0.matrix2x16.masterstage_0.masterRegAddrSel / Q Ending point: AHB_timer_0.HREADYOUT / E The start point is clocked by mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------- CoreAHBLite_0.matrix2x16.masterstage_0.masterRegAddrSel DFN1C0 Q Out 0.737 0.737 - masterRegAddrSel Net - - 2.037 - 13 CoreAHBLite_0.matrix2x16.masterstage_0.regHTRANS_RNIGJ8F MX2 S In - 2.774 - CoreAHBLite_0.matrix2x16.masterstage_0.regHTRANS_RNIGJ8F MX2 Y Out 0.396 3.170 - N_171 Net - - 1.776 - 11 CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNINF5A1[4] NOR3B A In - 4.946 - CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNINF5A1[4] NOR3B Y Out 0.641 5.588 - N_95 Net - - 0.322 - 1 CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNI2C1I1[6] NOR2 B In - 5.909 - CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNI2C1I1[6] NOR2 Y Out 0.646 6.556 - N_100 Net - - 0.386 - 2 CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNIIR6S2[1] OR2B B In - 6.941 - CoreAHBLite_0.matrix2x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNIIR6S2[1] OR2B Y Out 0.516 7.457 - masterAddrInProg[0] Net - - 1.279 - 5 AHB_timer_0.HREADYOUT_RNIHE1H4 OR2B B In - 8.737 - AHB_timer_0.HREADYOUT_RNIHE1H4 OR2B Y Out 0.627 9.364 - un6_hsel Net - - 0.322 - 1 AHB_timer_0.reg_load_ack2_RNI4MPN4 MX2 A In - 9.685 - AHB_timer_0.reg_load_ack2_RNI4MPN4 MX2 Y Out 0.568 10.254 - N_11 Net - - 0.322 - 1 AHB_timer_0.HCLKSTATE_RNIDJTN4[0] NOR2 A In - 10.575 - AHB_timer_0.HCLKSTATE_RNIDJTN4[0] NOR2 Y Out 0.363 10.938 - N_15 Net - - 0.386 - 2 AHB_timer_0.HREADYOUT DFN1E1P0 E In - 11.324 - ======================================================================================================================================================= Total path delay (propagation time + setup) of 11.933 is 5.104(42.8%) logic and 6.828(57.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- AHB_timer_0.prescl_cnt[0] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock DFN1C0 Q prescl_cnt[0] 0.737 -1.538 AHB_timer_0.prescl_cnt[1] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock DFN1C0 Q prescl_cnt[1] 0.737 -0.627 AHB_timer_0.Count[7] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock DFN1E0P0 Q Count[7] 0.737 0.574 AHB_timer_0.prescl_cnt[2] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock DFN1C0 Q prescl_cnt[2] 0.737 0.581 AHB_timer_0.Count[1] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock DFN1E0P0 Q Count[1] 0.737 0.612 AHB_timer_0.Count[13] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock DFN1E0P0 Q Count[13] 0.737 0.669 AHB_timer_0.Count[2] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock DFN1E0P0 Q Count[2] 0.737 0.678 AHB_timer_0.Count[8] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock DFN1E0P0 Q Count[8] 0.737 0.681 AHB_timer_0.Count[6] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock DFN1E0P0 Q Count[6] 0.737 0.697 AHB_timer_0.Count[0] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock DFN1E0P0 Q Count[0] 0.737 0.725 ================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- AHB_timer_0.new_count_pulse mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock DFN1C0 D Count_Pulse 9.427 -1.538 AHB_timer_0.Count[13] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock DFN1E0P0 D Count_5[13] 9.461 0.574 AHB_timer_0.Count[14] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock DFN1E0P0 D Count_5[14] 9.461 0.574 AHB_timer_0.Count[15] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock DFN1E0P0 D Count_5[15] 9.461 0.574 AHB_timer_0.Count[16] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock DFN1E0P0 D Count_5[16] 9.461 0.574 AHB_timer_0.Count[17] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock DFN1E0P0 D Count_5[17] 9.461 0.574 AHB_timer_0.Count[19] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock DFN1E0P0 D Count_5[19] 9.461 0.574 AHB_timer_0.Count[20] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock DFN1E0P0 D Count_5[20] 9.461 0.673 AHB_timer_0.Count[21] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock DFN1E0P0 D Count_5[21] 9.461 0.673 AHB_timer_0.Count[22] mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock DFN1E0P0 D Count_5[22] 9.461 0.673 =================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.573 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.427 - Propagation time: 10.964 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.538 Number of logic level(s): 8 Starting point: AHB_timer_0.prescl_cnt[0] / Q Ending point: AHB_timer_0.new_count_pulse / D The start point is clocked by mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock [rising] on pin CLK The end point is clocked by mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------- AHB_timer_0.prescl_cnt[0] DFN1C0 Q Out 0.737 0.737 - prescl_cnt[0] Net - - 1.184 - 4 AHB_timer_0.prescl_cnt_RNI3BT2[1] NOR2B B In - 1.921 - AHB_timer_0.prescl_cnt_RNI3BT2[1] NOR2B Y Out 0.627 2.548 - prescl_cnt_c1 Net - - 0.806 - 3 AHB_timer_0.prescl_cnt_RNIM0C4[2] OR2B A In - 3.354 - AHB_timer_0.prescl_cnt_RNIM0C4[2] OR2B Y Out 0.514 3.869 - prescl_cnt_c2 Net - - 0.806 - 3 AHB_timer_0.prescl_cnt_RNIAMQ5[3] OR2A B In - 4.675 - AHB_timer_0.prescl_cnt_RNIAMQ5[3] OR2A Y Out 0.514 5.189 - prescl_cnt_c3 Net - - 1.423 - 6 AHB_timer_0.new_count_pulse_RNO_11 OR2B A In - 6.613 - AHB_timer_0.new_count_pulse_RNO_11 OR2B Y Out 0.488 7.101 - Count_Pulse_1_sqmuxa_3_1 Net - - 0.322 - 1 AHB_timer_0.new_count_pulse_RNO_8 NOR3C C In - 7.423 - AHB_timer_0.new_count_pulse_RNO_8 NOR3C Y Out 0.641 8.064 - un1_TimerPre_1_2 Net - - 0.322 - 1 AHB_timer_0.new_count_pulse_RNO_4 AOI1B C In - 8.386 - AHB_timer_0.new_count_pulse_RNO_4 AOI1B Y Out 0.405 8.790 - un1_TimerPre_1_3 Net - - 0.322 - 1 AHB_timer_0.new_count_pulse_RNO_0 OR3C C In - 9.112 - AHB_timer_0.new_count_pulse_RNO_0 OR3C Y Out 0.641 9.753 - un1_TimerPre_1 Net - - 0.322 - 1 AHB_timer_0.new_count_pulse_RNO MX2C A In - 10.075 - AHB_timer_0.new_count_pulse_RNO MX2C Y Out 0.568 10.643 - Count_Pulse Net - - 0.322 - 1 AHB_timer_0.new_count_pulse DFN1C0 D In - 10.964 - =================================================================================================== Total path delay (propagation time + setup) of 11.538 is 5.711(49.5%) logic and 5.827(50.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 0.573 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.427 - Propagation time: 10.294 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.867 Number of logic level(s): 7 Starting point: AHB_timer_0.prescl_cnt[0] / Q Ending point: AHB_timer_0.new_count_pulse / D The start point is clocked by mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock [rising] on pin CLK The end point is clocked by mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------- AHB_timer_0.prescl_cnt[0] DFN1C0 Q Out 0.737 0.737 - prescl_cnt[0] Net - - 1.184 - 4 AHB_timer_0.prescl_cnt_RNI3BT2[1] NOR2B B In - 1.921 - AHB_timer_0.prescl_cnt_RNI3BT2[1] NOR2B Y Out 0.627 2.548 - prescl_cnt_c1 Net - - 0.806 - 3 AHB_timer_0.prescl_cnt_RNIM0C4[2] OR2B A In - 3.354 - AHB_timer_0.prescl_cnt_RNIM0C4[2] OR2B Y Out 0.514 3.869 - prescl_cnt_c2 Net - - 0.806 - 3 AHB_timer_0.prescl_cnt_RNIAMQ5[3] OR2A B In - 4.675 - AHB_timer_0.prescl_cnt_RNIAMQ5[3] OR2A Y Out 0.514 5.189 - prescl_cnt_c3 Net - - 1.423 - 6 AHB_timer_0.prescl_cnt_RNIVB97[4] OR2A B In - 6.613 - AHB_timer_0.prescl_cnt_RNIVB97[4] OR2A Y Out 0.514 7.127 - un23_prescl_cnt Net - - 0.386 - 2 AHB_timer_0.new_count_pulse_RNO_4 AOI1B B In - 7.513 - AHB_timer_0.new_count_pulse_RNO_4 AOI1B Y Out 0.607 8.120 - un1_TimerPre_1_3 Net - - 0.322 - 1 AHB_timer_0.new_count_pulse_RNO_0 OR3C C In - 8.441 - AHB_timer_0.new_count_pulse_RNO_0 OR3C Y Out 0.641 9.082 - un1_TimerPre_1 Net - - 0.322 - 1 AHB_timer_0.new_count_pulse_RNO MX2C A In - 9.404 - AHB_timer_0.new_count_pulse_RNO MX2C Y Out 0.568 9.972 - Count_Pulse Net - - 0.322 - 1 AHB_timer_0.new_count_pulse DFN1C0 D In - 10.294 - ================================================================================================== Total path delay (propagation time + setup) of 10.867 is 5.297(48.7%) logic and 5.570(51.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 0.573 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.427 - Propagation time: 10.276 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.850 Number of logic level(s): 7 Starting point: AHB_timer_0.prescl_cnt[0] / Q Ending point: AHB_timer_0.new_count_pulse / D The start point is clocked by mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock [rising] on pin CLK The end point is clocked by mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------- AHB_timer_0.prescl_cnt[0] DFN1C0 Q Out 0.737 0.737 - prescl_cnt[0] Net - - 1.184 - 4 AHB_timer_0.prescl_cnt_RNI3BT2[1] NOR2B B In - 1.921 - AHB_timer_0.prescl_cnt_RNI3BT2[1] NOR2B Y Out 0.627 2.548 - prescl_cnt_c1 Net - - 0.806 - 3 AHB_timer_0.prescl_cnt_RNIM0C4[2] OR2B A In - 3.354 - AHB_timer_0.prescl_cnt_RNIM0C4[2] OR2B Y Out 0.514 3.869 - prescl_cnt_c2 Net - - 0.806 - 3 AHB_timer_0.prescl_cnt_RNIAMQ5[3] OR2A B In - 4.675 - AHB_timer_0.prescl_cnt_RNIAMQ5[3] OR2A Y Out 0.514 5.189 - prescl_cnt_c3 Net - - 1.423 - 6 AHB_timer_0.prescl_cnt_RNIL1O8[5] OR2A B In - 6.613 - AHB_timer_0.prescl_cnt_RNIL1O8[5] OR2A Y Out 0.514 7.127 - un27_prescl_cnt Net - - 0.386 - 2 AHB_timer_0.new_count_pulse_RNO_3 OR3B B In - 7.513 - AHB_timer_0.new_count_pulse_RNO_3 OR3B Y Out 0.624 8.137 - Count_Pulse_1_sqmuxa_5_3 Net - - 0.322 - 1 AHB_timer_0.new_count_pulse_RNO_0 OR3C B In - 8.459 - AHB_timer_0.new_count_pulse_RNO_0 OR3C Y Out 0.607 9.065 - un1_TimerPre_1 Net - - 0.322 - 1 AHB_timer_0.new_count_pulse_RNO MX2C A In - 9.386 - AHB_timer_0.new_count_pulse_RNO MX2C Y Out 0.568 9.955 - Count_Pulse Net - - 0.322 - 1 AHB_timer_0.new_count_pulse DFN1C0 D In - 10.276 - ================================================================================================== Total path delay (propagation time + setup) of 10.850 is 5.280(48.7%) logic and 5.570(51.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 0.573 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.427 - Propagation time: 10.176 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.749 Number of logic level(s): 7 Starting point: AHB_timer_0.prescl_cnt[0] / Q Ending point: AHB_timer_0.new_count_pulse / D The start point is clocked by mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock [rising] on pin CLK The end point is clocked by mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------- AHB_timer_0.prescl_cnt[0] DFN1C0 Q Out 0.737 0.737 - prescl_cnt[0] Net - - 1.184 - 4 AHB_timer_0.prescl_cnt_RNI3BT2[1] NOR2B B In - 1.921 - AHB_timer_0.prescl_cnt_RNI3BT2[1] NOR2B Y Out 0.627 2.548 - prescl_cnt_c1 Net - - 0.806 - 3 AHB_timer_0.prescl_cnt_RNIM0C4[2] OR2B A In - 3.354 - AHB_timer_0.prescl_cnt_RNIM0C4[2] OR2B Y Out 0.514 3.869 - prescl_cnt_c2 Net - - 0.806 - 3 AHB_timer_0.prescl_cnt_RNIAMQ5[3] OR2A B In - 4.675 - AHB_timer_0.prescl_cnt_RNIAMQ5[3] OR2A Y Out 0.514 5.189 - prescl_cnt_c3 Net - - 1.423 - 6 AHB_timer_0.prescl_cnt_RNICN6A[6] OR2A B In - 6.613 - AHB_timer_0.prescl_cnt_RNICN6A[6] OR2A Y Out 0.514 7.127 - un31_prescl_cnt Net - - 0.386 - 2 AHB_timer_0.new_count_pulse_RNO_2 OR3C C In - 7.513 - AHB_timer_0.new_count_pulse_RNO_2 OR3C Y Out 0.666 8.179 - Count_Pulse_1_sqmuxa_6_3 Net - - 0.322 - 1 AHB_timer_0.new_count_pulse_RNO_0 OR3C A In - 8.500 - AHB_timer_0.new_count_pulse_RNO_0 OR3C Y Out 0.464 8.964 - un1_TimerPre_1 Net - - 0.322 - 1 AHB_timer_0.new_count_pulse_RNO MX2C A In - 9.286 - AHB_timer_0.new_count_pulse_RNO MX2C Y Out 0.568 9.854 - Count_Pulse Net - - 0.322 - 1 AHB_timer_0.new_count_pulse DFN1C0 D In - 10.176 - ================================================================================================== Total path delay (propagation time + setup) of 10.749 is 5.179(48.2%) logic and 5.570(51.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 0.573 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.427 - Propagation time: 10.054 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.627 Number of logic level(s): 8 Starting point: AHB_timer_0.prescl_cnt[1] / Q Ending point: AHB_timer_0.new_count_pulse / D The start point is clocked by mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock [rising] on pin CLK The end point is clocked by mss_highspeed_timerv2_tmp_MSS_CCC_0_MSS_CCC|mss_highspeed_timerv2_0_GLC_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------- AHB_timer_0.prescl_cnt[1] DFN1C0 Q Out 0.737 0.737 - prescl_cnt[1] Net - - 0.386 - 2 AHB_timer_0.prescl_cnt_RNI3BT2[1] NOR2B A In - 1.123 - AHB_timer_0.prescl_cnt_RNI3BT2[1] NOR2B Y Out 0.514 1.637 - prescl_cnt_c1 Net - - 0.806 - 3 AHB_timer_0.prescl_cnt_RNIM0C4[2] OR2B A In - 2.443 - AHB_timer_0.prescl_cnt_RNIM0C4[2] OR2B Y Out 0.514 2.958 - prescl_cnt_c2 Net - - 0.806 - 3 AHB_timer_0.prescl_cnt_RNIAMQ5[3] OR2A B In - 3.764 - AHB_timer_0.prescl_cnt_RNIAMQ5[3] OR2A Y Out 0.514 4.279 - prescl_cnt_c3 Net - - 1.423 - 6 AHB_timer_0.new_count_pulse_RNO_11 OR2B A In - 5.702 - AHB_timer_0.new_count_pulse_RNO_11 OR2B Y Out 0.488 6.190 - Count_Pulse_1_sqmuxa_3_1 Net - - 0.322 - 1 AHB_timer_0.new_count_pulse_RNO_8 NOR3C C In - 6.512 - AHB_timer_0.new_count_pulse_RNO_8 NOR3C Y Out 0.641 7.153 - un1_TimerPre_1_2 Net - - 0.322 - 1 AHB_timer_0.new_count_pulse_RNO_4 AOI1B C In - 7.475 - AHB_timer_0.new_count_pulse_RNO_4 AOI1B Y Out 0.405 7.880 - un1_TimerPre_1_3 Net - - 0.322 - 1 AHB_timer_0.new_count_pulse_RNO_0 OR3C C In - 8.201 - AHB_timer_0.new_count_pulse_RNO_0 OR3C Y Out 0.641 8.842 - un1_TimerPre_1 Net - - 0.322 - 1 AHB_timer_0.new_count_pulse_RNO MX2C A In - 9.164 - AHB_timer_0.new_count_pulse_RNO MX2C Y Out 0.568 9.732 - Count_Pulse Net - - 0.322 - 1 AHB_timer_0.new_count_pulse DFN1C0 D In - 10.054 - =================================================================================================== Total path delay (propagation time + setup) of 10.627 is 5.598(52.7%) logic and 5.030(47.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Target Part: A2F200M3F_FBGA484_Std Report for cell top_timer.def_arch Core Cell usage: cell count area count*area AND2 4 1.0 4.0 AND2A 3 1.0 3.0 AND3 16 1.0 16.0 AND3A 6 1.0 6.0 AND3B 3 1.0 3.0 AO1 20 1.0 20.0 AO1A 1 1.0 1.0 AO1B 2 1.0 2.0 AO1C 2 1.0 2.0 AOI1B 7 1.0 7.0 CLKINT 1 0.0 0.0 GND 11 0.0 0.0 INV 3 1.0 3.0 MSS_CCC 1 0.0 0.0 MX2 35 1.0 35.0 MX2A 1 1.0 1.0 MX2C 2 1.0 2.0 NOR2 12 1.0 12.0 NOR2A 8 1.0 8.0 NOR2B 56 1.0 56.0 NOR3 22 1.0 22.0 NOR3A 5 1.0 5.0 NOR3B 68 1.0 68.0 NOR3C 7 1.0 7.0 OA1 1 1.0 1.0 OA1A 3 1.0 3.0 OR2 4 1.0 4.0 OR2A 10 1.0 10.0 OR2B 16 1.0 16.0 OR3 23 1.0 23.0 OR3A 9 1.0 9.0 OR3B 14 1.0 14.0 OR3C 12 1.0 12.0 RCOSC 1 0.0 0.0 VCC 11 0.0 0.0 XA1B 2 1.0 2.0 XA1C 5 1.0 5.0 XNOR2 2 1.0 2.0 XOR2 23 1.0 23.0 XOR3 1 1.0 1.0 DFN1 1 1.0 1.0 DFN1C0 52 1.0 52.0 DFN1C1 1 1.0 1.0 DFN1E0C0 18 1.0 18.0 DFN1E0P0 24 1.0 24.0 DFN1E1C0 62 1.0 62.0 DFN1E1P0 49 1.0 49.0 DFN1P0 2 1.0 2.0 MSS_AHB 1 0.0 0.0 ----- ---------- TOTAL 643 617.0 IO Cell usage: cell count INBUF 1 INBUF_MSS 2 OUTBUF 5 OUTBUF_MSS 1 ----- TOTAL 9 Core Cells : 617 of 4608 (13%) IO Cells : 9 RAM/ROM Usage Summary Block Rams : 0 of 8 (0%) Mapper successful! Process took 0h:00m:04s realtime, 0h:00m:03s cputime # Fri Feb 18 11:47:44 2011 ###########################################################]