Timing Report Min Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Mon Dec 12 14:07:54 2011


Design: top_timer
Family: SmartFusion
Die: A2F200M3F
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               AHB_timer_0/TIMINT_int_hclk:Q
Period (ns):                0.698
Frequency (MHz):            1432.665
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                12.791
Frequency (MHz):            78.180
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      7.439
Max Clock-To-Out (ns):      12.125

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        -5.119
External Hold (ns):         4.172
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_glc
Period (ns):                8.826
Frequency (MHz):            113.302
Required Period (ns):       8.333
Required Frequency (MHz):   120.005
External Setup (ns):        5.649
External Hold (ns):         -0.240
Min Clock-To-Out (ns):      3.975
Max Clock-To-Out (ns):      10.220

Clock Domain:               \\Timerv2\\/MSS_CCC_0/I_RCOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             2.333
Max Delay (ns):             4.786

END SUMMARY
-----------------------------------------------------

Clock Domain AHB_timer_0/TIMINT_int_hclk:Q

Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin AHB_timer_0/TIMINT_pending_int:CLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        AHB_timer_0/reg_load_en0/U1:CLK
  To:                          AHB_timer_0/reg_load_en0/U1:D
  Delay (ns):                  0.789
  Slack (ns):                  0.770
  Arrival (ns):                5.133
  Required (ns):               4.363
  Hold (ns):                   0.000

Path 2
  From:                        AHB_timer_0/reg_load_ack1:CLK
  To:                          AHB_timer_0/reg_load_ack2:D
  Delay (ns):                  0.804
  Slack (ns):                  0.775
  Arrival (ns):                5.127
  Required (ns):               4.352
  Hold (ns):                   0.000

Path 3
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[10]/U1:CLK
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[10]/U1:D
  Delay (ns):                  0.796
  Slack (ns):                  0.778
  Arrival (ns):                5.138
  Required (ns):               4.360
  Hold (ns):                   0.000

Path 4
  From:                        CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState[0]:CLK
  To:                          CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState[0]:D
  Delay (ns):                  0.795
  Slack (ns):                  0.778
  Arrival (ns):                5.131
  Required (ns):               4.353
  Hold (ns):                   0.000

Path 5
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[3]/U1:CLK
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[3]/U1:D
  Delay (ns):                  0.796
  Slack (ns):                  0.780
  Arrival (ns):                5.127
  Required (ns):               4.347
  Hold (ns):                   0.000


Expanded Path 1
  From: AHB_timer_0/reg_load_en0/U1:CLK
  To: AHB_timer_0/reg_load_en0/U1:D
  data arrival time                              5.133
  data required time                         -   4.363
  slack                                          0.770
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.309          net: mss_highspeed_timerv2_0_FAB_CLK
  4.344                        AHB_timer_0/reg_load_en0/U1:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  4.592                        AHB_timer_0/reg_load_en0/U1:Q (r)
               +     0.149          net: AHB_timer_0/reg_load_en0
  4.741                        AHB_timer_0/reg_load_en0/U0:A (r)
               +     0.243          cell: ADLIB:MX2
  4.984                        AHB_timer_0/reg_load_en0/U0:Y (r)
               +     0.149          net: AHB_timer_0/reg_load_en0/Y
  5.133                        AHB_timer_0/reg_load_en0/U1:D (r)
                                    
  5.133                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.328          net: mss_highspeed_timerv2_0_FAB_CLK
  4.363                        AHB_timer_0/reg_load_en0/U1:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  4.363                        AHB_timer_0/reg_load_en0/U1:D
                                    
  4.363                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        AHB_timer_0/TIMINT_int_hclk:CLK
  To:                          TIMINT
  Delay (ns):                  3.126
  Slack (ns):
  Arrival (ns):                7.439
  Required (ns):
  Clock to Out (ns):           7.439


Expanded Path 1
  From: AHB_timer_0/TIMINT_int_hclk:CLK
  To: TIMINT
  data arrival time                              7.439
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.278          net: mss_highspeed_timerv2_0_FAB_CLK
  4.313                        AHB_timer_0/TIMINT_int_hclk:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  4.561                        AHB_timer_0/TIMINT_int_hclk:Q (r)
               +     0.830          net: AHB_timer_0/TIMINT_int_hclk_i
  5.391                        AHB_timer_0/TIMINT_int_hclk_RNI4603/U_CLKSRC:A (r)
               +     0.329          cell: ADLIB:CLKSRC
  5.720                        AHB_timer_0/TIMINT_int_hclk_RNI4603/U_CLKSRC:Y (r)
               +     0.324          net: TIMINT_c
  6.044                        TIMINT_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  6.323                        TIMINT_pad/U0/U1:DOUT (r)
               +     0.000          net: TIMINT_pad/U0/NET1
  6.323                        TIMINT_pad/U0/U0:D (r)
               +     1.116          cell: ADLIB:IOPAD_TRI
  7.439                        TIMINT_pad/U0/U0:PAD (r)
               +     0.000          net: TIMINT
  7.439                        TIMINT (r)
                                    
  7.439                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  N/C
                                    
  N/C                          TIMINT (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla0 to mss_ccc_gla1

Path 1
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          AHB_timer_0/DataOut_int[18]:CLR
  Delay (ns):                  2.010
  Slack (ns):                  0.672
  Arrival (ns):                5.042
  Required (ns):               4.370
  Hold (ns):

Path 2
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[1]/U1:CLR
  Delay (ns):                  2.387
  Slack (ns):                  1.059
  Arrival (ns):                5.419
  Required (ns):               4.360
  Hold (ns):

Path 3
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          AHB_timer_0/HREADYOUT/U1:PRE
  Delay (ns):                  2.403
  Slack (ns):                  1.063
  Arrival (ns):                5.435
  Required (ns):               4.372
  Hold (ns):

Path 4
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/CLDATASELInt_ORED/U1:CLR
  Delay (ns):                  2.403
  Slack (ns):                  1.063
  Arrival (ns):                5.435
  Required (ns):               4.372
  Hold (ns):

Path 5
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/CLDATASELInt[11]/U1:CLR
  Delay (ns):                  2.403
  Slack (ns):                  1.063
  Arrival (ns):                5.435
  Required (ns):               4.372
  Hold (ns):


Expanded Path 1
  From: _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To: AHB_timer_0/DataOut_int[18]:CLR
  data arrival time                              5.042
  data required time                         -   4.370
  slack                                          0.672
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  2.724
               +     0.308          net: _Timerv2_/MSS_ADLIB_INST_FCLK
  3.032                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.705          cell: ADLIB:MSS_AHB_IP
  4.737                        _Timerv2_/MSS_ADLIB_INST/U_CORE:M2FRESETn (r)
               +     0.060          net: _Timerv2_/MSS_ADLIB_INST/M2FRESETnINT_NET
  4.797                        _Timerv2_/MSS_ADLIB_INST/U_46:PIN2INT (r)
               +     0.044          cell: ADLIB:MSS_IF
  4.841                        _Timerv2_/MSS_ADLIB_INST/U_46:PIN2 (r)
               +     0.201          net: mss_highspeed_timerv2_0_M2F_RESET_N
  5.042                        AHB_timer_0/DataOut_int[18]:CLR (r)
                                    
  5.042                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.335          net: mss_highspeed_timerv2_0_FAB_CLK
  4.370                        AHB_timer_0/DataOut_int[18]:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1C0
  4.370                        AHB_timer_0/DataOut_int[18]:CLR
                                    
  4.370                        data required time


END SET mss_ccc_gla0 to mss_ccc_gla1

----------------------------------------------------

SET mss_ccc_glc to mss_ccc_gla1

Path 1
  From:                        AHB_timer_0/reg_load_ack0/U1:CLK
  To:                          AHB_timer_0/reg_load_ack1:D
  Delay (ns):                  0.429
  Slack (ns):                  -2.646
  Arrival (ns):                1.692
  Required (ns):               4.338
  Hold (ns):                   0.000

Path 2
  From:                        AHB_timer_0/DataOut[15]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[15]:D
  Delay (ns):                  0.434
  Slack (ns):                  -2.636
  Arrival (ns):                1.716
  Required (ns):               4.352
  Hold (ns):                   0.000

Path 3
  From:                        AHB_timer_0/DataOut[0]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[0]:D
  Delay (ns):                  0.429
  Slack (ns):                  -2.635
  Arrival (ns):                1.711
  Required (ns):               4.346
  Hold (ns):                   0.000

Path 4
  From:                        AHB_timer_0/DataOut[12]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[12]:D
  Delay (ns):                  0.429
  Slack (ns):                  -2.633
  Arrival (ns):                1.695
  Required (ns):               4.328
  Hold (ns):                   0.000

Path 5
  From:                        AHB_timer_0/DataOut[10]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[10]:D
  Delay (ns):                  0.663
  Slack (ns):                  -2.415
  Arrival (ns):                1.945
  Required (ns):               4.360
  Hold (ns):                   0.000


Expanded Path 1
  From: AHB_timer_0/reg_load_ack0/U1:CLK
  To: AHB_timer_0/reg_load_ack1:D
  data arrival time                              1.692
  data required time                         -   4.338
  slack                                          -2.646
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.957          Clock generation
  0.957
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.306          net: Timerv2_GLC
  1.263                        AHB_timer_0/reg_load_ack0/U1:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  1.511                        AHB_timer_0/reg_load_ack0/U1:Q (r)
               +     0.181          net: AHB_timer_0/reg_load_ack0
  1.692                        AHB_timer_0/reg_load_ack1:D (r)
                                    
  1.692                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.303          net: mss_highspeed_timerv2_0_FAB_CLK
  4.338                        AHB_timer_0/reg_load_ack1:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  4.338                        AHB_timer_0/reg_load_ack1:D
                                    
  4.338                        data required time


END SET mss_ccc_glc to mss_ccc_gla1

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_gla1

Path 1
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHMASTLOCK/U1:D
  Delay (ns):                  2.391
  Slack (ns):                  1.074
  Arrival (ns):                5.423
  Required (ns):               4.349
  Hold (ns):                   0.000

Path 2
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHWRITE/U1:D
  Delay (ns):                  2.405
  Slack (ns):                  1.088
  Arrival (ns):                5.437
  Required (ns):               4.349
  Hold (ns):                   0.000

Path 3
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[4]/U1:D
  Delay (ns):                  2.465
  Slack (ns):                  1.137
  Arrival (ns):                5.497
  Required (ns):               4.360
  Hold (ns):                   0.000

Path 4
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[12]/U1:D
  Delay (ns):                  2.504
  Slack (ns):                  1.176
  Arrival (ns):                5.536
  Required (ns):               4.360
  Hold (ns):                   0.000

Path 5
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[15]/U1:D
  Delay (ns):                  2.803
  Slack (ns):                  1.472
  Arrival (ns):                5.835
  Required (ns):               4.363
  Hold (ns):                   0.000


Expanded Path 1
  From: _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To: CoreAHBLite_0/matrix2x16/masterstage_0/regHMASTLOCK/U1:D
  data arrival time                              5.423
  data required time                         -   4.349
  slack                                          1.074
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.032          Clock generation
  3.032
               +     1.671          cell: ADLIB:MSS_AHB_IP
  4.703                        _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHLOCK (f)
               +     0.079          net: _Timerv2_/MSS_ADLIB_INST/MSSHLOCKINT_NET
  4.782                        _Timerv2_/MSS_ADLIB_INST/U_59:PIN1INT (f)
               +     0.042          cell: ADLIB:MSS_IF
  4.824                        _Timerv2_/MSS_ADLIB_INST/U_59:PIN1 (f)
               +     0.204          net: mss_highspeed_timerv2_0_MSS_MASTER_AHB_LITE_HLOCK
  5.028                        CoreAHBLite_0/matrix2x16/masterstage_0/regHMASTLOCK/U0:B (f)
               +     0.248          cell: ADLIB:MX2
  5.276                        CoreAHBLite_0/matrix2x16/masterstage_0/regHMASTLOCK/U0:Y (f)
               +     0.147          net: CoreAHBLite_0/matrix2x16/masterstage_0/regHMASTLOCK/Y
  5.423                        CoreAHBLite_0/matrix2x16/masterstage_0/regHMASTLOCK/U1:D (f)
                                    
  5.423                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.314          net: mss_highspeed_timerv2_0_FAB_CLK
  4.349                        CoreAHBLite_0/matrix2x16/masterstage_0/regHMASTLOCK/U1:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  4.349                        CoreAHBLite_0/matrix2x16/masterstage_0/regHMASTLOCK/U1:D
                                    
  4.349                        data required time


END SET mss_fabric_interface_clock to mss_ccc_gla1

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.276
  Slack (ns):
  Arrival (ns):                0.276
  Required (ns):
  Hold (ns):                   1.354
  External Hold (ns):          4.172


Expanded Path 1
  From: MSS_RESET_N
  To: _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.276
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        \\Timerv2\\/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.276          cell: ADLIB:IOPAD_IN
  0.276                        \\Timerv2\\/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: _Timerv2_/MSS_RESET_0_MSS_RESET_N_Y
  0.276                        _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.276                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  N/C
               +     0.370          net: _Timerv2_/MSS_ADLIB_INST_FCLK
  N/C                          _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.354          Library hold time: ADLIB:MSS_AHB_IP
  N/C                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glc

SET Register to Register

Path 1
  From:                        AHB_timer_0/reg_load_en1:CLK
  To:                          AHB_timer_0/reg_load_en2:D
  Delay (ns):                  0.402
  Slack (ns):                  0.377
  Arrival (ns):                1.684
  Required (ns):               1.307
  Hold (ns):                   0.000

Path 2
  From:                        AHB_timer_0/p_strecth_TIMINT_pulse.TIMINT_pulse_int[1]:CLK
  To:                          AHB_timer_0/p_strecth_TIMINT_pulse.TIMINT_pulse_int[2]:D
  Delay (ns):                  0.428
  Slack (ns):                  0.412
  Arrival (ns):                1.671
  Required (ns):               1.259
  Hold (ns):                   0.000

Path 3
  From:                        AHB_timer_0/p_strecth_TIMINT_pulse.TIMINT_pulse_int[2]:CLK
  To:                          AHB_timer_0/p_strecth_TIMINT_pulse.TIMINT_pulse_int[3]:D
  Delay (ns):                  0.429
  Slack (ns):                  0.413
  Arrival (ns):                1.672
  Required (ns):               1.259
  Hold (ns):                   0.000

Path 4
  From:                        AHB_timer_0/Sample[0]:CLK
  To:                          AHB_timer_0/Sample[1]:D
  Delay (ns):                  0.478
  Slack (ns):                  0.436
  Arrival (ns):                1.721
  Required (ns):               1.285
  Hold (ns):                   0.000

Path 5
  From:                        AHB_timer_0/prescl_cnt[0]:CLK
  To:                          AHB_timer_0/prescl_cnt[0]:D
  Delay (ns):                  0.697
  Slack (ns):                  0.681
  Arrival (ns):                1.954
  Required (ns):               1.273
  Hold (ns):                   0.000


Expanded Path 1
  From: AHB_timer_0/reg_load_en1:CLK
  To: AHB_timer_0/reg_load_en2:D
  data arrival time                              1.684
  data required time                         -   1.307
  slack                                          0.377
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.957          Clock generation
  0.957
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.325          net: Timerv2_GLC
  1.282                        AHB_timer_0/reg_load_en1:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  1.530                        AHB_timer_0/reg_load_en1:Q (r)
               +     0.154          net: AHB_timer_0/reg_load_en1
  1.684                        AHB_timer_0/reg_load_en2:D (r)
                                    
  1.684                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.957          Clock generation
  0.957
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.350          net: Timerv2_GLC
  1.307                        AHB_timer_0/reg_load_en2:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  1.307                        AHB_timer_0/reg_load_en2:D
                                    
  1.307                        data required time


END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        Pulse_in
  To:                          AHB_timer_0/Sample[0]:D
  Delay (ns):                  1.541
  Slack (ns):
  Arrival (ns):                1.541
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -0.240

Path 2
  From:                        Pulse_in
  To:                          AHB_timer_0/Count[2]/U1:D
  Delay (ns):                  2.993
  Slack (ns):
  Arrival (ns):                2.993
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -1.666

Path 3
  From:                        Pulse_in
  To:                          AHB_timer_0/Count[14]/U1:D
  Delay (ns):                  2.993
  Slack (ns):
  Arrival (ns):                2.993
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -1.678

Path 4
  From:                        Pulse_in
  To:                          AHB_timer_0/Count[3]/U1:D
  Delay (ns):                  2.993
  Slack (ns):
  Arrival (ns):                2.993
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -1.678

Path 5
  From:                        Pulse_in
  To:                          AHB_timer_0/Count[4]/U1:D
  Delay (ns):                  3.257
  Slack (ns):
  Arrival (ns):                3.257
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -1.943


Expanded Path 1
  From: Pulse_in
  To: AHB_timer_0/Sample[0]:D
  data arrival time                              1.541
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        Pulse_in (f)
               +     0.000          net: Pulse_in
  0.000                        Pulse_in_pad/U0/U0:PAD (f)
               +     0.276          cell: ADLIB:IOPAD_IN
  0.276                        Pulse_in_pad/U0/U0:Y (f)
               +     0.000          net: Pulse_in_pad/U0/NET1
  0.276                        Pulse_in_pad/U0/U1:YIN (f)
               +     0.018          cell: ADLIB:IOIN_IB
  0.294                        Pulse_in_pad/U0/U1:Y (f)
               +     1.247          net: Pulse_in_c_c
  1.541                        AHB_timer_0/Sample[0]:D (f)
                                    
  1.541                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glc
               +     0.000          Clock source
  N/C                          \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.957          Clock generation
  N/C
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  N/C                          \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.344          net: Timerv2_GLC
  N/C                          AHB_timer_0/Sample[0]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          AHB_timer_0/Sample[0]:D


END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        AHB_timer_0/Count[23]/U1:CLK
  To:                          Test_port[2]
  Delay (ns):                  2.740
  Slack (ns):
  Arrival (ns):                3.975
  Required (ns):
  Clock to Out (ns):           3.975

Path 2
  From:                        AHB_timer_0/count_zero_blk_instance/count23_3_zero:CLK
  To:                          Test_port[3]
  Delay (ns):                  3.839
  Slack (ns):
  Arrival (ns):                5.108
  Required (ns):
  Clock to Out (ns):           5.108

Path 3
  From:                        AHB_timer_0/Count[2]/U1:CLK
  To:                          Test_port[3]
  Delay (ns):                  3.908
  Slack (ns):
  Arrival (ns):                5.172
  Required (ns):
  Clock to Out (ns):           5.172

Path 4
  From:                        AHB_timer_0/Count[0]/U1:CLK
  To:                          Test_port[3]
  Delay (ns):                  3.915
  Slack (ns):
  Arrival (ns):                5.179
  Required (ns):
  Clock to Out (ns):           5.179

Path 5
  From:                        AHB_timer_0/Count[1]/U1:CLK
  To:                          Test_port[3]
  Delay (ns):                  4.305
  Slack (ns):
  Arrival (ns):                5.569
  Required (ns):
  Clock to Out (ns):           5.569


Expanded Path 1
  From: AHB_timer_0/Count[23]/U1:CLK
  To: Test_port[2]
  data arrival time                              3.975
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.957          Clock generation
  0.957
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.278          net: Timerv2_GLC
  1.235                        AHB_timer_0/Count[23]/U1:CLK (r)
               +     0.248          cell: ADLIB:DFN1P0
  1.483                        AHB_timer_0/Count[23]/U1:Q (r)
               +     1.120          net: Test_port_c[2]
  2.603                        Test_port_pad[2]/U0/U1:D (r)
               +     0.256          cell: ADLIB:IOTRI_OB_EB
  2.859                        Test_port_pad[2]/U0/U1:DOUT (r)
               +     0.000          net: Test_port_pad[2]/U0/NET1
  2.859                        Test_port_pad[2]/U0/U0:D (r)
               +     1.116          cell: ADLIB:IOPAD_TRI
  3.975                        Test_port_pad[2]/U0/U0:PAD (r)
               +     0.000          net: Test_port[2]
  3.975                        Test_port[2] (r)
                                    
  3.975                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glc
               +     0.000          Clock source
  N/C                          \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.957          Clock generation
  N/C
                                    
  N/C                          Test_port[2] (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_ccc_glc

Path 1
  From:                        AHB_timer_0/reg_load_en0/U1:CLK
  To:                          AHB_timer_0/reg_load_en1:D
  Delay (ns):                  0.930
  Slack (ns):                  3.970
  Arrival (ns):                5.274
  Required (ns):               1.304
  Hold (ns):                   0.000

Path 2
  From:                        CoreAHBLite_0/matrix2x16/slavestage_5/masterDataInProg[1]/U1:CLK
  To:                          AHB_timer_0/Load[4]/U1:D
  Delay (ns):                  1.335
  Slack (ns):                  4.411
  Arrival (ns):                5.677
  Required (ns):               1.266
  Hold (ns):                   0.000

Path 3
  From:                        CoreAHBLite_0/matrix2x16/slavestage_5/masterDataInProg_0[0]/U1:CLK
  To:                          AHB_timer_0/Load[7]/U1:D
  Delay (ns):                  1.408
  Slack (ns):                  4.448
  Arrival (ns):                5.752
  Required (ns):               1.304
  Hold (ns):                   0.000

Path 4
  From:                        CoreAHBLite_0/matrix2x16/slavestage_5/masterDataInProg_0[0]/U1:CLK
  To:                          AHB_timer_0/Load[5]/U1:D
  Delay (ns):                  1.408
  Slack (ns):                  4.448
  Arrival (ns):                5.752
  Required (ns):               1.304
  Hold (ns):                   0.000

Path 5
  From:                        CoreAHBLite_0/matrix2x16/slavestage_5/masterDataInProg_0[0]/U1:CLK
  To:                          AHB_timer_0/Load[4]/U1:D
  Delay (ns):                  1.408
  Slack (ns):                  4.486
  Arrival (ns):                5.752
  Required (ns):               1.266
  Hold (ns):                   0.000


Expanded Path 1
  From: AHB_timer_0/reg_load_en0/U1:CLK
  To: AHB_timer_0/reg_load_en1:D
  data arrival time                              5.274
  data required time                         -   1.304
  slack                                          3.970
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.309          net: mss_highspeed_timerv2_0_FAB_CLK
  4.344                        AHB_timer_0/reg_load_en0/U1:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  4.592                        AHB_timer_0/reg_load_en0/U1:Q (r)
               +     0.682          net: AHB_timer_0/reg_load_en0
  5.274                        AHB_timer_0/reg_load_en1:D (r)
                                    
  5.274                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.957          Clock generation
  0.957
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.347          net: Timerv2_GLC
  1.304                        AHB_timer_0/reg_load_en1:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  1.304                        AHB_timer_0/reg_load_en1:D
                                    
  1.304                        data required time


END SET mss_ccc_gla1 to mss_ccc_glc

----------------------------------------------------

SET mss_ccc_gla0 to mss_ccc_glc

Path 1
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          AHB_timer_0/DataOut[18]/U1:CLR
  Delay (ns):                  2.404
  Slack (ns):                  4.129
  Arrival (ns):                5.436
  Required (ns):               1.307
  Hold (ns):

Path 2
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          AHB_timer_0/IntEnable/U1:CLR
  Delay (ns):                  2.404
  Slack (ns):                  4.129
  Arrival (ns):                5.436
  Required (ns):               1.307
  Hold (ns):

Path 3
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          AHB_timer_0/LoadEnReg/U1:CLR
  Delay (ns):                  2.404
  Slack (ns):                  4.129
  Arrival (ns):                5.436
  Required (ns):               1.307
  Hold (ns):

Path 4
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          AHB_timer_0/IntClrEn/U1:CLR
  Delay (ns):                  2.404
  Slack (ns):                  4.129
  Arrival (ns):                5.436
  Required (ns):               1.307
  Hold (ns):

Path 5
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          AHB_timer_0/TIMINT1[18]/U1:PRE
  Delay (ns):                  2.404
  Slack (ns):                  4.129
  Arrival (ns):                5.436
  Required (ns):               1.307
  Hold (ns):


Expanded Path 1
  From: _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To: AHB_timer_0/DataOut[18]/U1:CLR
  data arrival time                              5.436
  data required time                         -   1.307
  slack                                          4.129
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     2.724          Clock generation
  2.724
               +     0.308          net: _Timerv2_/MSS_ADLIB_INST_FCLK
  3.032                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.705          cell: ADLIB:MSS_AHB_IP
  4.737                        _Timerv2_/MSS_ADLIB_INST/U_CORE:M2FRESETn (r)
               +     0.060          net: _Timerv2_/MSS_ADLIB_INST/M2FRESETnINT_NET
  4.797                        _Timerv2_/MSS_ADLIB_INST/U_46:PIN2INT (r)
               +     0.044          cell: ADLIB:MSS_IF
  4.841                        _Timerv2_/MSS_ADLIB_INST/U_46:PIN2 (r)
               +     0.595          net: mss_highspeed_timerv2_0_M2F_RESET_N
  5.436                        AHB_timer_0/DataOut[18]/U1:CLR (r)
                                    
  5.436                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.957          Clock generation
  0.957
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.350          net: Timerv2_GLC
  1.307                        AHB_timer_0/DataOut[18]/U1:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1C0
  1.307                        AHB_timer_0/DataOut[18]/U1:CLR
                                    
  1.307                        data required time


END SET mss_ccc_gla0 to mss_ccc_glc

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_glc

Path 1
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          AHB_timer_0/TimerPre[3]/U1:D
  Delay (ns):                  2.975
  Slack (ns):                  4.710
  Arrival (ns):                6.007
  Required (ns):               1.297
  Hold (ns):                   0.000

Path 2
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          AHB_timer_0/TimerPre[1]/U1:D
  Delay (ns):                  2.990
  Slack (ns):                  4.715
  Arrival (ns):                6.022
  Required (ns):               1.307
  Hold (ns):                   0.000

Path 3
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          AHB_timer_0/Load[7]/U1:D
  Delay (ns):                  3.022
  Slack (ns):                  4.750
  Arrival (ns):                6.054
  Required (ns):               1.304
  Hold (ns):                   0.000

Path 4
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          AHB_timer_0/Load[4]/U1:D
  Delay (ns):                  3.018
  Slack (ns):                  4.784
  Arrival (ns):                6.050
  Required (ns):               1.266
  Hold (ns):                   0.000

Path 5
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          AHB_timer_0/Load[5]/U1:D
  Delay (ns):                  3.058
  Slack (ns):                  4.786
  Arrival (ns):                6.090
  Required (ns):               1.304
  Hold (ns):                   0.000


Expanded Path 1
  From: _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To: AHB_timer_0/TimerPre[3]/U1:D
  data arrival time                              6.007
  data required time                         -   1.297
  slack                                          4.710
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.032          Clock generation
  3.032
               +     1.631          cell: ADLIB:MSS_AHB_IP
  4.663                        _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHWDATA[3] (f)
               +     0.078          net: _Timerv2_/MSS_ADLIB_INST/MSSHWDATA[3]INT_NET
  4.741                        _Timerv2_/MSS_ADLIB_INST/U_37:PIN3INT (f)
               +     0.041          cell: ADLIB:MSS_IF
  4.782                        _Timerv2_/MSS_ADLIB_INST/U_37:PIN3 (f)
               +     0.161          net: _mss_highspeed_timerv2_0_MSS_MASTER_AHB_LITE_HWDATA_[3]_
  4.943                        CoreAHBLite_0/matrix2x16/slavestage_5/masterDataInProg_RNIRE3E_0[0]:B (f)
               +     0.263          cell: ADLIB:NOR3B
  5.206                        CoreAHBLite_0/matrix2x16/slavestage_5/masterDataInProg_RNIRE3E_0[0]:Y (f)
               +     0.406          net: _CoreAHBLite_0_AHBmslave5_HWDATA_[3]_
  5.612                        AHB_timer_0/TimerPre[3]/U0:B (f)
               +     0.248          cell: ADLIB:MX2
  5.860                        AHB_timer_0/TimerPre[3]/U0:Y (f)
               +     0.147          net: AHB_timer_0/TimerPre[3]/Y
  6.007                        AHB_timer_0/TimerPre[3]/U1:D (f)
                                    
  6.007                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     0.957          Clock generation
  0.957
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.957                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.340          net: Timerv2_GLC
  1.297                        AHB_timer_0/TimerPre[3]/U1:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  1.297                        AHB_timer_0/TimerPre[3]/U1:D
                                    
  1.297                        data required time


END SET mss_fabric_interface_clock to mss_ccc_glc

----------------------------------------------------

Clock Domain \\Timerv2\\/MSS_CCC_0/I_RCOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_fabric_interface_clock

Path 1
  From:                        AHB_timer_0/DataOut_int[16]:CLK
  To:                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHRDATA[16]
  Delay (ns):                  1.090
  Slack (ns):                  0.993
  Arrival (ns):                5.423
  Required (ns):               4.430
  Hold (ns):                   1.398

Path 2
  From:                        AHB_timer_0/DataOut_int[20]:CLK
  To:                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHRDATA[20]
  Delay (ns):                  1.088
  Slack (ns):                  0.994
  Arrival (ns):                5.421
  Required (ns):               4.427
  Hold (ns):                   1.395

Path 3
  From:                        AHB_timer_0/DataOut_int[14]:CLK
  To:                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHRDATA[14]
  Delay (ns):                  1.088
  Slack (ns):                  1.004
  Arrival (ns):                5.430
  Required (ns):               4.426
  Hold (ns):                   1.394

Path 4
  From:                        AHB_timer_0/DataOut_int[13]:CLK
  To:                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHRDATA[13]
  Delay (ns):                  1.086
  Slack (ns):                  1.017
  Arrival (ns):                5.445
  Required (ns):               4.428
  Hold (ns):                   1.396

Path 5
  From:                        AHB_timer_0/DataOut_int[23]:CLK
  To:                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHRDATA[23]
  Delay (ns):                  1.332
  Slack (ns):                  1.245
  Arrival (ns):                5.674
  Required (ns):               4.429
  Hold (ns):                   1.397


Expanded Path 1
  From: AHB_timer_0/DataOut_int[16]:CLK
  To: _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHRDATA[16]
  data arrival time                              5.423
  data required time                         -   4.430
  slack                                          0.993
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     4.035          Clock generation
  4.035
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  4.035                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.298          net: mss_highspeed_timerv2_0_FAB_CLK
  4.333                        AHB_timer_0/DataOut_int[16]:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  4.581                        AHB_timer_0/DataOut_int[16]:Q (r)
               +     0.171          net: _CoreAHBLite_0_AHBmslave5_HRDATA_[16]_
  4.752                        CoreAHBLite_0/matrix2x16/masterstage_0/HRDATA[16]:A (r)
               +     0.221          cell: ADLIB:NOR2A
  4.973                        CoreAHBLite_0/matrix2x16/masterstage_0/HRDATA[16]:Y (r)
               +     0.133          net: _mss_highspeed_timerv2_0_MSS_MASTER_AHB_LITE_HRDATA_[16]_
  5.106                        _Timerv2_/MSS_ADLIB_INST/U_53:PIN5 (r)
               +     0.102          cell: ADLIB:MSS_IF
  5.208                        _Timerv2_/MSS_ADLIB_INST/U_53:PIN5INT (r)
               +     0.215          net: _Timerv2_/MSS_ADLIB_INST/MSSHRDATA[16]INT_NET
  5.423                        _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHRDATA[16] (r)
                                    
  5.423                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.032          Clock generation
  3.032
               +     1.398          Library hold time: ADLIB:MSS_AHB_IP
  4.430                        _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHRDATA[16]
                                    
  4.430                        data required time


END SET mss_ccc_gla1 to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

Path 1
  From:                        Pulse_in
  To:                          Test_port[0]
  Delay (ns):                  2.333
  Slack (ns):
  Arrival (ns):                2.333
  Required (ns):


Expanded Path 1
  From: Pulse_in
  To: Test_port[0]
  data arrival time                              2.333
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        Pulse_in (r)
               +     0.000          net: Pulse_in
  0.000                        Pulse_in_pad/U0/U0:PAD (r)
               +     0.390          cell: ADLIB:IOPAD_IN
  0.390                        Pulse_in_pad/U0/U0:Y (r)
               +     0.000          net: Pulse_in_pad/U0/NET1
  0.390                        Pulse_in_pad/U0/U1:YIN (r)
               +     0.018          cell: ADLIB:IOIN_IB
  0.408                        Pulse_in_pad/U0/U1:Y (r)
               +     0.553          net: Pulse_in_c_c
  0.961                        Test_port_pad[0]/U0/U1:D (r)
               +     0.256          cell: ADLIB:IOTRI_OB_EB
  1.217                        Test_port_pad[0]/U0/U1:DOUT (r)
               +     0.000          net: Test_port_pad[0]/U0/NET1
  1.217                        Test_port_pad[0]/U0/U0:D (r)
               +     1.116          cell: ADLIB:IOPAD_TRI
  2.333                        Test_port_pad[0]/U0/U0:PAD (r)
               +     0.000          net: Test_port[0]
  2.333                        Test_port[0] (r)
                                    
  2.333                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          Pulse_in (r)
                                    
  N/C                          Test_port[0] (r)
                                    
  N/C                          data required time


END SET Input to Output

----------------------------------------------------

Path set User Sets

