Timing Report Max Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Mon Dec 12 14:07:54 2011


Design: top_timer
Family: SmartFusion
Die: A2F200M3F
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               AHB_timer_0/TIMINT_int_hclk:Q
Period (ns):                0.698
Frequency (MHz):            1432.665
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla1
Period (ns):                12.791
Frequency (MHz):            78.180
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      7.439
Max Clock-To-Out (ns):      12.125

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        -5.119
External Hold (ns):         4.172
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_glc
Period (ns):                8.826
Frequency (MHz):            113.302
Required Period (ns):       8.333
Required Frequency (MHz):   120.005
External Setup (ns):        5.649
External Hold (ns):         -0.240
Min Clock-To-Out (ns):      3.975
Max Clock-To-Out (ns):      10.220

Clock Domain:               \\Timerv2\\/MSS_CCC_0/I_RCOSC:CLKOUT
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       10.000
Required Frequency (MHz):   100.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       12.500
Required Frequency (MHz):   80.000
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

                            Input to Output
Min Delay (ns):             2.333
Max Delay (ns):             4.786

END SUMMARY
-----------------------------------------------------

Clock Domain AHB_timer_0/TIMINT_int_hclk:Q

Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin AHB_timer_0/TIMINT_pending_int:CLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla1

SET Register to Register

Path 1
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[3]/U1:CLK
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHSIZE[0]/U1:D
  Delay (ns):                  12.364
  Slack (ns):                  -0.291
  Arrival (ns):                18.120
  Required (ns):               17.829
  Setup (ns):                  0.435
  Minimum Period (ns):         12.791

Path 2
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[3]/U1:CLK
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHTRANS/U1:D
  Delay (ns):                  12.364
  Slack (ns):                  -0.281
  Arrival (ns):                18.120
  Required (ns):               17.839
  Setup (ns):                  0.435
  Minimum Period (ns):         12.781

Path 3
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[3]/U1:CLK
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[18]/U1:D
  Delay (ns):                  12.364
  Slack (ns):                  -0.281
  Arrival (ns):                18.120
  Required (ns):               17.839
  Setup (ns):                  0.435
  Minimum Period (ns):         12.781

Path 4
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[3]/U1:CLK
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[17]/U1:D
  Delay (ns):                  12.364
  Slack (ns):                  -0.281
  Arrival (ns):                18.120
  Required (ns):               17.839
  Setup (ns):                  0.435
  Minimum Period (ns):         12.781

Path 5
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[3]/U1:CLK
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[1]/U1:D
  Delay (ns):                  12.364
  Slack (ns):                  -0.281
  Arrival (ns):                18.120
  Required (ns):               17.839
  Setup (ns):                  0.435
  Minimum Period (ns):         12.781


Expanded Path 1
  From: CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[3]/U1:CLK
  To: CoreAHBLite_0/matrix2x16/masterstage_0/regHSIZE[0]/U1:D
  data required time                             17.829
  data arrival time                          -   18.120
  slack                                          -0.291
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.507          net: mss_highspeed_timerv2_0_FAB_CLK
  5.756                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[3]/U1:CLK (r)
               +     0.440          cell: ADLIB:DFN1C0
  6.196                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[3]/U1:Q (r)
               +     1.219          net: CoreAHBLite_0_matrix2x16_xhdl1222[3]
  7.415                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNIUM0A[3]:B (r)
               +     0.390          cell: ADLIB:NOR2
  7.805                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNIUM0A[3]:Y (f)
               +     0.802          net: CoreAHBLite_0/matrix2x16/masterstage_0/hready_m_xhdl387_10_0
  8.607                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNI7P1P[8]:A (f)
               +     0.486          cell: ADLIB:NOR3B
  9.093                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNI7P1P[8]:Y (f)
               +     0.247          net: CoreAHBLite_0/matrix2x16/masterstage_0/HRESP_0_0_a2_6_a0_2
  9.340                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNIRQGC1[8]:C (f)
               +     0.486          cell: ADLIB:OR3C
  9.826                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNIRQGC1[8]:Y (r)
               +     0.247          net: CoreAHBLite_0/matrix2x16/masterstage_0/N_1_3_i
  10.073                       CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNIML1P2[1]:C (r)
               +     0.581          cell: ADLIB:AO1B
  10.654                       CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNIML1P2[1]:Y (f)
               +     1.415          net: CoreAHBLite_0/matrix2x16/masterstage_0/N_1076
  12.069                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_m_0_a2_1:A (f)
               +     0.469          cell: ADLIB:MX2
  12.538                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_m_0_a2_1:Y (f)
               +     0.746          net: CoreAHBLite_0_matrix2x16_masterstage_0_N_1064_2
  13.284                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState_RNI28NOO:A (f)
               +     0.707          cell: ADLIB:OA1C
  13.991                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState_RNI28NOO:Y (r)
               +     0.971          net: CoreAHBLite_0_matrix2x16_masterstage_0_HREADY_M_iv
  14.962                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState_RNIOU4UT:B (r)
               +     0.473          cell: ADLIB:NOR3C
  15.435                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState_RNIOU4UT:Y (r)
               +     2.156          net: CoreAHBLite_0/matrix2x16/masterstage_0/masterAddrClockEnable
  17.591                       CoreAHBLite_0/matrix2x16/masterstage_0/regHSIZE[0]/U0:S (r)
               +     0.282          cell: ADLIB:MX2
  17.873                       CoreAHBLite_0/matrix2x16/masterstage_0/regHSIZE[0]/U0:Y (f)
               +     0.247          net: CoreAHBLite_0/matrix2x16/masterstage_0/regHSIZE[0]/Y
  18.120                       CoreAHBLite_0/matrix2x16/masterstage_0/regHSIZE[0]/U1:D (f)
                                    
  18.120                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_gla1
               +     0.000          Clock source
  12.500                       \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  17.749
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  17.749                       \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  17.749                       \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.515          net: mss_highspeed_timerv2_0_FAB_CLK
  18.264                       CoreAHBLite_0/matrix2x16/masterstage_0/regHSIZE[0]/U1:CLK (r)
               -     0.435          Library setup time: ADLIB:DFN1C0
  17.829                       CoreAHBLite_0/matrix2x16/masterstage_0/regHSIZE[0]/U1:D
                                    
  17.829                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        AHB_timer_0/TIMINT_int_hclk:CLK
  To:                          TIMINT
  Delay (ns):                  6.398
  Slack (ns):
  Arrival (ns):                12.125
  Required (ns):
  Clock to Out (ns):           12.125


Expanded Path 1
  From: AHB_timer_0/TIMINT_int_hclk:CLK
  To: TIMINT
  data required time                             N/C
  data arrival time                          -   12.125
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.478          net: mss_highspeed_timerv2_0_FAB_CLK
  5.727                        AHB_timer_0/TIMINT_int_hclk:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  6.286                        AHB_timer_0/TIMINT_int_hclk:Q (f)
               +     1.369          net: AHB_timer_0/TIMINT_int_hclk_i
  7.655                        AHB_timer_0/TIMINT_int_hclk_RNI4603/U_CLKSRC:A (f)
               +     0.599          cell: ADLIB:CLKSRC
  8.254                        AHB_timer_0/TIMINT_int_hclk_RNI4603/U_CLKSRC:Y (f)
               +     0.563          net: TIMINT_c
  8.817                        TIMINT_pad/U0/U1:D (f)
               +     0.500          cell: ADLIB:IOTRI_OB_EB
  9.317                        TIMINT_pad/U0/U1:DOUT (f)
               +     0.000          net: TIMINT_pad/U0/NET1
  9.317                        TIMINT_pad/U0/U0:D (f)
               +     2.808          cell: ADLIB:IOPAD_TRI
  12.125                       TIMINT_pad/U0/U0:PAD (f)
               +     0.000          net: TIMINT
  12.125                       TIMINT (f)
                                    
  12.125                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla1
               +     0.000          Clock source
  N/C                          \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  N/C
                                    
  N/C                          TIMINT (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla0 to mss_ccc_gla1

Path 1
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[11]/U1:CLR
  Delay (ns):                  7.421
  Slack (ns):                  6.544
  Arrival (ns):                11.491
  Required (ns):               18.035
  Setup (ns):

Path 2
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[9]/U1:CLR
  Delay (ns):                  7.341
  Slack (ns):                  6.614
  Arrival (ns):                11.411
  Required (ns):               18.025
  Setup (ns):

Path 3
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[12]/U1:CLR
  Delay (ns):                  7.160
  Slack (ns):                  6.805
  Arrival (ns):                11.230
  Required (ns):               18.035
  Setup (ns):

Path 4
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[13]/U1:CLR
  Delay (ns):                  7.160
  Slack (ns):                  6.805
  Arrival (ns):                11.230
  Required (ns):               18.035
  Setup (ns):

Path 5
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[15]/U1:CLR
  Delay (ns):                  7.135
  Slack (ns):                  6.820
  Arrival (ns):                11.205
  Required (ns):               18.025
  Setup (ns):


Expanded Path 1
  From: _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To: CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[11]/U1:CLR
  data required time                             18.035
  data arrival time                          -   11.491
  slack                                          6.544
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  3.545
               +     0.525          net: _Timerv2_/MSS_ADLIB_INST_FCLK
  4.070                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     3.027          cell: ADLIB:MSS_AHB_IP
  7.097                        _Timerv2_/MSS_ADLIB_INST/U_CORE:M2FRESETn (r)
               +     0.102          net: _Timerv2_/MSS_ADLIB_INST/M2FRESETnINT_NET
  7.199                        _Timerv2_/MSS_ADLIB_INST/U_46:PIN2INT (r)
               +     0.079          cell: ADLIB:MSS_IF
  7.278                        _Timerv2_/MSS_ADLIB_INST/U_46:PIN2 (r)
               +     4.213          net: mss_highspeed_timerv2_0_M2F_RESET_N
  11.491                       CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[11]/U1:CLR (r)
                                    
  11.491                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_gla1
               +     0.000          Clock source
  12.500                       \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  17.749
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  17.749                       \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  17.749                       \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.511          net: mss_highspeed_timerv2_0_FAB_CLK
  18.260                       CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[11]/U1:CLK (r)
               -     0.225          Library recovery time: ADLIB:DFN1C0
  18.035                       CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[11]/U1:CLR
                                    
  18.035                       data required time


END SET mss_ccc_gla0 to mss_ccc_gla1

----------------------------------------------------

SET mss_ccc_glc to mss_ccc_gla1

Path 1
  From:                        AHB_timer_0/Count[1]/U1:CLK
  To:                          AHB_timer_0/TIMINT_int_hclk:D
  Delay (ns):                  5.889
  Slack (ns):                  1.826
  Arrival (ns):                7.659
  Required (ns):               9.485
  Setup (ns):                  0.409

Path 2
  From:                        AHB_timer_0/count_zero_blk_instance/count23_3_zero:CLK
  To:                          AHB_timer_0/TIMINT_int_hclk:D
  Delay (ns):                  5.360
  Slack (ns):                  2.321
  Arrival (ns):                7.138
  Required (ns):               9.459
  Setup (ns):                  0.435

Path 3
  From:                        AHB_timer_0/Count[0]/U1:CLK
  To:                          AHB_timer_0/TIMINT_int_hclk:D
  Delay (ns):                  5.230
  Slack (ns):                  2.485
  Arrival (ns):                7.000
  Required (ns):               9.485
  Setup (ns):                  0.409

Path 4
  From:                        AHB_timer_0/Count[2]/U1:CLK
  To:                          AHB_timer_0/TIMINT_int_hclk:D
  Delay (ns):                  5.225
  Slack (ns):                  2.490
  Arrival (ns):                6.995
  Required (ns):               9.485
  Setup (ns):                  0.409

Path 5
  From:                        AHB_timer_0/IntEnable/U1:CLK
  To:                          AHB_timer_0/TIMINT_int_hclk:D
  Delay (ns):                  4.010
  Slack (ns):                  3.644
  Arrival (ns):                5.815
  Required (ns):               9.459
  Setup (ns):                  0.435


Expanded Path 1
  From: AHB_timer_0/Count[1]/U1:CLK
  To: AHB_timer_0/TIMINT_int_hclk:D
  data required time                             9.485
  data arrival time                          -   7.659
  slack                                          1.826
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     1.246          Clock generation
  1.246
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  1.246                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  1.246                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.524          net: Timerv2_GLC
  1.770                        AHB_timer_0/Count[1]/U1:CLK (r)
               +     0.559          cell: ADLIB:DFN1P0
  2.329                        AHB_timer_0/Count[1]/U1:Q (f)
               +     1.114          net: AHB_timer_0/Count[1]
  3.443                        AHB_timer_0/count_zero_blk_instance/NOR3_0:B (f)
               +     0.473          cell: ADLIB:NOR3
  3.916                        AHB_timer_0/count_zero_blk_instance/NOR3_0:Y (r)
               +     0.308          net: AHB_timer_0/count_zero_blk_instance/count2_0_zero
  4.224                        AHB_timer_0/count_zero_blk_instance/count23_3_zero_RNI8HR1:B (r)
               +     0.392          cell: ADLIB:NOR2B
  4.616                        AHB_timer_0/count_zero_blk_instance/count23_3_zero_RNI8HR1:Y (r)
               +     1.186          net: Test_port_c[3]
  5.802                        AHB_timer_0/IntEnable_RNICLK5:A (r)
               +     0.308          cell: ADLIB:NOR2B
  6.110                        AHB_timer_0/IntEnable_RNICLK5:Y (r)
               +     0.280          net: AHB_timer_0/un1_timint_pulse_int_0
  6.390                        AHB_timer_0/TIMINT_int_hclk_RNO:A (r)
               +     0.399          cell: ADLIB:XOR3
  6.789                        AHB_timer_0/TIMINT_int_hclk_RNO:Y (r)
               +     0.870          net: AHB_timer_0/TIMINT_int_0
  7.659                        AHB_timer_0/TIMINT_int_hclk:D (r)
                                    
  7.659                        data arrival time
  ________________________________________________________
  Data required time calculation
  4.167                        mss_ccc_gla1
               +     0.000          Clock source
  4.167                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  9.416
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  9.416                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  9.416                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.478          net: mss_highspeed_timerv2_0_FAB_CLK
  9.894                        AHB_timer_0/TIMINT_int_hclk:CLK (r)
               -     0.409          Library setup time: ADLIB:DFN1C0
  9.485                        AHB_timer_0/TIMINT_int_hclk:D
                                    
  9.485                        data required time


END SET mss_ccc_glc to mss_ccc_gla1

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_gla1

Path 1
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          AHB_timer_0/HWRITE_int/U1:D
  Delay (ns):                  14.517
  Slack (ns):                  -0.759
  Arrival (ns):                18.587
  Required (ns):               17.828
  Setup (ns):                  0.435

Path 2
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          AHB_timer_0/HADDR_int[0]/U1:D
  Delay (ns):                  14.264
  Slack (ns):                  -0.526
  Arrival (ns):                18.334
  Required (ns):               17.808
  Setup (ns):                  0.435

Path 3
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHSIZE[0]/U1:D
  Delay (ns):                  14.201
  Slack (ns):                  -0.442
  Arrival (ns):                18.271
  Required (ns):               17.829
  Setup (ns):                  0.435

Path 4
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHTRANS/U1:D
  Delay (ns):                  14.201
  Slack (ns):                  -0.432
  Arrival (ns):                18.271
  Required (ns):               17.839
  Setup (ns):                  0.435

Path 5
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR[18]/U1:D
  Delay (ns):                  14.201
  Slack (ns):                  -0.432
  Arrival (ns):                18.271
  Required (ns):               17.839
  Setup (ns):                  0.435


Expanded Path 1
  From: _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To: AHB_timer_0/HWRITE_int/U1:D
  data required time                             17.828
  data arrival time                          -   18.587
  slack                                          -0.759
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.070          Clock generation
  4.070
               +     2.955          cell: ADLIB:MSS_AHB_IP
  7.025                        _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHADDR[19] (r)
               +     0.101          net: _Timerv2_/MSS_ADLIB_INST/MSSHADDR[19]INT_NET
  7.126                        _Timerv2_/MSS_ADLIB_INST/U_36:PIN2INT (r)
               +     0.079          cell: ADLIB:MSS_IF
  7.205                        _Timerv2_/MSS_ADLIB_INST/U_36:PIN2 (r)
               +     2.400          net: _mss_highspeed_timerv2_0_MSS_MASTER_AHB_LITE_HADDR_[19]_
  9.605                        CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR_RNIIEIA[19]:A (r)
               +     0.431          cell: ADLIB:MX2
  10.036                       CoreAHBLite_0/matrix2x16/masterstage_0/regHADDR_RNIIEIA[19]:Y (r)
               +     0.402          net: CoreAHBLite_0/matrix2x16/masterstage_0/M0GATEDHADDR[19]
  10.438                       CoreAHBLite_0/matrix2x16/masterstage_0/address_decode/cdec_20_sqmuxa_0_a2_0:A (r)
               +     0.276          cell: ADLIB:NOR2
  10.714                       CoreAHBLite_0/matrix2x16/masterstage_0/address_decode/cdec_20_sqmuxa_0_a2_0:Y (f)
               +     0.235          net: CoreAHBLite_0/matrix2x16/masterstage_0/N_80
  10.949                       CoreAHBLite_0/matrix2x16/masterstage_0/regHTRANS_RNIHOQ31:A (f)
               +     0.390          cell: ADLIB:OR2B
  11.339                       CoreAHBLite_0/matrix2x16/masterstage_0/regHTRANS_RNIHOQ31:Y (r)
               +     0.866          net: CoreAHBLite_0/matrix2x16/SADDRSEL_0[5]
  12.205                       CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState_RNI5MJC2[4]:C (r)
               +     0.518          cell: ADLIB:NOR3
  12.723                       CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState_RNI5MJC2[4]:Y (f)
               +     0.237          net: CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState_RNI5MJC2[4]
  12.960                       CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState_RNING4H2[6]:A (f)
               +     0.385          cell: ADLIB:NOR2
  13.345                       CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState_RNING4H2[6]:Y (r)
               +     0.896          net: CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/N_100
  14.241                       CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState_RNIL6OT4[1]:C (r)
               +     0.505          cell: ADLIB:OR3C
  14.746                       CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState_RNIL6OT4[1]:Y (f)
               +     2.382          net: CoreAHBLite_0/matrix2x16/slavestage_5/masterAddrInProg[0]
  17.128                       CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState_RNIJKVG5[0]:A (f)
               +     0.517          cell: ADLIB:NOR3B
  17.645                       CoreAHBLite_0/matrix2x16/slavestage_5/slave_arbiter/arbRegSMCurrentState_RNIJKVG5[0]:Y (f)
               +     0.254          net: CoreAHBLite_0_AHBmslave5_HWRITE
  17.899                       AHB_timer_0/HWRITE_int/U0:B (f)
               +     0.434          cell: ADLIB:MX2
  18.333                       AHB_timer_0/HWRITE_int/U0:Y (f)
               +     0.254          net: AHB_timer_0/HWRITE_int/Y
  18.587                       AHB_timer_0/HWRITE_int/U1:D (f)
                                    
  18.587                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_ccc_gla1
               +     0.000          Clock source
  12.500                       \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  17.749
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  17.749                       \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  17.749                       \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.514          net: mss_highspeed_timerv2_0_FAB_CLK
  18.263                       AHB_timer_0/HWRITE_int/U1:CLK (r)
               -     0.435          Library setup time: ADLIB:DFN1C0
  17.828                       AHB_timer_0/HWRITE_int/U1:D
                                    
  17.828                       data required time


END SET mss_fabric_interface_clock to mss_ccc_gla1

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.781
  Slack (ns):
  Arrival (ns):                0.781
  Required (ns):
  Setup (ns):                  -1.830
  External Setup (ns):         -5.119


Expanded Path 1
  From: MSS_RESET_N
  To: _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.781
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        \\Timerv2\\/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.781          cell: ADLIB:IOPAD_IN
  0.781                        \\Timerv2\\/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: _Timerv2_/MSS_RESET_0_MSS_RESET_N_Y
  0.781                        _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.781                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  N/C
               +     0.525          net: _Timerv2_/MSS_ADLIB_INST_FCLK
  N/C                          _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -1.830          Library setup time: ADLIB:MSS_AHB_IP
  N/C                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glc

SET Register to Register

Path 1
  From:                        AHB_timer_0/prescl_cnt[0]:CLK
  To:                          AHB_timer_0/new_count_pulse:D
  Delay (ns):                  8.395
  Slack (ns):                  -0.493
  Arrival (ns):                10.151
  Required (ns):               9.658
  Setup (ns):                  0.435
  Minimum Period (ns):         8.826

Path 2
  From:                        AHB_timer_0/Count[7]/U1:CLK
  To:                          AHB_timer_0/Count[19]/U1:D
  Delay (ns):                  8.055
  Slack (ns):                  -0.198
  Arrival (ns):                9.822
  Required (ns):               9.624
  Setup (ns):                  0.435
  Minimum Period (ns):         8.531

Path 3
  From:                        AHB_timer_0/Count[7]/U1:CLK
  To:                          AHB_timer_0/Count[22]/U1:D
  Delay (ns):                  8.047
  Slack (ns):                  -0.142
  Arrival (ns):                9.814
  Required (ns):               9.672
  Setup (ns):                  0.435
  Minimum Period (ns):         8.475

Path 4
  From:                        AHB_timer_0/Count[14]/U1:CLK
  To:                          AHB_timer_0/Count[22]/U1:D
  Delay (ns):                  7.975
  Slack (ns):                  -0.057
  Arrival (ns):                9.729
  Required (ns):               9.672
  Setup (ns):                  0.435
  Minimum Period (ns):         8.390

Path 5
  From:                        AHB_timer_0/Count[4]/U1:CLK
  To:                          AHB_timer_0/Count[19]/U1:D
  Delay (ns):                  7.919
  Slack (ns):                  -0.047
  Arrival (ns):                9.671
  Required (ns):               9.624
  Setup (ns):                  0.435
  Minimum Period (ns):         8.380


Expanded Path 1
  From: AHB_timer_0/prescl_cnt[0]:CLK
  To: AHB_timer_0/new_count_pulse:D
  data required time                             9.658
  data arrival time                          -   10.151
  slack                                          -0.493
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     1.246          Clock generation
  1.246
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  1.246                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  1.246                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.510          net: Timerv2_GLC
  1.756                        AHB_timer_0/prescl_cnt[0]:CLK (r)
               +     0.440          cell: ADLIB:DFN1C0
  2.196                        AHB_timer_0/prescl_cnt[0]:Q (r)
               +     0.976          net: AHB_timer_0/prescl_cnt[0]
  3.172                        AHB_timer_0/prescl_cnt_RNI3BT2[1]:B (r)
               +     0.392          cell: ADLIB:NOR2B
  3.564                        AHB_timer_0/prescl_cnt_RNI3BT2[1]:Y (r)
               +     0.681          net: AHB_timer_0/prescl_cnt_c1
  4.245                        AHB_timer_0/prescl_cnt_RNIM0C4[2]:A (r)
               +     0.308          cell: ADLIB:OR2B
  4.553                        AHB_timer_0/prescl_cnt_RNIM0C4[2]:Y (f)
               +     0.292          net: AHB_timer_0/prescl_cnt_c2
  4.845                        AHB_timer_0/prescl_cnt_RNIAMQ5[3]:B (f)
               +     0.490          cell: ADLIB:OR2A
  5.335                        AHB_timer_0/prescl_cnt_RNIAMQ5[3]:Y (f)
               +     0.955          net: AHB_timer_0/prescl_cnt_c3
  6.290                        AHB_timer_0/new_count_pulse_RNO_10:A (f)
               +     0.293          cell: ADLIB:OR2B
  6.583                        AHB_timer_0/new_count_pulse_RNO_10:Y (r)
               +     0.267          net: AHB_timer_0/Count_Pulse_1_sqmuxa_3_3
  6.850                        AHB_timer_0/new_count_pulse_RNO_7:C (r)
               +     0.505          cell: ADLIB:NOR3C
  7.355                        AHB_timer_0/new_count_pulse_RNO_7:Y (r)
               +     0.763          net: AHB_timer_0/un1_TimerPre_1_2
  8.118                        AHB_timer_0/new_count_pulse_RNO_4:C (r)
               +     0.302          cell: ADLIB:AOI1B
  8.420                        AHB_timer_0/new_count_pulse_RNO_4:Y (r)
               +     0.255          net: AHB_timer_0/un1_TimerPre_1_3
  8.675                        AHB_timer_0/new_count_pulse_RNO_0:C (r)
               +     0.505          cell: ADLIB:OR3C
  9.180                        AHB_timer_0/new_count_pulse_RNO_0:Y (f)
               +     0.255          net: AHB_timer_0/un1_TimerPre_1
  9.435                        AHB_timer_0/new_count_pulse_RNO:A (f)
               +     0.469          cell: ADLIB:MX2C
  9.904                        AHB_timer_0/new_count_pulse_RNO:Y (r)
               +     0.247          net: AHB_timer_0/Count_Pulse
  10.151                       AHB_timer_0/new_count_pulse:D (r)
                                    
  10.151                       data arrival time
  ________________________________________________________
  Data required time calculation
  8.333                        mss_ccc_glc
               +     0.000          Clock source
  8.333                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     1.246          Clock generation
  9.579
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  9.579                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  9.579                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.514          net: Timerv2_GLC
  10.093                       AHB_timer_0/new_count_pulse:CLK (r)
               -     0.435          Library setup time: ADLIB:DFN1C0
  9.658                        AHB_timer_0/new_count_pulse:D
                                    
  9.658                        data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        Pulse_in
  To:                          AHB_timer_0/Count[11]/U1:D
  Delay (ns):                  6.958
  Slack (ns):
  Arrival (ns):                6.958
  Required (ns):
  Setup (ns):                  0.435
  External Setup (ns):         5.649

Path 2
  From:                        Pulse_in
  To:                          AHB_timer_0/Count[1]/U1:D
  Delay (ns):                  6.914
  Slack (ns):
  Arrival (ns):                6.914
  Required (ns):
  Setup (ns):                  0.435
  External Setup (ns):         5.579

Path 3
  From:                        Pulse_in
  To:                          AHB_timer_0/Count[6]/U1:D
  Delay (ns):                  6.914
  Slack (ns):
  Arrival (ns):                6.914
  Required (ns):
  Setup (ns):                  0.435
  External Setup (ns):         5.579

Path 4
  From:                        Pulse_in
  To:                          AHB_timer_0/Count[13]/U1:D
  Delay (ns):                  6.844
  Slack (ns):
  Arrival (ns):                6.844
  Required (ns):
  Setup (ns):                  0.435
  External Setup (ns):         5.503

Path 5
  From:                        Pulse_in
  To:                          AHB_timer_0/Count[19]/U1:D
  Delay (ns):                  6.718
  Slack (ns):
  Arrival (ns):                6.718
  Required (ns):
  Setup (ns):                  0.435
  External Setup (ns):         5.427


Expanded Path 1
  From: Pulse_in
  To: AHB_timer_0/Count[11]/U1:D
  data required time                             N/C
  data arrival time                          -   6.958
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        Pulse_in (f)
               +     0.000          net: Pulse_in
  0.000                        Pulse_in_pad/U0/U0:PAD (f)
               +     0.529          cell: ADLIB:IOPAD_IN
  0.529                        Pulse_in_pad/U0/U0:Y (f)
               +     0.000          net: Pulse_in_pad/U0/NET1
  0.529                        Pulse_in_pad/U0/U1:YIN (f)
               +     0.030          cell: ADLIB:IOIN_IB
  0.559                        Pulse_in_pad/U0/U1:Y (f)
               +     2.626          net: Pulse_in_c_c
  3.185                        AHB_timer_0/new_count_pulse_RNIJB8H:C (f)
               +     0.369          cell: ADLIB:AOI1B
  3.554                        AHB_timer_0/new_count_pulse_RNIJB8H:Y (f)
               +     0.247          net: AHB_timer_0/Count_0_sqmuxa_a1_0
  3.801                        AHB_timer_0/LoadEnReg_RNI19HT:B (f)
               +     0.452          cell: ADLIB:AO1C
  4.253                        AHB_timer_0/LoadEnReg_RNI19HT:Y (f)
               +     2.064          net: AHB_timer_0/Count_0_sqmuxa
  6.317                        AHB_timer_0/Count[11]/U0:S (f)
               +     0.394          cell: ADLIB:MX2
  6.711                        AHB_timer_0/Count[11]/U0:Y (f)
               +     0.247          net: AHB_timer_0/Count[11]/Y
  6.958                        AHB_timer_0/Count[11]/U1:D (f)
                                    
  6.958                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glc
               +     0.000          Clock source
  N/C                          \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     1.246          Clock generation
  N/C
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  N/C                          \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.498          net: Timerv2_GLC
  N/C                          AHB_timer_0/Count[11]/U1:CLK (r)
               -     0.435          Library setup time: ADLIB:DFN1P0
  N/C                          AHB_timer_0/Count[11]/U1:D


END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        AHB_timer_0/TimerEn/U1:CLK
  To:                          Test_port[1]
  Delay (ns):                  8.415
  Slack (ns):
  Arrival (ns):                10.220
  Required (ns):
  Clock to Out (ns):           10.220

Path 2
  From:                        AHB_timer_0/Count[1]/U1:CLK
  To:                          Test_port[3]
  Delay (ns):                  8.185
  Slack (ns):
  Arrival (ns):                9.955
  Required (ns):
  Clock to Out (ns):           9.955

Path 3
  From:                        AHB_timer_0/count_zero_blk_instance/count23_3_zero:CLK
  To:                          Test_port[3]
  Delay (ns):                  7.765
  Slack (ns):
  Arrival (ns):                9.543
  Required (ns):
  Clock to Out (ns):           9.543

Path 4
  From:                        AHB_timer_0/Count[2]/U1:CLK
  To:                          Test_port[3]
  Delay (ns):                  7.577
  Slack (ns):
  Arrival (ns):                9.347
  Required (ns):
  Clock to Out (ns):           9.347

Path 5
  From:                        AHB_timer_0/Count[0]/U1:CLK
  To:                          Test_port[3]
  Delay (ns):                  7.551
  Slack (ns):
  Arrival (ns):                9.321
  Required (ns):
  Clock to Out (ns):           9.321


Expanded Path 1
  From: AHB_timer_0/TimerEn/U1:CLK
  To: Test_port[1]
  data required time                             N/C
  data arrival time                          -   10.220
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glc
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     1.246          Clock generation
  1.246
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  1.246                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  1.246                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.559          net: Timerv2_GLC
  1.805                        AHB_timer_0/TimerEn/U1:CLK (r)
               +     0.440          cell: ADLIB:DFN1C0
  2.245                        AHB_timer_0/TimerEn/U1:Q (r)
               +     1.794          net: AHB_timer_0/TimerEn
  4.039                        AHB_timer_0/TimerEn_RNIMFS5:A (r)
               +     0.276          cell: ADLIB:INV
  4.315                        AHB_timer_0/TimerEn_RNIMFS5:Y (f)
               +     2.597          net: AHB_timer_0_TimerEn_i
  6.912                        Test_port_pad[1]/U0/U1:D (f)
               +     0.500          cell: ADLIB:IOTRI_OB_EB
  7.412                        Test_port_pad[1]/U0/U1:DOUT (f)
               +     0.000          net: Test_port_pad[1]/U0/NET1
  7.412                        Test_port_pad[1]/U0/U0:D (f)
               +     2.808          cell: ADLIB:IOPAD_TRI
  10.220                       Test_port_pad[1]/U0/U0:PAD (f)
               +     0.000          net: Test_port[1]
  10.220                       Test_port[1] (f)
                                    
  10.220                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glc
               +     0.000          Clock source
  N/C                          \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     1.246          Clock generation
  N/C
                                    
  N/C                          Test_port[1] (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_ccc_glc

Path 1
  From:                        AHB_timer_0/HADDR_int[0]/U1:CLK
  To:                          AHB_timer_0/DataOut[2]/U1:D
  Delay (ns):                  8.045
  Slack (ns):                  -4.125
  Arrival (ns):                13.788
  Required (ns):               9.663
  Setup (ns):                  0.409

Path 2
  From:                        AHB_timer_0/HADDR_int[1]/U1:CLK
  To:                          AHB_timer_0/DataOut[2]/U1:D
  Delay (ns):                  7.928
  Slack (ns):                  -4.021
  Arrival (ns):                13.684
  Required (ns):               9.663
  Setup (ns):                  0.409

Path 3
  From:                        AHB_timer_0/HADDR_int[0]/U1:CLK
  To:                          AHB_timer_0/DataOut[5]/U1:D
  Delay (ns):                  7.939
  Slack (ns):                  -3.970
  Arrival (ns):                13.682
  Required (ns):               9.712
  Setup (ns):                  0.409

Path 4
  From:                        AHB_timer_0/HADDR_int[0]/U1:CLK
  To:                          AHB_timer_0/DataOut[22]/U1:D
  Delay (ns):                  7.904
  Slack (ns):                  -3.933
  Arrival (ns):                13.647
  Required (ns):               9.714
  Setup (ns):                  0.409

Path 5
  From:                        AHB_timer_0/HADDR_int[1]/U1:CLK
  To:                          AHB_timer_0/DataOut[5]/U1:D
  Delay (ns):                  7.822
  Slack (ns):                  -3.866
  Arrival (ns):                13.578
  Required (ns):               9.712
  Setup (ns):                  0.409


Expanded Path 1
  From: AHB_timer_0/HADDR_int[0]/U1:CLK
  To: AHB_timer_0/DataOut[2]/U1:D
  data required time                             9.663
  data arrival time                          -   13.788
  slack                                          -4.125
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.494          net: mss_highspeed_timerv2_0_FAB_CLK
  5.743                        AHB_timer_0/HADDR_int[0]/U1:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  6.302                        AHB_timer_0/HADDR_int[0]/U1:Q (f)
               +     0.292          net: AHB_timer_0/HADDR_int[0]
  6.594                        AHB_timer_0/HADDR_int_RNIFLSD[0]:B (f)
               +     0.490          cell: ADLIB:NOR2
  7.084                        AHB_timer_0/HADDR_int_RNIFLSD[0]:Y (r)
               +     0.916          net: AHB_timer_0/N_42
  8.000                        AHB_timer_0/HADDR_int_RNI86RK_0[2]:A (r)
               +     0.370          cell: ADLIB:OR2B
  8.370                        AHB_timer_0/HADDR_int_RNI86RK_0[2]:Y (f)
               +     0.832          net: AHB_timer_0/N_48_0
  9.202                        AHB_timer_0/HADDR_int_RNITJO21_2[4]:B (f)
               +     0.543          cell: ADLIB:AND3B
  9.745                        AHB_timer_0/HADDR_int_RNITJO21_2[4]:Y (r)
               +     1.341          net: AHB_timer_0/un19_reg_load_en2
  11.086                       AHB_timer_0/DataOut_RNO_4[2]:B (r)
               +     0.392          cell: ADLIB:OR2B
  11.478                       AHB_timer_0/DataOut_RNO_4[2]:Y (f)
               +     0.247          net: AHB_timer_0/TIMINT1_m_i[2]
  11.725                       AHB_timer_0/DataOut_RNO_0[2]:B (f)
               +     0.460          cell: ADLIB:NOR3C
  12.185                       AHB_timer_0/DataOut_RNO_0[2]:Y (f)
               +     0.235          net: AHB_timer_0/DataOut_12_0_iv_1[2]
  12.420                       AHB_timer_0/DataOut_RNO[2]:A (f)
               +     0.352          cell: ADLIB:OR3C
  12.772                       AHB_timer_0/DataOut_RNO[2]:Y (r)
               +     0.247          net: AHB_timer_0/DataOut_12[2]
  13.019                       AHB_timer_0/DataOut[2]/U0:B (r)
               +     0.514          cell: ADLIB:MX2
  13.533                       AHB_timer_0/DataOut[2]/U0:Y (r)
               +     0.255          net: AHB_timer_0/DataOut[2]/Y
  13.788                       AHB_timer_0/DataOut[2]/U1:D (r)
                                    
  13.788                       data arrival time
  ________________________________________________________
  Data required time calculation
  8.333                        mss_ccc_glc
               +     0.000          Clock source
  8.333                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     1.246          Clock generation
  9.579
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  9.579                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  9.579                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.493          net: Timerv2_GLC
  10.072                       AHB_timer_0/DataOut[2]/U1:CLK (r)
               -     0.409          Library setup time: ADLIB:DFN1C0
  9.663                        AHB_timer_0/DataOut[2]/U1:D
                                    
  9.663                        data required time


END SET mss_ccc_gla1 to mss_ccc_glc

----------------------------------------------------

SET mss_ccc_gla0 to mss_ccc_glc

Path 1
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          AHB_timer_0/TIMINT1[22]/U1:PRE
  Delay (ns):                  7.011
  Slack (ns):                  -1.199
  Arrival (ns):                11.081
  Required (ns):               9.882
  Setup (ns):

Path 2
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          AHB_timer_0/Count[20]/U1:PRE
  Delay (ns):                  6.969
  Slack (ns):                  -1.157
  Arrival (ns):                11.039
  Required (ns):               9.882
  Setup (ns):

Path 3
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          AHB_timer_0/DataOut[9]/U1:CLR
  Delay (ns):                  6.908
  Slack (ns):                  -1.096
  Arrival (ns):                10.978
  Required (ns):               9.882
  Setup (ns):

Path 4
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          AHB_timer_0/Count[19]/U1:PRE
  Delay (ns):                  6.745
  Slack (ns):                  -0.981
  Arrival (ns):                10.815
  Required (ns):               9.834
  Setup (ns):

Path 5
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To:                          AHB_timer_0/TIMINT2[11]/U1:PRE
  Delay (ns):                  6.709
  Slack (ns):                  -0.897
  Arrival (ns):                10.779
  Required (ns):               9.882
  Setup (ns):


Expanded Path 1
  From: _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK
  To: AHB_timer_0/TIMINT1[22]/U1:PRE
  data required time                             9.882
  data arrival time                          -   11.081
  slack                                          -1.199
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla0
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     3.545          Clock generation
  3.545
               +     0.525          net: _Timerv2_/MSS_ADLIB_INST_FCLK
  4.070                        _Timerv2_/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     3.027          cell: ADLIB:MSS_AHB_IP
  7.097                        _Timerv2_/MSS_ADLIB_INST/U_CORE:M2FRESETn (r)
               +     0.102          net: _Timerv2_/MSS_ADLIB_INST/M2FRESETnINT_NET
  7.199                        _Timerv2_/MSS_ADLIB_INST/U_46:PIN2INT (r)
               +     0.079          cell: ADLIB:MSS_IF
  7.278                        _Timerv2_/MSS_ADLIB_INST/U_46:PIN2 (r)
               +     3.803          net: mss_highspeed_timerv2_0_M2F_RESET_N
  11.081                       AHB_timer_0/TIMINT1[22]/U1:PRE (r)
                                    
  11.081                       data arrival time
  ________________________________________________________
  Data required time calculation
  8.333                        mss_ccc_glc
               +     0.000          Clock source
  8.333                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     1.246          Clock generation
  9.579
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  9.579                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  9.579                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.528          net: Timerv2_GLC
  10.107                       AHB_timer_0/TIMINT1[22]/U1:CLK (r)
               -     0.225          Library recovery time: ADLIB:DFN1P0
  9.882                        AHB_timer_0/TIMINT1[22]/U1:PRE
                                    
  9.882                        data required time


END SET mss_ccc_gla0 to mss_ccc_glc

----------------------------------------------------

SET mss_fabric_interface_clock to mss_ccc_glc

Path 1
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          AHB_timer_0/IntClrEn/U1:D
  Delay (ns):                  7.060
  Slack (ns):                  -1.401
  Arrival (ns):                11.130
  Required (ns):               9.729
  Setup (ns):                  0.409

Path 2
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          AHB_timer_0/Load[21]/U1:D
  Delay (ns):                  6.809
  Slack (ns):                  -1.207
  Arrival (ns):                10.879
  Required (ns):               9.672
  Setup (ns):                  0.409

Path 3
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          AHB_timer_0/Load[16]/U1:D
  Delay (ns):                  6.699
  Slack (ns):                  -1.046
  Arrival (ns):                10.769
  Required (ns):               9.723
  Setup (ns):                  0.409

Path 4
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          AHB_timer_0/Load[0]/U1:D
  Delay (ns):                  6.583
  Slack (ns):                  -0.924
  Arrival (ns):                10.653
  Required (ns):               9.729
  Setup (ns):                  0.409

Path 5
  From:                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To:                          AHB_timer_0/TimerMode/U1:D
  Delay (ns):                  6.583
  Slack (ns):                  -0.924
  Arrival (ns):                10.653
  Required (ns):               9.729
  Setup (ns):                  0.409


Expanded Path 1
  From: _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB
  To: AHB_timer_0/IntClrEn/U1:D
  data required time                             9.729
  data arrival time                          -   11.130
  slack                                          -1.401
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.070          Clock generation
  4.070
               +     2.942          cell: ADLIB:MSS_AHB_IP
  7.012                        _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHWDATA[0] (r)
               +     0.100          net: _Timerv2_/MSS_ADLIB_INST/MSSHWDATA[0]INT_NET
  7.112                        _Timerv2_/MSS_ADLIB_INST/U_36:PIN3INT (r)
               +     0.072          cell: ADLIB:MSS_IF
  7.184                        _Timerv2_/MSS_ADLIB_INST/U_36:PIN3 (r)
               +     0.974          net: _mss_highspeed_timerv2_0_MSS_MASTER_AHB_LITE_HWDATA_[0]_
  8.158                        CoreAHBLite_0/matrix2x16/slavestage_5/masterDataInProg_0_RNI6H2C[0]:B (r)
               +     0.473          cell: ADLIB:NOR3B
  8.631                        CoreAHBLite_0/matrix2x16/slavestage_5/masterDataInProg_0_RNI6H2C[0]:Y (r)
               +     1.027          net: _CoreAHBLite_0_AHBmslave5_HWDATA_[0]_
  9.658                        AHB_timer_0/IntClrEn_RNO:A (r)
               +     0.504          cell: ADLIB:NOR3A
  10.162                       AHB_timer_0/IntClrEn_RNO:Y (r)
               +     0.262          net: AHB_timer_0/IntClrEn_6
  10.424                       AHB_timer_0/IntClrEn/U0:B (r)
               +     0.444          cell: ADLIB:MX2
  10.868                       AHB_timer_0/IntClrEn/U0:Y (r)
               +     0.262          net: AHB_timer_0/IntClrEn/Y
  11.130                       AHB_timer_0/IntClrEn/U1:D (r)
                                    
  11.130                       data arrival time
  ________________________________________________________
  Data required time calculation
  8.333                        mss_ccc_glc
               +     0.000          Clock source
  8.333                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLC (r)
               +     1.246          Clock generation
  9.579
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLC_INT
  9.579                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  9.579                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE3:PIN5 (r)
               +     0.559          net: Timerv2_GLC
  10.138                       AHB_timer_0/IntClrEn/U1:CLK (r)
               -     0.409          Library setup time: ADLIB:DFN1C0
  9.729                        AHB_timer_0/IntClrEn/U1:D
                                    
  9.729                        data required time


END SET mss_fabric_interface_clock to mss_ccc_glc

----------------------------------------------------

Clock Domain \\Timerv2\\/MSS_CCC_0/I_RCOSC:CLKOUT

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

SET mss_ccc_gla1 to mss_fabric_interface_clock

Path 1
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[3]/U1:CLK
  To:                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHREADY
  Delay (ns):                  9.379
  Slack (ns):                  2.583
  Arrival (ns):                15.135
  Required (ns):               17.718
  Setup (ns):                  -1.148

Path 2
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/CLDATASELInt[4]/U1:CLK
  To:                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHREADY
  Delay (ns):                  9.319
  Slack (ns):                  2.652
  Arrival (ns):                15.066
  Required (ns):               17.718
  Setup (ns):                  -1.148

Path 3
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[3]/U1:CLK
  To:                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHRESP
  Delay (ns):                  9.353
  Slack (ns):                  2.815
  Arrival (ns):                15.109
  Required (ns):               17.924
  Setup (ns):                  -1.354

Path 4
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/CLDATASELInt[7]/U1:CLK
  To:                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHREADY
  Delay (ns):                  9.118
  Slack (ns):                  2.844
  Arrival (ns):                14.874
  Required (ns):               17.718
  Setup (ns):                  -1.148

Path 5
  From:                        CoreAHBLite_0/matrix2x16/masterstage_0/CLDATASELInt[4]/U1:CLK
  To:                          _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHRESP
  Delay (ns):                  9.259
  Slack (ns):                  2.938
  Arrival (ns):                15.006
  Required (ns):               17.944
  Setup (ns):                  -1.374


Expanded Path 1
  From: CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[3]/U1:CLK
  To: _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHREADY
  data required time                             17.718
  data arrival time                          -   15.135
  slack                                          2.583
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_gla1
               +     0.000          Clock source
  0.000                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLA (r)
               +     5.249          Clock generation
  5.249
               +     0.000          net: _Timerv2_/MSS_CCC_0/I_MSSCCC/GLA_INT
  5.249                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  5.249                        \\Timerv2\\/MSS_CCC_0/I_MSSCCC/U_TILE1:PIN5 (r)
               +     0.507          net: mss_highspeed_timerv2_0_FAB_CLK
  5.756                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[3]/U1:CLK (r)
               +     0.440          cell: ADLIB:DFN1C0
  6.196                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt[3]/U1:Q (r)
               +     1.219          net: CoreAHBLite_0_matrix2x16_xhdl1222[3]
  7.415                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNIUM0A[3]:B (r)
               +     0.390          cell: ADLIB:NOR2
  7.805                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNIUM0A[3]:Y (f)
               +     0.802          net: CoreAHBLite_0/matrix2x16/masterstage_0/hready_m_xhdl387_10_0
  8.607                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNI7P1P[8]:A (f)
               +     0.486          cell: ADLIB:NOR3B
  9.093                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNI7P1P[8]:Y (f)
               +     0.247          net: CoreAHBLite_0/matrix2x16/masterstage_0/HRESP_0_0_a2_6_a0_2
  9.340                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNIRQGC1[8]:C (f)
               +     0.486          cell: ADLIB:OR3C
  9.826                        CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNIRQGC1[8]:Y (r)
               +     0.247          net: CoreAHBLite_0/matrix2x16/masterstage_0/N_1_3_i
  10.073                       CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNIML1P2[1]:C (r)
               +     0.581          cell: ADLIB:AO1B
  10.654                       CoreAHBLite_0/matrix2x16/masterstage_0/SDATASELInt_RNIML1P2[1]:Y (f)
               +     1.415          net: CoreAHBLite_0/matrix2x16/masterstage_0/N_1076
  12.069                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_m_0_a2_1:A (f)
               +     0.469          cell: ADLIB:MX2
  12.538                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMNextState_m_0_a2_1:Y (f)
               +     0.746          net: CoreAHBLite_0_matrix2x16_masterstage_0_N_1064_2
  13.284                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState_RNI28NOO:A (f)
               +     0.707          cell: ADLIB:OA1C
  13.991                       CoreAHBLite_0/matrix2x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState_RNI28NOO:Y (r)
               +     0.700          net: CoreAHBLite_0_matrix2x16_masterstage_0_HREADY_M_iv
  14.691                       _Timerv2_/MSS_ADLIB_INST/U_58:PIN4 (r)
               +     0.065          cell: ADLIB:MSS_IF
  14.756                       _Timerv2_/MSS_ADLIB_INST/U_58:PIN4INT (r)
               +     0.379          net: _Timerv2_/MSS_ADLIB_INST/MSSHREADYINT_NET
  15.135                       _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHREADY (r)
                                    
  15.135                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       mss_fabric_interface_clock
               +     0.000          Clock source
  12.500                       _Timerv2_/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     4.070          Clock generation
  16.570
               -    -1.148          Library setup time: ADLIB:MSS_AHB_IP
  17.718                       _Timerv2_/MSS_ADLIB_INST/U_CORE:MSSHREADY
                                    
  17.718                       data required time


END SET mss_ccc_gla1 to mss_fabric_interface_clock

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

Path 1
  From:                        Pulse_in
  To:                          Test_port[0]
  Delay (ns):                  4.786
  Slack (ns):
  Arrival (ns):                4.786
  Required (ns):


Expanded Path 1
  From: Pulse_in
  To: Test_port[0]
  data required time                             N/C
  data arrival time                          -   4.786
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        Pulse_in (f)
               +     0.000          net: Pulse_in
  0.000                        Pulse_in_pad/U0/U0:PAD (f)
               +     0.529          cell: ADLIB:IOPAD_IN
  0.529                        Pulse_in_pad/U0/U0:Y (f)
               +     0.000          net: Pulse_in_pad/U0/NET1
  0.529                        Pulse_in_pad/U0/U1:YIN (f)
               +     0.030          cell: ADLIB:IOIN_IB
  0.559                        Pulse_in_pad/U0/U1:Y (f)
               +     0.977          net: Pulse_in_c_c
  1.536                        Test_port_pad[0]/U0/U1:D (f)
               +     0.442          cell: ADLIB:IOTRI_OB_EB
  1.978                        Test_port_pad[0]/U0/U1:DOUT (f)
               +     0.000          net: Test_port_pad[0]/U0/NET1
  1.978                        Test_port_pad[0]/U0/U0:D (f)
               +     2.808          cell: ADLIB:IOPAD_TRI
  4.786                        Test_port_pad[0]/U0/U0:PAD (f)
               +     0.000          net: Test_port[0]
  4.786                        Test_port[0] (f)
                                    
  4.786                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          Pulse_in (f)
                                    
  N/C                          Test_port[0] (f)
                                    
  N/C                          data required time


END SET Input to Output

----------------------------------------------------

Path set User Sets

