library ieee;
use ieee.std_logic_1164.all;
library smartfusion;
use smartfusion.all;

entity count_zero_blk is
    port( count2_0_zero     : out   std_logic;
          count23_3_zero    : out   std_logic;
          FABTIMER_CLK      : in    std_logic;
          Count : in    std_logic_vector(23 downto 0)
        );
end count_zero_blk;

architecture DEF_ARCH of count_zero_blk is 

  component NOR3
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;

    component AND3
    port( A : in    std_logic := 'U';
          B : in    std_logic := 'U';
          C : in    std_logic := 'U';
          Y : out   std_logic
        );
  end component;


    signal NOR3_Y : std_logic_vector(5 downto 0);
    signal NOR33_Y : std_logic_vector(1 downto 0);
    signal count5_3_zero, count23_3_zero_int : std_logic;

begin 
    
    NOR3_7 : NOR3 port map(A => Count(21), B => Count(22), C => Count(23), Y => NOR3_Y(5));
    NOR3_6 : NOR3 port map(A => Count(18), B => Count(19), C => Count(20), Y => NOR3_Y(4));
    NOR3_5 : NOR3 port map(A => Count(15), B => Count(16), C => Count(17), Y => NOR3_Y(3));
    NOR3_4 : NOR3 port map(A => Count(12), B => Count(13), C => Count(14), Y => NOR3_Y(2));
    NOR3_3 : NOR3 port map(A => Count(9),  B => Count(10), C => Count(11), Y => NOR3_Y(1));
    NOR3_2 : NOR3 port map(A => Count(6),  B => Count(7),  C => Count(8),  Y => NOR3_Y(0));        
    NOR3_1 : NOR3 port map(A => Count(3),  B => Count(4),  C => Count(5),  Y => count5_3_zero);
    NOR3_0 : NOR3 port map(A => Count(0),  B => Count(1),  C => Count(2),  Y => count2_0_zero);  

    AND3_01 : AND3 port map(A => NOR3_Y(3),  B => NOR3_Y(4),  C => NOR3_Y(5),  Y => NOR33_Y(1));
    AND3_00 : AND3 port map(A => NOR3_Y(0),  B => NOR3_Y(1),  C => NOR3_Y(2),  Y => NOR33_Y(0));

    AND3_000 : AND3 port map(A => NOR33_Y(0),  B => NOR33_Y(1),  C =>  count5_3_zero,  Y => count23_3_zero_int);

    p_zerocount : process (FABTIMER_CLK)
    begin
        if (FABTIMER_CLK'event and FABTIMER_CLK = '1') then
            count23_3_zero <= count23_3_zero_int;
        end if;
    end process;



end DEF_ARCH;