----------------------------------------------------------------------
-- Created by Actel SmartDesign Mon Dec 12 14:39:28 2011
-- Testbench Template
-- This is a basic testbench that instantiates your design with basic 
-- clock and reset pins connected.  If your design has special
-- clock/reset or testbench driver requirements then you should 
-- copy this file and modify it. 
----------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench;

architecture behavioral of testbench is

    constant SYSCLK_PERIOD : time := 100 ns;

    signal SYSCLK : std_logic := '0';
    signal NSYSRESET : std_logic := '0';

    component top_timer
        -- ports
        port( 
            -- Inputs
            UART_0_RXD : in std_logic;
            MSS_RESET_N : in std_logic;
            Pulse_in : in std_logic;

            -- Outputs
            UART_0_TXD : out std_logic;
            TIMINT : out std_logic;
            Test_port : out std_logic_vector(3 downto 0)

            -- Inouts

        );
    end component;

begin

    process
        variable vhdl_initial : BOOLEAN := TRUE;

    begin
        if ( vhdl_initial ) then
            -- Assert Reset
            NSYSRESET <= '0';
            wait for ( SYSCLK_PERIOD * 10 );
            
            NSYSRESET <= '1';
            wait;
        end if;
    end process;

    -- 10MHz Clock Driver
    SYSCLK <= not SYSCLK after (SYSCLK_PERIOD / 2.0 );

    -- Instantiate Unit Under Test:  top_timer
    top_timer_0 : top_timer
        -- port map
        port map( 
            -- Inputs
            UART_0_RXD => '0',
            MSS_RESET_N => NSYSRESET,
            Pulse_in => '0',

            -- Outputs
            UART_0_TXD =>  open,
            TIMINT =>  open,
            Test_port => open

            -- Inouts

        );

end behavioral;

