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                            Global Usage Report
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Product: Designer
Release: v10.0
Version: 10.0.9.37
Date: Mon Dec 12 14:07:46 2011
Design Name: top_timer  Family: SmartFusion  Die: A2F200M3F  Package: 484 FBGA
Design State: Post-Layout

The following nets have been routed to a chip global resource:

    Fanout            Name
    ----------------------
    101               Net   : mss_highspeed_timerv2_0_FAB_CLK
                      Driver: _Timerv2_/MSS_CCC_0/I_MSSCCC/U_TILE1
    148               Net   : Timerv2_GLC
                      Driver: _Timerv2_/MSS_CCC_0/I_MSSCCC/U_TILE3
    2                 Net   : TIMINT_c
                      Driver: AHB_timer_0/TIMINT_int_hclk_RNI4603/U_CLKSRC/U_GL




