----------------------------------------------------------------------
-- Created by Actel SmartDesign Mon Dec 12 13:33:24 2011
-- Testbench Template
-- This is a basic testbench that instantiates your design with basic 
-- clock and reset pins connected.  If your design has special
-- clock/reset or testbench driver requirements then you should 
-- copy this file and modify it. 
----------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench;

architecture behavioral of testbench is

    constant SYSCLK_PERIOD : time := 100 ns;

    signal SYSCLK : std_logic := '0';
    signal NSYSRESET : std_logic := '0';

    component Timerv2
        -- ports
        port( 
            -- Inputs
            MSSHREADY : in std_logic;
            MSSHRESP : in std_logic;
            FABINT : in std_logic;
            MSSHRDATA : in std_logic_vector(31 downto 0);
            UART_0_RXD : in std_logic;
            MSS_RESET_N : in std_logic;

            -- Outputs
            GLC : out std_logic;
            FAB_CLK : out std_logic;
            MSSHWRITE : out std_logic;
            MSSHLOCK : out std_logic;
            M2F_RESET_N : out std_logic;
            MSSHADDR : out std_logic_vector(19 downto 0);
            MSSHTRANS : out std_logic_vector(1 downto 0);
            MSSHSIZE : out std_logic_vector(1 downto 0);
            MSSHWDATA : out std_logic_vector(31 downto 0);
            UART_0_TXD : out std_logic

            -- Inouts

        );
    end component;

begin

    process
        variable vhdl_initial : BOOLEAN := TRUE;

    begin
        if ( vhdl_initial ) then
            -- Assert Reset
            NSYSRESET <= '0';
            wait for ( SYSCLK_PERIOD * 10 );
            
            NSYSRESET <= '1';
            wait;
        end if;
    end process;

    -- 10MHz Clock Driver
    SYSCLK <= not SYSCLK after (SYSCLK_PERIOD / 2.0 );

    -- Instantiate Unit Under Test:  Timerv2
    Timerv2_0 : Timerv2
        -- port map
        port map( 
            -- Inputs
            MSSHREADY => '0',
            MSSHRESP => '0',
            FABINT => '0',
            MSSHRDATA => (others=> '0'),
            UART_0_RXD => '0',
            MSS_RESET_N => NSYSRESET,

            -- Outputs
            GLC =>  open,
            FAB_CLK =>  open,
            MSSHWRITE =>  open,
            MSSHLOCK =>  open,
            M2F_RESET_N =>  open,
            MSSHADDR => open,
            MSSHTRANS => open,
            MSSHSIZE => open,
            MSSHWDATA => open,
            UART_0_TXD =>  open

            -- Inouts

        );

end behavioral;

