Timing Violation Report Min Delay Analysis

SmartTime Version v10.0
Actel Corporation - Actel Designer Software Release v10.0 (Version 10.0.9.37)
Copyright (c) 1989-2011
Date: Mon Dec 12 14:07:55 2011


Design: top_timer
Family: SmartFusion
Die: A2F200M3F
Package: 484 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


Path 1
  From:                        AHB_timer_0/reg_load_ack0/U1:CLK
  To:                          AHB_timer_0/reg_load_ack1:D
  Delay (ns):                  0.429
  Slack (ns):                  -2.646
  Arrival (ns):                1.692
  Required (ns):               4.338

Path 2
  From:                        AHB_timer_0/DataOut[15]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[15]:D
  Delay (ns):                  0.434
  Slack (ns):                  -2.636
  Arrival (ns):                1.716
  Required (ns):               4.352

Path 3
  From:                        AHB_timer_0/DataOut[0]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[0]:D
  Delay (ns):                  0.429
  Slack (ns):                  -2.635
  Arrival (ns):                1.711
  Required (ns):               4.346

Path 4
  From:                        AHB_timer_0/DataOut[12]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[12]:D
  Delay (ns):                  0.429
  Slack (ns):                  -2.633
  Arrival (ns):                1.695
  Required (ns):               4.328

Path 5
  From:                        AHB_timer_0/DataOut[10]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[10]:D
  Delay (ns):                  0.663
  Slack (ns):                  -2.415
  Arrival (ns):                1.945
  Required (ns):               4.360

Path 6
  From:                        AHB_timer_0/DataOut[7]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[7]:D
  Delay (ns):                  0.712
  Slack (ns):                  -2.369
  Arrival (ns):                1.994
  Required (ns):               4.363

Path 7
  From:                        AHB_timer_0/DataOut[2]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[2]:D
  Delay (ns):                  0.807
  Slack (ns):                  -2.310
  Arrival (ns):                2.053
  Required (ns):               4.363

Path 8
  From:                        AHB_timer_0/DataOut[11]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[11]:D
  Delay (ns):                  0.773
  Slack (ns):                  -2.301
  Arrival (ns):                2.037
  Required (ns):               4.338

Path 9
  From:                        AHB_timer_0/DataOut[19]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[19]:D
  Delay (ns):                  0.836
  Slack (ns):                  -2.231
  Arrival (ns):                2.111
  Required (ns):               4.342

Path 10
  From:                        AHB_timer_0/DataOut[13]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[13]:D
  Delay (ns):                  0.957
  Slack (ns):                  -2.175
  Arrival (ns):                2.206
  Required (ns):               4.381

Path 11
  From:                        AHB_timer_0/DataOut[21]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[21]:D
  Delay (ns):                  0.953
  Slack (ns):                  -2.155
  Arrival (ns):                2.208
  Required (ns):               4.363

Path 12
  From:                        AHB_timer_0/DataOut[6]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[6]:D
  Delay (ns):                  0.958
  Slack (ns):                  -2.141
  Arrival (ns):                2.222
  Required (ns):               4.363

Path 13
  From:                        AHB_timer_0/DataOut[8]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[8]:D
  Delay (ns):                  0.953
  Slack (ns):                  -2.127
  Arrival (ns):                2.215
  Required (ns):               4.342

Path 14
  From:                        AHB_timer_0/DataOut[4]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[4]:D
  Delay (ns):                  0.982
  Slack (ns):                  -2.117
  Arrival (ns):                2.246
  Required (ns):               4.363

Path 15
  From:                        AHB_timer_0/DataOut[23]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[23]:D
  Delay (ns):                  0.991
  Slack (ns):                  -2.087
  Arrival (ns):                2.273
  Required (ns):               4.360

Path 16
  From:                        AHB_timer_0/DataOut[3]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[3]:D
  Delay (ns):                  0.980
  Slack (ns):                  -2.085
  Arrival (ns):                2.262
  Required (ns):               4.347

Path 17
  From:                        AHB_timer_0/DataOut[5]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[5]:D
  Delay (ns):                  1.016
  Slack (ns):                  -2.072
  Arrival (ns):                2.291
  Required (ns):               4.363

Path 18
  From:                        AHB_timer_0/DataOut[9]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[9]:D
  Delay (ns):                  1.015
  Slack (ns):                  -2.066
  Arrival (ns):                2.281
  Required (ns):               4.347

Path 19
  From:                        AHB_timer_0/DataOut[20]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[20]:D
  Delay (ns):                  1.050
  Slack (ns):                  -2.046
  Arrival (ns):                2.303
  Required (ns):               4.349

Path 20
  From:                        AHB_timer_0/DataOut[16]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[16]:D
  Delay (ns):                  1.067
  Slack (ns):                  -2.029
  Arrival (ns):                2.320
  Required (ns):               4.349

Path 21
  From:                        AHB_timer_0/DataOut[18]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[18]:D
  Delay (ns):                  1.073
  Slack (ns):                  -2.012
  Arrival (ns):                2.358
  Required (ns):               4.370

Path 22
  From:                        AHB_timer_0/DataOut[14]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[14]:D
  Delay (ns):                  1.097
  Slack (ns):                  -1.997
  Arrival (ns):                2.363
  Required (ns):               4.360

Path 23
  From:                        AHB_timer_0/DataOut[1]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[1]:D
  Delay (ns):                  1.103
  Slack (ns):                  -1.982
  Arrival (ns):                2.378
  Required (ns):               4.360

Path 24
  From:                        AHB_timer_0/DataOut[17]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[17]:D
  Delay (ns):                  1.129
  Slack (ns):                  -1.968
  Arrival (ns):                2.404
  Required (ns):               4.372

Path 25
  From:                        AHB_timer_0/p_strecth_TIMINT_pulse.TIMINT_pulse_int[3]:CLK
  To:                          AHB_timer_0/TIMINT_int_hclk:D
  Delay (ns):                  1.148
  Slack (ns):                  -1.937
  Arrival (ns):                2.391
  Required (ns):               4.328

Path 26
  From:                        AHB_timer_0/DataOut[22]/U1:CLK
  To:                          AHB_timer_0/DataOut_int[22]:D
  Delay (ns):                  1.207
  Slack (ns):                  -1.884
  Arrival (ns):                2.483
  Required (ns):               4.367

Path 27
  From:                        AHB_timer_0/p_strecth_TIMINT_pulse.TIMINT_pulse_int[1]:CLK
  To:                          AHB_timer_0/TIMINT_int_hclk:D
  Delay (ns):                  1.520
  Slack (ns):                  -1.565
  Arrival (ns):                2.763
  Required (ns):               4.328

Path 28
  From:                        AHB_timer_0/p_strecth_TIMINT_pulse.TIMINT_pulse_int[2]:CLK
  To:                          AHB_timer_0/TIMINT_int_hclk:D
  Delay (ns):                  1.664
  Slack (ns):                  -1.421
  Arrival (ns):                2.907
  Required (ns):               4.328

Path 29
  From:                        AHB_timer_0/IntEnable/U1:CLK
  To:                          AHB_timer_0/TIMINT_int_hclk:D
  Delay (ns):                  2.229
  Slack (ns):                  -0.814
  Arrival (ns):                3.514
  Required (ns):               4.328

Path 30
  From:                        AHB_timer_0/count_zero_blk_instance/count23_3_zero:CLK
  To:                          AHB_timer_0/TIMINT_int_hclk:D
  Delay (ns):                  2.912
  Slack (ns):                  -0.147
  Arrival (ns):                4.181
  Required (ns):               4.328

Path 31
  From:                        AHB_timer_0/Count[2]/U1:CLK
  To:                          AHB_timer_0/TIMINT_int_hclk:D
  Delay (ns):                  2.981
  Slack (ns):                  -0.083
  Arrival (ns):                4.245
  Required (ns):               4.328

Path 32
  From:                        AHB_timer_0/Count[0]/U1:CLK
  To:                          AHB_timer_0/TIMINT_int_hclk:D
  Delay (ns):                  2.988
  Slack (ns):                  -0.076
  Arrival (ns):                4.252
  Required (ns):               4.328

