-- 24-bit decrementor used for counter.
-- Version: 9.0 9.0.0.101

library ieee;
use ieee.std_logic_1164.all;
library smartfusion;
use smartfusion.all;

entity Decrementor24 is 
    port( DataA : in std_logic_vector(23 downto 0); Sum : out 
        std_logic_vector(23 downto 0)) ;
end Decrementor24;


architecture DEF_ARCH of  Decrementor24 is

    component NOR2
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component XOR2
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component AND3
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component NOR3
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component AND3A
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component AND2
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component AND2A
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component XNOR2
        port(A, B : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component AND3B
        port(A, B, C : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    component INV
        port(A : in std_logic := 'U'; Y : out std_logic) ;
    end component;

    signal dec_1_net, dec_2_net, Rcout_4_net, Rcout_5_net, 
        dec_5_net, Rcout_6_net, Rcout_7_net, dec_8_net, 
        Rcout_8_net, dec_10_net, decb_2_net, Rcout_9_net, 
        dec_12_net, Rcout_10_net, dec_14_net, Rcout_11_net, 
        dec_16_net, decb_5_net, dec_17_net, Rcout_12_net, 
        Rcout_13_net, dec_20_net, Rcout_14_net, dec_22_net, 
        Rcout_15_net, dec_24_net, Rcout_16_net, dec1_25_net, 
        Rcout_17_net, dec_27_net, decb_16_net, dec_28_net, 
        decb_17_net, Rcout_18_net, Rcout_19_net, dec_31_net, 
        Rcout_20_net, dec_33_net, Rcout_21_net, dec_35_net, 
        Rcout_22_net, dec_37_net, Rcout_23_net : std_logic ;
    begin   

    NOR_14_inst : NOR2
      port map(A => DataA(12), B => DataA(13), Y => dec_20_net);
    AXOR2_4_inst : XOR2
      port map(A => Rcout_5_net, B => DataA(5), Y => Sum(5));
    QXOR2_16_inst : XOR2
      port map(A => Rcout_20_net, B => DataA(20), Y => Sum(20));
    TNOR_15_inst : AND3
      port map(A => dec_16_net, B => dec_17_net, C => dec_22_net, 
        Y => Rcout_15_net);
    SAND2_27_inst : NOR3
      port map(A => DataA(18), B => DataA(19), C => DataA(20), 
        Y => dec_33_net);
    UXOR2_3_inst : XOR2
      port map(A => Rcout_6_net, B => DataA(6), Y => Sum(6));
    YNORB_22_inst : AND3
      port map(A => decb_2_net, B => decb_5_net, C => dec_10_net, 
        Y => decb_17_net);
    UXOR_2_inst : XOR2
      port map(A => Rcout_23_net, B => DataA(23), Y => Sum(23));
    QAND2_25_inst : NOR2
      port map(A => DataA(18), B => DataA(19), Y => dec_31_net);
    SXOR2_17_inst : XOR2
      port map(A => Rcout_21_net, B => DataA(21), Y => Sum(21));
    OXOR2_15_inst : XOR2
      port map(A => Rcout_19_net, B => DataA(19), Y => Sum(19));
    XOR2_1_3_inst : XOR2
      port map(A => Rcout_7_net, B => DataA(7), Y => Sum(7));
    NOR_1_7_inst : AND3A
      port map(A => DataA(6), B => dec_2_net, C => dec_5_net, 
        Y => Rcout_7_net);
    YNOR_6_inst : NOR3
      port map(A => DataA(3), B => DataA(4), C => DataA(5), Y => 
        dec_5_net);
    TXOR_2_inst : XOR2
      port map(A => Rcout_22_net, B => DataA(22), Y => Sum(22));
    NOR_13_inst : AND3A
      port map(A => DataA(12), B => dec_17_net, C => dec_16_net, 
        Y => Rcout_13_net);
    TOR_1_inst : AND3
      port map(A => decb_17_net, B => dec_28_net, C => dec_35_net, 
        Y => Rcout_22_net);
    AND2_10_inst : NOR3
      port map(A => DataA(9), B => DataA(10), C => DataA(11), 
        Y => dec_16_net);
    VNOR_18_inst : AND3A
      port map(A => DataA(15), B => dec_17_net, C => dec_24_net, 
        Y => Rcout_16_net);
    SOR_28_inst : AND3
      port map(A => decb_17_net, B => dec_28_net, C => dec_33_net, 
        Y => Rcout_21_net);
    AND2_L_0_inst : AND2
      port map(A => dec_2_net, B => dec_5_net, Y => Rcout_6_net);
    NOR2B_10_inst : NOR3
      port map(A => DataA(3), B => DataA(4), C => DataA(5), Y => 
        decb_5_net);
    XOR2_2_inst : XOR2
      port map(A => dec_2_net, B => DataA(3), Y => Sum(3));
    XOR2_6_inst : XOR2
      port map(A => Rcout_8_net, B => DataA(8), Y => Sum(8));
    YNOR_21_inst : NOR3
      port map(A => DataA(15), B => DataA(16), C => DataA(17), 
        Y => dec_27_net);
    YNOR_22_inst : AND3
      port map(A => decb_16_net, B => dec_22_net, C => dec_27_net, 
        Y => dec_28_net);
    NOR_4_inst : AND2A
      port map(A => DataA(3), B => dec_2_net, Y => Rcout_4_net);
    NOR_11_inst : AND3
      port map(A => dec_14_net, B => dec_5_net, C => dec_10_net, 
        Y => Rcout_11_net);
    NOR_15_inst : AND3
      port map(A => dec_16_net, B => dec_17_net, C => dec_20_net, 
        Y => Rcout_14_net);
    PXOR2_13_inst : XOR2
      port map(A => Rcout_17_net, B => DataA(17), Y => Sum(17));
    OXOR2_11_inst : XOR2
      port map(A => Rcout_15_net, B => DataA(15), Y => Sum(15));
    YOR_23_inst : AND2
      port map(A => decb_17_net, B => dec_28_net, Y => 
        Rcout_18_net);
    XOR2_9_inst : XOR2
      port map(A => Rcout_11_net, B => DataA(11), Y => Sum(11));
    QOR_26_inst : AND3
      port map(A => decb_17_net, B => dec_28_net, C => dec_31_net, 
        Y => Rcout_20_net);
    YXOR2_14_inst : XOR2
      port map(A => Rcout_18_net, B => DataA(18), Y => Sum(18));
    PNOR_20_inst : AND3A
      port map(A => DataA(15), B => dec_17_net, C => dec1_25_net, 
        Y => Rcout_17_net);
    XNOR2_1_inst : XNOR2
      port map(A => DataA(0), B => DataA(1), Y => Sum(1));
    UOR_1_inst : AND3
      port map(A => decb_17_net, B => dec_28_net, C => dec_37_net, 
        Y => Rcout_23_net);
    VNOR_17_inst : AND2
      port map(A => dec_22_net, B => dec_16_net, Y => dec_24_net);
    FOR2_8_inst : XOR2
      port map(A => Rcout_10_net, B => DataA(10), Y => Sum(10));
    PNOR_19_inst : AND3A
      port map(A => DataA(16), B => dec_22_net, C => dec_16_net, 
        Y => dec1_25_net);
    TAND2_0_inst : AND2A
      port map(A => DataA(21), B => dec_33_net, Y => dec_35_net);
    UAND2_0_inst : AND3B
      port map(A => DataA(21), B => DataA(22), C => dec_33_net, 
        Y => dec_37_net);
    XOR2_10_inst : XOR2
      port map(A => Rcout_13_net, B => DataA(13), Y => Sum(13));
    tAND2_9_inst : NOR3
      port map(A => DataA(6), B => DataA(7), C => DataA(8), Y => 
        dec_10_net);
    UNOR_15_inst : NOR3
      port map(A => DataA(12), B => DataA(13), C => DataA(14), 
        Y => dec_22_net);
    NOR_1_12_inst : AND2
      port map(A => dec_16_net, B => dec_17_net, Y => 
        Rcout_12_net);
    LNOR_5_inst : AND3B
      port map(A => DataA(3), B => DataA(4), C => dec_2_net, Y => 
        Rcout_5_net);
    UAND2_10_inst : AND3B
      port map(A => DataA(9), B => DataA(10), C => decb_2_net, 
        Y => dec_14_net);
    LOR_8_inst : AND3
      port map(A => decb_2_net, B => dec_5_net, C => dec_10_net, 
        Y => Rcout_9_net);
    YNORBB_22_inst : NOR3
      port map(A => DataA(9), B => DataA(10), C => DataA(11), 
        Y => decb_16_net);
    OOR_24_inst : AND3A
      port map(A => DataA(18), B => decb_17_net, C => dec_28_net, 
        Y => Rcout_19_net);
    XOR2_2_1_inst : XOR2
      port map(A => dec_1_net, B => DataA(2), Y => Sum(2));
    XOR3_7_inst : XOR2
      port map(A => Rcout_9_net, B => DataA(9), Y => Sum(9));
    FND2_10_inst : AND2A
      port map(A => DataA(9), B => decb_2_net, Y => dec_12_net);
    tAND2n_9_inst : NOR3
      port map(A => DataA(0), B => DataA(1), C => DataA(2), Y => 
        decb_2_net);
    INV_0_inst : INV
      port map(A => DataA(0), Y => Sum(0));
    AND2_2_inst : NOR2
      port map(A => DataA(0), B => DataA(1), Y => dec_1_net);
    AND2_8_inst : NOR2
      port map(A => DataA(6), B => DataA(7), Y => dec_8_net);
    NOR_8_inst : AND3
      port map(A => dec_2_net, B => dec_5_net, C => dec_8_net, 
        Y => Rcout_8_net);
    NOR_2_11_inst : AND3
      port map(A => decb_2_net, B => decb_5_net, C => dec_10_net, 
        Y => dec_17_net);
    XOR2_1_10_inst : XOR2
      port map(A => Rcout_12_net, B => DataA(12), Y => Sum(12));
    VXOR2_13_inst : XOR2
      port map(A => Rcout_16_net, B => DataA(16), Y => Sum(16));
    JXOR2_10_inst : XOR2
      port map(A => Rcout_14_net, B => DataA(14), Y => Sum(14));
    AND2_3_inst : NOR3
      port map(A => DataA(0), B => DataA(1), C => DataA(2), Y => 
        dec_2_net);
    FOR_9_inst : AND3
      port map(A => dec_12_net, B => dec_5_net, C => dec_10_net, 
        Y => Rcout_10_net);
    XOR2_3_inst : XOR2
      port map(A => Rcout_4_net, B => DataA(4), Y => Sum(4));
end DEF_ARCH;
